Semiconductor device manufacturing: process

Patent class list (only not empty are listed)

Deeper subclasses:

Class / Patent application number	Description	Number of patent applications / Date published
438142000	MAKING FIELD EFFECT DEVICE HAVING PAIR OF ACTIVE REGIONS SEPARATED BY GATE STRUCTURE BY FORMATION OR ALTERATION OF SEMICONDUCTIVE ACTIVE REGIONS	4604
438584000	COATING WITH ELECTRICALLY OR THERMALLY CONDUCTIVE MATERIAL	4602
438689000	CHEMICAL ETCHING	3454
438048000	MAKING DEVICE OR CIRCUIT RESPONSIVE TO NONELECTRICAL SIGNAL	3085
438022000	MAKING DEVICE OR CIRCUIT EMISSIVE OF NONELECTRICAL SIGNAL	3017
438106000	PACKAGING (E.G., WITH MOUNTING, ENCAPSULATING, ETC.) OR TREATMENT OF PACKAGED SEMICONDUCTOR	2613
438478000	FORMATION OF SEMICONDUCTIVE ACTIVE REGION ON ANY SUBSTRATE (E.G., FLUID GROWTH, DEPOSITION)	1695
438758000	COATING OF SUBSTRATE CONTAINING SEMICONDUCTOR REGION OR OF SEMICONDUCTOR SUBSTRATE	1627
438014000	WITH MEASURING OR TESTING	1027
438381000	MAKING PASSIVE DEVICE (E.G., RESISTOR, CAPACITOR, ETC.)	991
438400000	FORMATION OF ELECTRICALLY ISOLATED LATERAL SEMICONDUCTIVE STRUCTURE	955
438005000	INCLUDING CONTROL RESPONSIVE TO SENSED CONDITION	779
438460000	SEMICONDUCTOR SUBSTRATE DICING	667
438510000	INTRODUCTION OF CONDUCTIVITY MODIFYING DOPANT INTO SEMICONDUCTIVE MATERIAL	644
438455000	BONDING OF PLURAL SEMICONDUCTOR SUBSTRATES	629
438104000	HAVING METAL OXIDE OR COPPER SULFIDE COMPOUND SEMICONDUCTOR COMPONENT	513
438003000	HAVING MAGNETIC OR FERROELECTRIC COMPONENT	493
438795000	RADIATION OR ENERGY TREATMENT MODIFYING PROPERTIES OF SEMICONDUCTOR REGION OF SUBSTRATE (E.G., THERMAL, CORPUSCULAR, ELECTROMAGNETIC, ETC.)	370
438099000	HAVING ORGANIC SEMICONDUCTIVE COMPONENT	240
438004000	REPAIR OR RESTORATION	137
438102000	HAVING SELENIUM OR TELLURIUM ELEMENTAL SEMICONDUCTOR COMPONENT	136
438471000	GETTERING OF SUBSTRATE	128
438133000	MAKING REGENERATIVE-TYPE SWITCHING DEVICE (E.G., SCR, IGBT, THYRISTOR, ETC.)	112
438128000	MAKING DEVICE ARRAY AND SELECTIVELY INTERCONNECTING	107
438309000	FORMING BIPOLAR TRANSISTOR BY FORMATION OR ALTERATION OF SEMICONDUCTIVE ACTIVE REGIONS	104
438021000	MANUFACTURE OF ELECTRICAL DEVICE CONTROLLED PRINTHEAD	84
438466000	DIRECT APPLICATION OF ELECTRICAL CURRENT	55
438570000	FORMING SCHOTTKY JUNCTION (I.E., SEMICONDUCTOR-CONDUCTOR RECTIFYING JUNCTION CONTACT)	43
438105000	HAVING DIAMOND SEMICONDUCTOR COMPONENT	20
438020000	ELECTRON EMITTER MANUFACTURE	20
438001000	HAVING BIOMATERIAL COMPONENT OR INTEGRATED WITH LIVING ORGANISM	15
438800000	MISCELLANEOUS	14
438379000	VOLTAGE VARIABLE CAPACITANCE DEVICE MANUFACTURE (E.G., VARACTOR, ETC.)	12
438019000	HAVING INTEGRAL POWER SOURCE (E.G., BATTERY, ETC.)	10
438002000	HAVING SUPERCONDUCTIVE COMPONENT	5
20110129945	SUPERCONDUCTIVITY BASED ON BOSE-EINSTEIN CONDENSATION OF ELECTRON OR ELECTRON-HOLE PAIRS IN SEMICONDUCTORS - The invention describes a method of achieving superconductivity in Group IV semiconductors via the addition of doubly charged impurity atoms to the crystal lattice. The doubly charged impurities function as composite bosons in the semiconductor. Increasing the density of the composite bosons to a level where their wavefunctions overlap, results in the formation of a Bose condensate. The concentration of the doubly charged impurity atoms in the host lattice and the binding energy of the impurities are important factors in determining whether a Bose condensate will form. Doubly charged impurities must be present in the semiconductor at a concentration at which they exhibit overlapping wavefunctions, but still exist within the crystal lattice as bosons.	06-02-2011
20150311422	SUSPENDED SUPERCONDUCTING QUBITS - A qubit system includes a substrate layer, a qubit circuit suspended above the substrate layer and fine structure disposed between the qubit circuit and the substrate layer.	10-29-2015
20150380632	DOUBLE-MASKING TECHNIQUE FOR INCREASING FABRICATION YIELD IN SUPERCONDUCTING ELECTRONICS - An improved microfabrication technique for Josephson junctions in superconducting integrated circuits, based on the use of a double-layer lithographic mask for partial anodization of the side-walls and base electrode of the junctions. The top layer of the mask is a resist material, and the bottom layer is a dielectric material chosen so to maximize adhesion between the resist and the underlying superconducting layer, be etch-compatible with the underlying superconducting layer, and be insoluble in the resist and anodization processing chemistries. The superconductor is preferably niobium, under a silicon dioxide layer, with a conventional photoresist or electron-beam resist as the top layer. This combination results in a substantial increase in the fabrication yield of high-density superconducting integrated circuits, increase in junction uniformity and reduction in defect density. A dry etch more compatible with microlithography may be employed.	12-31-2015
20160204331	REMOVAL OF SPURIOUS MICROWAVE MODES VIA FLIP-CHIP CROSSOVER	07-14-2016
20220140223	METHOD FOR PREPARING A JOSEPHSON JUNCTION, APPARATUS, AND DEVICE, AND SUPERCONDUCTING DEVICE - Methods, apparatuses, and devices for Josephson junction preparation includes: obtaining a first pattern structure for generating a first Josephson junction of a first type and a plurality of second pattern structures for generating a plurality of second Josephson junctions of a second type; evaporating a material on the first pattern structure and the plurality of second pattern structures based on a first evaporation direction to generate a first electrode layer for implementing information transmission; forming an insulating layer on the first electrode layer, the insulating layer including a compound corresponding to the material; evaporating the material on the first pattern structure and the plurality of second pattern structures based on a second evaporation direction to generate a second electrode layer for implementing information transmission; and forming the first Josephson junction and the plurality of second Josephson junctions.	05-05-2022
438380000	AVALANCHE DIODE MANUFACTURE (E.G., IMPATT, TRAPPAT, ETC.)	3
20140242771	METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A semiconductor component and a method for manufacturing the semiconductor component, wherein the semiconductor component includes a transient voltage suppression structure that includes at least two diodes and a Zener diode. In accordance with embodiments, a semiconductor material is provided that includes an epitaxial layer. The at least two diodes and the Zener diode are created at the surface of the epitaxial layer, where the at least two diodes may be adjacent to the Zener diode.	08-28-2014
20140363946	LOW CAPACITANCE TRANSIENT VOLTAGE SUPPRESSOR (TVS) WITH REDUCED CLAMPING VOLTAGE - A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. Each trench is lined with a dielectric layer. A set of source regions is formed within a top surface of the second epitaxial layer. The trenches and source regions alternate. A pair of implant regions is formed in the second epitaxial layer.	12-11-2014
20150118820	METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE - A method of manufacturing a semiconductor structure with a high voltage area and a low voltage area is provided. The method includes the following steps: providing a substrate of a first conductivity type; forming a second doped region of a second conductivity type in the substrate by a first implantation; forming a first doped region of a first conductivity type in the second doped region by a second implantation; forming an insulating layer on the substrate; forming a resistor on the insulating layer, wherein the resistor is electrically connecting the high voltage area and the low voltage area; and forming a conductor electrically connected to the resistor. The step of forming a first doped region defines the high voltage area and the low voltage area.	04-30-2015
438141000	MAKING CONDUCTIVITY MODULATION DEVICE (E.G., UNIJUNCTION TRANSISTOR, DOUBLE BASE DIODE, CONDUCTIVITY-MODULATED TRANSISTOR, ETC.)	2
20080286907	SEMICONDUCTOR LAYER FOR THIN FILM TRANSISTORS - A method for making a zinc oxide semiconductor layer for a thin film transistor using solution processing at low temperatures is disclosed. The method comprises making a solution comprising a zinc salt and a complexing agent; applying the solution to a substrate; and heating the solution to form a semiconductor layer on the substrate. A thin film transistor using this zinc oxide semiconductor layer has good mobility and on/off ratio.	11-20-2008
20110111564	METHOD AND APPARATUS FOR OPTICAL MODULATION - The present invention is a method and an apparatus for optical modulation, for example for use in optical communications links. In one embodiment, an apparatus for optical modulation includes a first silicon layer having one or more trenches formed therein, a dielectric layer lining the first silicon layer, and a second silicon layer disposed on the dielectric layer and filling the trenches.	05-12-2011