Entries |
Document | Title | Date |
20080206925 | Methods and apparatus to improve frit-sealed glass package - A hermetically sealed package includes: a first plate including inside and outside surfaces; a second plate including inside and outside surfaces; frit material disposed on the inside surface of the second plate; and at least one dielectric layer disposed directly or indirectly on at least one of: (i) the inside surface of the first plate at least opposite to the frit material, and (ii) the inside surface of the second plate at least directly or indirectly on the frit material, wherein the frit material forms a hermetic seal against the dielectric layer in response to heating. | 08-28-2008 |
20080227237 | Method of assembling chips - A method of assembling chips. A first chip and a second chip are provided. At least one conductive pillar is formed on the first chip, and a conductive connecting material is formed on the conductive pillar. The second chip also comprises at least one conductive pillar. The first chip is connected to the second chip via the conductive pillars and the conductive connecting material. | 09-18-2008 |
20080241991 | GANG FLIPPING FOR FLIP-CHIP PACKAGING - An improved method and apparatus for packaging integrated circuits are described. More particularly, a method and apparatus for use in securing a plurality of integrated circuit dice to a lead frame panel are described. Each integrated circuit die includes an active surface having a multiplicity of solder bumps. The lead frame panel includes an array of device areas, each including a plurality of leads. The method includes positioning a plurality of dice into designated positions on a carrier such that the active surfaces of the dice are facing upwards. The carrier includes a carrier frame including an associated array of carrier device areas. A lead frame panel may be positioned over the carrier such that the solder bumps on the active surfaces of the dice are adjacent and in contact with the associated leads of the associated device areas. | 10-02-2008 |
20080241992 | Method of assembling chips - A method of assembling chips. A first chip and a second chip are provided. At least one conductive pillar is formed on the first chip, and a conductive connecting material is formed on the conductive pillar. The second chip also comprises at least one conductive pillar. The first chip is connected to the second chip via the conductive pillars and the conductive connecting material. | 10-02-2008 |
20080261349 | PROTECTIVE COATING FOR PLANARIZATION - Various pattern transfer and etching steps can be used to create features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer. Planarizing techniques using a filler layer and a protective layer are disclosed. Portions of an integrated circuit having different heights can be etched to a common plane. | 10-23-2008 |
20080261350 | SOLDER INTERCONNECTION ARRAY WITH OPTIMAL MECHANICAL INTEGRITY - A method for assembling, and the resultant electronic module, includes attaching a chip to a substrate using a first solder interconnection array, and attaching a board to the substrate using a second solder interconnection array, which may be a single-melt or a dual-melt solder array. The second solder interconnection array resides entirely within a space defined between the board and substrate. A creep resistant structure is provided within this space for maintaining the defined space and optimizing integrity of the second solder interconnection array. The creep resistant structure may include an underfill material, balls, brackets, frames, collars or combinations thereof. Wherein the creep resistant structure is an underfill material, it is crucial that the substrate be attached to the board before either entirely encapsulating the second interconnection array with underfill material, or partially encapsulating the second solder interconnection array at discrete locations with underfill material. | 10-23-2008 |
20080274586 | SEMICONDUCTOR DEVICE, WAFER AND METHOD OF DESIGNING AND MANUFACTURING THE SAME - A process margin of an interconnect is to be expanded, to minimize the impact of vibration generated during a scanning motion of a scanning type exposure equipment. In a semiconductor device, the interconnect handling a greater amount of data (frequently used interconnect) is disposed in a same orientation such that the longitudinal direction of the interconnects is aligned with a scanning direction of a scanning type exposure equipment, in an interconnect layer that includes a narrowest interconnect or a narrowest spacing between the interconnects. Aligning thus the direction of the vibration with the longitudinal direction of the pattern can minimize the positional deviation due to the vibration. | 11-06-2008 |
20080280392 | CONVEX DIE ATTACHMENT METHOD - A method for assembling a microelectronic device is provided comprising the step of adhering a die to a substrate using a convex die attachment process. The convex die attachment process generally comprises a) providing a die having an underfill material thereon, b) picking up and inverting the die, c) heating the underfill until it liquefies at least slightly and forms a convex surface, and d) placing the die on a substrate. | 11-13-2008 |
20080318360 | DEVICE AND METHOD FOR FABRICATING DOUBLE-SIDED SOI WAFER SCALE PACKAGE WITH OPTICAL THROUGH VIA CONNECTIONS - A semiconductor package includes an SOI wafer having a first side including an integrated circuit system, and a second side, opposite the first side, forming at least one cavity. At least one chip or component is placed in the cavity. An optical through via is formed through a buried oxide which optically connects the chip(s) to the integrated circuit system. | 12-25-2008 |
20090011538 | Packaging system - A mounting system is provided with a substrate loader section, a chip mounting section, and a substrate unloader section for sequentially taking out substrates whereupon chips are mounted. The mounting system is characterized in that the substrate loader section is provided with an oven capable of heat insulating a substrate together with a substrate magazine capable of containing a plurality of substrates, a stage heater for heating/heat insulating a substrate is provided, respectively, at a substrate conveying portion from a substrate waiting stage for the chip mounting section to the chip mounting section, at the chip mounting section, and at a substrate conveying portion from the chip mounting section to the substrate unloader section, and the substrate unloader section is provided with an oven capable of heat insulating a substrate together with a substrate magazine capable of containing a plurality of substrates whereupon chips are mounted. The substrate can be sustained at a desirable temperature over the substantially entire mounting process having a series of steps, and in particular, occurrence of problems ascribed to moisture absorption can be suppressed or prevented. | 01-08-2009 |
20090017578 | Application of RFID labels - Disclosed is a method for producing an RFID label with the aid of a printing process. The aim of the invention is make it easy to apply the parts required onto the label while completing the label in a simple manner. Said aim is achieved by applying at least one portion of the antenna and the resonant circuit required for the function to the printing material by means of sheet-fed offset printing or directly or indirectly with the aid of a relief printing plate. The resonant circuits or chips are applied individually or to a packaging that is to be created or filled in the same alignment once several copies of the labels have been produced on one sheet and have been separated therefrom. | 01-15-2009 |
20090017579 | METHOD OF MANUFACTURING MICRO ELECTRO MECHANICAL SYSTEMS DEVICE - Provided is a MEMS device which is robust to the misalignment and does not require the double-side wafer processing in the manufacture of a MEMS device such as an angular velocity sensor, an acceleration sensor, a combined sensor or a micromirror. After preparing a substrate having a space therein, holes are formed in a device layer at positions where fixed components such as a fixing portion, a terminal portion and a base that are fixed to a supporting substrate are to be formed, and the holes are filled with a fixing material so that the fixing material reaches the supporting substrate, thereby fixing the device layer around the holes to the supporting substrate. | 01-15-2009 |
20090035890 | TECHNIQUES FOR DIRECT ENCASEMENT OF CIRCUIT BOARD STRUCTURES - A technique for processing an electronic apparatus (e.g., manufacturing an assembled circuit board, treating an assembled circuit board, etc.) involves applying encasement material to an area of the circuit board assembly while leaving at least a portion of the circuit board assembly exposed. The technique further involves causing the applied encasement material to harden (e.g., heating the encasement material in a curing oven, applying radiation, providing a chemical catalyst, etc.). Application and hardening of the encasement material may take place shortly after circuit board assembly (e.g., by automated equipment at a manufacturing facility in order to treat newly assembled boards) or at some later time in the field (e.g., by a technician servicing a legacy board). | 02-05-2009 |
20090053852 | MANUFACTURING APPARATUS AND METHOD FOR AN ELECTRONIC APPARATUS - A manufacturing method for an electronic apparatus and manufacturing apparatus are provided. The manufacturing method includes applying to a surface of a sheet an adhesive to be charged into a space between a mounting board and an electronic component mounted on the mounting board, bringing the one surface of the sheet into contact with a back surface of the electronic component mounted on the mounting board and charging the adhesive into the space by bringing the adhesive into contact with a peripheral portion of the electronic component under a low pressure, and pressing a heating head against the other surface of the sheet and heating the sheet with the heating head via the sheet to set the adhesive under atmospheric pressure, in a state that the sheet is in contact with the electronic component. | 02-26-2009 |
20090053853 | METHOD FOR MANUFACTURING ELECTRONIC COMPONENT - A chip element in the form of a substantially rectangular parallelepiped having end surfaces and side surfaces is formed (step of forming chip element). An electrically conductive green sheet is formed (step of forming electrically conductive green sheet). An electrically conductive paste is applied to the end surfaces of the chip element (step of application electrically conductive paste). A chip element is formed in which the electrically conductive green sheet is attached to the end surface via the electrically conductive paste applied to the end surface of the chip element (step of attaching electrically conductive sheet). In the step of attaching, the end surface of the electrically conductive green sheet on the side of the side surfaces is positioned on the outside of the side surfaces, and the electrically conductive paste applied to the end surface is pressed out into a space between the electrically conductive green sheet and ridge portions. | 02-26-2009 |
20090061560 | METHOD OF FABRICATING ORGANIC ELECTRONIC DEVICE - A fabricating method of organic electronic device is provided. The method comprises: providing a flexible substrate; fabricating a plurality of organic elements on the flexible substrate; depositing a spacing material layer on the flexible substrate; patterning the spacing material layer to form a patterned spacing layer; and arranging a cover substrate on the patterned spacing layer, and sealing the edges of the flexible substrate and the cover substrate with a sealant, wherein the patterned spacing layer is used to maintain a space between the flexible substrate and the cover substrate. | 03-05-2009 |
20090075422 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - An internal connecting terminal | 03-19-2009 |
20090117687 | Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument - A method of manufacturing a semiconductor device forms a penetrating hole in a substrate so that the penetrating hole extends from a first surface of the substrate to a second surface of the substrate being opposite to the first surface. An internal wall surface of the penetrating hole has a protrusion formed of a material constituting the substrate, the first surface of the substrate being closer to the protrusion than the second surface. A conductive member is formed on the first surface so that the conductive member covers the penetrating hole. A semiconductor chip is mounted on the first surface so that an electrode of the semiconductor chip is electrically connected to the conductive member. An external electrode is provided through the penetrating hole so that the external electrode is electrically connected to the conductive member and the external electrode projects from the second surface of the substrate. | 05-07-2009 |
20090124043 | Method of manufacturing a package board - A method of manufacturing a package board is disclosed. The method is for manufacturing a package board that has a pad electrically connected with a component, and includes: forming an indentation, which is in correspondence with the pad, in one side of a first insulating layer; filling a metal paste in the indentation; mounting the component on the first insulating layer in correspondence with a location of the indentation; and hardening the metal paste. Using this method, damage to the component can be prevented during the forming of vias, as the component is mounted after filling paste in an indentation formed in an insulating layer. | 05-14-2009 |
20090137082 | Manufacturing method for electronic devices - A manufacturing method for manufacturing an electronic device includes a first electronic component and a second electronic component; and a bond part for the first electronic component joined to another bond part for the second electronic component. In a first process of this manufacturing method, the metallic bond part for the first electronic component is placed directly against the metallic bond part for the second electronic component, pressure is applied to the first electronic component and the second electronic component and, after metallically joining the above two bond parts, the pressure applied to the first electronic component and the second electronic component is released. In a second process in the manufacturing method, a clamping member affixes the relative positions of the joined first electronic component and second electronic component, and heats the first electronic component and the second electronic component to maintain a specified temperature. | 05-28-2009 |
20090155953 | Semiconductor device fabricating method and fabricating apparatus - Respective attracting openings of a bonding head are disposed so as to avoid joining regions at which bump electrodes (obverse electrodes) of a semiconductor chip are joined with bump electrodes of a package substrate. Bump electrodes (reverse electrodes) that are connected to the bump electrodes are provided at a reverse side of the semiconductor chip at positions opposing the bump electrodes. Because the attracting openings do not overlap the joining regions, the bump electrodes (reverse electrodes) are not suctioned at the joining regions. | 06-18-2009 |
20090155954 | THERMAL ENHANCED LOW PROFILE PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME - A thermal enhanced low profile package structure and a method for fabricating the same are provided. The package structure typically includes a metallization layer with an electronic component thereon which is between two provided dielectric layers. The metallization layer as well as the electronic component is embedded and packaged while the substrates are laminated via a lamination process. The fabricated package structure performs not only a superior electric performance, but also an excellent enhancement in thermal dissipation. | 06-18-2009 |
20090162974 | SEMICONDUCTOR PACKAGE BOARD USING A METAL BASE - A semiconductor package board for mounting thereon a semiconductor chip includes a metal base having an opening for receiving therein the semiconductor chip and a multilayer wiring film layered onto the metal base. The semiconductor chip is flip-chip bonded onto the metal pads disposed on the multilayer wiring film within the opening. The surface of the metal base is flush with the top surface of the semiconductor chip received in the opening. The resultant semiconductor device has a larger number of external pins and a smaller deformation without using a stiffener. | 06-25-2009 |
20090170239 | UTILIZING APERTURE WITH PHASE SHIFT FEATURE IN FORMING MICROVIAS - A method, comprises drilling a set of one or more microvias in a semiconductor package with an aperture, wherein drilling the set of microvias comprises to use an aperture that has a phase shift region to reduce a spot size of a drilling beam that is used to form the set of microvias. | 07-02-2009 |
20090170240 | Optimized Circuit Design Layout for High Performance Ball Grid Array Packages - A method of laying out traces for connection of bond pads of a semiconductor chip to a printed wiring board or the like and the layout. There is provided a substrate having top and bottom surfaces with a plurality of rows and columns of vias extending therethrough from the top surface to the bottom surface and having a solder ball secured at the bottom surface to each via. A plurality of pairs of traces is provided on the top surface, each trace of each pair of traces extending to a different one of the vias and extending to vias on a plurality of the rows and columns, each of the traces of each pair being spaced from the other trace by a ball pitch, being maximized for identity in length and being maximized for parallelism and spacing. Each of the traces of a pair is preferably be further maximized for identity in cross-sectional geometry. A differential signal pair is preferably applied to at least one of a pair of traces. The layout can further include a further surface between the top and bottom surfaces insulated from the top and bottom surfaces, a plurality of the traces being disposed on the further surface. | 07-02-2009 |
20090191664 | Apparatus for Improved Power Distribution in Wirebond Semiconductor Packages - A semiconductor package comprising a die adjacent a substrate, a supporting plate adjacent the die, and a conducting plate abutting the supporting plate and electrically coupled to a metal apparatus adjacent the substrate and the die using a plurality of bond wires. The metal apparatus supplies power to the conducting plate. | 07-30-2009 |
20090203167 | Method for Manufacturing Bonded Substrate - The present invention provides a method for manufacturing a bonded substrate that is a method for manufacturing a bonded substrate where an active layer wafer is bonded to a support substrate wafer, comprising: a first step of providing a groove on an inner side on a surface of the active layer wafer along an outer peripheral portion over an entire circumference; a second step of determining a surface where the groove is formed as a bonding surface and bonding the active layer wafer to the support substrate wafer; and a third step of reducing a film thickness of the active layer wafer and removing an unbonded portion on an outer side of the groove of the active layer wafer. As a result, there is provided the method for manufacturing a bonded substrate that can simplify processes, avoid breakage, cracks, or particle generation, and manage a shape of an edge portion of an active layer wafer when reducing a film thickness of the active layer wafer. | 08-13-2009 |
20090215226 | Method of Detaching a Thin Semiconductor Circuit From Its Base - In order to provide a method of detaching a thin semiconductor circuit ( | 08-27-2009 |
20090215227 | Chip Scale Package Fabrication Methods - Embodiments of the present invention includes a method of assembling a chip scale package (CSP). The method comprises adding bumps, sawing the saw streets from the front of a wafer, molding the front of the wafer, grinding the back of the wafer, sawing the saw streets from the back of the wafer, molding the back of the wafer, and sawing between devices to form a plurality of packaged devices. Sawing the saw streets from the front of the wafer establishes a first cut. Molding the front of the wafer includes using a first mold compound such that the mold compound fills in the first cut. Sawing the saw streets from the back of the wafer establishes a second cut. | 08-27-2009 |
20090246909 | Semiconductor device and method of manufacturing the same - In a semiconductor device, via holes are formed around a chip buried in a package, one end of a conductor filled in the via hole is covered with a pad portion exposed to the outside, and a wiring layer connected to the other end of the conductor is formed. The portion (pad portion) of the wiring layer which correspond to the conductor is exposed from a protective film, or an external connection terminal is bonded to the top of the pad portion. Electrode terminals of the chip are connected to the wiring layer, and the opposite surface of the chip is exposed to the outside. | 10-01-2009 |
20090263935 | RECYCLING FAULTY MULTI-DIE PACKAGES - The present invention teaches the recycling of a faulty multi-die memory package by isolating the functional part of the package and using it as a smaller memory package. | 10-22-2009 |
20090275170 | LOW TEMPERATURE HERMETIC BONDING AT WATER LEVEL AND METHOD OF BONDING FOR MICRO DISPLAY APPLICATION - A spatial light modulator is fabricated by bonding a capping layer over a wafer bearing active reflecting surfaces utilizing a low temperature bonding agent capable of providing a hermetic seal, such as a glass frit. The low temperature bonding agent may be B-stage cured after application to the capping layer, prior to any exposure to the substrate bearing the reflecting surfaces. In accordance with one embodiment of the present invention, the capping layer may comprise a glass wafer pre-bonded with an interposer spacer layer to provide sufficient stand-off between the capping layer and the underlying reflecting structures. In accordance with an alternative embodiment of the present invention, the capping layer may comprise a glass wafer alone, and the bonding agent may include additional materials such as beads or balls to provide the necessary stand-off between the capping layer and the underlying reflective structures. | 11-05-2009 |
20090286353 | Apparatus and Methods for Packaging Electronic Devices for Optical Testing - Apparatus and methods are provided for packaging IC (integrated circuit) chips to enable both optical access to the back side of an IC chip and electrical access to the front side of the IC chip. | 11-19-2009 |
20090311826 | ASSEMBLY INCLUDING PLURAL THROUGH WAFER VIAS, METHOD OF COOLING THE ASSEMBLY AND METHOD OF FABRICATING THE ASSEMBLY - An assembly includes a chip including an integrated circuit, a casing including an integrated circuit and having an upper portion formed on a side of the chip and lower portion formed on another side of the chip, plural through-wafer vias (TWVs) for electrically connecting the integrated circuit of the chip and the integrated circuit of the casing, and a card connected to the casing for electrically connecting the casing to a system board. | 12-17-2009 |
20090325342 | METHOD OF FABRICATING STACKED SEMICONDUCTOR PACKAGE WITH LOCALIZED CAVITIES FOR WIRE BONDING - A method of fabricating a semiconductor die and a low profile semiconductor package are disclosed. The semiconductor package may include at least first and second stacked semiconductor die mounted to a substrate. The first and/or second semiconductor die may be fabricated with localized cavities through a bottom surface of the semiconductor die, along a side edge of the semiconductor die. The one or more localized cavities in a side take up less than the entire side. Thus, the localized cavities allow low height stacking of semiconductor die while providing each die with a high degree of structural integrity to prevent cracking or breaking of the die edge during fabrication. | 12-31-2009 |
20100003784 | METHOD FOR MOUNTING ELECTRONIC COMPONENT ON PRINTED CIRCUIT BOARD - A method for assembling an electronic component on a printed circuit board includes following steps. Firstly, a printed circuit board substrate including a central main portion and a peripheral unwanted portion is provided. Secondly, electrically conductive patterns and reinforcing patterns are formed on the main portion and the unwanted portion respectively. Thirdly, an electronic component is mounted on the main portion and electrically connected with the electrically conductive patterns. Fifthly, the unwanted portion is removed. | 01-07-2010 |
20100022050 | Standoff Height Improvement for Bumping Technology Using Solder Resist - A semiconductor device is made by disposing a film layer over a substrate having first conductive layer. An opening is formed in the film layer to expose the first conductive layer. A second conductive layer is formed over the first conductive layer. A first bump is formed over the second conductive layer which promotes reflow of the first bump at a eutectic temperature. A standoff bump is formed on the film layer around a perimeter of the substrate. The film layer prevents reflow of the standoff bump at the eutectic temperature. A second bump is disposed between a semiconductor die and the first bump. The second bump is reflowed to electrically connect the semiconductor die to the first bump. After reflow of the second bump, the standoff bump has a height at least 70% of the second bump prior to reflow to maintain separation between the semiconductor die and substrate. | 01-28-2010 |
20100047961 | Placement Of An Integrated Circuit - Disclosed herein is a method of positioning and placing an integrated circuit on a printed circuit board. The integrated circuit comprises first geometrical elements. The first geometrical elements are of one or more predefined shapes and are located on one or more predefined surfaces of the integrated circuit. The printed circuit board comprises second geometrical elements. The second geometrical elements are shaped to accommodate the first geometrical elements. The first geometrical elements are designed to fit into the second geometrical elements. The first geometrical elements are positioned and placed over the second geometrical elements. The first geometrical elements come in contact with the second geometrical elements at two or more points. The positioning and placement of the first geometrical elements over the second geometrical elements limits displacement of connections of the integrated circuit from the printed circuit board. | 02-25-2010 |
20100062563 | METHOD OF MANUFACTURING A STACKED DIE MODULE - A method of manufacturing a stacked die module includes applying a plurality of stacked die structures to a carrier. Each stacked die structure includes a first semiconductor die applied to the carrier and a second semiconductor die stacked over the first semiconductor die. The second semiconductor die has a larger lateral surface area than the first semiconductor die. A dam is applied around each of the stacked die structures, thereby forming an enclosed cavity for each of the stacked die structures. The enclosed cavity for each stacked die structure surrounds the first semiconductor die of the stacked die structure. | 03-11-2010 |
20100062564 | METHOD FOR PRODUCING ELECTRONIC PART PACKAGE - A peeling off layer | 03-11-2010 |
20100075459 | THERMAL BARRIER LAYER FOR INTEGRATED CIRCUIT MANUFACTURE - Exemplary embodiments provide methods and systems for assembling electronic devices, such as integrated circuit (IC) chips, by selectively and scalably embedding or seating IC elements onto/into a receiving substrate, such as a chip substrate. Preparing of the chip substrate can be performed by depositing or patterning an activatable thermal barrier material on a surface of the substrate. The IC chips are secured on the prepared substrate by activating the thermal barrier material between the chip substrate and IC chips. Securing can include softening of the chip substrate with the activated thermal barrier material to an amount suitable for embedding the IC chips. Securing can also include adhesively bonding the IC chips to the substrate with the activated thermal barrier material in the case of a non-pliable substrate. | 03-25-2010 |
20100099219 | MITIGATION OF PLATING STUB RESONANCE BY CONTROLLING SURFACE ROUGHNESS - Plating stub resonance in a circuit board may be mitigated by increasing surface roughness of the plating stub conductor. Roughening the plating stub increases its resistance due to the skin effect at higher frequencies, which decreases the quality factor of the transmission line and consequently increases the damping factor, to reduce any resonance that would occur in the plating stub as formed prior to roughening. The surface roughness can be increased in a variety of ways, including chemical processes, by selectively applying a laser beam, or by applying an etch-resistance material in selected locations. | 04-22-2010 |
20100120198 | METHOD AND ARTICLE OF MANUFACTURE FOR WIRE BONDING WITH STAGGERED DIFFERENTIAL WIRE BOND PAIRS - A method and article of manufacture for performing wire-bonding operations in an integrated circuit. In one aspect, the operations include the steps of bonding a wire to a first bond site in the integrated circuit and terminating the wire at a second bond site. The bonding and terminating steps are repeated for at least two differential wire bond pairs, and proximate differential wire bond pairs of the at least two differential wire bond pairs have substantially different wire bond profiles. | 05-13-2010 |
20100129959 | Semiconductor Chip Package Fixture - Various methods and apparatus for holding a semiconductor chip package are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first plate adapted to hold a semiconductor chip package. The semiconductor chip package includes a carrier substrate and at least one semiconductor chip coupled to the carrier substrate. A second plate is formed with a first opening defining an interior peripheral surface adapted to compress an outer edge of the carrier substrate between the first plate and the second plate without engaging the at least one semiconductor chip. | 05-27-2010 |
20100323474 | METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SUBSTRATE FOR THE SEMICONDUCTOR PACKAGE - A method of manufacturing a semiconductor package, includes the steps of: forming a substrate on which a semiconductor chip is to be mounted; and mounting the semiconductor chip on the substrate through connection bumps, the substrate forming step including a first step of forming a plurality of electrode pads to be bonded to the connection bumps on a part of a support plate, a second step of forming one or more wiring layers on the support plate including the electrode pads with an insulation layer interposed between them, thereby forming a substrate having the electrode pads formed thereon on one side thereof, and a third step of removing the substrate from the support plate, wherein a plurality of first convex portions are formed on the support plate prior to the first step, and the electrode pads are formed on the first convex portions at the first step. | 12-23-2010 |
20100330740 | METHOD AND APPARATUS PROVIDING INTEGRATED CIRCUIT HAVING REDISTRIBUTION LAYER WITH RECESSED CONNECTORS - A method of making a semiconductor die includes forming a trench around a conductive stud extending from the first side to a second side of a substrate to expose a portion of the stud and then forming a conductive layer inside the trench and in electrical contact with the stud. | 12-30-2010 |
20110027941 | METHOD OF FORMING MONOLITHIC CMOS-MEMS HYBRID INTEGRATED, PACKAGED STRUCTURES - A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing a semiconductor substrate with pre-fabricated cmos circuits on the front side and a polished back-side with through substrate conductive vias; forming at least one opening in the polished backside of the semiconductor substrate by appropriately protecting the front-side; applying at least one filler material in the at least one opening on the semiconductor substrate; positioning at least one prefabricated mems, nems or cmos chip on the filler material, the chip including a front face and a bare back face with the prefabricated mems/nems chips containing mechanical and dielectric layers; applying at least one planarization layer overlying the substrate, filler material and the chip; forming at least one via opening on a portion of the planarization layer interfacing pads on the chip and the through substrate conductive vias; applying at least one metallization layer overlying the planarization layer on the substrate and the chip connecting the through substrate conductive vias to the at least one chip; applying at least one second insulating layer overlying the metallization layer; performing at least one micro/nano fabrication etching step to release the mechanical layer on the prefabricated mems/nems chips; positioning protective cap to package the integrated device over the mems/nems device area on the pre-fabricated chips. | 02-03-2011 |
20110092018 | WAFER LEVEL PACKAGED MEMS DEVICE - An apparatus and method for sensor architecture based on bulk machining of silicon wafers and fusion bond joining which provides a nearly all-silicon, hermetically sealed, microelectromechanical system (MEMS) device. An example device includes a device sensor mechanism formed in an active semiconductor layer and separated from a handle layer by a dielectric layer, and a silicon cover plate having a handle layer with a dielectric layer being bonded to portions of the active layer. Pit are included in one of the handle layers and corresponding dielectric layers to access electrical leads on the active layer. Another example includes set backs from the active components formed by anisotropically etching the handle layer while the active layer has been protectively doped. | 04-21-2011 |
20110092019 | Method for Stacked Contact with Low Aspect Ratio - A method for an integrated circuit structure includes providing a semiconductor substrate; forming a metallization layer over the semiconductor substrate; forming a first dielectric layer between the semiconductor substrate and the metallization layer; forming a second dielectric layer between the semiconductor substrate and the metallization layer, wherein the second dielectric layer is over the first dielectric layer; and forming a contact plug with an upper portion substantially in the second dielectric layer and a lower portion substantially in the first dielectric layer. The contact plug is electrically connected to a metal line in the metallization layer. The contact plug is discontinuous at an interface between the upper portion and the lower portion. | 04-21-2011 |
20110092020 | METHOD FOR PRODUCING ELECTRONIC PART PACKAGE - A peeling off layer | 04-21-2011 |
20110097845 | Method and Apparatus for Packaging Circuit Devices - A hermetically sealed package includes a lid ( | 04-28-2011 |
20110136296 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method for manufacturing a semiconductor device. The method includes: providing a first substrate where an active layer is formed on a buried insulation layer; forming a gate insulation layer on the active layer; forming a gate electrode on the gate insulation layer; forming a source/drain region on the active layer at both sides of the gate electrode; exposing the buried insulation layer around a thin film transistor (TFT) including the gate electrode and the source/drain region; forming an under cut at the bottom of the TFT by partially removing the buried insulation layer; and transferring the TFT on a second substrate. | 06-09-2011 |
20110151620 | METHOD FOR MANUFACTURING CHIPS - A method for manufacturing chips ( | 06-23-2011 |
20110171776 | IC CHIP, ANTENNA, AND MANUFACTURING METHOD OF THE IC CHIP AND THE ANTENNA - An antenna used for an ID chip or the like is disclosed with planarized antenna unevenness and an IC chip having such the antenna with a flat surface is disclosed. Manufacturing an integrated circuit mounted with an antenna is facilitated. A laminated body formed by stacking a conductive film | 07-14-2011 |
20110195543 | FLIP-CHIP ASSEMBLY WITH ORGANIC CHIP CARRIER HAVING MUSHROOM-PLATED SOLDER RESIST OPENING - Disclosed are embodiments of a flip-chip assembly and method using lead-free solder. This assembly incorporates mushroom-plated metal layers that fill and overflow solder resist openings on an organic laminate substrate. The lower portion of metal layer provides structural support to its corresponding solder resist opening. The upper portion (i.e., cap) of each metal layer provides a landing spot for a solder joint between an integrated circuit device and the substrate and, thereby, allows for enhanced solder volume control. The additional structural support, in combination with the enhanced solder volume control, minimizes strain on the resulting solder joints. Additionally, the cap further allows the minimum diameter of the solder joint on the substrate-side of the assembly to be larger than the diameter of the solder resist opening. Thus, the invention decouples C4 reliability concerns from laminate design concerns and, thereby, allows for greater design flexibility. | 08-11-2011 |
20110212572 | SEMICONDUCTOR DEVICE SUPPORT FOR BONDING - In one embodiment, a support structure comprises a base, a compliant layer, and a protective layer which is used to secure a semiconductor device, such as a lead-frame, to a window clamp during a bonding process. The compliant layer distributes even loading over the surface of the semiconductor device while clamped. In other embodiments, the compliant layer may be segmented into individual portions corresponding with openings in the window clamp. The window clamp may also have a compliant layer and a protective layer and may be used with or without a compliant layer on the support structure. Features on the protective layer may be included to support structures of the semiconductor device. | 09-01-2011 |
20110275176 | Method of Assembly and Assembly Thus Made - An assembly ( | 11-10-2011 |
20120003791 | Method for Packaging Electronic Devices and Integrated Circuits - The present invention relates to the field of electronic devices and their associated driver and/or controller integrated circuits and in particular to the mechanical packaging of electronic devices and to the packaging of electronic devices and their associated driver and/or controller integrated circuits. | 01-05-2012 |
20120034738 | SEMICONDUCTOR PACKAGE AND METHOD OF ATTACHING SEMICONDUCTOR DIES TO SUBSTRATES - A method of mounting a semiconductor die on a substrate with a solder mask on a first surface includes placing a die on the solder mask, and mounting the die to the substrate by applying pressure and heat. The applied pressure ranges from a bond force of approximately 5 to 10 Kg, the heat has a temperature range from approximately 150 to 200° C. and the pressure is applied for a range of approximately 1 to 10 seconds. | 02-09-2012 |
20120064666 | MANUFACTURING METHOD OF SUBSTRATE FOR A SEMICONDUCTOR PACKAGE, MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE, SUBSTRATE FOR A SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE - A manufacturing method of a substrate for a semiconductor package includes a resist layer forming step to form a resist layer on a surface of a conductive substrate; an exposure step to expose the resist layer using a glass mask with a mask pattern including a transmission area, a light shielding area, and an intermediate transmission area, wherein transmittance of the intermediate transmission area is lower than that of the transmission area and is higher than that of the light shielding area; a development step to form a resist pattern including a hollow with a side shape including a slope part decreasing in hollow circumference as the hollow circumference approaches the substrate; and a plating step to plate on an exposed area to form a metal layer with a side shape including a slope part decreasing in circumference as the circumference approaches the substrate. | 03-15-2012 |
20120077310 | Manufacturing Method of Semiconductor Device - Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device. | 03-29-2012 |
20120135564 | SOFT ERROR RATE MITIGATION BY INTERCONNECT STRUCTURE - A method creates a structure that comprises a carrier connected to an integrated circuit chip by pillars and openings. Thus, in this structure, at least one conductive pillar extends a distance or height from the surface of the integrated circuit chip and a barrier surrounds the lower portion of the conductive pillar such that the barrier covers at least some portion of the height of the pillar that is closest to the chip surface. There is at least one opening in the carrier that is large enough to accommodate the conductive pillar and the barrier, and the conductive pillar and the barrier are positioned in opening. A solder is used in the bottom of the opening to connect the conductive pillar to the bottom of the opening. The barrier prevents the solder from contacting the portion of the conductive pillar protected by the barrier. | 05-31-2012 |
20120164787 | VACUUM WAFER LEVEL PACKAGING METHOD FOR MICRO ELECTRO MECHANICAL SYSTEM DEVICE - Disclosed is a vacuum wafer level packaging method for a micro electro mechanical system device, including: forming a plurality of via holes on an upper wafer for protecting a micro electro mechanical system (MEMS) wafer; forming at least one metal layer on inner walls of the plurality of via holes and regions extended from the plurality of via holes; arranging and bonding the upper wafer and the MEMS wafer at atmospheric pressure; applying solder paste to the regions extended from the plurality of via holes; filling a solder in the plurality of via holes by increasing the temperature of a high-vacuum chamber to melt the solder paste; and changing the solder in the plurality of via holes to a solid state by lowering the temperature of the high-vacuum chamber. | 06-28-2012 |
20120184067 | Releasing and post-releasing processes in fabrications for micromirror array devices - A releasing and post-releasing method for making a micromirror device and a micromirror array device are disclosed herein. The releasing method removes the sacrificial materials in the micromirror and micromirror array so as to enabling movements of the movable elements in the micromirror and micromirror array device. The post-releasing method is applied to improve the performance and quality of the released micromirrors and micromirror array devices. | 07-19-2012 |
20120202319 | MOLD APPARATUS AND METHOD - An apparatus and method for producing an article by molding is disclosed. In one embodiment, the method includes a mold with an upper part, a lower part and at least one mold cavity, and has a vacuum clamping ring with a least one closable vent, which is arranged between the upper part and the lower part. The mold cavity is at least partially filled with a mold material. The vent is closed, and the mold cavity is filled with a thermoplastic or thermoset material. | 08-09-2012 |
20120225521 | BOARD ON CHIP PACKAGE SUBSTRATE AND MANUFACTURING METHOD THEREOF - A single-layer board on chip package substrate and a method of manufacturing the same are disclosed. The single-layer board on chip package substrate in accordance with an embodiment of the present invention includes an insulator, which has a window perforated therethrough, a wiring pattern, a wire bonding pad and a solder ball pad, which are embedded in one surface of the insulator, and a solder resist layer, which is formed on the one surface of the insulator such that the solder resist layer covers the wiring pattern but at least portions of the wire bonding pad and the solder ball pad are exposed. | 09-06-2012 |
20120258570 | SUBSTRATE PROCESSING APPARATUS, PROGRAM FOR CONTROLLING THE SAME, AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A substrate processing apparatus includes a mounting stand, a cover opening and closing unit, a substrate checking unit, a substrate transfer mechanism, a substrate processing unit, and a controller. While the substrate processing unit is processing a substrate within a first substrate accommodation container mounted on the mounting stand, when a second substrate accommodation container is mounted on the mounting stand, the controller provides control to open the cover of a second substrate accommodation container and check a substrate within the second substrate accommodation container by means of the substrate checking unit, and when the substrate checking is terminated, the controller provides control to close the cover of the second substrate accommodation container. | 10-11-2012 |
20120276689 | Glass Wafers for Semiconductor Fabrication Processes and Methods of Making Same - The present disclosure is directed to the use of glass wafers as carriers, interposers, or in other selected applications in which electronic circuitry or operative elements, such as transistors, are formed in the creation of electronic devices. The glass wafers generally include a glass having a coefficient of thermal expansion equal to or substantially equal to a coefficient of thermal expansion of semiconductor silicon, an indexing feature, and a coating on at least a portion of one face of the glass. | 11-01-2012 |
20130059415 | FILM DEPOSITION APPARATUS, FILM DEPOSITION METHOD AND STORAGE MEDIUM - A film deposition apparatus includes a turntable having a substrate mounting area, a first plasma gas supplying part, a second plasma supplying part, a first plasma gas generating part to convert the first plasma generating gas to first plasma, and a second plasma generating part provided away from the first plasma generating part in a circumferential direction and to convert the second plasma generating gas to second plasma. The first plasma generating part includes an antenna facing the turntable so as to convert the first plasma generating gas to the first plasma, and a grounded Faraday shield between the antenna and an area where a plasma process is performed, and to include plural slits respectively extending in directions perpendicular to the antenna and arranged along an antenna extending direction to prevent an electric field from passing toward the substrate and to pass a magnetic field toward the substrate. | 03-07-2013 |
20130084677 | METHOD OF FABRICATING A MEMORY CARD USING SIP/SMT HYBRID TECHNOLOGY - A portable memory card formed from a multi-die assembly, and methods of fabricating same, are disclosed. One such multi-die assembly includes an LGA SiP semiconductor package and a leadframe-based SMT package both affixed to a PCB. The multi-die assembly thus formed may be encased within a standard lid to form a completed portable memory card, such as a standard SDTM card. Test pads on the LGA SiP package, used for testing operation of the package after it is fabricated, may also be used for physically and electrically coupling the LGA SiP package to the PCB. | 04-04-2013 |
20130095607 | Methods and Apparatus For Alignment In Flip Chip Bonding - Methods and apparatus for alignment in a flip chip bonding. A method includes attaching an integrated circuit having connector terminals to a bonding arm, the bonding arm having a chuck for attaching the integrated circuit at the backside surface, the bonding arm having a plurality of CCD imagers mounted thereon; receiving a substrate having pads corresponding to the connector terminals; using the bonding arm, positioning the integrated circuit proximal to the substrate; aligning the integrated circuit connector terminals with the pads on the substrate using the CCD imagers on the bonding arm; positioning the connector terminals in contact with the pads on the substrate; and performing a solder reflow to attach the integrated circuit to the substrate. An apparatus includes a bonding arm with a chuck for carrying a component and CCD imagers mounted on the arm for alignment. | 04-18-2013 |
20130115734 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING FACE-TO-FACE SEMICONDUCTOR DICE - Methods of manufacturing semiconductor device assemblies include attaching a back side of a first semiconductor die to a substrate and structurally and electrically coupling a first end of laterally extending conductive elements to conductive terminals on or in a surface of the substrate. Second ends of the laterally extending conductive elements are structurally and electrically coupled to bond pads on or in an active surface of the first semiconductor die. Conductive structures are structurally and electrically coupled to bond pads of a second semiconductor die. At least some of the conductive structures are aligned with at least some of the bond pads of the first semiconductor die. An active surface of the second semiconductor die faces an active surface of the first semiconductor die. At least some of the conductive structures are structurally and electrically coupled to at least some of the bond pads of the first semiconductor die. | 05-09-2013 |
20130130439 | FORMED METALLIC HEAT SINK SUBSTRATE, CIRCUIT SYSTEM, AND FABRICATION METHODS - A thermally conductive substrate for suitable for use as a three dimensional heat sink for electrical device systems. The substrate comprises a base element with a cavity comprising a recessed device mounting site. Associated device systems include one or more devices arranged in the three dimensional heat sink which can be encapsulated into a device package and associated construction methodologies. | 05-23-2013 |
20130189812 | COAXIAL PLATED THROUGH HOLES (PTH) FOR ROBUST ELECTRICAL PERFORMANCE - In some embodiments, coaxial plated through holes (PTH) for robust electrical performance are presented. in this regard, an apparatus is introduced comprising an integrated circuit device and a substrate coupled with the integrated circuit device, wherein the substrate includes: a plated through hole, the plated through hole filled with dielectric material and a coaxial copper wire, and conductive traces to separately route the plated through hole and the coaxial copper wire. Other embodiments are also disclosed. | 07-25-2013 |
20130224909 | PROCESS OF FORMING THROUGH-SILICON VIA STRUCTURE - In a process, an opening is formed to extend from a front surface of a semiconductor substrate through at least a part of the semiconductor substrate. A metal seed layer is formed on a sidewall of the opening. A metal silicide layer is formed on at least one portion of the metal seed layer. A metal layer is formed on the metal silicide layer and the metal seed layer to fill the opening. | 08-29-2013 |
20130252374 | SEMICONDUCTOR PACKAGING METHOD AND STRUCTURE THEREOF - A semiconductor packaging method includes providing a substrate having a plurality of pads, each of the pads comprises a first coupling surface having a plurality of first conductive contact areas and a plurality of first non-conductive contact areas; forming a conductible gel with anti-dissociation function on the substrate, said conductible gel includes a plurality of conductive particles and a plurality of anti-dissociation substances; mounting a chip on the substrate, said chip comprises a plurality of copper-containing bumps, each of the copper-containing bumps comprises a ring surface and a second coupling surface having a plurality of second conductive contact areas and a plurality of second non-conductive contact areas, wherein the conductive particles are electrically connected with the first conductive contact areas and the second conductive contact areas, said anti-dissociation substances are in contact with the second non-conductive contact area, and the ring surfaces are covered with the anti-dissociation substances. | 09-26-2013 |
20130267062 | Dispensing Tool - A dispensing tool includes a dispensing outlet for depositing a specific amount of a mounting material on a carrier when the dispensing outlet is at a predetermined dispensing distance from the carrier. The dispensing tool also includes a protrusion element protruding past the dispensing outlet by spanning the dispensing distance between dispensing outlet and carrier during dispensing. | 10-10-2013 |
20130316494 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - An embodiment of the invention provides a chip package, which includes: a substrate having an upper surface and a lower surface; a passivation layer located overlying the upper surface of the substrate; a plurality of conducting pad structures disposed overlying the upper surface of the substrate, wherein at least portions of upper surfaces of the conducting pad structures are exposed; a plurality of openings extending from the upper surface towards the lower surface of the substrate; and a plurality of movable bulks located between the openings and connected with the substrate, respectively, wherein each of the movable bulks is electrically connected to one of the conducting pad structures. | 11-28-2013 |
20140024174 | USING AN OPTICALLY TRANSPARENT SOLID MATERIAL AS A SUPPORT STRUCTURE FOR ATTACHMENT OF A SEMICONDUCTOR MATERIAL TO A SUBSTRATE - Electronic devices and methods for fabricating electronic devices are described. One method includes attaching an optically transparent solid material to a body of semiconducting material in which microelectronic devices are formed. The method also includes attaching a first surface of a body portion, comprising a portion of the body, to a substrate while a portion of the optically transparent solid material is attached to a second surface of the body portion. The method also includes removing the optically transparent solid material from the second surface of the body portion after the attaching the first surface of the body portion to the substrate. | 01-23-2014 |
20140113409 | PACKAGE SUBSTRATE DYNAMIC PRESSURE STRUCTURE - Devices and methods for their formation, including electronic assemblies having a shape memory material structure, are described. In one embodiment, a device includes a package substrate and an electronic component coupled to the package substrate. The device also includes a shape memory material structure coupled to the package substrate. In one aspect of certain embodiments, the shape memory material structure is formed from a material selected to have a martensite to austenite transition temperature in the range of 50-300 degrees Celsius. In another aspect of certain embodiments, the shape memory material structure is positioned to extend around a periphery of the electronic component. Other embodiments are described and claimed. | 04-24-2014 |
20140127856 | Electronic Assembly with Three Dimensional Inkjet Printed Traces - One method of making an electronic assembly includes mounting one electrical substrate on another electrical substrate with a face surface on the one substrate oriented transversely of a face surface of the other substrate. The method also includes inkjet printing on the face surfaces a conductive trace that connects an electrical contact on the one substrate with an electrical connector on the other substrate. An electronic assembly may include a first substrate having a generally flat surface with a first plurality of electrical contacts thereon; a second substrate having a generally flat surface with a second plurality of electrical contacts thereon, the surface of the second substrate extending transversely of the surface of said first substrate; and at least one continuous conductive ink trace electrically connecting at least one of the first plurality of electrical contacts with at least one of the second plurality of electrical contacts. | 05-08-2014 |
20140179059 | PACKAGE-LEVEL INTEGRATED CIRCUIT CONNECTION WITHOUT TOP METAL PADS OR BONDING WIRE - An integrated circuit method is provided with package-level connectivity, between internal electronic circuitry thereof and contact points on a package substrate thereof, without requiring top metal pads or bonding wires. | 06-26-2014 |
20140186999 | WAFER LEVEL PACKAGING OF MICROBOLOMETER VACUUM PACKAGE ASSEMBLIES - An apparatus for the wafer level packaging (WLP) of micro-bolometer vacuum package assemblies (VPAs), in one embodiment, includes a wafer alignment and bonding chamber, a bolometer wafer chuck and a lid wafer chuck disposed within the chamber in vertically facing opposition to each other, means for creating a first ultra-high vacuum (UHV) environment within the chamber, means for heating and cooling the bolometer wafer chuck and the lid wafer chuck independently of each other, means for moving the lid wafer chuck in the vertical direction and relative to the bolometer wafer chuck, means for moving the bolometer wafer chuck translationally in two orthogonal directions in a horizontal plane and rotationally about a vertical axis normal to the horizontal plane, and means for aligning a fiducial on a bolometer wafer held by the bolometer wafer chuck with a fiducial on a lid wafer held by the lid wafer chuck. | 07-03-2014 |
20140193948 | INTEGRATED BONDLINE SPACERS FOR WAFER LEVEL PACKAGED CIRCUIT DEVICES - A method of forming a wafer level packaged circuit device includes forming a device wafer, the device wafer including a first group of one or more material layers left remaining in a first region of a substrate of the device wafer; and forming a cap wafer configured to be attached to the device wafer, the cap wafer including a second group of one or more material layers left remaining in a second region of a substrate of the cap wafer; wherein a combined thickness of the first and second groups of one or more material layers defines an integrated bond gap control structure upon bonding of the device wafer and the cap wafer. | 07-10-2014 |
20140193949 | SOCKET TYPE MEMS BONDING - A method for fabricating an integrated circuit device is disclosed. The method includes providing a first substrate; bonding a second substrate to the first substrate, the second substrate including a microeelectromechanical system (MEMS) device; and bonding a third substrate to the first substrate. | 07-10-2014 |
20140193950 | ELECTRONIC DEVICE PACKAGE AND FABRICATION METHOD THEREOF - An electronic device package is disclosed. The package includes at least one semiconductor chip having a first surface and a second surface opposite thereto, in which at least one redistribution layer is disposed on the first surface of the semiconductor chip and is electrically connected to at least one conductive pad structure. At least one abut portion is disposed on the redistribution layer and electrically contacting thereto. A passivation layer covers the first surface of the semiconductor chip and surrounds the abut portion. A substrate is attached onto the second surface of the semiconductor chip. A fabrication method of the electronic device package is also disclosed. | 07-10-2014 |
20140235016 | METHOD OF FABRICATING SEMICONDUCTOR PACKAGE - Provided is a method of fabricating a semiconductor package, including preparing a die including a first metal layer and a second metal layer which are sequentially stacked on a silicon substrate, preparing a package substrate including a lead frame, and forming an adhesive layer between the lead frame and the first metal layer and attaching the die to the package substrate, wherein the forming of the adhesive layer is performed by eutectic bonding between the silicon substrate and the second metal layer. According to the semiconductor package according to an embodiment of the present invention, an adhesive layer can be easily formed by eutectic bonding without a process of forming a preform. | 08-21-2014 |
20150037936 | Strength of Micro-Bump Joints - A device includes a work piece including a metal bump; and a dielectric layer having a portion directly over the metal bump. The metal bump and a surface of the portion of the dielectric layer form an interface. A metal finish is formed over and contacting the metal bump. The metal finish extends from over the dielectric layer to below the interface. | 02-05-2015 |
20150072473 | DIE ATTACHMENT APPARATUS AND METHOD UTILIZING ACTIVATED FORMING GAS - A die attachment apparatus for attaching a semiconductor die onto a substrate having a metallic surface comprises a material dispensing station for dispensing a bonding material onto the substrate and a die attachment station for placing the semiconductor die onto the bonding material which has been dispensed onto the substrate. An activating gas generator positioned before the die attachment station introduces activated forming gas onto the substrate in order to reduce oxides on the substrate. | 03-12-2015 |
20150118791 | METHOD FOR TREATING A BOND PAD OF A PACKAGE SUBSTRATE - A method of making a package substrate having a copper bond pad and a location for receiving a semiconductor die having a remnant of one of a group consisting of HEDP and an HEDP derivative on a top surface of the copper bond pad. The semiconductor die is attached to the substrate. A wirebond connection is attached between the remnant and the semiconductor die. | 04-30-2015 |
20150132888 | METHODS OF FORMING WIRE INTERCONNECT STRUCTURES - A method of forming a wire interconnect structure includes the steps of: (a) forming a wire bond at a bonding location on a substrate using a wire bonding tool; (b) extending a length of wire, continuous with the wire bond, to another location; (c) pressing a portion of the length of wire against the other location using the wire bonding tool; (d) moving the wire bonding tool, and the pressed portion of the length of wire, to a position above the wire bond; and (e) separating the length of wire from a wire supply at the pressed portion, thereby providing a wire interconnect structure bonded to the bonding location. | 05-14-2015 |
20150325548 | DEVICES AND METHODS FOR PROCESSING SINGULATED RADIO-FREQUENCY UNITS - Devices and methods for processing singulated radio-frequency (RF) units. In some embodiments, a device for processing singulated RF packages can include a plate having a plurality of apertures. Each aperture can be dimensioned to receive and position a singulated RF package to thereby facilitate processing of the singulated RF packages positioned in their respective apertures. In some embodiments, such a device can be utilized to batch process high volume of RF packages as if the RF packages are still in a panel format. | 11-12-2015 |
20150333032 | BONDING TOOL COOLING APPARATUS AND METHOD FOR COOLING BONDING TOOL - A bonding tool cooling apparatus ( | 11-19-2015 |
20160027648 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device including a semiconductor chip having a front surface electrode and a rear surface electrode provided on a front surface and a rear surface, respectively, the method includes a front surface electrode layer forming step of forming a front surface electrode layer as the front surface electrode on a front surface of a semiconductor wafer forming the semiconductor chip; a thinning step of grinding a rear surface of the semiconductor wafer to reduce a thickness of the semiconductor wafer after the front surface electrode layer forming step; a plating step of forming an electrode plating film as the front surface electrode on a surface of the front surface electrode layer after the thinning step; and a rear surface electrode forming step of forming the rear surface electrode on the ground rear surface of the semiconductor wafer after the plating step. | 01-28-2016 |
20160049315 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A conventional semiconductor device used for a power supply circuit such as a DC/DC converter has problems of heat dissipation and downsizing, in particular has the problems of heat dissipation and others in the event of downsizing. A semiconductor device has a structure formed by covering a principal surface of a semiconductor chip having the principal surface and a plurality of MIS type FETs formed over the principal surface with a plurality of metal plate wires having pectinate shapes; allocating the pectinate parts alternately in a planar view over the principal surface; and further electrically coupling the plural metal plate wires to a plurality of terminals. | 02-18-2016 |
20160049376 | METHOD FOR FABRICATING PACKAGE STRUCTURE - A method for fabricating a package structure is provided, which includes the steps of: providing an encapsulant encapsulating at least an electronic element; forming a shaping layer on a surface of the encapsulant, wherein the shaping layer has at least an opening exposing a portion of the surface of the encapsulant; forming at least a through hole corresponding in position to the opening and penetrating the encapsulant; and forming a conductor in the through hole. The shaping layer facilitates to prevent deformation of the through hole. | 02-18-2016 |
20160141186 | DECAPSULATION METHOD AND DECAPSULATION SYSTEM FOR PLASTIC MOLDED IC PACKAGE - A plastic mold decapsulation method and decapsulation system is provided for decapsulating a semiconductor device molded by plastic. A plastic mold decapsulation method and decapsulation system for decapsulating a plastic molded semiconductor device includes decapsulating the molded semiconductor device using a solution having dissolved metal in a liquid including acid. In this way, it is possible to prevent damage to the metal used in a package such as a bonding wire by a solution used in decapsulation. | 05-19-2016 |
20160167959 | HERMETICALLY SEALED PACKAGE HAVING STRESS REDUCING LAYER | 06-16-2016 |