Entries |
Document | Title | Date |
20080199988 | CONDUCTIVE PATTERN FORMATION METHOD - The objective of the present invention is to offer a method for forming a conductive pattern on a substrate and solder protrusions on the conductive pattern. The pitch of the conductive pattern corresponds to the pitch of electrodes on a semiconductor chip. | 08-21-2008 |
20080206928 | SOLDERING METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING SOLDERING METHOD - A soldering method of soldering first and second members includes shooting a laser light to at least one part of an outer peripheral portion surrounding a soldering-target region of the first member thereby to form an oxide film, and bonding the second member with the soldering-target region through a solder. According to the method, the solder resist is never exfoliated even after cleaning with chemicals for removing flux residues contained in solder. | 08-28-2008 |
20080280399 | Methods for Forming Co-Planar Wafer-Scale Chip Packages - Economical methods for forming a co-planar multi-chip wafer-level packages are proposed. Partial wafer bonding and partial wafer dicing techniques are used to create chips as well as pockets. The finished chips are then mounted in the corresponding pockets of a carrier substrate, and global interconnects among the chips are formed on the top planar surface of the finished chips. The proposed methods facilitate the integration of chips fabricated with different process steps and materials. There is no need to use a planarization process such as chemical-mechanical polish to planarize the top surfaces of the chips. Since the chips are precisely aligned to each other and all the chips are mounted facing up, the module is ready for global wiring, which eliminates the need to flip the chips from an upside-down position. | 11-13-2008 |
20090215231 | METHOD OF MANUFACTURING ELECTRONIC COMPONENT BUILT-IN SUBSTRATE - In a method of manufacturing an electronic component built-in substrate of the present invention, a mounted body including a first insulating layer, a stopper metal layer formed under the first insulating layer of a portion corresponding to a component mounting region and a second insulating layer formed on a lower surface of the first insulating layer and covering the stopper metal layer is prepared, and a concave portion is obtained by penetration-processing a portion of the first insulating layer, which corresponds to the component mounting region to form an opening portion, while using the stopper metal layer as a stopper. Also, the stopper metal layer in the concave portion is removed, then an electronic component is mounted on the concave portion, and then a third insulating layer is formed on the electronic component. | 08-27-2009 |
20090280604 | Heat radiation structure of semiconductor device, and manufacturing method thereof - The invention of the present application provides a heat radiation structure of a semiconductor device, comprising a substrate having, on a surface thereof, a first area on which the semiconductor device is mounted, and a second area which surrounds the first area, and the semiconductor device which has a first surface and a second surface opposite to the first surface and is formed with a plurality of terminals provided on the first surface, wherein the semiconductor device is mounted on the substrate in such a manner that the first surface is opposite to the surface of the substrate, and wherein a first heat radiating film is formed on the second area of the substrate, and a second heat radiating film is formed on the second surface of the semiconductor device with being spaced away from the first heat radiating film. | 11-12-2009 |
20090305467 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An object is to provide a highly reliable semiconductor device that is reduced in thickness and size and has tolerance to external stress and electrostatic discharge. Another object is to prevent defective shapes and defective characteristics due to the external stress or an electrostatic discharge in the manufacturing process, and to manufacture a semiconductor device with high yield. Still another object is to manufacture a semiconductor device at low cost and with high productivity. With the use of a conductive shield covering a semiconductor integrated circuit, electrostatic breakdown (malfunctions of the circuit or damages of a semiconductor element) due to electrostatic discharge of the semiconductor integrated circuit is prevented. The conductive shield is formed so that at least the conductive shields on the top and bottom surfaces are electrically connected by a plating method. In addition, a semiconductor device can be formed at low cost with high productivity because a plating method is used for the formation of the conductive shield. | 12-10-2009 |
20100068854 | MEMS Switch Capping and Passivation Method - A MEMS switch with a platinum-series contact is capped through a process that also passivates the contact by controlling, over time, the amount of oxygen in the environment, pressures and temperatures. Some embodiments passivate a contact in an oxygenated atmosphere at a first temperature and pressure, before hermetically sealing the cap at a higher temperature and pressure. Some embodiments hermetically seal the cap at a temperature below which passivating dioxides will form, thus trapping oxygen within the volume defined by the cap, and later passivate the contact with the trapped oxygen at a higher temperature. | 03-18-2010 |
20100330746 | METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - A method of manufacturing a semiconductor package, including at least a step A that forms a first transforming portion by irradiating a laser beam on at least a portion of a first substrate; a step B that joins together the first substrate and a second substrate in which a functional element is disposed; a step C that removes the first transforming portion that is disposed on the first substrate by etching; and a step D that forms a conductive portion in the first substrate by filling a conductive material in a portion where the first transforming portion has been removed. | 12-30-2010 |
20100330747 | Method of fabricating semiconductor plastic package - A method of fabricating a semiconductor plastic package can include: providing a core board, which includes at least one pad, and which has a coefficient of thermal expansion of 9 ppm/° C. or lower; stacking a build-up insulation layer over the core board; forming an opening by removing a portion of the build-up insulation layer such that the pad is exposed to the exterior; and placing a semiconductor chip in the opening and electrically connecting the semiconductor chip with the pad. This method can be utilized to provide higher reliability in the connection between the semiconductor chip and the circuit board. | 12-30-2010 |
20110027945 | SUBSTRATE FOR MOUNTING DEVICE AND METHOD FOR PRODUCING THE SAME, SEMICONDUCTOR MODULE AND METHOD FOR PRODUCING THE SAME, AND PORTABLE APPARATUS PROVIDED WITH THE SAME - A substrate for mounting a device comprises: an insulating resin layer; a plurality of projected electrodes that are connected electrically to a wiring layer provided on one major surface of the insulating resin layer, and that project toward the insulating resin layer from the wiring layer; and a counter electrode provided at a position corresponding to each of the plurality of projected electrodes on the other major surface of the insulating resin layer. Among the projected electrodes, a projected length of part of the projected electrodes is smaller than that of the other projected electrodes; and the projected electrode and the counter electrode corresponding thereto are capacitively-coupled, and the projected electrode and the counter electrode are connected electrically. | 02-03-2011 |
20110076808 | Packaging configurations for vertical electronic devices using conductive traces disposed on laminated board layers - This invention discloses an electronic package for containing a vertical semiconductor chip that includes a laminated board having a via connector and conductive traces distributed on multiple layers of the laminated board connected to the via connector. The semiconductor chip having at least one electrode connected to the conductive traces for electrically connected to the conductive traces at a different layer on the laminated board and the via connector dissipating heat generated from the vertical semiconductor. A ball grid array (BGA) connected to the via connector functioning as contact at a bottom surface of the package for mounting on electrical terminals disposed on a printed circuit board (PCB) wherein the laminated board having a thermal expansion coefficient in substantially a same range the PCB whereby the BGA having a reliable electrical contact with the electrical terminals. | 03-31-2011 |
20110117705 | MULTI-LAYER THICK-FILM RF PACKAGE - A method for producing a multi-layer thick-film RF package includes forming conductive layer(s) including one or more source portions, one or more gate portions, and/or one or more drain portions on a ceramic substrate. The conductive layer(s) and the ceramic substrate are fired or otherwise heated in a furnace until sintered. Thereafter, a dielectric pattern is formed on the conductive layer(s) and fired or otherwise heated in the furnace until sintered. Then, a conductive bridge is formed on the dielectric pattern, over the one or more drain portions and between the one or more source portions, which is then fired until sintered in the furnace. As a result, a monolithic, single-piece, sintered, high-frequency RF power transistor package having circuit features including a highly conductive and low capacitive bridge is produced. | 05-19-2011 |
20110159644 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - Wire connection failure in semiconductor device is prevented. | 06-30-2011 |
20110165736 | Mounting structures for integrated circuit modules - A structure of an integrated circuit module includes a wiring board, a plurality of integrated circuits and at least one terminating resistance circuit. The wiring board has a mounting region on at least one surface thereof. The plurality of integrated circuits are mounted in the mounting region of the wiring board and spaced from one another in a first direction. The at least one terminating resistance circuit is arranged between at least two adjacent integrated circuits, and coupled to an output of a last of the plurality of integrated circuits. | 07-07-2011 |
20110256671 | SEMICONDUCTOR MEMORY MODULE WITH REVERSE MOUNTED CHIP RESISTOR - A semiconductor memory module having a reverse mounted chip resistor, and a method of fabricating the same are provided. By reverse mounting the chip resistor on the semiconductor memory module, the resistive material is protected, thereby preventing open circuits caused by damage to the resistive material. Also, a chip-resistor connection pad of a module substrate is formed to extend higher from the module substrate than other connection pads connected to other elements. Thus, the resistive material of the chip resistor does not contact the module substrate, thereby preventing poor alignment and defective connections. | 10-20-2011 |
20110318886 | METHOD FOR FORMING CIRCUIT PATTERNS ON SURFACE OF SUBSTRATE - A method for forming circuit patterns on a surface of a substrate is provided and has steps of: providing and pre-heating a substrate having an insulation surface on one side thereof; providing an activation connection device for oscillating and painting an activation solder onto the pre-heated insulation surface to heat and melt the activation solder; applying ultrasonic waves to the melted activation solder by the activation connection device, so as to activate the activation solder and the insulation surface by the ultrasonic waves; and moving the activation connection device, so as to form a circuit pattern on the insulation surface by the activation solder. | 12-29-2011 |
20120070940 | FIXTURE TO CONSTRAIN LAMINATE AND METHOD OF ASSEMBLY - A fixture assembly and method of forming a chip assembly is provided. The fixture assembly includes a first plate having an opening sized to accommodate a chip mounted on a laminate. The fixture assembly further includes a second plate mated to the first plate by at least one mechanical fastening mechanism. The fixture assembly further includes a space defined by facing surfaces of the first plate and the second plate and confined by a raised stepped portion of at least one of the first plate and the second plate. The space is coincident with the opening. The space is sized and shaped such that the laminate is confined within the space and directly abuts the stepped portion and the facing surfaces of the first plate and the second plate to be confined in X, Y and Z directions. | 03-22-2012 |
20120083073 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - It is aimed at improving the reliability of a semiconductor device. | 04-05-2012 |
20120108014 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - An object is to provide a highly reliable semiconductor device that has tolerance to external stress and electrostatic discharge. Another object is to prevent defective shapes and defective characteristics due to the external stress or an electrostatic discharge in the manufacturing process, and to manufacture a semiconductor device with high yield. Still another object is to manufacture a semiconductor device at low cost and with high productivity. With the use of a conductive shield, electrostatic breakdown (malfunctions of the circuit or damages of a semiconductor element) due to electrostatic discharge of the semiconductor integrated circuit is prevented. The conductive shield is formed so that at least the conductive shields on the top and bottom surfaces are electrically connected by a plating method. In addition, a semiconductor device can be formed at low cost with high productivity because a plating method is used for the formation of the conductive shield. | 05-03-2012 |
20120178217 | METHOD AND APPARATUS FOR LOW INDUCTIVE DESIGN PATTERN - Provided is an interleaved or wavy spatial arrangement of the micro-vias providing the electrical pathways for the power and ground leads are described. The spatial arrangement increases the coupling pairs between power and ground vias or leads. This spatial arrangement is maintained even as the micro-vias transition across a plane from a direction of travel. Thus, the charge from the decoupling capacitor is able to more efficiently be delivered as the inductances are minimized through this design. | 07-12-2012 |
20120196407 | SINGLE LAYER BGA SUBSTRATE PROCESS - Embodiments of the present disclosure provide semiconductor packaging techniques that form a substrate using metal and insulating materials. The substrate includes a first surface that is bonded to a semiconductor device and a second surface that is bonded to a printed circuit board. The substrate is formed using several techniques that minimize the amount of mask levels used to form the substrate. For example, a metal substrate is patterned to form a three dimensional pattern on the surface. A dielectric material is deposited on the three dimensional pattern. Using several patterning and polishing embodiments described herein, the metal/dielectric substrate is patterned and polished to form a substantially flush surface that is bonded to the semiconductor device. In one embodiment, the top surface of the metal/dielectric substrate is patterned to expose the underlying metal substrate and the bottom surface of the metal substrate is polished to be substantially flush with the dielectric material. | 08-02-2012 |
20120295404 | METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - A method of manufacturing a semiconductor package, the method including: forming an insulating layer on a board; forming an electrode pattern portion by redistribution plating in order to make a circuit connection on the insulating layer; manufacturing a semiconductor chip by forming a protecting portion on the electrode pattern portion such that a portion of the electrode pattern portion is exposed; and mounting the semiconductor chip on a receiving space of a circuit board and electrically connecting the semiconductor chip to the circuit board. | 11-22-2012 |
20120302010 | MULTILAYER PRINTED WIRING BOARD - A method for manufacturing a printed wiring board includes forming an uncalcined layer containing a raw ceramic material on a first metal layer, firing the uncalcined layer formed on the first metal layer such that a high dielectric constant layer having a ceramic body calcined in a sheet form is formed on the first metal layer, forming a second metal layer on the high dielectric constant layer on the opposite side of the high dielectric constant layer with respect to the first metal layer such that a layered capacitor having the high dielectric constant layer and first and second layer electrodes sandwiching the high dielectric constant layer is formed, and disposing the layered capacitor in a main body. | 11-29-2012 |
20130023090 | FIBER SOI SUBSTRATE, SEMICONDUCTOR DEVICE USING THIS, AND MANUFACTURING METHOD THEREOF - The present invention provides a SOI substrate that can realize a composite device formed of a MOS integrated circuit and a passive device and can reduce a size and a manufacturing cost of a semiconductor device. There is provided a fiber SOI substrate | 01-24-2013 |
20130143367 | METHODS OF FORMING 3-D CIRCUITS WITH INTEGRATED PASSIVE DEVICES - Methods of forming 3-D ICs with integrated passive devices (IPDs) include stacking separately prefabricated substrates coupled by through-substrate-vias (TSVs). An active device (AD) substrate has contacts on its upper portion. An isolator substrate is bonded to the AD substrate so that TSVs in the isolator substrate are coupled to the contacts on the AD substrate. An IPD substrate is bonded to the isolator substrate so that TSVs therein are coupled to an interconnect zone on the isolator substrate and/or TSVs therein. The IPDs of the IPD substrate are coupled by TSVs in the IPD and isolator substrates to devices in the AD substrate. The isolator substrate provides superior IPD to AD cross-talk attenuation while permitting each substrate to have small high aspect ratio TSVs, thus facilitating high circuit packing density and efficient manufacturing. | 06-06-2013 |
20130337615 | POLYMER HOT-WIRE CHEMICAL VAPOR DEPOSITION IN CHIP SCALE PACKAGING - Embodiments of the present invention provide a vapor phase organic polymer film deposited using a CVD process at low temperature during a process sequence for wafer-level chip scale packaging (WL-CSP), including system-in package (SiP), Package-on-Package (PoP) and Package-in-Package (PiP). | 12-19-2013 |
20130344662 | BUMPLESS BUILD-UP LAYER AND LAMINATED CORE HYBRID STRUCTURES AND METHODS OF ASSEMBLING SAME - A structure includes a hybrid substrate for supporting a semiconductive device that includes a bumpless build-up layer in which the semiconductive device is embedded and a laminated-core structure. The bumpless build-up layer and the laminated-core structure are rendered an integral apparatus by a reinforcement plating that connects to a plated through hole in the laminated-core structure and to a subsequent bond pad of the bumpless build-up layer structure. | 12-26-2013 |
20140004664 | Method Of Making 3D Integration Microelectronic Assembly For Integrated Circuit Devices | 01-02-2014 |
20140017855 | METHOD OF MANUFACTURING A BALL GRID ARRAY SUBSTRATE OR A SEMICONDUCTOR CHIP PACKAGE - A method of manufacturing a ball grid array substrate includes: forming a first circuit pattern and a second circuit pattern on a first metal carrier and a second metal carrier, respectively; stacking a first insulating layer and a second insulating layer with a separable material interposed therebetween, wherein each of the first and second insulating layers has first and second surfaces opposing each other, and the first surface contacts the separable material; burying the first and second circuit patterns in the second surfaces of the first and second insulating layers, respectively; removing the first and second metal carriers; removing the separable material to separate the first and second insulating layers from each other; and forming an opening in each of the first and second insulating layers to connect the first and second surfaces with each other. The method may also be part of a process for manufacturing a semiconductor package. | 01-16-2014 |
20140080266 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein are a semiconductor package and a method of manufacturing the same, the semiconductor package including: a molding member having a cavity formed therein; a device mounted in the cavity; an insulating member formed inside the cavity and on and/or beneath the molding member and the device; a circuit layer formed on the insulating member, and including vias and connection pads electrically connected with the device; a solder resist layer formed on the circuit layer, and having openings exposing upper portions of the connection pads; and solder balls formed in the openings. | 03-20-2014 |
20140113415 | METHOD OF MANUFACTURING CIRCUIT BOARD AND CHIP PACKAGE AND CIRCUIT BOARD MANUFACTURED BY USING THE METHOD - Provided is a method of manufacturing a circuit board. The method includes: preparing a base substrate including a core layer and a first conductive layer that is formed on at least one surface of the core layer and includes an internal circuit pattern; forming a build-up material to cover the first conductive layer; forming in the build-up material at least one cavity through which the core layer and the first conductive layer are exposed; forming a laminated body by curing the build-up material in which the at least one cavity is formed; and forming a second conductive layer including an external circuit pattern on an outer surface of the laminated body. | 04-24-2014 |
20140141572 | SEMICONDUCTOR ASSEMBLIES WITH MULTI-LEVEL SUBSTRATES AND ASSOCIATED METHODS OF MANUFACTURING - Various embodiments of semiconductor assemblies with multi-level substrates and associated methods of manufacturing are described below. In one embodiment, a substrate for carrying a semiconductor die includes a first routing level, a second routing level, and a conductive via between the first and second routing levels. The conductive via has a first end proximate the first routing level and a second end proximate the second routing level. The first routing level includes a terminal and a first trace between the terminal and the first end of the conductive via. The second routing level includes a second trace between the second end of the conductive via and a ball site. The terminal of the first routing level and the ball site of the second routing level are both accessible for electrical connections from the same side of the substrate. | 05-22-2014 |
20140147974 | BUMP STRUCTURE INCLUDING NANO-WIRES AND A BODY CONNECTING ENDS OF THE NANO-WIRES, SEMICONDUCTOR PACKAGE HAVING THE BUMP STRUCTURE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - Provided are a bump structure includes a first bump and a second bump, a semiconductor package including the same, and a method of manufacturing the same. The bump structure includes: first bump provided on a connection pad of a substrate, the first bump including a plurality of nano-wires extending from the connection pad and a body connecting end portions of the plurality of nano-wires; and a second bump provided on the body of the first bump. | 05-29-2014 |
20140154844 | COMPUTER MODULES WITH SMALL THICKNESSES AND ASSOCIATED METHODS OF MANUFACTURING - Computer modules with small thicknesses and associated methods of manufacturing are disclosed. In one embodiment, the computer modules can include a module substrate having a module material and an aperture extending at least partially into the module material. The computer modules can also include a microelectronic package carried by the module substrate. The microelectronic package includes a semiconductor die carried by a package substrate. At least a portion of the semiconductor die extends into the substrate material via the aperture. | 06-05-2014 |
20140162411 | SUBSTRATE FOR MOUNTING SEMICONDUCTOR, SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A substrate for mounting a semiconductor includes a first insulation layer having first and second surfaces on the opposite sides and having a penetrating hole penetrating through the first insulation layer, an electrode formed in the penetrating hole in the first insulation layer and having a protruding portion protruding from the second surface of the first insulation layer, a first conductive pattern formed on the first surface of the first insulation layer and connected to the electrode, a second insulation layer formed on the first surface of the first insulation layer and the first conductive pattern and having a penetrating hole penetrating through the second insulating layer, a second conductive pattern formed on the second insulation layer and for mounting a semiconductor element, and a via conductor formed in the penetrating hole in the second insulation layer and connecting the first and second conductive patterns. | 06-12-2014 |
20140162412 | METHODS OF MAKING AN INTERPOSER STRUCTURE WITH EMBEDDED CAPACITOR STRUCTURE - A device is disclosed which includes an interposer, at least one capacitor formed at least partially within an opening formed in the interposer and an integrated circuit that is operatively coupled to the interposer. A method is disclosed which includes obtaining an interposer having at least one capacitor formed at least partially within an opening in the interposer and operatively coupling an integrated circuit to the interposer. A method is also disclosed which includes obtaining an interposer comprising a dielectric material, forming an opening in the interposer and forming a capacitor that is positioned at least partially within the opening. | 06-12-2014 |
20140170815 | EMBEDDED BALL GRID ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - Disclosed herein are an embedded ball grid array substrate and a manufacturing method thereof. The embedded ball grid array includes: a core layer having a cavity therein; a semiconductor device embedded in the cavity of the core layer; a first circuit layer having a circuit pattern including a wire bonding pad formed thereon; a second circuit layer having a circuit pattern including a solder ball pattern formed thereon; and a wire electrically connecting the semiconductor device to the wire bonding pad. | 06-19-2014 |
20140193954 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The reliability of a semiconductor device is to be improved. A microcomputer chip (semiconductor chip) having a plurality of pads formed on a main surface thereof is mounted over an upper surface of a wiring substrate in an opposed state of the chip main surface to the substrate upper surface. Pads coupled to a plurality of terminals (bonding leads) formed over the substrate upper surface comprise a plurality of first pads in which a unique electric current different from the electric current flowing through other pads flows and a plurality of second pads in which an electric current common to the pads flows or does not flow. Another first pad of the first pads or one of the second pads are arranged next to the first pad. The first pads are electrically coupled to a plurality of bonding leads respectively via a plurality of bumps (first conductive members), while the second pads are bonded to the terminals via a plurality of bumps (second conductive members). | 07-10-2014 |
20140206152 | SINGLE LAYER BGA SUBSTRATE PROCESS - The present disclosure provides semiconductor packaging techniques that form a substrate using metal and insulating materials. The substrate includes a first surface that is bonded to a semiconductor device and a second surface that is bonded to a printed circuit board. The substrate is formed using several techniques that minimize the amount of mask levels used to form the substrate. For example, a metal substrate is patterned to form a three dimensional pattern on the surface. A dielectric material is deposited on the three dimensional pattern. Using several patterning and polishing embodiments described herein, the metal/dielectric substrate is patterned and polished to form a substantially flush surface that is bonded to the semiconductor device. In one embodiment, the top surface of the metal/dielectric substrate is patterned to expose the underlying metal substrate and the bottom surface of the metal substrate is polished to be substantially flush with the dielectric material. | 07-24-2014 |
20140206153 | METHOD FOR FABRICATING SOLDER COLUMNS FOR A COLUMN GRID ARRAY PACKAGE - A method for fabricating an electronic device package having a column grid array is disclosed. A column grid array package includes a substrate, an integrated circuit located on a first side of the substrate, and a set of solder columns located on a second side of the substrate. The column grid array package also includes multiple two-tab electronic devices located on the second side of the substrate. The heights of the two-tab electronic devices are substantially identical to the heights of the solder columns. | 07-24-2014 |
20140248746 | MAKING A FLIP-CHIP ASSEMBLY WITH BOND FINGERS - A method of making a flip chip assembly includes a substrate having a top surface and forming a plurality of generally longitudinally extending, laterally spaced apart bond fingers are formed on the top surface. Each of the plurality of bond fingers has a first longitudinal end portion and a second longitudinal end portion. Applying a transversely extending solder resist strip over the first longitudinal end portions of the bond fingers. The strip has an edge wall with a plurality of longitudinally projecting tooth portions separated by gaps. Each tooth portion and each gap aligned with a different one of the bond fingers in each adjacent pair of bond fingers. | 09-04-2014 |
20140273353 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To improve reliability of a semiconductor device in which wire bonding using a wire made of copper is performed. A semiconductor device is configured so that one of end parts (wide width part) of a copper wire is joined via a bump on a pad (electrode pad) formed over a main surface (first main surface) of a semiconductor chip of the semiconductor device. The bump is made of gold, which is a metal material having a hardness lower than that of copper, and the width of the bump is narrower than the width of the wide width part of the wire. | 09-18-2014 |
20140322868 | BARRIER LAYER ON BUMP AND NON-WETTABLE COATING ON TRACE - Some implementations provide a semiconductor device that includes a die, an under bump metallization (UBM) structure coupled to the die, and a barrier layer. The UBM structure has a first oxide property. The barrier layer has a second oxide property that is more resistant to oxide removal from a flux material than the first oxide property of the UBM structure. The barrier layer includes a top portion, a bottom portion and a side portion. The top portion is coupled to the UBM structure, and the side portion is substantially oxidized. | 10-30-2014 |
20140329362 | QFN/SON-Compatible Package - A leadless package and method for manufacturing silicon based leadless QFN/SON compatible packages are described. In addition the package allows for hermetic sealing of devices while maintaining electrical and optical access. Micro-vias with feed-through metallization through a silicon structure facilitates a surface mount technology compatible silicon package with bottom SMT pads and top surface device integration. Sloped edges on the SMT side enable solder filleting for post solder inspection. Hermetic seal can be attained for example using anodic bonding of a glass lid or using metal soldering. Metal soldering enables the use of solder bumps to provide electrical connections for the package to the lid with integrated device functionality used for sealing. Hermetically sealed silicon packages eliminates the need for an extra packaging layer required in plastic packages and provides a standard interface for enclosing one or more discrete devices. | 11-06-2014 |
20140342506 | METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE - Disclosed is a method for fabricating a semiconductor package, including providing a package unit having an insulating layer and at least a semiconductor element embedded into the insulating layer, wherein the semiconductor element is exposed from the insulting layer and a plurality of recessed portions formed in the insulating layer; and electrically connecting a redistribution structure to the semiconductor element. The formation of the recessed portions release the stress of the insulating layer and prevent warpage of the insulating layer from taking place. | 11-20-2014 |
20140357024 | RECESSED AND EMBEDDED DIE CORELESS PACKAGE - Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a plating material to hold a die, attaching the die in the cavity, forming a dielectric material adjacent the die, forming vias in the dielectric material adjacent the die, forming PoP lands in the vias, forming interconnects in the vias, and then removing the plating material to expose the PoP lands and die, wherein the die is disposed above the PoP lands. | 12-04-2014 |
20140363927 | Novel Terminations and Couplings Between Chips and Substrates - A method of attaching a chip to the substrate with an outer layer comprising via pillars embedded in a dielectric such as solder mask, with ends of the via pillars flush with said dielectric, the method comprising the steps of: (o) optionally removing organic varnish, (p) positioning a chip having legs terminated with solder bumps in contact with exposed ends of the via pillars, and (q) applying heat to melt the solder bumps and to wet the ends of the vias with solder. | 12-11-2014 |
20140363928 | MICRO DEVICE STABILIZATION POST - A method and structure for stabilizing an array of micro devices is disclosed. The array of micro devices is formed on an array of stabilization posts formed from a thermoset material. Each micro device includes a bottom surface that is wider than a corresponding stabilization post directly underneath the bottom surface. | 12-11-2014 |
20140370662 | Copper Post Solder Bumps on Substrates - A method comprises forming semiconductor flip chip interconnects having electrical connecting pads and electrically conductive posts terminating in distal ends operatively associated with the pads. We solder bump the distal ends by injection molding, mask the posts on the pads with a mask having a plurality of through hole reservoirs and align the reservoirs in the mask to be substantially concentric with the distal ends. Injecting liquid solder into the reservoirs and allowing it to cool provides solidified solder on the distal ends, which after mask removal produces a solder bumped substrate which we position on a wafer to leave a gap between the wafer and the substrate. The wafer has electrically conductive sites on the surface for soldering to the posts. Abutting the sites and the solder bumped posts followed by heating joins the wafer and substrate. The gap is optionally filled with a material comprising an underfill. | 12-18-2014 |
20140370663 | Method for Producing a Semiconductor Module - A semiconductor module is produced by providing a circuit carrier having a metallization, an electrically conductive wire and a bonding device. With the aid of the bonding device, a bonding connection is produced between the metallization and a first section of the wire. A separating location and a second section of the wire, the second section being spaced apart from the separating location, are defined on the wire. The wire is reshaped in the second section. Before or after reshaping, the wire is severed at the separating location, such that a terminal conductor of the semiconductor module is formed from a part of the wire. The terminal conductor is bonded to the metallization and having a free end at the separating location. | 12-18-2014 |
20150024555 | SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device, includes: a connection member including a first pad formed on a principal surface thereof; a semiconductor chip including a circuit-formed surface on which a second pad is formed, the chip mounted on the connection member so that the circuit-formed surface faces the principal surface; and a solder bump that connects the first and second pads and is made of metal containing Bi and Sn, wherein the bump includes a first interface-layer formed adjacent to the second pad, a second interface-layer formed adjacent to the first pad, a first intermediate region formed adjacent to either one of the interface-layers, and a second intermediate region formed adjacent to the other one of the interface-layers and formed adjacent to the first intermediate region; Bi-concentration in the first intermediate region is higher than a Sn-concentration; and a Sn-concentration in the second intermediate region is higher than a Bi-concentration. | 01-22-2015 |
20150031172 | METHOD FOR INTERCONNECTION OF COMPONENTS ON A SUBSTRATE - A method is described for interconnecting first, | 01-29-2015 |
20150056754 | VACUUM MOLDING APPARATUS, SUBSTRATE PROCESSING SYSTEM HAVING THE SAME AND SUBSTRATE PROCESSING METHOD USING THE SAME - Disclosed herein is a substrate processing system, including: a feeding apparatus which feeds a substrate including a plurality of unit substrates into the substrate processing system; a vacuum molding apparatus which molds the substrate fed by the feeding apparatus; a paste printing apparatus which prints a solder paste on the substrate molded by the vacuum molding apparatus; a mounting apparatus which mounts an electronic device on the substrate on which the solder paste is printed; and a reflow apparatus which performs a reflow on the substrate on which the electronic device is mounted, wherein the vacuum molding apparatus includes a substrate molding control unit which controls the molding of the substrate. Therefore, the warpage (CAW) of the substrate is limitedly formed to improve the warpage (CAW) dispersion of the substrate, thereby improving bonding reliability and a mounting yield between the chip die and the bump of the substrate. | 02-26-2015 |
20150056755 | ELECTRONIC DEVICE PACKAGES HAVING BUMPS AND METHODS OF MANUFACTURING THE SAME - An electronic device package includes a bump having a post disposed on a contact portion of a semiconductor chip and an enlarged portion laterally protruded from an upper portion of the post; an interconnection portion having a locking portion that substantially surrounds the enlarged portion and an upper sidewall of the post; and a dielectric layer substantially surrounding the bump and the locking portion to separate the interconnection portion from the semiconductor chip. | 02-26-2015 |
20150064850 | METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE - A method for fabricating a semiconductor structure is disclosed. First, an interposer is disposed on a carrier. The carrier has a base body and a bonding layer bonded to the base body. The interposer has opposite first and second sides and the first side has a plurality of conductive elements. The interposer is disposed on the carrier with the first side bonded to the bonding layer and the conductive elements embedded in the bonding layer. Then, at least a semiconductor element is disposed on the second side of the interposer. As such, the semiconductor element and the interposer form a semiconductor structure. Since the conductive elements are embedded in the bonding layer instead of the base body, the present invention eliminates the need to form concave portions in the base body for receiving the conductive elements. Therefore, the method of the present invention is applicable to interposers of different specifications. | 03-05-2015 |
20150079735 | ELECTROSTATIC DISCHARGE PROTECTION APPARATUS AND PROCESS - In a process, at least one circuit element is formed in a substrate. A conductive layer is formed over the substrate and in electrical contact with the at least one circuit element. Electrostatic charges are discharged from the substrate via the conductive layer. | 03-19-2015 |
20150093860 | ORIENTATION-INDEPENDENT DEVICE CONFIGURATION AND ASSEMBLY - The present disclosure is directed to orientation-independent device configuration and assembly. An electronic device may comprise conductive pads arranged concentrically on a surface of the device. The conductive pads on the device may mate with conductive pads in a device location in circuitry. Example conductive pads may include at least a first circular conductive pad and a second ring-shaped conductive pad arranged to concentrically surround the first conductive pad. The concentric arrangement of the conductive pads allows for orientation-independent placement of the device in the circuitry. In particular, the conductive pads of the device will mate correctly with the conductive pads of the circuitry regardless of variability in device orientation. In one embodiment, the device may also be configured for use with fluidic self-assembly (FSA). For example, a device housing may be manufactured with pockets that cause the device to attain neutral buoyancy during manufacture. | 04-02-2015 |
20150099330 | Glass Wafers for Semiconductors Fabrication Processes and Methods of Making Same - The present disclosure is directed to the use of glass wafers as carriers, interposers, or in other selected applications in which electronic circuitry or operative elements, such as transistors, are formed in the creation of electronic devices. The glass wafers generally include a glass having a coefficient of thermal expansion equal to or substantially equal to a coefficient of thermal expansion of semiconductor silicon, an indexing feature, and a coating on at least a portion of one face of the glass. | 04-09-2015 |
20150111346 | SEMICONDUCTOR CHIPS HAVING THROUGH SILICON VIAS AND RELATED FABRICATION METHODS AND SEMICONDUCTOR PACKAGES - A semiconductor chip including through silicon vias (TSVs), wherein the TSVs may be prevented from bending and the method of fabricating the semiconductor chip may be simplified, and a method of fabricating the semiconductor chip. The semiconductor chip includes a silicon substrate having a first surface and a second surface; a plurality of TSVs which penetrate the silicon substrate and protrude above the second surface of the silicon substrate; a polymer pattern layer which is formed on the second surface of the silicon substrate, surrounds side surfaces of the protruding portion of each of the TSVs, and comprises a flat first portion and a second portion protruding above the first portion; and a plated pad which is formed on the polymer pattern layer and covers a portion of each of the TSVs exposed from the polymer pattern layer. | 04-23-2015 |
20150118799 | MECHANISM TO ATTACH A DIE TO A SUBSTRATE - A mechanism to attach a die to a substrate and method of use are disclosed. The vacuum carrier includes a frame composed of material compatible with solder reflow process. The vacuum carrier further includes a vacuum port extending from a top surface to an underside surface of the frame. The vacuum carrier further includes a seal mechanism provided about a perimeter on the underside surface of the frame of the vacuum carrier. The frame and seal mechanism are structured to maintain a flatness of a die attached to the vacuum carrier by a vacuum source during the solder reflow process. | 04-30-2015 |
20150118800 | SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, a buffer layer on the substrate, and a plurality of nitride semiconductor layers on the buffer layer. The semiconductor device further includes at least one masking layer and at least one inter layer between the plurality of nitride semiconductor layers. The at least one inter layer is on the at least one masking layer. | 04-30-2015 |
20150325539 | METHOD OF FORMING POST-PASSIVATION INTERCONNECT STRUCTURE - A method includes coating a passivation layer overlying a semiconductor substrate and forming an interconnect layer overlying the passivation layer. The interconnect layer includes a line region and a landing pad region. The method further includes forming a metallic layer including tin on a surface of the interconnect layer using an immersion process, forming a protective layer on the metallic layer, and exposing a portion of the metallic layer on the landing pad region of the interconnect layer through the protective layer. | 11-12-2015 |
20150348893 | METHOD OF MANUFACTURING THREE-DIMENSIONAL INTEGRATED CIRCUIT COMPRISING ALUMINUM NITRIDE INTERPOSER - A method of manufacturing a three-dimensional integrated circuit comprising an aluminum nitride interposer is introduced. The method includes providing a first circuit component; providing a plurality of first conductive blocks on the first circuit component; providing an aluminum nitride interposer on the first circuit component, wherein the aluminum nitride interposer has microvias each comprising therein a conductor with an end in contact with a corresponding one of the first conductive blocks; providing second conductive blocks on the aluminum nitride interposer, wherein the second conductive blocks are in contact with the other ends of the conductors in the microvias; and providing at least a second circuit component disposed on the aluminum nitride interposer and electrically connected to the first circuit component through the first and second conductive blocks and the conductors. | 12-03-2015 |
20150348952 | INTERCONNECT DEVICES FOR ELECTRONIC PACKAGING ASSEMBLIES - An electronic packaging assembly having a semiconductor integrated circuit and a plurality of interconnect components is provided. The plurality of interconnect components is operatively coupled to the semiconductor integrated circuit. Further, one or more interconnect components include one or more support elements having a first surface and a second surface, and one or more spring elements having a first end and a second end, and wherein first ends of the one or more spring elements are coupled to the first surface or the second surface of a respective support element. | 12-03-2015 |
20150364506 | METHOD OF MANUFACTURING A DISPLAY DEVICE - An object of the present invention is to improve yield when manufacturing a display device. A method of manufacturing a display device for displaying an image using a display element includes exposing a first surface of a glass substrate o an aqueous solution containing hydrogen fluoride, forming an organic resin film having a polar group above the first surface of the glass substrate, forming a layer including a display element for displaying an image above the organic resin film, and bonding an opposing substrate so as to cover the display element. | 12-17-2015 |
20150380382 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor chip SC includes an electrode pad PAD. A Cu pillar PIL is formed on the electrode pad PAD. In addition, an interconnect substrate INT includes a connection terminal TER. The connection terminal TER contains Cu. For example, the connection terminal TER is formed of Cu, and is formed, for example, in a land shape. However, the connection terminal TER may not be formed in a land shape. The Cu pillar PIL and the connection terminal TER are connected to each other through a solder layer SOL. The solder layer SOL contains Sn. A Ni layer NIL is formed on either the Cu pillar PIL or the connection terminal TER. The minimum value L of the thickness of the solder layer SOL is equal to or less than 20 μm. | 12-31-2015 |
20160042986 | REINFORCING SHEET AND METHOD FOR PRODUCING SECONDARY MOUNTED SEMICONDUCTOR DEVICE - Provided are a reinforcing sheet which is capable of forming a secondary mounted semiconductor device excellent in impact resistance and which is capable of enhancing efficiency of a secondary mounting process; and a method for producing a secondary mounted semiconductor device using the reinforcing sheet. The present invention provides a reinforcing sheet for reinforcing a secondary mounted semiconductor device in which a primary mounted semiconductor device with a bump electrode formed on a first main surface is electrically connected to a wiring substrate through the bump electrode, wherein the reinforcing sheet includes a base material layer, a pressure-sensitive adhesive layer, and a thermosetting resin layer in this order, and the pressure-sensitive adhesive layer has a breaking strength of 0.07 MPa or more, and a melt viscosity of 4000 Pa·s or less at 60 to 100° C. | 02-11-2016 |
20160043115 | METHOD OF MANUFACTURING ALIGNMENT FILM - A method of manufacturing an alignment film is provided, and has steps of determining printing regions for an alignment agent, which including display portions and transfer portions; printing the alignment agent within the printing regions to form an alignment thin layer; and performing an alignment process to the alignment thin layer to form the alignment film. The unevenness on the edge of the alignment film is moved away from the display portions by expanding the printing regions for the alignment agent, so as to promote the imaging quality of the finished LCD. | 02-11-2016 |
20160049316 | EMBEDDED PACKAGE IN PCB BUILD UP - An apparatus including a printed circuit board including a body of a plurality of alternating layers of conductive material and insulating material; and a package including a die disposed within the body of the printed circuit board. A method including forming a printed circuit board including a core and a build-up section including alternating layers of conductive material and insulating material coupled to the core; and coupling a package including a die to the core of the printed circuit board such that at least a portion of a sidewall of the package is embedded in at least a portion of the build-up section. An apparatus including a printed circuit board including a body; a computing device including a package including a microprocessor disposed within the body of the printed circuit board; and a peripheral device that provides input or output to the computing device. | 02-18-2016 |
20160049381 | LASER ASSISTED BONDING FOR SEMICONDUCTOR DIE INTERCONNECTIONS - Laser assisted bonding for semiconductor die interconnections is disclosed and may, for example, include forming flux on a circuit pattern on a circuit board, placing a semiconductor die on the circuit board where a bump on the semiconductor die contacts the flux, and reflowing the bump by directing a laser beam toward the semiconductor die. The laser beam may volatize the flux and make an electrical connection between the bump and the circuit pattern. A jig plate may be placed on the semiconductor die when the laser beam is directed toward the semiconductor die. Warpage may be reduced during heating or cooling of the semiconductor die by applying pressure to the jig plate. Jig bars may extend outward from the jig plate and may be in contact with the circuit board during the application of pressure to the jig plate. The jig plate may comprise one or more of: silicon, silicon carbide, and glass. | 02-18-2016 |
20160086823 | Systems and Methods for Mechanical and Electrical Package Substrate Issue Mitigation - Systems and methods are provided for an integrated circuit package. A plurality of electrical contacts are configured to provide a structure for electrically connecting the integrated circuit package to a printed circuit board. A package substrate includes at least one patterned metallic layer formed to electrically interconnect I/O contacts of an integrated circuit to the plurality of electrical contacts, and at least one generally uniform metallic layer having a plurality of voids that are respectively situated in axial alignment with corresponding ones of the electrical contacts, and one or more dielectric layers disposed between the plurality of electrical contacts and the metallic layers. Further, the package substrate includes a plurality of metallic elements disposed within the plurality of voids and electrically isolated from the generally uniform metallic layer, the metallic elements configured to reduce a physical size of respective voids without electrically contacting the generally uniform metallic layer. | 03-24-2016 |
20160086918 | NOVEL THREE DIMENSIONAL INTEGRATED CIRCUITS STACKING APPROACH - A semiconductor package and a method of forming a semiconductor package with one or more dies over an interposer are provided. In some embodiments, the method is performed by placing an interposer with one or more through-substrate-vias (TSVs) on a first adhesive layer overlying a first carrier substrate. Connection structures are arranged along a first surface of the interposer facing the first adhesive layer. A first molding compound is formed over the first adhesive layer and surrounding the interposer. The first molding compound is arranged to expose the TSVs along a second surface of the interposer. A first redistribution structure is formed over the second surface of the interposer and the first molding compound, and conductive bump structures are formed over the first redistribution structure. A first packaged die is bonded to the conductive bump structures. | 03-24-2016 |
20160093514 | MANUFACTURING PROCESS FOR SUBSTRATE STRUCTURE HAVING COMPONENT-DISPOSING AREA - A process for a substrate having a component-disposing area is provided, and includes the following steps. A core layer including a first surface, a metallic layer and a component-disposing area is provided. The metallic layer is disposed on the first surface and patterned to form a patterned metallic layer including pads located in the component-disposing area. A first dielectric layer is formed on the first surface and covers the patterned metallic layer. A laser-resistant metallic pattern is formed on the first dielectric layer and surrounds a projection area of the first dielectric layer. A release film is disposed on the projection area and covers a portion of the laser-resistant metallic pattern within the projection area. A second dielectric layer is formed on the first dielectric layer and covers the release film and the laser-resistant metallic pattern. A first open hole and a plurality of second open holes are formed. | 03-31-2016 |
20160104632 | NON-UNIFORM SUBSTRATE STACKUP - Some embodiments described herein include apparatuses and methods of forming such apparatuses. One such embodiment may include a routing arrangement having pads to be coupled to a semiconductor die, with a first trace coupled to a first pad among the pads, and a second trace coupled to a second pad among the pads. The first and second traces may have different thicknesses. Other embodiments including additional apparatuses and methods are described. | 04-14-2016 |
20160111301 | CORELESS PACKAGING SUBSTRATE AND METHOD OF FABRICATING THE SAME - A coreless packaging substrate includes: a circuit buildup structure having at least a dielectric layer, a wiring layer and a plurality of conductive elements, a plurality of electrical pads embedded in the dielectric layer of the circuit buildup structure, a plurality of metal bumps formed on the wiring layer of the circuit buildup structure, and a dielectric passivation layer formed on the surface of the circuit buildup structure and the metal bumps with the metal bumps exposed from the dielectric passivation layer. The metal bumps each have a metal column portion and a wing portion integrally connected to the metal column portion, such that the bonding force between the metal bumps and a semiconductor chip can be enhanced by the entire top surface of the wing portions of the metal bumps being completely exposed. | 04-21-2016 |
20160126110 | METHOD FOR MANUFACTURING THREE-DIMENSIONAL INTEGRATED CIRCUIT - A method for manufacturing a three-dimensional integrated circuit is disclosed. The method includes: providing a substrate; forming at least one metal layer and at least one dielectric layer on the substrate; forming a plurality of electrical connection points on the metal layer; dicing to generate a plurality package units, each of the package units adhered to a diced substrate; reversing each of the package units and connecting each of the reversed package units to a surface of a wiring substrate to form an integrated substrate; and removing the diced substrate of each of the reversed package units. The present disclosure can improve an assembling process. | 05-05-2016 |
20160172244 | METHOD FOR MANUFACTURING ELECTRONIC DEVICE COMPRISING A RESIN SUBSTRATE AND AN ELECTRONIC COMPONENT | 06-16-2016 |
20160181124 | 3D Packages and Methods for Forming the Same | 06-23-2016 |
20160181145 | LAND SIDE AND DIE SIDE CAVITIES TO REDUCE PACKAGE Z-HEIGHT | 06-23-2016 |
20160181181 | PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING SAME | 06-23-2016 |
20160189979 | METHOD FOR PRODUCING WIRING BOARD - The method for producing a wiring board according to the present invention includes the steps of: preparing an insulating board including a cavity forming area and a wiring forming area; forming a first wiring conductor in the wiring forming area; forming a cavity in the cavity forming area and an opening in a part of the wiring forming area; inserting an electronic component including an external electrode into the cavity; forming insulating layers on upper and lower surfaces of the insulating board, the insulating layers filled into a gap in the cavity and into the opening; forming a through-hole penetrating through the opening from the insulating layer on an upper surface side to the insulating layer on a lower surface side; and forming a second wiring conductor on a surface of the insulating layer and in the through-hole. | 06-30-2016 |
20160380018 | Method Of Making Low Profile Sensor Package With Cooling Feature - A sensor device and method of making same that includes a silicon substrate with opposing first and second surfaces, a sensor formed at or in the first surface, a plurality of first contact pads formed at the first surface which are electrically coupled to the sensor, and a plurality of cooling channels formed as first trenches extending into the second surface but not reaching the first surface. The cooling channels instead can be formed on one or more separate substrates that are attached to the silicon substrate for cooling the silicon substrate. | 12-29-2016 |
20190148169 | METHOD FOR MANUFACTURING PACKAGE SUBSTRATE FOR MOUNTING A SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE MOUNTING SUBSTRATE | 05-16-2019 |