| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438126000 | And encapsulating | 87 |
| 20080206929 | PRINTING DEVICE, PRODUCTION UNIT, AND PRODUCTION METHOD OF ELECTRONIC PARTS - A printing device, a production unit and a production method of electronic parts suitable for production of precise electronic parts are provided. A squeegee is attached to a rotating machine, and is autorotated and self-driven, and moreover, a printing pressure is generated in the squeegee, and resin is strongly filled, thereby achieving a print having a precision-shape. Further, with a perforated plate as a boundary, upper and lower chambers are provided so as to control a pressure, thereby performing cutting and dispensing of the resin and achieving a print having a precision-shape. This method is applied to the packaging of electronic parts. A printing device E | 08-28-2008 |
| 20080213947 | Resin encapsulation molding method for semiconductor device - According to a resin encapsulation molding method for a semiconductor device, a resin-encapsulated substrate having a semiconductor device that is mounted on the substrate and that has a portion exposed is formed. With the method, a device-mounted substrate on which the semiconductor device is mounted is prepared and then the device-mounted substrate is set in one mold part. A release film is thereafter provided between the device-mounted substrate and the other mold part opposite to that one mold part. The one and other mold parts are then closed to press the release film against the portion of the semiconductor device. The device-mounted substrate has a projection enclosing the portion of the semiconductor device for preventing resin flash from being formed. When the mold parts are closed, the release film is pressed against the projection to allow the projection to dig into the release film. | 09-04-2008 |
| 20080254574 | SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SAME - By preparing a package substrate which has a plurality of lands of NSMD structure, and the output wiring and dummy wiring which were connected to each of the lands, and have been arranged mutually in the location of 180° symmetry, and printing solder by a printing method to the lands after the package assembly, the variation in the height of the solder coat between lands can be reduced, and improvement in the mountability of LGA (semiconductor device) is achieved. | 10-16-2008 |
| 20080293191 | SEMICONDUCTOR PACKAGE - There is provided a semiconductor package including: a substrate having a plurality of electrode pads on a surface thereof; a semiconductor chip mounted on the substrate, the semiconductor chip electrically connecting with the plurality of electrode pads; and a stiffener arranged on the substrate so as to surround the semiconductor chip. The stiffener includes: an insulating material layer; and a rigid plate mounted substantially parallel to a surface of the substrate in the insulating material layer, the rigid plate having formed therein a plurality of through holes, at least a part of the through holes being filled with the insulating material. | 11-27-2008 |
| 20080299709 | METAL CORE FOLDOVER PACKAGE STRUCTURES - Chip-scale packages and assemblies thereof and methods of fabricating such packages including Chip-On-Board, Board-On-Chip, and vertically stacked Package-On-Package modules are disclosed. The chip-scale package includes a core member of a metal or alloy having a recess for at least partially receiving a die therein and includes at least one flange member partially folded over another portion of the core member. Conductive traces extend from one side of the package over the at least one flange member to an opposing side of the package. Systems including the chip-scale packages and assemblies are also disclosed. | 12-04-2008 |
| 20090075431 | Wafer level package with cavities for active devices - According to one exemplary embodiment, a method for forming a wafer level package includes fabricating an active device on a substrate in a semiconductor wafer, forming polymer walls around the active device, and applying a blanket film over the semiconductor wafer and the polymer walls to house the active device in a substantially enclosed cavity formed by the polymer walls and the blanket film. By way of examples and without limitation, the active device can be a microelectromechanical systems (“MEMS”) device, a bulk acoustic wave (“BAW”) filter, or a surface acoustic wave (“SAW”) filter. According to one embodiment, solder bumps can be applied to interconnect traces of the active device, and the semiconductor wafer can then be diced to form an individual die. According to another embodiment, the semiconductor wafer can be diced to form an individual die, then the individual die is wire bonded to a circuit board. | 03-19-2009 |
| 20090263939 | SEMICONDUCTOR ELEMENT, METHOD OF MANUFACTURING SEMICONDUCTOR ELEMENT, MULTI-LAYER PRINTED CIRCUIT BOARD, AND METHOD OF MANUFACTURING MULTI-LAYER PRINTED CIRCUIT BOARD - A transition layer | 10-22-2009 |
| 20090291531 | Method of manufacturing a semiconductor device and molding die - A method of manufacturing a semiconductor device capable of obtaining high joining force between a heat spreader and resin is provided. The method of manufacturing a semiconductor device according to the present invention includes: setting a heat spreader | 11-26-2009 |
| 20100022054 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor package includes: a build-up wiring layer including a metal wiring layer and an insulation resin layer; and a low thermal expansion material layer having a coefficient of thermal expansion closer to that of a semiconductor chip mounted on the build-up wiring layer as compared with the insulation resin layer of the build-up wiring layer, the low thermal expansion material layer being bonded to an entire region of a rear surface of the build-up wiring layer corresponding to a region of a front surface of the build-up wiring layer on which the semiconductor chip is mounted. | 01-28-2010 |
| 20100029047 | METHOD OF FABRICATING PRINTED CIRCUIT BOARD HAVING SEMICONDUCTOR COMPONENTS EMBEDDED THEREIN - A method for fabricating a printed circuit board having semiconductor components embedded therein is provided. A carrier board having at least a predetermined hole area is provided. A plurality of through holes are formed in the surround of the predetermined hole area on the carrier board. A rectangular cavity is formed by punching to remove the predetermined hole area, and a plurality of through holes are formed around the rectangular cavity The through holes facilitate receipt of the semiconductor chip and filling of a fixing material in the rectangular cavity, to avoid displacement of the semiconductor chip in subsequent fabricating steps that would otherwise cause a drawback, that is, a wiring to be formed later is improperly electrically connected to the semiconductor chip. | 02-04-2010 |
| 20100055847 | METHODS OF PROMOTING ADHESION BETWEEN TRANSFER MOLDED IC PACKAGES AND INJECTION MOLDED PLASTICS FOR CREATING OVER-MOLDED MEMORY CARDS - A flash memory card and methods of manufacturing same are disclosed. The card includes a semiconductor package fabricated to receive a single-sided or double-sided lid. A surface of the semiconductor package may be formed with holes, trenches and/or pockmarks. After the holes, trenches and/or pockmarks are formed, a lid may be attached to the package surface in an injection molding process. During the injection molding process, the molten plastic flows into the holes, trenches and/or pockmarks to interconnect with the surface of the semiconductor package. Thus, when the molten plastic hardens, the holes, trenches and/or pockmarks ensure that the lid remains firmly attached to semiconductor package. | 03-04-2010 |
| 20100075464 | METHOD OF REDUCING VOIDS IN ENCAPSULANT - A method of reducing voids within a bead of encapsulant material deposited on a series of wire bonds connecting a micro-electronic device with die contact pads extending along one edge, and a plurality of conductors on a support structure such that the wire bonds extend across a gap defined between the edge of the micro-electronic device and the plurality of conductors. The method has the steps of depositing at least one transverse bead of encapsulant in the gap extending at an angle to the edge of the micro-electronic device, and, depositing at least one longitudinal bead of encapsulant in the gap extending parallel to the edge of the micro-electronic device. | 03-25-2010 |
| 20100210074 | SEMICONDUCTOR PACKAGE, INTEGRATED CIRCUIT CARDS INCORPORATING THE SEMICONDUCTOR PACKAGE, AND METHOD OF MANUFACTURING THE SAME - One embodiment of a semiconductor package described herein includes a substrate having a first through-hole extending therethrough; a conductive pattern overlying the substrate and extending over the first through-hole; a first semiconductor chip facing the conductive pattern such that at least a portion of the first semiconductor chip is disposed within the first through-hole; and a first external contact terminal within the first through-hole and electrically connecting the conductive pattern to the first semiconductor chip. | 08-19-2010 |
| 20100267208 | COMPONENT FOR SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD OF COMPONENT FOR SEMICONDUCTOR PACKAGE - A component for semiconductor package which has a protective insulating layer on at least one surface of a component body and exposes a conductive material of the component body to an opening part of the protective insulating layer is manufactured by a method including the steps of (a) forming a mask on at least one surface of the component body, (b) forming the protective insulating layer by filling an opening part of the mask with a protective insulating material by a molding method using a metal mold comprising a mold release film, and (c) removing the metal mold and removing the mask. A typical component is a lead frame or a substrate for semiconductor package. | 10-21-2010 |
| 20110045642 | METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - A method of manufacturing a semiconductor package comprises: preparing a photosensitive insulating material having a first surface and a second surface opposite to the first surface; bonding a semiconductor chip to the first surface of the photosensitive insulating material with a connecting terminal of the semiconductor chip facing the first surface of the photosensitive insulating material; exposing the second surface of the photosensitive insulating material after the bonding the semi-conductor to the first surface of the photosensitive material; encapsulating the first surface of the photosensitive insulating material, and the semiconductor chip bonded to the first surface, with a resin to form a resin encapsulated portion after exposing the second surface of the photosensitive insulating material; and developing the photosensitive insulating material, thereby forming a through-hole communicating with the connecting terminal of the semiconductor chip in the photosensitive insulating material after the exposing the second surface of the photosensitive insulating material. | 02-24-2011 |
| 20110053320 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - According to one embodiment, a method of fabricating a semiconductor device is disclosed. The method can include forming a debonding layer constituted with a thermoplastic resin on a supporting material, and forming an insulating layer constituted with a thermosetting resin including a solvent dissolving the thermoplastic resin on the debonding layer. | 03-03-2011 |
| 20110129966 | SEMICONDUCTOR DEVICE HAS ENCAPSULANT WITH CHAMFER SUCH THAT PORTION OF SUBSTRATE AND CHAMFER ARE EXPOSED FROM ENCAPSULANT AND REMAINING PORTION OF SURFACE OF SUBSTRATE IS COVERED BY ENCAPSULANT - A semiconductor device and a fabrication method thereof are provided. An opening having at least one slanted side is formed on a substrate. At least one chip and at least one passive component are mounted on the substrate. An encapsulant having a cutaway corner is formed on the substrate to encapsulate the chip and the passive component, wherein the cutaway corner of the encapsulant is spaced apart from the slanted side of the opening by a predetermined distance. A singulation process is performed to cut the encapsulant to form a package with a chamfer. The package is embedded in a lid to form the semiconductor device, wherein a portion of the substrate located between the slanted side of the opening and the cutaway corner of the encapsulant is exposed from the encapsulant to form an exposed portion. The present invention also provides a carrier for the semiconductor device. | 06-02-2011 |
| 20110207266 | PRINTED CIRCUIT BOARD (PCB) INCLUDING A WIRE PATTERN, SEMICONDUCTOR PACKAGE INCLUDING THE PCB, ELECTRICAL AND ELECTRONIC APPARATUS INCLUDING THE SEMICONDUCTOR PACKAGE, METHOD OF FABRICATING THE PCB, AND METHOD OF FABRICATING THE SEMICONDUCTOR PACKAGE - A printed circuit board (PCB) includes a wire pattern that has a low processing cost and a high yield by simplifying the structure of the PCB and can increase the joining characteristics and reliability of minute bumps when a flip-chip bonding process is performed. The PCB includes a body resin layer having lower and upper surfaces, a wire pattern on or in one of the upper and lower surfaces of the body resin layer, at least one through-hole contact extending from the wire pattern through the body resin layer, and a solder resist on the upper and lower surfaces of the body resin layer, openings of the solder resist corresponding to at least one of a solder ball land and a bump land, the solder ball land and the bump land being configured to couple the PCB to a semiconductor chip. If the solder ball land is on the one-layer wire pattern, the bump land is on the through-hole contact, and if the bump land is on the wire pattern, the solder ball land is on the through-hole contact. | 08-25-2011 |
| 20110269272 | MICROELECTRONIC PACKAGES AND METHODS THEREFOR - A microelectronic package includes a microelectronic element having faces and contacts, the microelectronic element having an outer perimeter, and a substrate overlying and spaced from a first face of the microelectronic element, whereby an outer region of the substrate extends beyond the outer perimeter of the microelectronic element. The microelectronic package includes a plurality of etched conductive posts exposed at a surface of the substrate and being electrically interconnected with the microelectronic element, whereby at least one of the etched conductive posts is disposed in the outer region of the substrate. The package includes an encapsulating mold material in contact with the microelectronic element and overlying the outer region of the substrate, the encapsulating mold material extending outside of the etched conductive posts for defining an outermost edge of the microelectronic package. | 11-03-2011 |
| 20110269273 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. | 11-03-2011 |
| 20110287589 | METHOD FOR MANUFACTURING ANTENNA AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The present invention provides an antenna with low resistance and a semiconductor device having an antenna whose communication distance is improved. A fluid containing conductive particles is applied over an object. After curing the fluid containing the conductive particles, the fluid is irradiated with a laser to form an antenna. As a method for applying the fluid containing the conductive particles, screen printing, spin coating, dipping, or a droplet discharging method is used. Further, a solid laser having a wavelength of 1 nm or more and 380 nm or less is used as the laser. | 11-24-2011 |
| 20110300673 | POST-DISPENSE VACUUM OVEN FOR REDUCING UNDERFILL VOIDS DURING IC ASSEMBLY - An IC assembly method for reducing voids in underfill material. An IC die is bonded to a substrate which creates a gap between the IC die and the substrate. An underfill material that has a curing temperature (Tuc) is dispensed around at least one side along a perimeter of the gap, where capillary forces draw the underfill material into the gap to at least partially fill the gap to form an underfilled IC assembly. After the dispensing, a vacuum oven process is applied to the underfilled IC assembly which applies a vacuum of 15 to 140 torr and a temperature that is between Tuc −85° C. and Tuc −5° C., for reducing voids in the underfill material. The underfill material is then cured by heating the underfilled IC assembly to a temperature ≧ Tuc. | 12-08-2011 |
| 20110318887 | METHOD OF MOLDING SEMICONDUCTOR PACKAGE - A method of molding a semiconductor package includes coating liquid molding resin or disposing solid molding resin on a top surface of a semiconductor chip arranged on a substrate. The solid molding resin may include powdered molding resin or sheet-type molding resin. In a case where liquid molding resin is coated on the top surface of the semiconductor chip, the substrate is mounted between a lower molding and an upper molding, and then melted molding resin is filled in a space between the lower molding and the upper molding. In a case where the solid molding resin is disposed on the top surface of the semiconductor chip, the substrate is mounted on a lower mold and then the solid molding resin is heated and melts into liquid molding resin having flowability. An upper mold is mounted on the lower mold, and melted molding resin is filled in a space between the lower molding and the upper molding. | 12-29-2011 |
| 20120021567 | NOVEL REWORKABLE UNDERFILLS FOR CERAMIC MCM C4 PROTECTION - The present invention provides chip containing electronic devices such as Multichip Ceramic Modules (MCM's) containing a plurality of chips on a substrate which chips are underfilled with a reworkable composition which allows one or more chips to be removed from the device and replaced. The reworkable compositions contain a base resin which is not cross-linkable and which forms a matrix with a linear curable component or preferably a combination of linear curable components which curable components are cross-linkable and when cured form a cross-linked domain in the base resin matrix. A suitable cross-linking catalyst such as Pt is used and optionally a filler preferably silane surface treated silica. The preferred base resin is linear polydimethylsiloxane and the preferred curable components are vinyl terminated linear poly dimethyl siloxane and hydrogen terminated linear poly dimethyl siloxane. | 01-26-2012 |
| 20120178218 | SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR CHIP, AND METHOD FOR THE PRODUCTION THEREOF - A semiconductor device having a semiconductor chip having an active surface with flip-chip contacts and a passive surface is disclosed. The flip-chip contacts are surrounded by an electrically insulating layer as underfill material, the layer having a UV B-stageable material. The UV B-stageable material is applied on the active surface of the semiconductor wafer. | 07-12-2012 |
| 20120196408 | MULTICHIP ELECTRONIC PACKAGES AND METHODS OF MANUFACTURE - A multi-chip electronic package and methods of manufacture are provided. The multi-chip package includes a plurality of chips mounted on a chip carrier. The multi-chip package further includes a lid mounted on the chip carrier using a bonding material or compression seal, and at least one single piston extending from the lid. Each piston covers an entirety of multiple chips of the plurality of chips. | 08-02-2012 |
| 20120244666 | PRINTED SUBSTRATE MANUFACTURING EQUIPMENT AND MANUFACTURING METHOD - Solder bumps are formed on a plurality of electrode parts of a printed substrate and a semiconductor chip is loaded on the printed substrate via the plurality of solder bumps. In this case, a thermoplastic film is prepared as an underfill that covers a surface of the printed substrate on which the solder bumps are formed. In the film, parts corresponding to the solder bumps are removed and a peripheral edge of a part on which the semiconductor chip will be loaded has a protruded form. After the printed substrate has been covered with the film, the film is bonded onto the board and the semiconductor chip is loaded on the printed substrate and carried into a reflow furnace. In the reflow furnace, heat and pressure are applied to fuse the solder bumps. | 09-27-2012 |
| 20130122658 | MANUFACTURING A SEMICONDUCTOR PACKAGE INCLUDING AN EMBEDDED CIRCUIT COMPONENT WITHIN A SUPPORT STRUCTURE OF THE PACKAGE - A method and apparatus are provided in which a cavity is formed in a support structure, the support structure being operable to support a semiconductor device, disposing at least a portion of a circuit element in the cavity in the support structure, filling the cavity in the support structure with an electrically non-conductive filling material so as to at least partially surround the circuit element with the non-conductive filling material, and electrically connecting the semiconductor device to the circuit element. In an example embodiment, the circuit element is operable to substantially block direct current that is output by the semiconductor device or another semiconductor device. | 05-16-2013 |
| 20130122659 | Assembly Method for Three Dimensional Integrated Circuit - A method comprises attaching a first side of an interposer on a carrier wafer. The first side of the interposer comprises a plurality of bumps. The carrier wafer comprises a plurality of cavities formed in the carrier wafer. Each bump on the first side of the interposer can fit into its corresponding cavity on the carrier wafer. Subsequently, the method comprises attaching a semiconductor die on the second side of the interposer to form a wafer stack, detaching the wafer stack from the carrier wafer and attaching the wafer stack to a substrate. | 05-16-2013 |
| 20130203219 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A semiconductor package includes a substrate having an insulation layer. The insulation layer has a first region having a first surface roughness and a second region having a second surface roughness. A semiconductor chip is mounted in the first region, and an underfill resin solution is filled into the space between the semiconductor chip and the insulation layer. The roughness of the second region prevents the underfill resin from flowing out from the semiconductor chip to thereby reduce a size of the semiconductor package. | 08-08-2013 |
| 20130203220 | METHOD OF MOLDING SEMICONDUCTOR PACKAGE - A method of molding a semiconductor package includes coating liquid molding resin or disposing solid molding resin on a top surface of a semiconductor chip arranged on a substrate. The solid molding resin may include powdered molding resin or sheet-type molding resin. In a case where liquid molding resin is coated on the top surface of the semiconductor chip, the substrate is mounted between a lower molding and an upper molding, and then melted molding resin is filled in a space between the lower molding and the upper molding. In a case where the solid molding resin is disposed on the top surface of the semiconductor chip, the substrate is mounted on a lower mold and then the solid molding resin is heated and melts into liquid molding resin having flowability. An upper mold is mounted on the lower mold, and melted molding resin is filled in a space between the lower molding and the upper molding. | 08-08-2013 |
| 20130210198 | PROCESS FOR FORMING SEMICONDUCTOR STRUCTURE - A method for forming a semiconductor structure. A semiconductor substrate including a plurality of dies mounted thereon is provided. The substrate includes a first portion proximate to the dies and a second portion distal to the dies. In some embodiments, the first portion may include front side metallization. The second portion of the substrate is thinned and a plurality of conductive through substrate vias (TSVs) is formed in the second portion of the substrate after the thinning operation. Prior to thinning, the second portion may not contain metallization. In one embodiment, the substrate may be a silicon interposer. Further back side metallization may be formed to electrically connect the TSVs to other packaging substrates or printed circuit boards. | 08-15-2013 |
| 20130224914 | METHOD FOR PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BONDS TO ENCAPSULATION SURFACE - A microelectronic assembly includes a substrate having a first and second opposed surfaces. A microelectronic element overlies the first surface and first electrically conductive elements can be exposed at at least one of the first surface or second surfaces. Some of the first conductive elements are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the substrate and the bases, each wire bond defining an edge surface extending between the base and the end surface. An encapsulation layer can extend from the first surface and fill spaces between the wire bonds, such that the wire bonds can be separated by the encapsulation layer. Unencapsulated portions of the wire bonds are defined by at least portions of the end surfaces of the wire bonds that are uncovered by the encapsulation layer. | 08-29-2013 |
| 20130230947 | FABRICATION METHOD OF PACKAGE STRUCTURE HAVING EMBEDDED SEMICONDUCTOR COMPONENT - A package structure having an embedded semiconductor component, includes: a chip having an active surface with electrode pads and an inactive surface opposite to the active surface; a first insulating protection layer having a chip mounting area for the chip to be mounted thereon via the active surface thereof; a plurality of connection columns disposed in the first insulating protection layer at positions corresponding to the electrode pads and electrically connected to the electrode pads via solder bumps; an encapsulant formed on one surface of the first insulating protection layer having the chip mounted thereon for encapsulating the chip; and a built-up structure formed on the other surface of the first insulating protection layer and the connection columns. Due to the bending resistance of the encapsulant, the warpage of the built-up structure is prevented. | 09-05-2013 |
| 20130260513 | MICROELECTRONIC PACKAGE WITH TERMINALS ON DIELECTRIC MASS - A package for a microelectronic element | 10-03-2013 |
| 20130316501 | ULTRA-THIN NEAR-HERMETIC PACKAGE BASED ON RAINIER - A microelectronic package including a dielectric layer having top and bottom surfaces, the dielectric layer having terminals exposed at the bottom surface; a metallic wall bonded to the dielectric layer and projecting upwardly from the top surface of the dielectric layer and surrounding a region of the top surface; a metallic lid bonded to the wall and extending over the region of the top surface so that the lid, the wall and the dielectric layer cooperatively define an enclosed space; and a microelectronic element disposed within the space and electrically connected to the terminals. | 11-28-2013 |
| 20140106511 | FLIP-CHIP PACKAGING TECHNIQUES AND CONFIGURATIONS - Embodiments of the present disclosure flip-chip packaging techniques and configurations. An apparatus may include a package substrate having a plurality of pads formed on the package substrate, the plurality of pads being configured to receive a corresponding plurality of interconnect structures formed on a die and a fluxing underfill material disposed on the package substrate, the fluxing underfill material comprising a fluxing agent configured to facilitate formation of solder bonds between individual interconnect structures of the plurality of interconnect structures and individual pads of the plurality of pads and an epoxy material configured to harden during formation of the solder bonds to mechanically strengthen the solder bonds. Other embodiments may also be described and/or claimed. | 04-17-2014 |
| 20140170816 | Copper Post Solder Bumps on Substrates - A method comprises forming semiconductor flip chip interconnects having electrical connecting pads and electrically conductive posts terminating in distal ends operatively associated with the pads. We solder bump the distal ends by injection molding, mask the posts on the pads with a mask having a plurality of through hole reservoirs and align the reservoirs in the mask to be substantially concentric with the distal ends. Injecting liquid solder into the reservoirs and allowing it to cool provides solidified solder on the distal ends, which after mask removal produces a solder bumped substrate which we position on a wafer to leave a gap between the wafer and the substrate. The wafer has electrically conductive sites on the surface for soldering to the posts. Abutting the sites and the solder bumped posts followed by heating joins the wafer and substrate. The gap is optionally filled with a material comprising an underfill. | 06-19-2014 |
| 20140235019 | Decoupling MIM Capacitor Designs for Interposers and Methods of Manufacture Thereof - Decoupling metal-insulator-metal (MIM) capacitor designs for interposers and methods of manufacture thereof are disclosed. In one embodiment, a method of forming a decoupling capacitor includes providing a packaging device, and forming a decoupling MIM capacitor in at least two metallization layers of the packaging device. | 08-21-2014 |
| 20140248747 | CHIP-ON-LEAD PACKAGE AND METHOD OF FORMING - In one embodiment, a chip-on-lead package structures includes an electronic chip having opposing major surfaces. One major surface of the electronic chip is attached to first and second leads. The one major surface is electrically connected to the first lead, and electrically isolated from the second lead. The other major surface where active device are formed may be electrically connected to the second lead. | 09-04-2014 |
| 20140273354 | FABRICATION OF 3D CHIP STACKS WITHOUT CARRIER PLATES - A method of fabricating a 3D chip stack uses an interposer and an electronic circuit substrate comprising a plurality of electronic circuits. The electrical contacts of the electronic circuit substrate are bonded and electrically coupled to bumps of the interposer. A molding compound is applied over the electronic circuits to form a molded structure. The molded structure is thinned to have a second molded thickness that is less than the first molded thickness, and the interposer is thinned to a second interposer thickness that is less than a first interposer thickness. | 09-18-2014 |
| 20140273355 | METHOD OF MAKING PACKAGE WITH INTERPOSER FRAME - A method of forming a package on package structure includes bonding a semiconductor die and an interposer frame to a substrate, and the interposer frame surrounds the semiconductor die. The semiconductor die is disposed in an opening of the interposer frame, and the interposer frame has a plurality of TSHs. The plurality of TSHs is aligned with a plurality of bumps on the substrate. The method also includes positioning a packaged die over the semiconductor die and the interposer frame. The packaged die has a plurality of bumps aligned with the plurality of TSHs of the interposer. The method further includes performing a reflow process to allow solder of the plurality of bumps of the substrate and the solder of the plurality of bumps of the packaged die to fill the plurality of TSHs. | 09-18-2014 |
| 20140295623 | METHOD OF PACKAGING A CHIP AND A SUBSTRATE - Disclosed is a method of packaging a chip and a substrate, including the steps of forming a substrate with a thickness ranging from 70 to 150 μm, which comprises a dielectric layer, a circuit metal layer stacked on the dielectric layer and bonding pads higher than the dielectric layer by 10 to 15 μm; forming a stabilizing structure around the substrate to provide a receiving space; disposing the chip on the receiving space and bonding the pins of the chip with the bonding pads; and filling up the receiving space under the chip with a filling material to a total thickness ranging from 300 to 850 μm. Without the plastic molding process, the present invention reduces the cost and the total thickness, and further prevents the substrate from warping by use of the stabilizing fixing structure. | 10-02-2014 |
| 20140295624 | Package with Passive Devices and Method of Forming the Same - An embodiment is a device comprising a substrate, a metal pad over the substrate, and a passivation layer comprising a portion over the metal pad. The device further comprises a metal pillar over and electrically coupled to the metal pad, and a passive device comprising a first portion at a same level as the metal pillar, wherein the first portion of the passive device is formed of a same material as the metal pillar. | 10-02-2014 |
| 20140302643 | CONNECTION DEVICE, METHOD FOR MANUFACTURING CONNECTION STRUCTURE, METHOD FOR MANUFACTURING STACKED CHIP COMPONENT AND METHOD FOR MOUNTING ELECTRONIC COMPONENT - A connection device includes a mounting section on which an electronic component stacked with a thermosetting adhesive agent layer is mounted, a heat press head for heating and pressing the electronic component, a first elastic body that is disposed between the electronic component and a pressing surface of the heat press head so as to press an upper surface of the electronic component, and a support member that is disposed on a periphery of the electronic component and supports the first elastic body. | 10-09-2014 |
| 20140308780 | FABRICATION METHOD OF SEMICONDUCTOR PACKAGE - A fabrication method of a semiconductor package is provided, which includes the steps of: forming a packaging substrate on a first carrier; bonding a second carrier to the packaging substrate; removing the first carrier; disposing a chip on the packaging substrate; forming an encapsulant on the packaging substrate for encapsulating the chip; and removing the second carrier. The first and second carriers provide the thin-type packaging substrate with sufficient rigidity for undergoing the fabrication processes without cracking or warpage, thereby meeting the miniaturization requirement and improving the product yield. | 10-16-2014 |
| 20140315354 | PACKAGE PROCESS - A package structure and a package process are provided. The package structure comprises a carrier having a carrying portion and a plurality of supporting bar remnants disposed around and extending outward from the carrying portion, a chip mounted to the carrying portion, and an encapsulant disposed on the carrier and covering the chip, wherein the supporting bar remnants are encapsulated by the encapsulant, and each of the supporting bar remnants has a distal end shrank from an outer surface of the encapsulant. A package process for fabricating the package structure is also provided. | 10-23-2014 |
| 20140322869 | METHOD FOR MANUFACTURING CHIP PACKAGE STRUCTURE - A method for manufacturing a chip package structure includes following steps. A carrier having a metal layer is provided. A patterned photoresist layer is formed on the metal layer. The patterned photoresist layer has a plurality of first openings exposing a portion of the metal layer. Connection terminals are formed in the first openings, respectively, and the connection terminals are connected to the metal layer. A chip is placed on the carrier, and first pads of the chip are respectively connected to the connection terminals through a plurality of connection conductors. After the chip is placed on the carrier, the patterned photoresist layer is removed. A encapsulant is formed on the carrier. The encapsulant encapsulates the chip, the connection conductors, and the metal layer. The carrier and the metal layer are removed to expose the connection terminals. | 10-30-2014 |
| 20140335661 | METHODS AND APPARATUS TO FORM THIN FILM NANOCRYSTAL INTEGRATED CIRCUITS ON OPHTHALMIC DEVICES - This invention discloses methods and apparatus to form thin film nanocrystal integrated circuit transistors upon three dimensionally formed insert devices. In some embodiments, the present invention includes incorporating the three dimensional surfaces with thin film nanocrystal integrated circuit based thin film transistors, electrical interconnects and energization elements into an insert for incorporation into ophthalmic lenses. In some embodiments the formed insert may be directly used as an ophthalmic device or incorporated into an ophthalmic device. | 11-13-2014 |
| 20140335662 | METHODS FOR FORMING PACKAGE-ON-PACKAGE STRUCTURES HAVING BUFFER DAMS - Package-on-Package (PoP) structures and methods of forming the same are disclosed. In some embodiments, a method of forming a PoP structure may include: placing a device die having a plurality of metal posts over a release layer, wherein the release layer is over a first carrier; forming a plurality of through-assembly vias (TAVs) over the release layer; forming a dam member between the device die and the plurality of TAVs; molding the device die, the dam member, and the plurality of TAVs in a molding compound; and grinding the molding compound to expose ends of the plurality of metal posts and ends of the plurality of TAVs, wherein a top surface of the molding compound is substantially level with the exposed ends of the plurality of metal posts and exposed ends of the plurality of TAVs. | 11-13-2014 |
| 20140342507 | FABRICATION METHOD OF SEMICONDUCTOR PACKAGE - A semiconductor package includes: a dielectric layer having opposite first and second surfaces; a semiconductor chip embedded in the dielectric layer and having a plurality of electrode pads; a plurality of first metal posts disposed on the electrode pads of the semiconductor chip, respectively, such that top ends of the first metal posts are exposed from the first surface; at least a second metal post penetrating the dielectric layer such that two opposite ends of the second metal post are exposed from the first and second surfaces, respectively; a first circuit layer formed on the first surface for electrically connecting the first and second metal posts; and a second circuit layer formed on the second surface for electrically connecting the second metal post. The semiconductor package dispenses with conventional laser ablation and electroplating processes for forming conductive posts in a molding compound, thereby saving fabrication time and cost. | 11-20-2014 |
| 20140342508 | HYBRID SUBSTRATES, SEMICONDUCTOR PACKAGES INCLUDING THE SAME AND METHODS FOR FABRICATING SEMICONDUCTOR PACKAGES - Provided are a hybrid substrate, a semiconductor package including the same, and a method for fabricating the semiconductor package. The hybrid substrate may include an insulation layer, and an organic layer. The insulation layer may include a top, a bottom opposite to the top, and a conductive pattern having different pitches. The organic layer may be connected to the bottom of the insulation layer, and may include a circuit pattern connected to the conductive pattern. The conductive pattern may include a first metal pattern, and a second conductive pattern. The first metal pattern may have a first pitch, and may be disposed in the top of the insulation layer. The second conductive pattern may have a second pitch greater than the first pitch, and may be extended from the first metal pattern to be connected to the circuit pattern through the insulation layer. | 11-20-2014 |
| 20140377914 | Single Layer Coreless Substrate - An electronic chip package comprising at least one chip bonded to a routing layer of an interposer comprising a routing layer and a via post layer that is surrounded by a dielectric material comprising glass fibers in a polymer matrix, wherein the electronic chip package further comprises a second layer of a dielectric material encapsulating the at least one chip, the routing layer and the wires, and methods of fabricating such electronic chip packages. | 12-25-2014 |
| 20150017765 | METHOD FOR PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BONDS TO ENCAPSULATION SURFACE - A microelectronic assembly ( | 01-15-2015 |
| 20150031173 | COPPER POST SOLDER BUMPS ON SUBSTRATES - A method comprises forming semiconductor flip chip interconnects having electrical connecting pads and electrically conductive posts terminating in distal ends operatively associated with the pads. We solder bump the distal ends by injection molding, mask the posts on the pads with a mask having a plurality of through hole reservoirs and align the reservoirs in the mask to be substantially concentric with the distal ends. Injecting liquid solder into the reservoirs and allowing it to cool provides solidified solder on the distal ends, which after mask removal produces a solder bumped substrate which we position on a wafer to leave a gap between the wafer and the substrate. The wafer has electrically conductive sites on the surface for soldering to the posts. Abutting the sites and the solder bumped posts followed by heating joins the wafer and substrate. The gap is optionally filled with a material comprising an underfill. | 01-29-2015 |
| 20150044823 | MICROELECTRONIC PACKAGE WITH INTEGRATED BEARING SURFACES - A method of forming a wire bond having a free end includes joining an end of a metal wire to a conductive element at a surface of a first component, the end of the metal wire being proximate a surface of a bonding tool adjacent an aperture through which the metal wire extends. A predetermined length of the metal wire is drawn out from the aperture. The surface of the bonding tool is used to plastically deform a region of the metal wire between the surface of the bonding tool and a metal element at the surface of the first component. The bonding tool then applies tension to the metal wire to cause a first portion of the metal wire having the end joined to the conductive element to detach from a remaining portion of the metal wire at the plastically deformed region. | 02-12-2015 |
| 20150044824 | Fan-Out WLP With Package - The present disclosure is directed to a method for making a microelectronic package that includes assembling a microelectronic unit with a substrate, and electrically connecting redistribution contacts on the microelectronic unit and terminals on the substrate with a conductive matrix material extending within at least one opening extending through the substrate. | 02-12-2015 |
| 20150056756 | ENCAPSULANT MATERIALS AND A METHOD OF MAKING THEREOF - The present disclosure relates generally to encapsulant materials, a method of making thereof and the use thereof for maintaining the electrical and mechanical integrity of solder connections between electronic devices and substrates. More specifically, the present disclosure relates to reflow encapsulant materials with fluxing properties and a method of making thereof. The present disclosure further relates to a method of manufacturing flip-chip assemblies using the reflow encapsulant materials of the present disclosure wherein only one heating cycle is utilized. | 02-26-2015 |
| 20150079736 | UNDERFILL MATERIAL AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE BY USING THE SAME - A method for manufacturing a semiconductor device by using underfill material includes: a semiconductor chip mounting step configured to mount a semiconductor chip having a solder bump on a substrate via an underfill film including a film forming resin having a weight average molecular weight of not more than 30000 g/mol and a molecular weight distribution of not more than 2.0, an epoxy resin, and an epoxy curing agent; and a reflow step configured to solder-bond the semiconductor chip and the substrate by a reflow furnace. The film forming resin of the underfill material has a weight average molecular weight of not more than 30000 g/mol and a molecular weight distribution of not more than 2.0, and accordingly, the viscosity at the time of heat melting can be reduced, and a semiconductor chip can be mounted at a low pressure. | 03-19-2015 |
| 20150087115 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - According to an embodiment of the present invention, a method for forming a chip package is provided. The method includes: providing a conducting plate, wherein a plurality of conducting pads are disposed on an upper surface of the conducting plate; forming a plurality of conducting bumps on a lower surface of the conducting plate; patterning the conducting plate by removing a portion of the conducting plate, wherein the patterned conducting plate has a plurality of conducting sections electrically insulated from each other, and each of the conducting bumps is electrically connected to a corresponding one of the conducting sections of the patterned conducting plate; forming an insulating support layer to partially surround the conducting bumps; and disposing a chip on the conducting pads. | 03-26-2015 |
| 20150099331 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. | 04-09-2015 |
| 20150118801 | SEMICONDUCTOR DEVICE - To provide a semiconductor device characterized in that lands for mounting thereon solder balls placed in an inner area of a chip mounting area have an NSMD structure. This means that lands for mounting thereon solder balls placed in an area of the back surface of a through-hole wiring board overlapping with a chip mounting area in a plan view have an NSMD structure. According to the invention, a semiconductor device to be mounted on a mounting substrate with balls has improved reliability. | 04-30-2015 |
| 20150147851 | NO FLOW UNDERFILL OR WAFER LEVEL UNDERFILL AND SOLDER COLUMNS - A preassembly semiconductor device comprises chip soldering structures on a semiconductor chip and substrate soldering structures on a substrate corresponding to the chip soldering structures. The substrate soldering structures extend toward the chip soldering structures for forming solder connections with the chip soldering structures. The chip and the substrate are in preassembly positions relative to one another. The height of the substrate soldering structures is greater than the height of the chip soldering structures. A pre-applied underfill is contiguous with the substrate and is sufficiently thick so as to extend substantially no further than the full height of the substrate soldering structures. In another embodiment the height of the chip soldering structures is greater than the height of the substrate soldering structures and the pre-applied underfill is contiguous with the semiconductor chip and sufficiently thick so as to extend substantially no further than the full height of the chip soldering structures. A process comprises manufacturing semiconductor assemblies from these devices by soldering the chip and the substrate to one another | 05-28-2015 |
| 20150303158 | Warpage Reduction and Adhesion Improvement of Semiconductor Die Package - A method of forming a die package includes forming a conductive column over a first side of a carrier, attaching a semiconductor die to the first side of the carrier, and forming a molding compound over the first side of the carrier. The semiconductor die and the conductive column are embedded in the molding compound. A second side of the carrier opposite the first side is under a compressive stress. The method also includes forming a first compressive dielectric layer over the semiconductor die, the conductive column, and the molding compound, forming a first redistribution layer (RDL) over the first compressive dielectric layer, and forming a first passivation layer over the first RDL. | 10-22-2015 |
| 20150325512 | MULTI-DIE, HIGH CURRENT WAFER LEVEL PACKAGE - Wafer-level package semiconductor devices for high-current applications are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar. The wafer-level package device also includes an integrated circuit chip device (e.g., small die) configured upon the integrated circuit chip (e.g., large die). In the wafer-level package device, the height of the integrated circuit chip device is less than the height of the pillar and/or less than the combined height of the pillar and the one or more solder contacts. | 11-12-2015 |
| 20150348858 | UNDERFILL MATERIAL AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - An underfill material enabling voidless packaging and excellent solder bonding properties, and a method for manufacturing a semiconductor device using the same are provided. An underfill material, including an epoxy resin, an acid anhydride, an acrylic resin, and an organic peroxide, the minimum melt viscosity being between 1000 Pa*s and 2000 Pa*s, and gradient of melt viscosity between 10° C. higher than the minimum melt viscosity attainment temperature and a temperature 10° C. higher being between 900 Pa*s/° C. and 3100 Pa*s/° C., is applied to a semiconductor chip having a solder-tipped electrode formed thereon, and the semiconductor chip is mounted onto a circuit substrate having a counter electrode opposing the solder-tipped electrode, and the semiconductor chip and the circuit substrate are thermocompressed under bonding conditions of raising the temperature from a first temperature to a second temperature at a predetermined rate. | 12-03-2015 |
| 20150348859 | UNDERFILL MATERIAL AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME - An underfill material enabling voidless packaging and excellent solder bonding properties, and a method for manufacturing a semiconductor device using the same are provided. An underfill material is used which contains an epoxy resin and a curing agent, and a time for a reaction rate to reach 20% at 240° C. calculated by Ozawa method using a differential scanning calorimeter is 2.0 sec or less and a time for the reaction rate to reach 60% is 3.0 sec or more. This enables voidless packaging and excellent solder connection properties. | 12-03-2015 |
| 20150380274 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Entry of resin into a cylindrical electrode can be suppressed without excessively increasing the number of parts and without unnecessarily damaging members. For this purpose, a semiconductor chip and a cylindrical electrode are mounted on one main surface of substrate. The substrate, the semiconductor chip, and the cylindrical electrode are sealed with resin material such that the cylindrical electrode has one end mounted to the substrate and the other opposite end at least exposed. After the step of sealing, an opening extending from the other end of the cylindrical electrode to a cavity in the cylindrical electrode is formed. Before performing the step of forming an opening, the other end of the cylindrical electrode is closed. | 12-31-2015 |
| 20160013074 | FABRICATION METHOD OF PACKAGING SUBSTRATE | 01-14-2016 |
| 20160013077 | SUBSTRATE INCLUDING A DAM FOR SEMICONDUCTOR PACKAGE, SEMICONDUCTOR PACKAGE USING THE SAME, AND MANUFACTURING METHOD THEREOF | 01-14-2016 |
| 20160020130 | APPARATUS AND METHODS FOR MICRO-TRANSFER-PRINTING - In an aspect, a system and method for assembling a semiconductor device on a receiving surface of a destination substrate is disclosed. In another aspect, a system and method for assembling a semiconductor device on a destination substrate with topographic features is disclosed. In another aspect, a gravity-assisted separation system and method for printing semiconductor device is disclosed. In another aspect, various features of a transfer device for printing semiconductor devices are disclosed. | 01-21-2016 |
| 20160035591 | Methods and Apparatus for bump-on-trace Chip Packaging - Methods and apparatuses for a attaching a first substrate to a second substrate are provided. In some embodiments, a first substrate has a protective layer, such as a solder mask, around a die attach area, at which a second substrate is attached. A keep-out region (e.g., an area between the second substrate and the protective layer) is a region around the second substrate in which the protective layer is not formed or removed. The keep-out region is sized such that a sufficient gap exists between the second substrate and the protective layer to place an underfill between the first substrate and the second substrate while reducing or preventing voids and while allowing traces in the keep-out region to be covered by the underfill. | 02-04-2016 |
| 20160043049 | TALL SOLDERS FOR THROUGH-MOLD INTERCONNECT - Generally discussed herein are systems and apparatuses that include an extended TSBA ball and techniques for making the same. According to an example, a technique can include forming a circuit substrate including forming a circuit on a substrate, the circuit exposed along an upper surface of the substrate, wherein the substrate is for coupling the circuit with a die along a lower surface of the circuit substrate. A molding can be formed onto an upper surface of the circuit substrate, over the circuit of the circuit substrate. An opening can be defined in the molding so that the opening can extend to a top surface of the molding to at least a portion of the circuit. Solder can be formed into the opening, including conforming the solder to the opening and the circuit substrate. | 02-11-2016 |
| 20160064297 | UNDER-FILL MATERIAL, SEALING SHEET, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - Provided are an under-fill material which is capable of reducing a difference in thermal response behavior between a semiconductor element and an adherend and which makes it easy and convenient to perform alignment for mounting the semiconductor element, a sealing sheet including the under-fill material, and a method for producing a semiconductor device using the under-fill material. In the under-fill material of the present invention, a haze is 70% or less before a heat curing treatment, and a storage elastic modulus E′ [MPa] and a thermal expansion coefficient α [ppm/K] after the under-fill material is subjected to a heat curing treatment at 175° C. for 1 hour satisfy the following formula (1) at 25° C.: 10000| 03-03-2016 | |
| 20160086822 | PACKAGING SUBSTRATE HAVING A HOLDER, METHOD OF FABRICATING THE PACKAGING SUBSTRATE, PACKAGE STRUCTURE HAVING A HOLDER, AND METHOD OF FABRICATING THE PACKAGE STRUCTURE - A packaging substrate includes a holder, a first conductive pad disposed on the holder, a core layer disposed on the holder, a circuit layer disposed on the core layer, a plurality of conductive vias disposed in the core layer, and an insulating protection layer disposed on the core layer, wherein the first electrical pad is embedded in the core layer. By combining the holder on one side of the packaging substrate, cracks due to over-thinness can be prevented during transferring or packaging. A method of fabricating the packaging substrate, a package structure having a holder, a method of fabricating the package structure are also provided. | 03-24-2016 |
| 20160093546 | PACKAGE STUCTURE AND METHOD OF FABRICATING THE SAME - A method of fabricating a package structure is provided. The method includes providing a carrier having two opposing surfaces, forming dielectric bodies on the two surfaces of the carrier, respectively, each of the dielectric bodies having a wiring layer embedded therein and a conductive layer formed on the wiring layer, and removing the carrier. Therefore, the wiring layers, the conductive layers and the dielectric bodies are formed on the two surfaces of the carrier, respectively, and the production yield is thus increased. The present invention further provides the package structure thus fabricated. | 03-31-2016 |
| 20160111392 | Method and Apparatus for Connecting Packages onto Printed Circuit Boards - Methods and apparatus are disclosed for attaching the integrated circuit (IC) packages to printed circuit boards (PCBs) to form smooth solder joints. A polymer flux may be provided in the process to mount an IC package to a PCB. The polymer flux may be provided on connectors of the IC package, or provided on PCB contact pad and/or pre-solder of the PCB. When the IC package is mounted onto the PCB, the polymer flux may cover a part of the connector, and may extend to cover a surface of the molding compound on the IC package. The polymer flux may completely cover the connector as well. The polymer flux delivers a fluxing component that facilitates smooth solder joint formation as well as a polymer component that offers added device protection by encapsulating individual connectors. The polymer component may be an epoxy. | 04-21-2016 |
| 20160118289 | METHOD TO PROVIDE THE THINNEST AND VARIABLE SUBSTRATE THICKNESS FOR RELIABLE PLASTIC AND FLEXIBLE ELECTRONIC DEVICE - An electronic device is formed by depositing polyimide on a glass substrate. A conductive material is deposited on the polyimide and patterned to form electrodes and signal traces. Remaining portions of the electronic device are formed on the polyimide. A second polyimide layer is then formed on the first polyimide layer. The glass substrate is then removed, exposing the electrodes and the top surface of the electronic device. | 04-28-2016 |
| 20160126111 | METHODS OF MANUFACTURING A PRINTED CIRCUIT MODULE HAVING A SEMICONDUCTOR DEVICE WITH A PROTECTIVE LAYER IN PLACE OF A LOW-RESISTIVITY HANDLE LAYER - A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned die attached to the printed circuit substrate. The thinned die includes at least one device layer over the printed circuit substrate and at least one deep well within the at least one device layer. A protective layer is disposed over the at least one deep well, wherein the protective layer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 10 | 05-05-2016 |
| 20160148895 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a semiconductor device, includes providing a wiring substrate having a first surface and a second surface, the first surface being provided with a plurality of leads, after the providing of the wiring substrate, arranging a semiconductor chip with a main surface, a plurality of electrode pads formed at the main surface, and a back surface opposite to the main surface, over the first surface of the wiring substrate such that the back surface of the semiconductor chip is opposed to the first surface of the wiring substrate, after the arranging of the semiconductor chip, electrically coupling the electrode pads formed along three out of four sides of the main surface of the semiconductor chip to the leads disposed at the first surface of the wiring substrate via a plurality of metal wires, and after the electrically coupling of the electrode pads, forming a seal body over the first surface of the wiring substrate. | 05-26-2016 |
| 20160155650 | Via Structure For Packaging And A Method Of Forming | 06-02-2016 |
| 20160189980 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a semiconductor device and a semiconductor device produced thereby. For example and without limitation, various aspects of this disclosure provide methods for manufacturing a semiconductor device, and semiconductor devices produced thereby, that comprise forming an interposer including a reinforcement layer. | 06-30-2016 |
| 20160196987 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | 07-07-2016 |
| 20160204077 | METHOD FOR MANUFACTURING ELECTRONIC DEVICE BY USING FLIP-CHIP BONDING | 07-14-2016 |
| 20160379845 | SEMICONDUCTOR PACKAGES INCLUDING INTERPOSER AND METHODS OF MANUFACTURING THE SAME - A semiconductor package may include a semiconductor die mounted on a first surface of an interposer die so that a die connection portion of the semiconductor die faces to the first surface of the interposer die, a protection portion may be disposed on the first surface of the interposer die to cover the semiconductor die, and an interconnection structure disposed in and on the interposer die. The interconnection structure may include an external connection portion that is located on a second surface of the interposer die opposite to the semiconductor die, a through electrode portion that penetrates the interposer die to have an end portion combined with the die connection portion, and an extension portion that connects the through electrode portion to the external connection portion. Related methods are also provided. | 12-29-2016 |
| 20170236725 | METHOD OF MANUFACTURING PACKAGE SUBSTRATE AND SEMICONDUCTOR PACKAGE | 08-17-2017 |
| 20180026007 | PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS | 01-25-2018 |
