| Entries |
| Document | Title | Date |
|---|
| 20080200002 | Plasma Sputtering Film Deposition Method and Equipment - A method for generating metal ions by sputtering a metal target ( | 08-21-2008 |
| 20080213966 | INDUCTOR EMBEDDED IN SUBSTRATE, MANUFACTURING METHOD THEREOF, MICRO DEVICE PACKAGE, AND MANUFACTURING METHOD OF CAP FOR MICRO DEVICE PACKAGE - An inductor embedded in a substrate, including a substrate, a coil electrode formed by filling a metal in a spiral hole formed on the substrate, an insulation layer formed on the substrate, and an external connection pad formed on the insulation layer to be connected to the coil electrode. The inductor-embedded substrate can be used as a cap for a micro device package by forming a cavity on its bottom surface. | 09-04-2008 |
| 20080233704 | Integrated Resistor Capacitor Structure - A resistor capacitor structure and a method of fabrication. A resistor capacitor structure provides a capacitance between at least two nodes within a microelectronic circuit. A bottom plate of the resistor capacitor structure comprises a resistance layer, which in turn provides a resistance path between an additional node within the circuit. The resistor capacitor structure may be formed on top or within interlevel dielectric layers. The resistance layer, alternatively, may be used to fill a cavity located between interlevel dielectric layers and accordingly provide a resistance path between the interlevel dielectric layers. | 09-25-2008 |
| 20080286933 | INTEGRATED CIRCUIT INDUCTOR WITH INTEGRATED VIAS - Integrated circuit inductors ( | 11-20-2008 |
| 20080293209 | Thin film multiplayer ceramic capacitor devices and manufacture thereof - A process for forming a capacitor including the steps of:
| 11-27-2008 |
| 20080293210 | POST LAST WIRING LEVEL INDUCTOR USING PATTERNED PLATE PROCESS - A method of forming a semiconductor substrate. A substrate is provided. At least one metal wiring level is within the substrate. A first insulative layer is deposited on a surface of the substrate. A portion of a wire bond pad is formed within the first insulative layer. A second insulative layer is deposited on the first insulative layer. An iductor is within the second insulative layer using a patterned plate process. A remaining portion of the wire bond pad is formed within the second insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor. | 11-27-2008 |
| 20080299738 | METHOD FOR FORMING INDUCTOR ON SEMICONDUCTOR SUBSTRATE - An inductor formed on a semiconductor substrate is provided in the present invention. The inductor includes a metal layer and an insulator layer. The metal layer constitutes the coil of the inductor. The insulator layer includes at least one insulator slot, and each insulator slot is encompassed in the metal layer. | 12-04-2008 |
| 20080305603 | Forming carbon nanotube capacitors - A capacitor may be formed of carbon nanotubes. Carbon nanotubes, grown on substrates, may be formed in a desired pattern. The pattern may be defined by placing catalyst in appropriate locations for carbon nanotube growth from a substrate. Then, intermeshing arrays of carbon nanotubes may be formed by juxtaposing the carbon nanotubes formed on opposed substrates. In some embodiments, the carbon nanotubes may be covered by a dielectric which may be adhered by functionalizing the carbon nanotubes. | 12-11-2008 |
| 20090004807 | PASSIVE ELEMENTS, ARTICLES, PACKAGES, SEMICONDUCTOR COMPOSITES, AND METHODS OF MANUFACTURING SAME - Systems and methods associated with semiconductor articles are disclosed, including forming a first layer of material on a substrate, etching trenches within regions defining a passive element in the first layer, forming metal regions on sidewalls of the trenches, and forming a region of dielectric or polymer material over or in the substrate. Moreover, an exemplary method may also include forming areas of metal regions on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the passive element(s) that are aligned substantially perpendicularly with respect to a primary plane of the substrate. Other exemplary embodiments may comprise various articles or methods including capacitive and/or inductive aspects, Titanium- and/or Tantalum-based resistive aspects, products, products by processes, packages and composites consistent with one or more aspects of the innovations set forth herein. | 01-01-2009 |
| 20090061587 | METHOD FOR FABRICATING CAPACITOR IN SEMICONDUCTOR DEVICE - A method for fabricating a capacitor includes providing a substrate having a capacitor region is employed, forming a first Ru | 03-05-2009 |
| 20090111234 | Method for forming min capacitor in a copper damascene interconnect - A method for forming a metal-insulator-metal capacitor in a multilevel semiconductor device utilizes the copper interconnect levels of the semiconductor device as parts of the capacitor. A lower capacitor plate consists of a copper interconnect level and a first metal layer formed on the copper interconnect level by selective deposition methods. The upper capacitor plate includes the same pattern as the capacitor dielectric, the pattern having an area less than the area of the lower capacitor plate. The upper capacitor plate is formed of a second metal layer. The first and second metal layers may each be formed of cobalt, tungsten, nickel, molybdenum, or a combinations of one of the aforementioned elements with boron and/or phosphorus. Conductive vias provide contact from the upper capacitor plate and lower capacitor plate, to interconnect levels. | 04-30-2009 |
| 20090117702 | Method of Forming an Inductor on a Semiconductor Wafer - A semiconductor device has a substrate with an inductor formed on its surface. First and second contact pads are formed on the substrate. A passivation layer is formed over the substrate and first and second contact pads. An insulating layer is formed over the passivation layer. The insulating layer is removed over the first contact pad, but not from the second contact pad. A metal layer is formed over the first contact pad. The metal layer is coiled on the surface of the substrate to produce inductive properties. The formation of the metal layer involves use of a wet etchant. The second contact pad is protected from the wet etchant by the insulating layer. The insulating layer is removed from the second contact pad after forming the metal layer over the first contact pad. An external connection is formed on the second contact pad. | 05-07-2009 |
| 20090130813 | Method and System to Provide a Polysilicon Capacitor with Improved Oxide Integrity - A system and method in accordance with the present invention allows for an improved oxide integrity of a polysilicon capacitor compared to capacitors manufactured using conventional semiconductor processing techniques. This is accomplished by moving the capacitor implant step to a time after the deposition of the polysilicon. As an additional benefit, a separate capacitor oxide growth does not need to be performed. | 05-21-2009 |
| 20090130814 | SEMICONDUCTOR METHODS - A method includes forming an amorphous carbon layer over a first dielectric layer formed over a substrate, forming a second dielectric layer over the amorphous carbon layer; and forming an opening within the amorphous carbon layer and second dielectric layer by a first etch process to partially expose a top surface of the first dielectric layer. A substantially conformal metal-containing layer is formed over the second dielectric layer and within the opening. The second dielectric layer and a portion of the metal-containing layer are removed. The amorphous carbon layer is removed by an oxygen-containing plasma process to expose a top surface of the first dielectric layer. An insulating layer is formed over the metal-containing layer, and a second metal-containing layer is formed over the insulating layer to form a capacitor. | 05-21-2009 |
| 20090170272 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - A semiconductor device includes a first insulating layer, a capacitor, an adhesive layer, and an intermediate layer. The first insulating layer may include a first insulating film. The first insulating layered structure has a first hole. The capacitor is disposed in the first hole. The capacitor may include bottom and top electrodes and a capacitive insulating film. The capacitive insulating film is sandwiched between the bottom and top electrodes. The adhesive layer contacts with the bottom electrode. The adhesive layer has adhesiveness to the bottom electrode. The intermediate layer is interposed between the adhesive layer and the first insulating film. The intermediate layer contacts with the adhesive layer and with the first insulating film. The intermediate layer has adhesiveness to the adhesive layer and to the first insulating film. | 07-02-2009 |
| 20090176345 | Process for producing thin-film capacitor - It is an object of the invention to provide a process for production of a thin-film capacitor that can simultaneously achieve improved capacity density and reduced leakage current density for barium strontium titanate thin-films. There is provided a process for production of thin-film capacitors that includes a metal oxide thin-film forming step in which an organic dielectric starting material is fired to form a barium strontium titanate thin-film, wherein the firing atmosphere used is an oxygen-containing inert gas atmosphere, and the barium strontium titanate thin-film formed by the process has a larger capacity density than the capacity density of the barium strontium titanate thin-film fired in an oxygen atmosphere. | 07-09-2009 |
| 20090275185 | METHODS OF FORMING CAPACITORS - A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across the opening, with a void being received within the opening above the shield and a void being received within the opening below the shield. The shield comprises a nitride. Etching is conducted within the opening through the nitride-comprising shield. After the etching, a first capacitor electrode is formed within the opening in electrical connection with the node location. A capacitor dielectric and a second capacitor electrode are formed operatively adjacent the first capacitor electrode. Other aspects and implementations are contemplated. | 11-05-2009 |
| 20090286377 | Methods of Forming Integrated Circuit Devices - The invention includes methods of forming semiconductor constructions and methods of forming pluralities of capacitor devices. An exemplary method of the invention includes forming conductive material within openings in an insulative material to form capacitor electrode structures. A lattice is formed in physical contact with at least some of the electrode structures, a protective cap is formed over the lattice, and subsequently some of the insulative material is removed to expose outer surfaces of the electrode structures. The lattice can alleviate toppling or other loss of structural integrity of the electrode structures, and the protective cap can protect covered portions of the insulative material from the etch. After the outer sidewalls of the electrode structures are exposed, the protective cap is removed. The electrode structures are then incorporated into capacitor constructions. | 11-19-2009 |
| 20090291542 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes: forming an etch stop pattern over a conductive layer, the etch stop pattern having a first opening exposing a top surface of the conductive layer; forming an insulation layer over the etch stop pattern; selectively etching the insulation layer to form a second opening exposing the top surface of the conductive layer; and enlarging the second opening until the etch stop pattern is exposed. | 11-26-2009 |
| 20090298251 | NORMAL PRESSURE AEROSOL SPRAY APPARATUS AND METHOD OF FORMING A FILM USING THE SAME - An aerosol spray apparatus and a method of forming a film using the aerosol spray apparatus are disclosed. The aerosol spray apparatus in accordance with an embodiment of the present invention includes: a carrier gas injection unit, which forms carrier gas by vaporizing liquefied gas and increases the pressure of the carrier gas; an aerosol forming unit, which forms an aerosol by mixing the carrier gas with powder; and a film forming unit, which sprays the aerosol in a normal pressure environment such that the film is formed on the surface of the board. The apparatus can perform a coating process with no restriction of the type and size of powder, simplify the process because the film can be formed in a normal temperature and pressure environment, and control a wide range of film thickness in a short time. | 12-03-2009 |
| 20090311841 | Method of Manufacturing a Through-Silicon-Via On-Chip Passive MMW Bandpass Filter - A method for forming a through-silicon via bandpass filter includes forming a substrate comprising a silicon layer and providing a metal layer on a bottom side of the silicon layer. Additionally, the method includes providing a dielectric layer on a top side of the silicon layer and forming a top-side interconnect of the through-silicon via bandpass filter on a surface of the dielectric layer. Further, the method includes forming a plurality of contacts in the dielectric layer in contact with the top-side interconnect and forming a plurality through-silicon vias through the substrate and in contact with the plurality of contacts, respectively, and the metal layer. | 12-17-2009 |
| 20100009508 | Methods of fabricating stack type capacitors of semiconductor devices - Provided are methods of fabricating capacitors of semiconductor devices, the methods including: forming a lower electrode on a semiconductor substrate, performing a pre-process operation on the lower electrode for suppressing deterioration of the lower electrode during a process, forming a dielectric layer on the lower electrode using a source gas and an ozone gas, and forming an upper electrode on the dielectric layer, wherein the pre-process operation and the forming of the dielectric layer may be performed in one device capable of atomic layer deposition. | 01-14-2010 |
| 20100009509 | DUAL-DAMASCENE PROCESS TO FABRICATE THICK WIRE STRUCTURE - A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer. | 01-14-2010 |
| 20100022063 | METHOD OF FORMING ON-CHIP PASSIVE ELEMENT - Various methods of forming a passive element such as an inductor raised off the surface of the substrate to improve the performance of the passive element are presented. A first wafer may be provided, and passive elements diced from a second wafer. The passive elements are flipped, and then aligned to be bonded on the first wafer such that the passive elements are raised a distance off the first wafer because of the presence of chip connections such as C4 solder bumps. A gap between the passive elements and the first wafer can be filled with underfill or air. If air is used, a hermetic seal around the gap can be created using chip connections such as C4 solder bumps or other known bonding means to seal the gap. | 01-28-2010 |
| 20100029054 | HAFNIUM TANTALUM OXIDE DIELECTRICS - A dielectric layer containing a hafnium tantalum oxide film and a method of fabricating such a dielectric layer produce a dielectric layer for use in a variety of electronic devices. Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectric layers containing a hafnium tantalum oxide film structured as one or more monolayers. | 02-04-2010 |
| 20100047988 | METHODS OF FORMING A LAYER, METHODS OF FORMING A GATE STRUCTURE AND METHODS OF FORMING A CAPACITOR - In a method of forming a layer, a precursor including a metal and a ligand coordinating to the metal is stabilized by contacting the precursor with an electron donating compound to provide a stabilized precursor into a substrate. A reactant is introduced into the substrate to bind to the metal in the stabilized precursor. The precursor stabilized by the electron donating compound has an improved thermal stability and thus the precursor is not dissociated at a high temperature atmosphere, and the layer having a uniform thickness is formed on the substrate. | 02-25-2010 |
| 20100047989 | CAPACITOR WITH ZIRCONIUM OXIDE AND METHOD FOR FABRICATING THE SAME - A capacitor with zirconium oxide and a method for fabricating the same are provided. The method includes: forming a storage node; forming a multi-layered dielectric structure on the storage node, the multi-layered dielectric structure including a zirconium oxide (ZrO | 02-25-2010 |
| 20100047990 | METHOD OF FABRICATING A HIGH Q FACTOR INTEGRATED CIRCUIT INDUCTOR - A method of forming an inductor. The method including: (a) forming a dielectric layer on a top surface of a substrate; after (a), (b) forming a lower trench in the dielectric layer; after (b), (c) forming a resist layer on a top surface of the dielectric layer; after (c), (d) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and after (d), (e) completely filling the lower trench and at least partially filling the upper trench with a conductor in order to form the inductor. | 02-25-2010 |
| 20100068864 | APPARATUS AND METHOD FOR WAFER LEVEL FABRICATION OF HIGH VALUE INDUCTORS ON SEMICONDUCTOR INTEGRATED CIRCUITS - Methods for forming multiple inductors on a semiconductor wafer are described. A plating layer and a photoresist layer are applied over a semiconductor wafer. Recess regions are etched in the photoresist layer using photolithographic techniques, which exposes portions of the underlying plating layer. Metal is electroplated into the recess regions in the photoresist layer to form multiple magnetic core inductor members. A dielectric insulating layer is applied over the magnetic core inductor members. Additional plating and photoresist layers are applied over the dielectric insulating layer. Recess regions are formed in the newly applied photoresist layer. Electroplating is used to form inductor windings in the recess regions. Optionally, a magnetic paste can be applied over the inductor coils. | 03-18-2010 |
| 20100105186 | Methods For Forming Semiconductor Constructions, And Methods For Selectively Etching Silicon Nitride Relative To Conductive Material - The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containers over a semiconductor substrate, with such containers having upwardly-extending openings with lateral widths of less than or equal to about 4000 angstroms; and the silicon nitride can be in the form of a layer extending between the containers. The selective etching can comprise exposure of at least some of the silicon nitride and the containers to Cl | 04-29-2010 |
| 20100112773 | PIXEL STRUCTURE AND METHOD FOR FORMING THE SAME - A pixel structure comprising at least one transistor, a first storage capacitor, a first conductive layer, an interlayer dielectric layer, a second conductive layer, a passivation layer, and a third conductive layer is provided. The first storage capacitor is electrically connected to the transistor. The interlayer dielectric layer having at least one first opening covers the first conductive layer. The second conductive layer is formed on a part of the interlayer dielectric layer and is electrically connected to the first conductive layer through the first opening. The passivation layer having at least one second opening covers the transistor and the second conductive layer. The third conductive layer is formed on a part of the passivation layer and is electrically connected to the transistor through the second opening. The first storage capacitor is formed by the third conductive layer, the passivation layer, and the second conductive layer. | 05-06-2010 |
| 20100129976 | Methods of Fabricating Electromechanical Non-Volatile Memory Devices - Electromechanical non-volatile memory devices are provided including a semiconductor substrate having an upper surface including insulation characteristics. A first electrode pattern is provided on the semiconductor substrate. The first electrode pattern exposes portions of a surface of the semiconductor substrate therethrough. A conformal bit line is provided on the first electrode pattern and the exposed surface of semiconductor substrate. The bit line is spaced apart from a sidewall of the first electrode pattern and includes a conductive material having an elasticity generated by a voltage difference. An insulating layer pattern is provided on an upper surface of the bit line located on the semiconductor substrate. A second electrode pattern is spaced apart from the bit line and provided on the insulating layer pattern. The second electrode pattern faces the first electrode pattern. Related methods are also provided. | 05-27-2010 |
| 20100173468 | PASSIVE ELEMENTS, ARTICLES, PACKAGES, SEMICONDUCTOR COMPOSITES, AND METHODS OF MANUFACTURING SAME - Systems and methods associated with semiconductor articles are disclosed, including forming a first layer of material on a substrate, etching trenches within regions defining a passive element in the first layer, forming metal regions on sidewalls of the trenches, and forming a region of dielectric or polymer material over or in the substrate. Moreover, an exemplary method may also include forming areas of metal regions on the sidewalls of the trenches such that planar strip portions of the areas form electrically conductive regions of the passive element(s) that are aligned substantially perpendicularly with respect to a primary plane of the substrate. Other exemplary embodiments may comprise various articles or methods including capacitive and/or inductive aspects, Titanium- and/or Tantalum-based resistive aspects, products, products by processes, packages and composites consistent with one or more aspects of the innovations set forth herein. | 07-08-2010 |
| 20100190310 | Gap-filling composition with excellent shelf life by end-capping - A composition with improved shelf life for filling small gaps in a semiconductor device is provided. The composition comprises an end-capped silicone polymer. The molecular weight of the end-capped silicone polymer is not varied during storage. In addition, the dissolution rate (DR) of the composition in an alkaline developing solution is maintained at a desired level during storage. That is, the composition is highly stable during storage. Therefore, the composition is suitable for use in a node separation process for the fabrication of a semiconductor capacitor. | 07-29-2010 |
| 20100190311 | Method of Forming a MEMS Topped Integrated Circuit with a Stress Relief Layer - The bow in a wafer that results from fabricating a large number of MEMS devices on the top surface of the passivation layer of the wafer so that a MEMS device is formed over each die region is reduced by forming a stress relief layer between the passivation layer and the MEMS devices. | 07-29-2010 |
| 20100190312 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - To provide a semiconductor device which is higher functional and reliable and a technique capable of manufacturing the semiconductor device with a high yield at low cost without complexing the apparatus or process. At least one of a first conductive layer and a second conductive layer is formed containing one kind or plural kinds of indium, tin, lead, bismuth, calcium, manganese, or zinc; or oxidation treatment is performed at least one of interfaces between an organic compound layer and the first conductive layer and between the organic compound layer and the second conductive layer. The first conductive layer, the organic compound layer, and the second conductive layer which are formed over a first substrate with a peeling layer interposed therebetween can be peeled from the first substrate with the peeling layer, and transposed to a second substrate. | 07-29-2010 |
| 20100197104 | PROGRAMMABLE METALLIZATION MEMORY CELLS VIA SELECTIVE CHANNEL FORMING - Methods for making a programmable metallization memory cell are disclosed. | 08-05-2010 |
| 20100203699 | Method of forming semiconductor device - Provided may be a method of forming a semiconductor device. The method may include performing a pre-anisotropic etching process on a dielectric layer exposed by a guide opening, performing an etch-back process on a mask layer and performing a post anisotropic etching process through a guide opening using the etched mask layer as an etching mask. | 08-12-2010 |
| 20100210087 | Methods of Manufacturing Semiconductor Devices Having Contact Plugs in Insulation Layers - Methods of manufacturing semiconductor devices are provided in which a first contact plug is formed on a first active region in a substrate and a second contact plug is formed on a second active region in the substrate. A height of an upper surface of the second contact plug from the substrate is greater than a height of an upper surface of the first contact plug from the substrate. A third contact plug is formed on the second contact plug. A first spacer is formed on a side surface of the third contact plug. A third interlayer insulation layer is formed that covers the third contact plug. The third interlayer insulation layer is patterned to form a third opening that exposes the first contact plug. A fourth contact plug is formed in the third opening that is electrically connected to the first contact plug. | 08-19-2010 |
| 20100227448 | SEMICONDUCTOR DEVICE WITH CONTACT STABILIZATION BETWEEN CONTACT PLUGS AND BIT LINES AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate divided into a cell array region, a core region, and a peripheral region. Bit lines are formed in the respective regions. Storage node contact plugs are formed in the cell array region, and blocking patterns are simultaneously formed around the bit lines of the core region and the peripheral region. Capacitors are formed in the cell array region to come into contact with the storage node contact plugs, and metal contact plugs are formed to come into contact with the capacitors of the cell array region and the bit lines of the core region and the peripheral region. In the semiconductor device, even if the metal contact plugs are not aligned with the bit lines, the blocking pattern works to stabilize the contact between the metal contact plugs and the bit lines. | 09-09-2010 |
| 20100233865 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - Provided is a semiconductor device manufacturing method for a capacitor having a dielectric film which can be formed into a thin film, can be formed at a low temperature, and has a readily controllable property. The manufacturing method includes: forming an oxide film or an oxynitride film on a conductor for serving as one electrode of a capacitor; forming, on the oxide film or the oxynitride film, a manganese oxide film for serving as a dielectric film of the capacitor; and forming, on the manganese oxide film, a conductive film for serving as the other electrode of the capacitor. | 09-16-2010 |
| 20100240188 | METHOD FOR FABRICATING CAPACITOR - A method for fabricating a capacitor includes: forming a storage node contact plug over a substrate; forming an insulation layer having an opening exposing a surface of the storage node contact plug over the storage contact plug; forming a conductive layer for a storage node over the insulation layer and the exposed surface of the storage node contact plug through two steps performed at different temperatures; performing an isolation process to isolate parts of the conductive layer; and sequentially forming a dielectric layer and a plate electrode over the isolated conductive layer. | 09-23-2010 |
| 20100261329 | MEMORY DEVICE HAVING WIDE AREA PHASE CHANGE ELEMENT AND SMALL ELECTRODE CONTACT AREA - A memory cell device of the type that includes a memory material switchable between electrical property states by application of energy, situated between first and second (“bottom” and “top”) electrodes has a top electrode including a larger body portion and a stem portion. The memory material is disposed as a layer over a bottom electrode layer, and a base of the stem portion of the top electrode is in electrical contact with a small area of the surface of the memory material. Methods for making the memory cell are described. | 10-14-2010 |
| 20100267214 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - According to the method for manufacturing a semiconductor device, a surface of a lower, insulating film ( | 10-21-2010 |
| 20100297824 | MEMORY STRUCTURE WITH REDUCED-SIZE MEMORY ELEMENT BETWEEN MEMORY MATERIAL PORTIONS - A memory cell device includes a memory cell access layer, a dielectric material over the memory cell access layer, a memory material structure within the dielectric material, and a top electrode in electrical contact with the memory material structure. The memory material structure has upper and lower memory material portions and a memory material element therebetween. The lower memory material layer is in electrical contact with a bottom electrode. The lower memory material layer has an average lateral dimension. The memory material element defines an electrical property state change region therein and has a minimum lateral dimension which is substantially less than the average lateral dimension. In some examples the memory material element is a tapered structure with the electrical property state change region at the junction of the memory material element and the lower memory material layer. | 11-25-2010 |
| 20100323489 | Method of forming a vertical diode and method of manufacturing a semiconductor device using the same - A method of forming a vertical diode and a method of manufacturing a semiconductor device (e.g., a semiconductor memory device such as a phase-change memory device) includes forming an insulating structure having an opening on a substrate and filling the opening with an amorphous silicon layer. A metal silicide layer is formed to contact at least a portion of the amorphous silicon layer and a polysilicon layer is then formed in the opening by crystallizing the amorphous silicon layer using the metal silicide layer. A doped polysilicon layer is formed by implanting impurities into the polysilicon layer. Thus, the polysilicon layer is formed in the opening without performing a selective epitaxial growth (SEG) process, so that electrical characteristics of the diode may be improved. | 12-23-2010 |
| 20100323490 | Self-Aligned Cross-Point Memory Fabrication - Fabricating a cross-point memory structure using two lithography steps with a top conductor and connector or memory element and a bottom conductor orthogonal to the top connector. A first lithography step followed by a series of depositions and etching steps patterns a first channel having a bottom conductor. A second lithography step followed by a series of depositions and etching steps patterns a second channel orthogonal to the first channel and having a memory element connecting the an upper conductor and the lower conductor at their overlaid intersections. | 12-23-2010 |
| 20100323491 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Any of a plurality of contact plugs which reaches a diffusion layer serving as a drain layer of an MOS transistor has an end provided in contact with a lower surface of a thin insulating film provided selectively on an interlayer insulating film. A phase change film constituted by GST to be a chalcogenide compound based phase change material is provided on the thin insulating film, and an upper electrode is provided thereon. Any of the plurality of contact plugs which reaches the diffusion layer serving as a source layer has an end connected directly to an end of a contact plug penetrating an interlayer insulating film. | 12-23-2010 |
| 20100330766 | Method for Producing a Plurality of Integrated Semiconductor Components - A method for producing a plurality of integrated semiconductor components on a carrier, in which an active basic structure is introduced into the carrier in a continuous fashion at least across a portion of the boundaries of the semiconductor components to be created. The regions of the semiconductor components on the carrier are defined, and a covering layer is applied to the carrier in the region of each semiconductor component with the aid of a mask. The carrier is severed to form the individual semiconductor components at the boundaries thereof. | 12-30-2010 |
| 20100330767 | MOSFET with a second poly and an inter-poly dielectric layer over gate for synchronous rectification - This invention discloses a new trenched vertical semiconductor power device that includes a capacitor formed between a conductive layer covering over an inter-dielectric layer disposed on top of a trenched gate. In a specific embodiment, the trenched vertical semiconductor power device may be a trenched metal oxide semiconductor field effect transistor (MOSFET) power device. The trenched gate is a trenched polysilicon gate and the conductive layer is a second polysilicon layer covering an inter-poly dielectric layer disposed on top of the trenched polysilicon gate. The conductive layer is further connected to a source of the vertical power device. | 12-30-2010 |
| 20100330768 | METHODS FOR ETCHING DOPED OXIDES IN THE MANUFACTURE OF MICROFEATURE DEVICES - Methods for selectively etching doped oxides in the manufacture of microfeature devices are disclosed herein. An embodiment of one such method for etching material on a microfeature workpiece includes providing a microfeature workpiece including a doped oxide layer and a nitride layer adjacent to the doped oxide layer. The method include selectively etching the doped oxide layer with an etchant comprising DI:HF and an acid to provide a pH of the etchant such that the etchant includes (a) a selectivity of phosphosilicate glass (PSG) to nitride of greater than 250:1, and (b) an etch rate through PSG of greater than 9,000 Å/minute. | 12-30-2010 |
| 20100330769 | Semiconductor device and method of manufacturing thereof - A semiconductor device has a semiconductor substrate, and a capacitor which is provided on the upper side of the semiconductor substrate and composed of a lower electrode, an upper electrode and a dielectric film, the dielectric film being placed in between the lower electrode and the upper electrode, the lower electrode including a noble metal film, and a plurality of conductive oxide films formed in an islands arrangement on the noble metal film. | 12-30-2010 |
| 20110003453 | MANUFACTURING METHOD OF CAPACITOR IN SEMICONDUCTOR - A manufacturing method of a capacitor of a semiconductor device includes a first step of forming a graphene seed film over a substrate; a second step of increasing surface energy of the graphene seed film and performing a first plasma process to the graphene seed film; a third step of growing a graphene on the graphene seed film; a fourth step of growing a nano tube or a nano wire using the graphene as a mask; and a fifth step of sequentially forming a dielectric film and a conductive layer over the nano tube or the nano wire. | 01-06-2011 |
| 20110003454 | LATERAL PHASE CHANGE MEMORY - A lateral phase change memory includes a pair of electrodes separated by an insulating layer. The first electrode is formed in an opening in an insulating layer and is cup-shaped. The first electrode is covered by the insulating layer which is, in turn, covered by the second electrode. As a result, the spacing between the electrodes may be very precisely controlled and limited to very small dimensions. The electrodes are advantageously formed of the same material, prior to formation of the phase change material region. | 01-06-2011 |
| 20110008945 | Nonvolatile memory device made of resistance material and method of fabricating the same - A nonvolatile memory device using a resistance material and a method of fabricating the same are provided. The nonvolatile memory device includes a switching element, and a data storage part electrically connected to the switching element. In the data storage part, a lower electrode is connected to the switching element, and an insulating layer is formed on the lower electrode to a predetermined thickness. The insulating layer has a contact hole exposing the lower electrode. A data storage layer is filled in the contact hole and the data storage layer is formed of transition metal oxide. An upper electrode is formed on the insulating layer and the data storage layer. | 01-13-2011 |
| 20110014770 | Methods of forming a dielectric thin film of a semiconductor device and methods of manufacturing a capacitor having the same - A method of forming a dielectric thin film of a semiconductor device, the method including supplying a first nuclear atom precursor source and a second nuclear atom precursor source having different thermal decomposition temperatures to a substrate and forming a chemical adsorption layer including first nuclear atoms and second nuclear atoms on the substrate. A reactant including oxygen atoms may be supplied to the substrate on which the chemical adsorption layer is formed. An atomic layer including an oxide of the first nuclear atoms and the second nuclear atoms may be formed on the chemical adsorption layer. | 01-20-2011 |
| 20110020998 | METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING A METAL ALLOY ELECTRODE - A semiconductor device includes an electrode having a metal silicide layer and a metal alloy layer, and a data storage element formed on the electrode. The metal silicide layer has a concave surface to correspond to a convex surface of the metal alloy layer such that the concave surface of the metal silicide layer and the convex surface of the metal alloy layer form a curved boundary. | 01-27-2011 |
| 20110020999 | Methods of Forming Dielectric Material-Containing Structures - Some embodiments include dielectric structures. The structures include first and second portions that are directly against one another. The first portion may contain a homogeneous mixture of a first phase and a second phase. The first phase may have a dielectric constant of greater than or equal to 25, and the second phase may have a dielectric constant of less than or equal to 20. The second portion may be entirely a single composition having a dielectric constant of greater than or equal to 25. Some embodiments include electrical components, such as capacitors and transistors, containing dielectric structures of the type described above. Some embodiments include methods of forming dielectric structures, and some embodiments include methods of forming electrical components. | 01-27-2011 |
| 20110027960 | Methods of Forming Strontium Titanate Films - Embodiments of the current invention include methods of forming a strontium titanate (SrTiO | 02-03-2011 |
| 20110034002 | SYSTEMS AND METHODS TO LAMINATE PASSIVES ONTO SUBSTRATE - A method may include depositing a dielectric layer onto a substrate, removing portions of the dielectric layer to create a plurality of separated non-removed portions of the dielectric layer, depositing one or more passive electronic components into each of the plurality of separated non-removed portions, and curing the separated non-removed portions of the dielectric layer. | 02-10-2011 |
| 20110053332 | SEMICONDUCTOR CIRCUIT - A semiconductor memory device includes a substrate and an interconnect region carried by the substrate. A donor layer is coupled to the interconnect region through a bonding interface. An electronic device is formed with the donor layer, wherein the electronic device is formed after the bonding interface is formed. A capacitor is connected to the electronic device so that the electronic device and capacitor operate as a dynamic random access memory device. | 03-03-2011 |
| 20110053333 | PHASE CHANGE MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME - Phase change memory devices and methods for manufacturing the same are provided. An exemplary embodiment of a phase change memory device includes a bottom electrode formed over a substrate. A first dielectric layer is formed over the bottom electrode. A heating electrode is formed in the first dielectric layer and partially protrudes over the first dielectric layer, wherein the heating electrode includes an intrinsic portion embedded within the first dielectric layer, a reduced portion stacked over the intrinsic portion, and an oxide spacer surrounding a sidewall of the reduced portion. A phase change material layer is formed over the first dielectric layer and covers the heating electrode, the phase change material layer contacts a top surface of the reduced portion of the heating electrode. A top electrode is formed over the phase change material layer and contacts the phase change material layer. | 03-03-2011 |
| 20110053334 | PHASE CHANGE MEMORY DEVICE WITH HEATER ELECTRODES HAVING FINE CONTACT AREA AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device includes a semiconductor substrate having a conductive region, a heater electrode formed on the semiconductor substrate and including a connection element which is composed of carbon nanotubes electrically connected with the conductive region, and a phase change pattern layer contacting the connection element of the heater electrode. | 03-03-2011 |
| 20110059590 | METHOD FOR FORMING A REDUCED ACTIVE AREA IN A PHASE CHANGE MEMORY STRUCTURE - A phase change memory structure and method for forming the same, the method including providing a substrate comprising a conductive area; forming a spacer having a partially exposed sidewall region at an upper portion of the spacer defining a phase change memory element contact area; and, wherein the spacer bottom portion partially overlaps the conductive area. Both these two methods can reduce active area of a phase change memory element, therefore, reducing a required phase changing electrical current. | 03-10-2011 |
| 20110059591 | PHASE CHANGE MEMORY DEVICE HAVING DIELECTRIC LAYER FOR ISOLATING CONTACT STRUCTURE FORMED BY GROWTH, SEMICONDUCTOR DEVICE HAVING THE SAME, AND METHODS FOR MANUFACTURING THE DEVICES - A phase change memory device includes a semiconductor substrate having an impurity region and an interlayer dielectric applying a tensile stress formed on the semiconductor substrate and having contact holes exposing the impurity region. Switching elements are formed in the contact holes; and sidewall spacers interposed between the switching elements and the interlayer dielectric and formed as a dielectric layer applying a compressive stress. | 03-10-2011 |
| 20110065251 | METHOD FOR FABRICATING STORAGE NODE ELECTRODE IN SEMICONDUCTOR DEVICE - A method for fabricating a storage node electrode in a semiconductor device includes: performing a primary high density plasma (HDP) process to form a first HDP oxide film over an etch stop film; performing a secondary HDP process to form a second HDP oxide film on the first HDP oxide film; forming a support film over the second HDP oxide film; performing a tertiary HDP process to form a third HDP oxide film over the support film; forming a storage node electrode on an exposed surface of the storage node contact hole; partially removing the third HDP oxide film and the support film so that a support pattern supporting the storage node electrode is formed; and exposing an outer surface of the storage node electrode by removing the second HDP oxide film and the first HDP oxide film. | 03-17-2011 |
| 20110070711 | METHOD FOR MANUFACTURING NANO-CRYSTALLINE SILICON MATERIAL FROM CHLORIDE CHEMISTRIES FOR THE SEMICONDUCTOR INTEGRATED CIRCUITS - A method for forming a nanocrystalline silicon structure for the manufacture of integrated circuit devices, e.g., memory, dynamic random access memory, flash memory, read only memory, microprocessors, digital signal processors, application specific integrated circuits. The method includes providing a semiconductor substrate including a surface region. The method forms an insulating layer (e.g., silicon dioxide, silicon nitride, silicon oxynitride) overlying the surface region. In a specific embodiment, the method includes forming an amorphous silicon material of a determined thickness of less than twenty nanometers overlying the insulating layer using a chloro-silane species. The method includes subjecting the amorphous silicon material to a thermal treatment process to cause formation of a plurality of nanocrsytalline silicon structures derived from the thickness of amorphous silicon material less than twenty nanometers. | 03-24-2011 |
| 20110076824 | FABRICATION METHOD OF PHASE CHANGE RANDOM ACCESS MEMORY DEVICE - A method of fabricating a phase change random access memory device includes forming a sacrificial layer of a predetermined height within a bottom electrode contact hole. The method also includes forming an insulating layer on a whole resultant structure including the bottom electrode contact hole. The method also includes forming a spacer on a sidewall of the bottom electrode contact hole by etching the insulating layer and removing the sacrificial layer. | 03-31-2011 |
| 20110076825 | Method for Making a Self Aligning Memory Device - A self aligning memory device, with a memory element switchable between electrical property states by the application of energy, includes a substrate and word lines, at least the sides of the word lines covered with a dielectric material which defines gaps. An access device within a substrate has a first terminal under a second gap and second terminals under first and third gaps. First and second source lines are in the first and third gaps and are electrically connected to the second terminals. A first electrode in the second gap is electrically connected to the first terminal. A memory element in the second gap is positioned over and electrically connected to the first electrode. A second electrode is positioned over and contacts the memory element. The first contact, the first electrode, the memory element and the second electrode are self aligning. A portion of the memory element may have a sub lithographically dimensioned width. | 03-31-2011 |
| 20110086486 | Methods of Forming Integrated Circuit Chips Having Vertically Extended Through-Substrate Vias Therein - Methods of forming an integrated circuit device include forming an interlayer dielectric layer on a first surface of a semiconductor substrate and then forming an interconnect hole that extends through the interlayer dielectric layer and into the semiconductor substrate. A first sidewall spacer layer is formed on a sidewall of the interconnect hole. The semiconductor substrate at a bottom of the interconnect hole is isotropically etched to define an undercut recess in the semiconductor substrate. This etching step is performed using the first sidewall spacer layer as an etching mask. The interconnect hole and the uncut recess are then filled with a through-via electrode. A second surface of the semiconductor substrate is removed for a sufficient duration to expose the uncut recess containing the through-via electrode. | 04-14-2011 |
| 20110086487 | Semiconductor Device with Reduced Capacitance Tolerance Value - A semiconductor device includes a capacitance, the numerical value of which is relevant for a device function. The capacitance is formed from a parallel connection of at least a first and a second capacitor element, wherein the first and second capacitor elements are formed in respective manufacturing steps that exhibit uncorrelated process fluctuations. | 04-14-2011 |
| 20110092041 | Phase Change Memory with Diodes Embedded in Substrate - An integrated circuit structure includes a semiconductor substrate; a diode; and a phase change element over and electrically connected to the diode. The diode includes a first doped semiconductor region of a first conductivity type, wherein the first doped semiconductor region is embedded in the semiconductor substrate; and a second doped semiconductor region over and adjoining the first doped semiconductor region, wherein the second doped semiconductor region is of a second conductivity type opposite the first conductivity type. | 04-21-2011 |
| 20110117715 | Methods of Forming Capacitors For Semiconductor Memory Devices - A capacitor of a semiconductor memory device, and methods of forming the same, are disclosed. A pad interlayer insulating layer is disposed on a semiconductor substrate of an active region. Landing pads and a central landing pad are disposed in peripheral portions and a central portion of the active region, respectively, to penetrate the pad interlayer insulating layer. The upper surface of the central landing pad has a different area from the upper surfaces of the landing pads. A buried interlayer insulating layer is formed on the pad interlayer insulating layer to cover the landing pads and the central landing pad. Buried plugs are formed on the respective landing pads to penetrate the buried interlayer insulating layer. Lower electrodes are formed on the buried plugs. | 05-19-2011 |
| 20110117716 | PROGRAMMABLE CAPACITOR ASSOCIATED WITH AN INPUT/OUTPUT PAD - The present invention provides a method and apparatus for a programmable capacitor associated with an input/output pad in the semiconductor device. The apparatus includes a semiconductor die having an upper surface, a first capacitor deployed above the upper surface of the semiconductor die, a separation layer deployed above the first capacitor, and a bond pad deployed above the separation layer such that at least a portion of the bond pad lies above the first capacitor. | 05-19-2011 |
| 20110117717 | PROGRAMMABLE RESISTIVE MEMORY CELL WITH FILAMENT PLACEMENT STRUCTURE - Programmable metallization memory cells having a first metal contact and a second metal contact with an ion conductor solid electrolyte material between the metal contacts. The first metal contact has a filament placement structure thereon extending into the ion conductor material. In some embodiments, the second metal contact also has a filament placement structure thereon extending into the ion conductor material toward the first filament placement structure. The filament placement structure may have a height of at least about 2 nm. | 05-19-2011 |
| 20110129981 | FILLER FOR FILLING A GAP AND METHOD FOR MANUFACTURING SEMICONDUCTOR CAPACITOR USING THE SAME - A filler for filling a gap includes a hydrogenated polysiloxazane having an oxygen content of about 0.2 to about 3 wt %. A chemical structure of the hydrogenated polysiloxazane includes first, second, and third moieties represented by the following respective Chemical Formulas 1-3: | 06-02-2011 |
| 20110136315 | Multi-Level Phase Change Memory - A phase change memory may be formed which is amenable to multilevel programming. The phase change material may be formed with a lateral extent which does not exceed the lateral extent of an underlying heater. As a result, the possibility of current bypassing the amorphous phase change material in the reset state is reduced, reducing the programming current that is necessary to prevent this situation. In addition, a more controllable multilevel phase change memory may be formed in some embodiments. | 06-09-2011 |
| 20110143514 | MRAM cell structure - Disclosed herein is an improved memory device, and related methods of manufacturing, wherein the area occupied by a conventional landing pad is significantly reduced to around 50% to 10% of the area occupied by conventional landing pads. This is accomplished by removing the landing pad from the cell structure, and instead forming a conductive via structure that provides the electrical connection from the memory stack or device in the structure to an under-metal layer. By forming only this via structure, rather than separate vias formed on either side of a landing pad, the overall width occupied by the connective via structure from the memory stack to an under-metal layer is substantially reduced, and thus the via structure and under-metal layer may be formed closer to the memory stack (or conductors associated with the stack) so as to reduce the overall width of the cell structure. | 06-16-2011 |
| 20110151639 | SEMICONDUCTOR DEVICE, METHOD OF FABRICATING THE SAME, SEMICONDUCTOR MODULE, ELECTRONIC CIRCUIT BOARD, AND ELECTRONIC SYSTEM INCLUDING THE DEVICE - Provided are a semiconductor device, a method of fabricating the same, and a semiconductor module, an electronic circuit board, and an electronic system including the device. The semiconductor device includes a lower electrode, a rutile state lower vanadium dioxide layer on the lower electrode, a rutile state titanium oxide on the lower vanadium dioxide layer, and an upper electrode on the titanium oxide layer. | 06-23-2011 |
| 20110151640 | COMPOUND FOR FILLING SMALL GAPS IN A SEMICONDUCTOR DEVICE, COMPOSITION INCLUDING THE COMPOUND, AND METHOD OF FABRICATING A SEMICONDUCTOR CAPACITOR - A compound for filling small gaps in a semiconductor device, a composition for filling small gaps in a semiconductor device, and a method of fabricating a semiconductor capacitor, the compound including hydrolysates prepared by hydrolysis, in the presence of an acid catalyst, of compounds represented by Formulae 1, 2, and 3: | 06-23-2011 |
| 20110159660 | Methods of Forming Integrated Circuit Capacitors Having Sidewall Supports and Capacitors Formed Thereby - In a method of forming a capacitor, a first mold layer pattern including a first insulating material may be formed on a substrate. The first mold layer pattern may have a trench. A supporting layer including a second insulating material may be formed in the trench. The second insulating material may have an etching selectivity with respect to the first insulating material. A second mold layer may be formed on the first mold layer pattern and the supporting layer pattern. A lower electrode may be formed through the second mold layer and the first mold layer pattern. The lower electrode may make contact with a sidewall of the supporting layer pattern. The first mold layer pattern and the second mold layer may be removed. A dielectric layer and an upper electrode may be formed on the lower electrode and the supporting layer pattern. | 06-30-2011 |
| 20110165751 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device which previously form sidewalls between lower electrodes to prevent bunkers and leaning phenomena during a sacrificial layer dip out process, thereby improving characteristic of the device, is provided. The method includes forming a mesh pattern defining a storage node region over a semiconductor substrate, forming a lower electrode over the semiconductor substrate and sidewalls of the mesh pattern, forming a dielectric layer over the semiconductor substrate including the lower electrode, and forming an upper electrode over the dielectric layer. | 07-07-2011 |
| 20110165752 | PHASE CHANGE MEMORY DEVICE CAPABLE OF INCREASING SENSING MARGIN AND METHOD FOR MANUFACTURING THE SAME - A phase change memory device capable of increasing a sensing margin and a method for manufacturing the same. The phase change memory device includes a semiconductor substrate formed with a device isolation structure which defines active regions; first conductivity type impurity regions formed in surfaces of the active regions and having the shape of a line; a second conductivity type well formed in the semiconductor substrate at a position lower than the device isolation structure; a second conductivity type ion-implantation layer formed in the semiconductor substrate at a boundary between a lower end of the device isolation structure and the semiconductor substrate; a plurality of vertical PN diodes formed on the first conductivity type impurity regions; and phase change memory cells formed on the vertical PN diodes. | 07-07-2011 |
| 20110165753 | Method for Making Self Aligning Pillar Memory Cell Device - A method for making a memory cell assembly includes forming a memory cell access layer over a substrate to create an access device with a bottom electrode. A memory material layer is formed over the memory cell access layer in electrical contact with the bottom electrode. A first electrically conductive layer is formed over the memory material layer. A first mask, extending in a first direction, is formed over the first electrically conductive layer and then trimmed so that those portions of the first electrically conductive layer and the memory material layer not covered by the first mask are removed. | 07-07-2011 |
| 20110171806 | Integrated electronic device and method of making the same - An integrated electronic device includes a substrate, passive components, pads for external connection, and three-dimensional wiring. The passive components includes a multi-stage coil inductor provided on the substrate. The multi-stage coil inductor has a plurality of coils disposed in several layers. Mutually adjacent coil wires are spaced-apart from each other. The three-dimensional wiring includes a first wiring portion which extends on the substrate, a second wiring portion which extends off the substrate but along the substrate, and a third wiring portion connecting with the first wiring portion and the second wiring portion. | 07-14-2011 |
| 20110171807 | METHOD FOR FABRICATING CAPACITOR - A method for fabricating a capacitor includes forming an isolation layer over a cell region and a peripheral region of a substrate. The isolation layer forms a plurality of open regions in the cell region. Storage nodes are formed on surfaces of the open regions. An upper portion of the isolation layer is etched to expose upper outer walls of the storage nodes. A sacrificial pattern is formed over the isolation layer to enclose the upper outer walls of the storage nodes. The isolation layer in the peripheral region is etched to expose side portions of the resulting structure obtained after forming the sacrificial pattern in the cell region. With the sacrificial pattern supporting the storage nodes, the isolation layer in the cell region is removed. The sacrificial pattern is then removed. | 07-14-2011 |
| 20110171808 | METHOD FOR FABRICATING A CAPACITOR - A method for fabricating a capacitor includes forming an isolation layer over a cell region and a peripheral region of a substrate. The isolation layer forms a plurality of open regions in the cell region. Storage nodes are formed on surfaces of the open regions. A sacrificial pattern is formed over the isolation layer and covers the cell region. The isolation layer is etched in the peripheral region to expose side portions of the resulting structure obtained after forming the sacrificial pattern in the cell region. With the sacrificial pattern supporting the storage nodes, the isolation layer in the cell region is removed. The sacrificial pattern is then removed. | 07-14-2011 |
| 20110171809 | METHOD FOR FABRICATING HIGH DENSITY PILLAR STRUCTURES BY DOUBLE PATTERNING USING POSITIVE PHOTORESIST - A method of making a semiconductor device includes forming a first photoresist layer over an underlying layer, patterning the first photoresist layer into a first photoresist pattern, wherein the first photoresist pattern comprises a plurality of spaced apart first photoresist features located over the underlying layer, and etching the underlying layer using the first photoresist pattern as a mask to form a plurality of first spaced apart features. The method further includes removing the first photoresist pattern, forming a second photoresist layer over the plurality of first spaced apart features, and patterning the second photoresist layer into a second photoresist pattern, wherein the second photoresist pattern comprises a plurality of second photoresist features covering edge portions of the plurality of first spaced apart features. The method also includes etching exposed portions of the plurality of first spaced apart features using the second photoresist pattern as a mask, such that a plurality of spaced apart edge portions of the plurality of first spaced apart features remain, and removing the second photoresist pattern. | 07-14-2011 |
| 20110183488 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method for forming a semiconductor device includes the following processes. A substrate structure having an insulating upper surface is formed. The insulating upper surface has a step. An insulating layer is formed over the insulating upper surface. The insulating layer covers the step. The insulating layer includes first and second portions which are bounded by the step. The first portion is thinner than the second portion. First and second grooves are formed in the first and second portions, respectively. The first groove is shallower than the second groove. First and second conductive films which fill up the first and second grooves, respectively are formed. The first conductive film is thinner than the second conductive film. | 07-28-2011 |
| 20110189832 | Phase Change Material Memory Device - A lower electrode may be covered by a protective film to reduce the exposure of the lower electrode to subsequent processing steps or the open environment. As a result, materials that may have advantageous properties as lower electrodes may be utilized despite the fact that they may be sensitive to subsequent processing steps or the open environment. | 08-04-2011 |
| 20110207283 | HIGH TEMPERATURE ATOMIC LAYER DEPOSITION OF DIELECTRIC OXIDES - Methods are provided herein for forming metal oxide thin films by atomic layer deposition. The metal oxide thin films can be deposited at high temperatures such that the thin film is crystalline as deposited. The metal oxide thin films can be used, for example, as dielectric oxides in transistors, flash devices, capacitors, integrated circuits, and other semiconductor applications. | 08-25-2011 |
| 20110207284 | SOLID-STATE MEMORY MANUFACTURING METHOD - A method of at least one embodiment of the present invention of manufacturing a solid-state memory is a method of manufacturing a solid-state memory, the solid-state memory including a recording film whose electric characteristics are varied by phase transformation, the method including: forming the recording film by forming a laminate of two or more layers so that a superlattice structure is provided, each of the layers having a parent phase which shows solid-to-solid phase-transformation, the recording film being formed at a temperature not lower than a temperature highest among crystallization temperatures of the parent phases. It is thus possible to manufacture a solid-state memory which requires lower current for recording and erasing data and has a greater rewriting cycle number. | 08-25-2011 |
| 20110212593 | CMP Process Flow for MEMS - The present invention generally relates to the formation of a micro-electromechanical system (MEMS) cantilever switch in a complementary metal oxide semiconductor (CMOS) back end of the line (BEOL) process. The cantilever switch is formed in electrical communication with a lower electrode in the structure. The lower electrode may be either blanket deposited and patterned or simply deposited in vias or trenches of the underlying structure. The excess material used for the lower electrode is then planarized by chemical mechanical polishing or planarization (CMP). The cantilever switch is then formed over the planarized lower electrode. | 09-01-2011 |
| 20110217822 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method is described for manufacturing a semiconductor device. The method can form a conductive layer including tungsten on a foundation layer. The method can form a trench by selectively etching the conductive layer. The trench is shallower than a depth from a surface of the conductive layer to the foundation layer. The method can form a protective film on a side surface and a bottom surface of the conductive layer in the trench using a gas containing bromine. The protective film includes a compound of the tungsten and the bromine. The method can remove the protective film on the bottom surface of the conductive layer. The method can etch a portion of the conductive layer below the trench with the protective film on the side surface of the conductive layer. | 09-08-2011 |
| 20110217823 | STORAGE CAPACITOR HAVING AN INCREASED APERTURE RATIO AND METHOD OF MANUFACTURING THE SAME - Disclosed is a method of manufacturing a storage capacitor having increased aperture ratio: providing a substrate having a metal layer disposed thereon, and said metal layer is covered correspondingly with a first dielectric layer and a second dielectric layer in sequence; forming a photoresist layer with a uniform thickness to cover said second dielectric layer; performing a process of exposure-to-light and development to a portion of said photoresist layer that is correspondingly disposed over said metal layer sequentially, so that its thickness is less than its original thickness; removing said photoresist layer and etching said portion of said second dielectric layer, so that a thickness of said portion of said second dielectric layer is less than its original thickness, and the etching depth of said portion is greater than that of the other remaining portions of said second dielectric layer; and forming an electrode layer on said second dielectric layer. | 09-08-2011 |
| 20110223738 | FORMING PHASE CHANGE MEMORY CELLS - Small phase change memory cells may be formed by forming a segmented heater over a substrate. A stop layer may be formed over the heater layer and segmented with the heater layer. Then, sidewall spacers may be formed over the segmented heater to define an aperture between the sidewall spacers that may act as a mask for etching the stop layer over the segmented heater. As a result of the etching using the sidewall spacers as a mask, sublithographic pore may be formed over the heater. Phase change material may be formed within the pore. | 09-15-2011 |
| 20110237043 | METHOD FOR MANUFACTURING CAPACITOR OF SEMICONDUCTOR DEVICE AND CAPACITOR OF SEMICONDUCTOR DEVICE MANUFACTURED THEREBY - A method of manufacturing a capacitor of a semiconductor device includes forming a high-k dielectric pattern on a semiconductor substrate, the high-k dielectric pattern having a pillar shape including a hole therein, forming a lower electrode in the hole of the high-k dielectric pattern, locally forming a blocking insulating pattern on an upper surface of the lower electrode, and forming an upper electrode covering the high-k dielectric pattern and the blocking insulating pattern. | 09-29-2011 |
| 20110237044 | METHODS OF MANUFACTURING CAPACITOR AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - A capacitor includes a first capacitor structure on a substrate, the first capacitor structure including a first electrode, a first dielectric layer pattern, and a second electrode, a second capacitor structure on the first capacitor structure, the second capacitor structure including a third electrode, a second dielectric layer pattern, and a fourth electrode, at least one first contact pad on a side of the first electrode, and a wiring structure connecting the at least one first contact pad and the fourth electrode. | 09-29-2011 |
| 20110256685 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A film structure including at least one film is formed on a face of a semiconductor substrate and then a first mask with a pattern is formed on the film structure. A second mask is formed so as to cover the first mask over a bevel region. The film structure is etched using the first and second masks and thereafter the remaining first and second masks are removed away. | 10-20-2011 |
| 20110287601 | METHODS OF FORMING A DIELECTRIC CONTAINING DYSPROSIUM DOPED HAFNIUM OXIDE - The use of a monolayer or partial monolayer sequencing process, such as atomic layer deposition, to form a dielectric layer of hafnium oxide doped with dysprosium and a method of fabricating such a combination produces a reliable structure for use in a variety of electronic devices. Forming the dielectric structure can include depositing hafnium oxide onto a substrate surface using precursor chemicals, followed by depositing dysprosium oxide onto the substrate using precursor chemicals, and repeating to form a thin laminate structure. A dielectric layer of dysprosium doped hafnium oxide may be used as the gate insulator of a MOSFET, as a capacitor dielectric in a DRAM, as a tunnel gate insulator in flash memories, or as a dielectric in NROM devices, because the high dielectric constant (high-k) of the film provides the functionality of a thinner silicon dioxide film, and because the reduced leakage current of the dielectric layer when the percentage of dysprosium doping is optimized improves memory function. | 11-24-2011 |
| 20110294275 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming an isolation layer over a substrate, forming a plurality of open regions exposing the substrate by selectively etching the isolation layer, performing a surface treatment over the isolation layer, expanding the open regions by removing the surface-treated portion of the isolation layer, and forming a conductive layer in the expanded open regions. | 12-01-2011 |
| 20110294276 | Method of manufacturing semiconductor device - SiOC film ( | 12-01-2011 |
| 20110300683 | Semiconductor device and method of forming the same - A semiconductor device and a method of forming the same are provided. The method includes preparing a semiconductor substrate. Insulating layers may be sequentially formed on the semiconductor substrate. Active elements may be formed between the insulating layers. A common node may be formed in the insulating layers to be electrically connected to the active elements. The common node and the active elements may be 2-dimensionally and repeatedly arranged on the semiconductor substrate. | 12-08-2011 |
| 20110306173 | METHOD FABRICATING SEMICONDUCTOR DEVICE USING MULTIPLE POLISHING PROCESSES - A method of fabricating a phase change memory device includes the use of first, second and third polishing processes. The first polishing process forms a first contact portion using a first sacrificial layer and the second polishing process forms a phase change material pattern using a second sacrificial layer. After removing the first and second sacrificial layers to expose resultant protruding structures of the first contact portion and the phase change material pattern, a third polishing process is used to polish the resultant protruding structures using an insulation layer as a polishing stopper layer. | 12-15-2011 |
| 20110306174 | Patterning Method for High Density Pillar Structures - A method of making a device includes forming a first photoresist layer over a sacrificial layer, patterning the first photoresist layer to form first photoresist features, rendering the first photoresist features insoluble to a solvent, forming a second photoresist layer over the first photoresist features, patterning the second photoresist layer to form second photoresist features, forming a spacer layer over the first and second photoresist features, etching the spacer layer to form spacer features and to expose the first and second photoresist features, forming third photoresist features between the spacer features, removing the spacer features, and patterning the sacrificial layer using the first, second and third photoresist features as a mask to form sacrificial features. | 12-15-2011 |
| 20110312148 | CHEMICAL VAPOR DEPOSITION OF RUTHENIUM FILMS CONTAINING OXYGEN OR CARBON - Methods for depositing ruthenium-containing films are provided herein. In some embodiments, a method of depositing a ruthenium-containing film on a substrate may include depositing a ruthenium-containing film on a substrate using a ruthenium-containing precursor, the deposited ruthenium-containing film having carbon incorporated therein; and exposing the deposited ruthenium-containing film to an oxygen-containing gas to remove at least some of the carbon from the deposited ruthenium-containing film. In some embodiments, the oxygen-containing gas exposed ruthenium-containing film may be annealed in a hydrogen-containing gas to remove at least some oxygen from the ruthenium-containing film. In some embodiments, the deposition, exposure, and annealing may be repeated to deposit the ruthenium-containing film to a desired thickness. | 12-22-2011 |
| 20120003807 | METHOD FOR FORMING SEMICONDUCTOR REGION AND METHOD FOR MANUFACTURING POWER STORAGE DEVICE - To provide a method for manufacturing a power storage device which enables improvement in performance of the power storage device, such as an increase in discharge capacity. To provide a method for forming a semiconductor region which is used for a power storage device or the like so as to improve performance. A method for forming a crystalline semiconductor region includes the steps of: forming, over a conductive layer, a crystalline semiconductor region that includes a plurality of whiskers including a crystalline semiconductor by an LPCVD method; and performing heat treatment on the crystalline semiconductor region after supply of a source gas containing a deposition gas including silicon is stopped. A method for manufacturing a power storage device includes the step of using the crystalline semiconductor region as an active material layer of the power storage device. | 01-05-2012 |
| 20120003808 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A method for fabricating semiconductor memory device, includes providing a semiconductor substrate; forming a lower region which includes a first data storage device, which is carried by the semiconductor substrate; forming a switching device which is carried by the first data storage device; and forming an upper region which includes a second data storage device, which is carried by the switching device. The step of forming the first storage device includes forming a first electrode having a cylindrical or pillar shape, the first electrode being connected to the switching device. | 01-05-2012 |
| 20120028433 | METHOD FOR MANUFACTURING SOLID ELECTROLYTIC CAPACITOR - A dielectric layer is formed in the surface of an anode body which is composed of a sintered body, a semiconductor layer composed of an electrically-conductive polymer is formed on the dielectric layer, and then an electric conductor layer is formed on the semiconductor layer with an electrically-conductive paste which contains a dispersant to obtain a solid electrolytic capacitor element: The electric conductor layer of the solid electrolytic capacitor element is electrically connected to a cathode terminal using the electrically-conductive paste which contains a dispersant, and the anode body is electrically connected to an anode terminal through a lead wire by welding. The solid electrolytic capacitor element connected to the terminals is immersed in a solvent, and then the solid electrolytic capacitor element is encapsulated with a resin to obtain a solid electrolytic capacitor. | 02-02-2012 |
| 20120034751 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a flash memory cell in a first region, forming a first electrode of a capacitor in a second region, forming a first silicon oxide film, a silicon nitride film, and a second silicon oxide film in this order as a second insulating film, removing the silicon nitride film and the second silicon oxide film in a partial region of the first electrode, wet-etching a first insulating film and the second insulating film in the third region, forming a second electrode of the capacitor, and etching and removing the first silicon oxide film in the partial region. | 02-09-2012 |
| 20120034752 | METHODS OF FORMING A GATE STRUCTURE AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME - In a method of forming a gate structure, a gate pattern including a gate insulation layer pattern and a gate electrode sequentially stacked on a substrate is formed. The gate electrode includes a metal. A first plasma process is performed on the gate pattern using a reaction gas to reduce an oxidized edge portion of the gate electrode. The reaction gas includes nitrogen. A spacer is formed on a sidewall of the gate pattern. A threshold voltage is adjusted by reducing the oxidized edge portion of the gate electrode. Therefore, a semiconductor device including the gate pattern has excellent electrical characteristics. | 02-09-2012 |
| 20120040507 | METHODS OF FORMING A PLURALITY OF CAPACITORS - A method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes, an elevationally inner insulative retaining material received laterally about the capacitor electrodes, an elevationally outer insulative retaining material received laterally about the capacitor electrodes, a first material received laterally about the capacitor electrodes elevationally inward of the inner insulative retaining material, and a second material received laterally about the capacitor electrodes elevationally between the inner and outer insulative retaining materials. Openings are anisotropically etched to extend through the outer insulative retaining material and the second material. After the anisotropic etching, remaining of the second material is isotropically etched through the openings from being received laterally about the capacitor electrodes between the inner and outer insulative retaining materials. The isotropic etching of the second material is conducted selectively relative to the capacitor electrodes and the inner and outer insulative retaining materials. The capacitor electrodes are ultimately incorporated into a plurality of capacitors. | 02-16-2012 |
| 20120064689 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes at least forming a lower electrode comprising titanium nitride on a semiconductor substrate, forming a dielectric film comprising zirconium oxide as a primary constituent on the lower electrode, forming a first protective film comprising a titanium compound on the dielectric film, and forming an upper electrode comprising titanium nitride on the first protective film. The method can include a step of forming a second protective film on the lower electrode before the step of forming the dielectric film on the lower electrode. | 03-15-2012 |
| 20120064690 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes at least forming a lower electrode made of titanium nitride on a semiconductor substrate, forming a dielectric film comprising zirconium oxide, in which at least the uppermost layer of the dielectric film is formed by an atomic layer deposition (ALD) method on the lower electrode, forming a first protective film on the dielectric film without exceeding the film forming temperature of the ALD method over 70° C., and forming an upper electrode made of a titanium nitride on the first protective film. | 03-15-2012 |
| 20120064691 | Method For Fabricating Multi Resistive State Memory Devices - A treated conductive element is provided. A conductive element can be treated by depositing either a reactive metal or a very thin layer of material on the conductive element. The reactive metal (or very thin layer of material) would typically be sandwiched between the conductive element and an electrode. The structure additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays. | 03-15-2012 |
| 20120070955 | Methods of Forming Conductive Contacts to Source/Drain Regions and Methods of Forming Local Interconnects - The invention comprises methods of forming a conductive contact to a source/drain region of a field effect transistor, and methods of forming local interconnects. In one implementation, a method of forming a conductive contact to a source/drain region of a field effect transistor includes providing gate dielectric material intermediate a transistor gate and a channel region of a field effect transistor. At least some of the gate dielectric material extends to be received over at least one source/drain region of the field effect transistor. The gate dielectric material received over the one source/drain region is exposed to conditions effective to change it from being electrically insulative to being electrically conductive and in conductive contact with the one source/drain region. Other aspects and implementations are contemplated. | 03-22-2012 |
| 20120070956 | Method for Manufacturing Memory Element - A conductive paste including conductive particles each of which has a size of greater than or equal to 0.1 μm and less than or equal to 10 μm, a resin, and a solvent is placed over a first conductor and the solvent is vaporized. In this manner, a second conductor having the conductive particles and a memory layer including the resin between the first conductor and the conductive particles is formed. | 03-22-2012 |
| 20120077322 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME AND ADSORPTION SITE BLOCKING ATOMIC LAYER DEPOSITION METHOD - To provide a dielectric film having good crystallinity while suppressing an influence of the size effects and preventing the dielectric film from being divided by an Al-doped layer although there is provided the Al-doped layer for improving the leakage characteristics in the dielectric film of a capacitor, the dielectric film has at least one Al-doped layer, and an area density of Al atoms in one layer of the Al-doped layer is smaller than 1.4E+14′ atoms/cm | 03-29-2012 |
| 20120088347 | Methods Of Manufacturing Non-Volatile Phase-Change Memory Devices - Methods of manufacturing non-volatile memory devices may include separating first phase-change material groups and second phase-change material groups, which have different sizes, from a target including phase-change materials and faulting a phase-change material layer on an object by using the first phase-change material groups and the second phase-change material groups. | 04-12-2012 |
| 20120088348 | Methods of Forming Patterns in Semiconductor Constructions, Methods of Forming Container Capacitors, and Methods of Forming Reticles Configured for Imprint Lithography - The invention includes methods of forming reticles configured for imprint lithography, methods of forming capacitor container openings, and methods in which capacitor container openings are incorporated into DRAM arrays. An exemplary method of forming a reticle includes formation of a radiation-imageable layer over a material. A lattice pattern is then formed within the radiation-imageable layer, with the lattice pattern defining a plurality of islands of the radiation-imageable layer. The lattice-patterned radiation-imageable layer is utilized as a mask while subjecting the material under the lattice-patterned layer to an etch which transfers the lattice pattern into the material. The etch forms a plurality of pillars which extend only partially into the material, with the pillars being spaced from one another by gaps. The gaps are subsequently narrowed with a second material which only partially fills the gaps. | 04-12-2012 |
| 20120094462 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device, includes: a first storage node contact plug penetrating a first interlayer insulation layer and partially protruding above the first interlayer insulation layer; a second storage node contact plug contacting the first storage node contact plug that protrudes above the first interlayer insulation layer; a storage node contacting a top surface of the second storage node contact plug; and a second interlayer insulation layer formed over the first interlayer insulation layer, wherein the second interlayer insulation layer surrounds an outer sidewall at a bottom region of the first storage node, and the second storage node contact plug, and wherein the first storage node contact plug protruding above the first interlayer insulation layer and the second storage node contact plug. | 04-19-2012 |
| 20120100687 | METHODS FOR FABRICATING CAPACITOR AND METHODS FOR FABRICATING SEMICONDUCTOR DEVICE INCLUDING THE CAPACITOR - Example embodiments relate to methods for fabricating a capacitor and methods for fabricating a semiconductor device including the capacitor. The methods for fabricating a capacitor may include forming a preliminary lower electrode with a first area on a substrate; implanting ions in the preliminary lower electrode to form a lower electrode with a second area that is larger or substantially larger than the first area; and forming a dielectric layer and an upper electrode on the lower electrode. | 04-26-2012 |
| 20120108028 | Methods of Forming Electrical Components and Memory Cells - Some embodiments include methods of forming electrical components. First and second exposed surface configurations are formed over a first structure, and material is then formed across the surface configurations. The material is sub-divided amongst two or more domains, with a first of the domains being induced by the first surface configuration, and with a second of the domains being induced by the second surface configuration. A second structure is then formed over the material. The first domains of the material are incorporated into electrical components. The second domains may be replaced with dielectric material to provide isolation between adjacent electrical components, or may be utilized as intervening regions between adjacent electrical components. | 05-03-2012 |
| 20120108029 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - It is an object of the present invention to provide a technique in which a high-performance and high reliable memory device and a semiconductor device provided with the memory device are manufactured at low cost with high yield. The semiconductor device includes an organic compound layer including an insulator over a first conductive layer and a second conductive layer over the organic compound layer including an insulator. Further, the semiconductor device is manufactured by forming a first conductive layer, discharging a composition of an insulator and an organic compound over the first conductive layer to form an organic compound layer including an insulator, and forming a second conductive layer over the organic compound layer including an insulator. | 05-03-2012 |
| 20120115300 | METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE - In a method for manufacturing a semiconductor memory device, a three dimensional lower electrode including a titanium nitride film is formed on a semiconductor substrate, and a dielectric film is formed on the surface of the lower electrode. After a first upper electrode is formed at a temperature that the crystal of the dielectric film is not grown on the surface of the dielectric film, the first upper electrode and the dielectric film are heat-treated at a temperature that the crystal of the dielectric film is grown to convert at least a portion of the dielectric film into a crystalline state. Thereafter, a second upper electrode is formed on the surface of the first upper electrode. | 05-10-2012 |
| 20120115301 | METAL CAPACITOR AND METHOD OF MAKING THE SAME - A method of making a metal capacitor includes the following steps. A dielectric layer having a dual damascene metal interconnection and a damascene capacitor electrode is provided. Then, a treatment is performed to increase the dielectric constant of the dielectric layer surrounding the damascene capacitor electrode. The treatment can be UV radiation, a plasma treatment or an ion implantation. Accordingly, the metal capacitor will have a higher capacitance and RC delay between the dual damascene metal interconnection and the dielectric layer can be prevented. | 05-10-2012 |
| 20120122289 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - Provided is a semiconductor device manufacturing method for a capacitor having a dielectric film which can be formed into a thin film, can be formed at a low temperature, and has a readily controllable property. The manufacturing method includes: forming, on a conductor for serving as one electrode of a capacitor, a manganese oxide film for serving as a dielectric film of the capacitor; and forming, on the manganese oxide film, a conductive film for serving as the other electrode of the capacitor. | 05-17-2012 |
| 20120129312 | METHOD OF FORMING E-FUSE IN REPLACEMENT METAL GATE MANUFACTURING PROCESS - Embodiment of the present invention provides a method of forming electronic fuse or commonly known as e-fuse. The method includes forming a polysilicon structure and a field-effect-transistor (FET) structure together on top of a common semiconductor substrate, the FET structure having a sacrificial gate electrode; implanting at least one dopant into the polysilicon structure to create a doped polysilicon layer in at least a top portion of the polysilicon structure; subjecting the polysilicon structure and the FET structure to a reactive-ion-etching (RIE) process, the RIE process selectively removing the sacrificial gate electrode of the FET structure while the doped polysilicon layer being substantially unaffected by the RIE process; and converting the polysilicon structure including the doped polysilicon layer into a silicide to form the electronic fuse. | 05-24-2012 |
| 20120129313 | THERMALLY INSULATED PHASE MATERIAL CELLS - A memory cell structure and method for forming the same. The method includes forming a pore within a dielectric layer. The pore is formed over the center of an electrically conducting bottom electrode. The method includes depositing a thermally insulating layer along at least one sidewall of the pore. The thermally insulating layer isolates heat from phase change current to the volume of the pore. In one embodiment phase change material is deposited within the pore and the volume of the thermally insulating layer. In another embodiment a pore electrode is formed within the pore and the volume of the thermally insulating layer, with the phase change material being deposited above the pore electrode. The method also includes forming an electrically conducting top electrode above the phase change material. | 05-24-2012 |
| 20120135579 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method uses a line pattern to form a semiconductor device including asymmetrical contact arrays. The method includes forming a plurality of parallel first conductive line layers extending in a first direction on a semiconductor substrate. In this method, the semiconductor substrate may have active regions forming an oblique angle with the first direction. The method may further include forming a first mask layer and a second mask layer and using the first mask layer and the second mask layer to form a trench comprising a line area and a contact area by etching the first conductive line layers using the first mask layer and the second mask layer. The method further includes forming a gap filling layer filling the line area of the trench and forming a spacer of sidewalls of the contact area and forming a second conductive line layer electrically connected to the active region. | 05-31-2012 |
| 20120135580 | Three-Dimensional Memory Structures Having Shared Pillar Memory Cells - A three-dimensional non-volatile memory system is disclosed including a memory array utilizing shared pillar structures for memory cell formation. A shared pillar structure includes two non-volatile storage elements. A first end surface of each pillar contacts one array line from a first set of array lines and a second end surface of each pillar contacts two array lines from a second set of array lines that is vertically separated from the first set of array lines. Each pillar includes a first subset of layers that are divided into portions for the individual storage elements in the pillar. Each pillar includes a second subset of layers that is shared between both non-volatile storage elements formed in the pillar. The individual storage elements each include a steering element and a state change element. | 05-31-2012 |
| 20120142160 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING DEUTERIUM ANNEALING - A method of fabricating a semiconductor device is disclosed, the method generally including the steps of: forming a gate dielectric layer on a semiconductor substrate;forming a gate electrode on the gate dielectric layer;forming an etch stop layer on the gate electrode;forming a capacitor on the semiconductor substrate adjacent to the gate electrode;after forming the capacitor, forming a contact hole passing through the etch stop layer on the gate electrode;and, diffusing deuterium into the gate dielectric layer through the contact hole. | 06-07-2012 |
| 20120142161 | METHODS FOR MANUFACTURING A PHASE-CHANGE MEMORY DEVICE - A method of manufacturing a phase-change memory device comprises forming a contact region on a substrate, forming a lower electrode electrically connected to the contact region, forming a phase-change material layer on the lower electrode using a chalcogenide compound target including carbon and metal, or carbon, nitrogen and metal, and forming an upper electrode on the phase-change material layer. | 06-07-2012 |
| 20120142162 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - The present invention relates to a semiconductor and manufacturing method thereof, in which a nano tube structure is vertically grown to form a lower electrode of a cell region and a via contact of peripheral circuit region. Therefore, capacitance of the lower electrode is secured without an etching process for high aspect ratio. Also, the via contact can be formed for corresponding to the height of the lower electrode. | 06-07-2012 |
| 20120149163 | PHASE CHANGE MEMORY DEVICE WITH ALTERNATING ADJACENT CONDUCTION CONTACTS AND FABRICATION METHOD THEREOF - A phase change memory device and an associated method of making same are presented. The phase change memory device, includes first wiring lines, second wiring lines, memory cells, and conduction contacts. The first wiring lines are arranged substantially in parallel to each other so that the first wiring lines are grouped into odd and even numbered first wiring lines. The memory cells are coupled to the first and second wiring lines. The conduction contacts coupled to the first wiring lines so that only one conduction contact is coupled to a center of a corresponding odd numbered first wiring line. Also only two corresponding conduction contacts are coupled to opposing edges of a corresponding even numbered first wiring line. Accordingly, the conduction contacts are arranged on the first wiring lines so that conduction contacts are not adjacent to each other with respect to immediately adjacent first wiring lines. | 06-14-2012 |
| 20120156849 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a storage node contact plug over a cell region of a substrate, forming a first inter-layer dielectric layer over the substrate, forming a first bit line over the first inter-layer dielectric layer in a peripheral region of the substrate, forming a second inter-layer dielectric layer over the first inter-layer dielectric layer, forming a second bit line over the second inter-layer dielectric layer, etching the second inter-layer dielectric layer to expose an upper surface of the storage node contact plug in the cell region, forming a capacitor contacting the storage node contact plug, forming a third inter-layer dielectric layer over the substrate having the capacitor formed thereon, forming a metal contact through the third inter-layer dielectric layer to contact the second bit line in the peripheral region, and forming a metal line contacting the metal contact over the third inter-layer dielectric layer. | 06-21-2012 |
| 20120156850 | METHOD FOR FABRICATING FINE PATTERN - A method for fabricating a fine pattern includes forming a first photomask including first light transmission regions set in a line shape over a first phase shift mask (PSM) region and a first binary mask (BM) region adjacent to the first phase shift mask region. A second photomask may be formed to include second light transmission regions set in a line shape over a second phase shift mask region and a second binary mask region adjacent to the second phase shift mask region, wherein the second light transmission regions intersect the first light transmission regions. A resist layer may first be exposed using the first photomask and secondly exposed using the second photomask. The first and secondly exposed resist layer may be developed to form resist patterns with open regions corresponding to portions where the first light transmission regions intersect the second light transmission regions. | 06-21-2012 |
| 20120164812 | Methods of Manufacturing Semiconductor Devices - In a method of manufacturing a semiconductor device, a mask is formed on a substrate. The substrate is divided into a first region and a second region. An upper portion of the substrate in the first region is partially removed using the mask as an etching mask to form a recess. A first gate structure is formed in the recess. A portion of the mask in the first region is removed. A blocking layer pattern is formed on the substrate in the first region over the first gate structure. | 06-28-2012 |
| 20120171835 | METHOD FOR PROCESSING A GLASS SUBSTRATE - A method for processing a glass substrate is disclosed. A glass substrate including a first surface, a second surface, and a side surface between the first surface and the second surface is provided. An opaque conductive layer is formed on the second surface and a part of the side surface close to the second surface. Thereafter, a semiconductor process is performed on the first surface. Thereafter, the opaque conductive layer on the second surface and the part of the side surface close to the second surface is removed. The problem of transporting a transparent glass substrate by some semiconductor tools is solved without increasing tool cost by enabling the sensing and transportation of glass substrates with optical sensor and/or electrical chuck. The fabrication of devices with a glass substrate is also achieved. | 07-05-2012 |
| 20120171836 | Method for Forming MEMS Variable Capacitors - A method for fabricating an out-of-plane variable overlap MEMS capacitor comprises: providing a substrate ( | 07-05-2012 |
| 20120178233 | NANOWIRE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A nanowire memory device and a method of manufacturing the same are provided. A memory device includes: a substrate; a first electrode formed on the substrate; a first nanowire extending from an end of the first electrode; a second electrode formed over the first electrode to overlap the first electrode; and a second nanowire extending from an end of the second electrode corresponding to the end of the first electrode in the same direction as the first nanowire, wherein an insulating layer exists between the first and second electrodes. | 07-12-2012 |
| 20120190164 | DUAL-DAMASCENE PROCESS TO FABRICATE THICK WIRE STRUCTURE - A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer. | 07-26-2012 |
| 20120190165 | Creating Integrated Circuit Capacitance From Gate Array Structures - Techniques for using gate arrays to create capacitive structures within an integrated circuit are disclosed. Embodiments comprise placing a gate array of P-type field effect transistors (P-fets) and N-type field effect transistors (N-fets) in an integrated circuit design, coupling drains and sources for one or more P-fets and gates for one or more N-fets to a power supply ground, and coupling gates for the one or more P-fets and the drains and sources for one or more N-fets to a positive voltage of the power supply. In some embodiments, source-to-drain leakage current for capacitive apparatuses of P-fets and N-fets are minimized by biasing one or more P-fets and one or more N-fets to the positive voltage and the ground, respectively. In other embodiments, the capacitive structures may be implemented using fusible elements to isolate the capacitive structures in case of shorts. | 07-26-2012 |
| 20120196423 | METHOD OF FABRICATION BODIES FOR AN EMBEDDED POLYSILICON RESISTOR AND AN EMBEDDED eFUSE ISOLATED FROM A SUBSTRATE - A method includes providing a substrate having insulating layers thereon; forming a first trench in a first region of the substrate and a second trench in a second region of the substrate; thermally growing layers of oxide along the sides of the trenches; filling the first trench and the second trench with a polysilicon material, planarizing the polysilicon material, and creating a shallow trench isolation between the first region and the second region, wherein the step f) of creating the shallow trench isolation is performed only after the steps of d) filling and e) planarizing. | 08-02-2012 |
| 20120202333 | METHOD FOR FORMING A SELF-ALIGNED BIT LINE FOR PCRAM AND SELF-ALIGNED ETCH BACK PROCESS - A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and fowling at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided. | 08-09-2012 |
| 20120214288 | METHOD FOR PRODUCING MIM CAPACITORS WITH HIGH K DIELECTRIC MATERIALS AND NON-NOBLE ELECTRODES - A method of producing a Metal-Insulator-Metal (MIM) capacitor stack through doping to achieve low current leakage and low equivalent oxide thickness is disclosed. A high K dielectric material is deposited on a non-noble electrode; the dielectric material is doped with oxides from group IIA. The dopant increases the barrier height of metal/insulator interface and neutralizes free electrons in dielectric material, therefore reduces the leakage current of MIM capacitor. The electrode may also be doped to increase work function while maintaining a rutile crystalline structure. The method thereby enhances the performance of DRAM MIM capacitor. | 08-23-2012 |
| 20120220098 | Methods of Forming Dielectric Material-Containing Structures - Some embodiments include dielectric structures. The structures include first and second portions that are directly against one another. The first portion may contain a homogeneous mixture of a first phase and a second phase. The first phase may have a dielectric constant of greater than or equal to 25, and the second phase may have a dielectric constant of less than or equal to 20. The second portion may be entirely a single composition having a dielectric constant of greater than or equal to 25. Some embodiments include electrical components, such as capacitors and transistors, containing dielectric structures of the type described above. Some embodiments include methods of forming dielectric structures, and some embodiments include methods of forming electrical components. | 08-30-2012 |
| 20120220099 | Forming a Phase Change Memory With an Ovonic Threshold Switch - A phase change memory may include an ovonic threshold switch formed over an cyanic memory. In one embodiment, the switch includes a chalcogenide layer that overlaps an underlying electrode. Then, edge damage, due to etching the chalcogenide layer, may be isolated to reduce leakage current. | 08-30-2012 |
| 20120220100 | PILLAR STRUCTURE FOR MEMORY DEVICE AND METHOD - A method of forming a memory device. The method provides a semiconductor substrate having a surface region. A first dielectric layer is formed overlying the surface region of the semiconductor substrate. A bottom wiring structure is formed overlying the first dielectric layer and a second dielectric material is formed overlying the top wiring structure. A bottom metal barrier material is formed to provide a metal-to-metal contact with the bottom wiring structure. The method forms a pillar structure by patterning and etching a material stack including the bottom metal barrier material, a contact material, a switching material, a conductive material, and a top barrier material. The pillar structure maintains a metal-to-metal contact with the bottom wiring structure regardless of the alignment of the pillar structure with the bottom wiring structure during etching. A top wiring structure is formed overlying the pillar structure at an angle to the bottom wiring structure. | 08-30-2012 |
| 20120225530 | METHODS OF FABRICATING A SEMICONDUCTOR MEMORY DEVICE - A method of fabricating a semiconductor memory device includes forming a hard mask pattern using a damascene method on a lower mold layer stacked on a substrate and etching the lower mold layer using the hard mask pattern as an etch mask to define a protrusion under the hard mask pattern. A support pattern is formed on a top surface of the etched lower mold layer, the top surface of the etched lower mold layer being located at a lower level than a top surface of the protrusion. A lower electrode supported by the support pattern is formed. | 09-06-2012 |
| 20120225531 | SEMICONDUCTOR DEVICE INCLUDING MEMORY CELL HAVING CAPACITOR - A semiconductor device includes a semiconductor substrate; a memory cell array including a plurality of memory cells formed on the semiconductor substrate and arranged in a matrix in a first direction and a second direction on the surface of the semiconductor substrate; a plurality of sense amplifiers formed on the semiconductor substrate and including a first sense amplifier and a second sense amplifier; and a plurality of bit lines extending along the first direction above the memory cell array, and arranged side by side in the second direction, wherein the plurality of bit lines include a first bit line pair formed in a first wiring layer and a second bit line pair formed in a second wiring layer located above the first wiring layer. | 09-06-2012 |
| 20120231601 | Methods of fabricating a semiconductor device having metallic storage nodes - The present disclosure describes methods of fabricating a semiconductor device. An exemplary method includes forming a metal pattern on a substrate and etching the metal pattern using an etchant including at least an alkaline solution and an oxidant to form a metal electrode, where at least a portion of the surface of the metal electrode is uneven. | 09-13-2012 |
| 20120231602 | REVERSE CONSTRUCTION INTEGRATED CIRCUIT - A method of fabricating a memory cell comprises forming a plurality of doped semiconductor layers on a carrier substrate. The method further comprises forming a plurality of digit lines separated by an insulating material. The digit lines are arrayed over the doped semiconductor layers. The method further comprises etching a plurality of trenches into the doped semiconductor layers. The method further comprises depositing an insulating material into the plurality of trenches to form a plurality of electrically isolated transistor pillars. The method further comprises bonding at least a portion of the structure formed on the carrier substrate to a host substrate. The method further comprises separating the carrier substrate from the host substrate. | 09-13-2012 |
| 20120238069 | ESD NETWORK CIRCUIT WITH A THROUGH WAFER VIA STRUCTURE AND A METHOD OF MANUFACTURE - A method includes forming an ESD active device on a substrate, forming a ground plane on a backside of the substrate and forming at least one through wafer via electrically connected to a negative power supply of the ESD active device and the ground plane to provide a low series resistance path to the substrate. | 09-20-2012 |
| 20120244676 | SEMICONDUCTURE STRUCTURE AND METHOD OF FORMING THE SEMICONDUCTOR STRUCTURE THAT PROVIDES TWO INDIVIDUAL RESISTORS OR A CAPACITOR - A semiconductor structure is formed in the metal interconnect structure of an integrated circuit in a method that provides either two individual resistors that are vertically isolated from each other, or a metal-insulator-metal (MIM) capacitor. As a result, both semiconductor resistors and MIM capacitors can be formed in the same process flow. | 09-27-2012 |
| 20120252181 | SEMICONDUCTOR DEVICE HAVING CAPACITOR CAPABLE OF REDUCING ADDITIONAL PROCESSES AND ITS MANUFACTURE METHOD - A first capacitor recess and a wiring trench are formed through an interlayer insulating film. A lower electrode fills the first capacitor recess, and a first wiring fills the wiring trench. An etching stopper film and a via layer insulating film are disposed over the interlayer insulating film. A first via hole extends through the via layer insulating film and etching stopper film and reaches the first wiring, and a first plug fills the first via hole. A second capacitor recess is formed through the via layer insulating film, the second capacitor recess at least partially overlapping the lower electrode, as viewed in plan. The upper electrode covers the bottom and side surfaces of the second capacitor recess. A capacitor is constituted of the upper electrode, etching stopper film and lower electrode. A second wring connected to the first plug is formed over the via layer insulating film. | 10-04-2012 |
| 20120264271 | METHOD OF FORMING A CAPACITOR AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME - A capacitor is fabricated by forming a mold layer of a silicon based material that is not an oxide of silicon, e.g., polysilicon or doped polysilicon, on a substrate, forming an opening through the mold layer, forming a barrier layer pattern along the sides of the opening, subsequently forming a lower electrode in the opening, then removing the mold layer and the barrier layer pattern, and finally sequentially forming dielectric layer and an upper electrode on the lower electrode. | 10-18-2012 |
| 20120264272 | Methods Of Forming A Nonvolatile Memory Cell And Methods Of Forming An Array Of Nonvolatile Memory Cells Array Of Nonvolatile Memory Cells - A method of forming a nonvolatile memory cell includes forming a first electrode and a second electrode of the memory cell. Sacrificial material is provided between the first second electrodes. The sacrificial material is exchanged with programmable material. The sacrificial material may additionally be exchanged with select device material. | 10-18-2012 |
| 20120276705 | METHOD OF MAKING A SEMICONDUCTOR DEVICE AS A CAPACITOR - Forming a capacitor structure includes forming a first dielectric layer over a conductive region, wherein the first dielectric layer has a first conductive layer at a top surface of the first dielectric layer; forming a first opening in the first dielectric layer over the conductive region, wherein the first opening exposes a first sidewall of the first conductive layer; forming a second conductive layer within the first opening, wherein the second conductive layer contacts the first sidewall of the first conductive layer; removing a portion of the second conductive layer from the bottom of the first opening; forming an insulating layer within the first opening; removing a portion of the insulating layer from the bottom of the first opening; extending the first opening through the first dielectric layer to expose the conductive region; and filling the first opening with a conductive material, wherein the conductive material contacts the conductive region. | 11-01-2012 |
| 20120276706 | DAMASCENE METAL-INSULATOR-METAL (MIM) DEVICE IMPROVED SCALEABILITY - A present method of fabricating a memory device includes the steps of providing a dielectric layer;, providing an opening in the dielectric layer, providing a first conductive body in the opening, providing a switching body in the opening, the first conductive body and switching body Filling the opening, and providing a second conductive body over the switching body. In an alternate embodiment, a second dielectric layer is provided over the first-mentioned dielectric layer, and the switching body is provided in an opening in the second dielectric layer. | 11-01-2012 |
| 20120282749 | HIGH PERFORMANCE RESONANT ELEMENT - A method of forming a semiconductor device for processing a signal includes providing a circuit board including an input signal line, providing a high performance resonant element connected to the input signal line, and providing an output signal line connected to the high performance resonant element. The high performance resonant element includes a via. | 11-08-2012 |
| 20120282750 | SEMICONDUCTOR DEVICE HAVING CAPACITORS FIXED TO SUPPORT PATTERNS AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device containing a cylindrical shaped capacitor and a method for manufacturing the same is presented. The semiconductor device includes a plurality of storage nodes and a support pattern. The plurality of storage nodes is formed over a semiconductor substrate. The support pattern is fixed to adjacent storage nodes in which the support pattern has a flowable insulation layer buried within the support pattern. The buried flowable insulation layer direct contacts adjacent storage nodes. | 11-08-2012 |
| 20120289019 | METHODS OF FORMING A PATTERN AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME - In a method of forming a pattern, a plurality of first line patterns and first spacers filling spaces between the adjacent first line patterns are formed on an object layer. The first line patterns and the first spacers extend in a first direction. A plurality of second line patterns are formed on the first line patterns and the first spacers. The second line patterns extend in a second direction substantially perpendicular to the first direction. The first spacers are partially removed by a wet etching process. The object layer is etched using the first and second line patterns as an etching mask. | 11-15-2012 |
| 20120302028 | MIXED VALENT OXIDE MEMORY AND METHOD - Memory devices and methods of forming include a mixed valent oxide located between a first electrode and a second electrode. Implantation of a metal below a surface of one of the electrodes allows formation of the mixed valent oxide with a direct interface to the electrode. An intermetallic oxide can be subsequently formed between the mixed valent oxide and the electrode by annealing the structure. | 11-29-2012 |
| 20120309159 | METHOD TO SELECTIVELY GROW PHASE CHANGE MATERIAL INSIDE A VIA HOLE - An example embodiment is a method for filling a via hole with phase change material. The method steps include forming a bottom electrode in a substrate, depositing a dielectric layer above the bottom electrode, and forming a via hole within the dielectric layer down to a top surface of the bottom electrode. The substrate is heated to a reaction temperature and a first phase change material precursor is deposited within the via hole. The first precursor is configured to decompose on the top surface of the bottom electrode and chemisorb on a top surface of the dielectric layer at the reaction temperature. A second precursor is deposited within the via hole after the first precursor at least partially decomposes on the top surface of the bottom electrode. | 12-06-2012 |
| 20120309160 | METHOD FOR FABRICATING A DRAM CAPACITOR - A method for fabricating a dynamic random access memory (DRAM) capacitor stack is disclosed wherein the stack includes a first electrode, a dielectric layer, and a second electrode. The first electrode is formed from a conductive binary metal. A dielectric layer is formed over the first electrode. The dielectric layer is subjected to a milliseconds anneal process that serves to crystallize the dielectric material and decrease the concentration of oxygen vacancies. | 12-06-2012 |
| 20120315737 | METHODS OF FORMING VARIABLE RESISTIVE MEMORY DEVICES - A method of forming a variable resistive memory device includes forming a conductive pattern that alternates with a first insulation pattern along a first direction on a substrate that is parallel with a surface of the substrate, forming a preliminary sacrificial pattern on the conductive pattern that contacts a sidewall of the first insulation pattern, etching the conductive pattern using the preliminary sacrificial pattern as an etch masks to form a preliminary bottom electrode pattern, patterning the preliminary sacrificial pattern and the preliminary bottom electrode pattern to form a sacrificial pattern and a bottom electrode pattern that each include at least two portions which are separated from each other along a second direction intersecting the first direction, and replacing the sacrificial pattern with a variable resistive pattern. | 12-13-2012 |
| 20120322220 | METHOD OF PROCESSING MIM CAPACITORS TO REDUCE LEAKAGE CURRENT - A method for processing dielectric materials and electrodes to decrease leakage current is disclosed. The method includes a post dielectric anneal treatment in an oxidizing atmosphere to reduce the concentration of oxygen vacancies in the dielectric material. The method further includes a post metallization anneal treatment in an oxidizing atmosphere to reduce the concentration of interface states at the electrode/dielectric interface and to further reduce the concentration of oxygen vacancies in the dielectric material. | 12-20-2012 |
| 20120322221 | MOLYBDENUM OXIDE TOP ELECTRODE FOR DRAM CAPACITORS - A metal oxide bilayer second electrode for a MIM DRAM capacitor is formed wherein the layer of the electrode that is in contact with the dielectric layer (i.e. bottom layer) has a desired composition and crystal structure. An example is crystalline MoO | 12-20-2012 |
| 20120322222 | METHOD FOR IMPROVING CAPACITANCE UNIFORMITY IN A MIM DEVICE - A method for improving capacitance uniformity in a MIM device, mainly for the purpose of improving uniformity of a thin film within the MIM device, includes eight steps in order and step S | 12-20-2012 |
| 20120329235 | WET ETCH AND CLEAN CHEMISTRIES FOR MoOx - A method of removing non-noble metal oxides from material (e.g., semiconductor material) used to make a microelectronic device includes providing the material comprising traces of the conducting non-noble metal oxides; applying a chemical mixture (or chemical solution) to the material; removing the traces of the non-noble metal oxides from the material; and removing the chemical mixture from the material. The non-noble metal oxides comprise MoO | 12-27-2012 |
| 20120329236 | METHOD OF MANUFACTURING DEVICE - A method of manufacturing a device includes: forming a fifth insulating film on a semiconductor substrate having a peripheral circuit region and a memory cell region in which a contact pad is formed; forming a second sacrifice film in the memory cell region in which the fifth insulating film is formed; forming, after the forming of the second sacrifice, a second insulating film in the peripheral circuit region on the semiconductor substrate to have a sidewall coming into contact with the second sacrifice film; forming a third insulating film to cover an upper surface of the second sacrifice film and an upper surface of the second insulating film; forming a hole penetrating through the third insulating film, the second sacrifice film and the fifth insulating film in the memory cell region; forming a lower electrode in the hole; and removing all of the second sacrifice film. | 12-27-2012 |
| 20130005109 | METHOD FOR FORMING A TOROIDAL INDUCTOR IN A SEMICONDUCTOR SUBSTRATE - A toroidal inductor formed in a semiconductor substrate. Through-silicon vias are used to connect metal layers formed on top and bottom surfaces of the semiconductor substrate. In one embodiment, the vias are elongated and laid out in two concentric circles, an inner circle enclosed by an outer circle. The vias of the outer concentric circle are longer than the vias of the inner circle so that spaces between vias are the same for both circles. In another embodiment, each elongated via may include a plurality of circular vias formed in a line. Metals layers on the top and bottom of the semiconductor substrate are patterned to form wedge shaped connectors between the inner and outer vias to form the spirals of the toroidal inductor. The wedge shaped connectors with elongated vias allow spacing between spirals to be constant. | 01-03-2013 |
| 20130005110 | Method of fabricating semiconductor device - Provided is a method of manufacturing a semiconductor device having a capacitor. The method includes forming a composite layer, including sequentially stacking on a substrate alternating layers of first through nth sacrificial layers and first through nth supporting layers. A plurality of openings that penetrate the composite layer are formed. A lower electrode is formed in the plurality of openings. At least portions of the first through nth sacrificial layers are removed to define a support structure for the lower electrode extending between adjacent ones of the plurality of openings and the lower electrode formed therein, the support structure including the first through nth supporting layers and a gap region between adjacent ones of the first through nth supporting layers where the first through nth sacrificial layers have been removed. A dielectric layer is formed on the lower electrode and an upper electrode is formed on the dielectric layer. | 01-03-2013 |
| 20130005111 | Methods of Forming Capacitors - Some embodiments include methods of making stud-type capacitors utilizing carbon-containing support material. Openings may be formed through the carbon-containing support material to electrical nodes, and subsequently conductive material may be grown within the openings. The carbon-containing support material may then be removed, and the conductive material utilized as stud-type storage nodes of stud-type capacitors. The stud-type capacitors may be incorporated into DRAM, and the DRAM may be utilized in electronic systems. | 01-03-2013 |
| 20130011987 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH VERTICAL GATE - A method for fabricating a semiconductor device includes forming a plurality of pillars by etching a semiconductor substrate, forming a conductive layer over a semiconductor substrate structure including the pillars, forming preliminary gates on sidewalls of each pillar by performing a first etch process on the conductive layer, and forming vertical gates by performing a second etch process on upper portions of the preliminary gates. | 01-10-2013 |
| 20130011988 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A LAMINATED STRUCTURE COMPRISING A BORON-DOPED SILICON GERMANIUM FILM AND A METAL FILM - A semiconductor device has memory cell portions and compensation capacitance portions on a single substrate. The memory cell portion and the compensation capacitance portion have mutually different planar surface areas. The memory cell portion and the compensation capacitance portion include capacitance plate electrodes of the same structure. The capacitance plate electrode has a laminated structure including a boron-doped silicon germanium film and a metal film. | 01-10-2013 |
| 20130011989 | METHODS OF MANUFACTURING A DRAM DEVICE - In methods of manufacturing a DRAM device, a buried-type gate is formed in a substrate. A capping insulating layer pattern is formed on the buried-type gate. A conductive layer pattern filling up a gap between portions of the capping insulating layer pattern, and an insulating interlayer covering the conductive layer pattern and the capping insulating layer pattern are formed. The insulating interlayer, the conductive layer pattern, the capping insulating layer pattern and an upper portion of the substrate are etched to form an opening, and a first pad electrode making contact with a first pad region. A spacer is formed on a sidewall of the opening corresponding to a second pad region. A second pad electrode is formed in the opening. A bit line electrically connected with the second pad electrode and a capacitor electrically connected with the first pad electrode are formed. | 01-10-2013 |
| 20130011990 | Methods of Making Crystalline Tantalum Pentoxide - There is disclosed a method of forming crystalline tantalum pentoxide on a ruthenium-containing material having an oxygen-containing surface wherein the oxygen-containing surface is contacted with a treating composition, such as water, to remove at least some oxygen. Crystalline tantalum pentoxide is formed on at least a portion of the surface having reduced oxygen content. | 01-10-2013 |
| 20130011991 | METHOD OF FORMING A MEMORY DEVICE INCORPORATING A RESISTANCE VARIABLE CHALCOGENIDE ELEMENT - A method of forming a memory device, such as a PCRAM, including selecting a chalcogenide glass backbone material for a resistance variable memory function and devices formed using such a method. | 01-10-2013 |
| 20130017662 | FILLER FOR FILLING A GAP, METHOD OF PREPARING THE SAME AND METHOD OF MANUFACTURING SEMICONDUCTOR CAPACITOR USING THE SAMEAANM PARK; Eun-SuAACI Uiwang-siAACO KRAAGP PARK; Eun-Su Uiwang-si KRAANM Kim; Bong-HwanAACI Uiwang-siAACO KRAAGP Kim; Bong-Hwan Uiwang-si KRAANM Lim; Sang-HakAACI Uiwang-siAACO KRAAGP Lim; Sang-Hak Uiwang-si KRAANM Kwak; Taek-SooAACI Uiwang-siAACO KRAAGP Kwak; Taek-Soo Uiwang-si KRAANM Bae; Jin-HeeAACI Uiwang-siAACO KRAAGP Bae; Jin-Hee Uiwang-si KRAANM Yun; Hui-ChanAACI Uiwang-siAACO KRAAGP Yun; Hui-Chan Uiwang-si KRAANM Kim; Sang-KyunAACI Uiwang-siAACO KRAAGP Kim; Sang-Kyun Uiwang-si KRAANM Lee; Jin-WookAACI Uiwang-siAACO KRAAGP Lee; Jin-Wook Uiwang-si KR - A filler for filling a gap includes a compound represented by the following Chemical Formula 1. | 01-17-2013 |
| 20130023105 | MEMORY DEVICE WITH A TEXTURED LOWERED ELECTRODE - Embodiments of the invention generally relate to memory devices and methods for manufacturing such memory devices. In one embodiment, a method for forming a memory device with a textured electrode is provided and includes forming a silicon oxide layer on a lower electrode disposed on a substrate, forming metallic particles on the silicon oxide layer, wherein the metallic particles are separately disposed from each other on the silicon oxide layer. The method further includes etching between the metallic particles while removing a portion of the silicon oxide layer and forming troughs within the lower electrode, removing the metallic particles and remaining silicon oxide layer by a wet etch process while revealing peaks separated by the troughs disposed on the lower electrode, forming a metal oxide film stack within the troughs and over the peaks of the lower electrode, and forming an upper electrode over the metal oxide film stack. | 01-24-2013 |
| 20130029467 | METHOD OF FORMING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes the following processes. A first groove is formed in a semiconductor substrate. A first conductive film is formed in the first groove and over the semiconductor substrate. The first conductive film is planarized over the semiconductor substrate. The planarized first conductive film is selectively etched to have the planarized first conductive film remain in a lower portion of the first groove. | 01-31-2013 |
| 20130052784 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - To reduce dent defects formed in interlayer CMP process on a capacitor array after forming an interlayer insulating film on the capacitor array thicker than the height of a capacitor, the interlayer insulating film on the capacitor array is subjected to a step height reduction etching to form an opening with etching depth H | 02-28-2013 |
| 20130059425 | Imprinted Memory - The rising mask cost would make mask-ROM economically un-viable below 90 nm. The present invention discloses an imprinted memory, more particularly a three-dimensional imprinted memory (3D-iP). It uses imprint-lithography (also referred to as nano-imprint lithography, or NIL) to record data. The data-template used by imprint-lithography is much less expensive than the data-mask used by photo-lithography. | 03-07-2013 |
| 20130065375 | Methods of Forming Semiconductor Devices Having Capacitor and Via Contacts - Disclosed herein are various methods of forming semiconductor devices that have capacitor and via contacts. In one example, the method includes forming a first conductive structure and a bottom electrode of a capacitor in a layer of insulating material, forming a layer of conductive material above the first conductive structure and the bottom electrode and performing an etching process on the layer of conductive material to define a conductive material hard mask and a top electrode for the capacitor, wherein the conductive material hard mask is positioned above at least a portion of the first conductive structure. This illustrative method includes the further steps of forming an opening in the conductive material hard mask and forming a second conductive structure that extends through the opening in the conductive material hard mask and conductively contacts the first conductive structure. | 03-14-2013 |
| 20130065376 | SEMICONDUCTOR CAPACITOR - A semiconductor capacitor and its method of fabrication are disclosed. A non-linear nitride layer is used to increase the surface area of a capacitor plate, resulting in increased capacitance without increase in chip area used for the capacitor. | 03-14-2013 |
| 20130071982 | Nonvolatile Memory Elements with Metal-Deficient Resistive-Switching Metal Oxides - Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed by depositing a metal-containing material on a silicon-containing material. The metal-containing material may be oxidized to form a resistive-switching metal oxide. The silicon in the silicon-containing material reacts with the metal in the metal-containing material when heat is applied. This forms a metal silicide lower electrode for the nonvolatile memory element. An upper electrode may be deposited on top of the metal oxide. Because the silicon in the silicon-containing layer reacts with some of the metal in the metal-containing layer, the resistive-switching metal oxide that is formed is metal deficient when compared to a stoichiometric metal oxide formed from the same metal. | 03-21-2013 |
| 20130071983 | Inductors and Methods for Integrated Circuits - Inductors and methods for integrated circuits that result in inductors of a size compatible with integrated circuits, allowing the fabrication of inductors, with or without additional circuitry on a first wafer and the bonding of that wafer to a second wafer without wasting of wafer area. The inductors in the first wafer are comprised of coils formed by conductors at each surface of the first wafer coupled to conductors in holes passing through the first wafer. Various embodiments are disclosed. | 03-21-2013 |
| 20130078782 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device prevents a lower electrode from leaning, in a dip-out process of an interlayer insulation film forming a lower electrode. A conductive material of a lower electrode is used as a support layer instead of a conventional nitride film support layer. This prevents a crack from being generated in a nitride film support layer. A method for manufacturing the semiconductor device is also disclosed. | 03-28-2013 |
| 20130089964 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A lower electrode includes a metal-containing oxide layer having a thickness of 2 nm or less on the surface layer. A metal-containing oxide layer is formed by oxidizing the surface of the lower electrode. A dielectric film includes a first phase appearing at room temperature in the bulk state and a second phase appearing at a higher temperature than that in the first phase in the bulk state. The second phase has a higher relative permittivity than that of the first phase. | 04-11-2013 |
| 20130095632 | Enhanced Work Function Layer Supporting Growth of Rutile Phase Titanium Oxide - This disclosure provides a method of fabricating a semiconductor stack and associated device, such as a capacitor and DRAM cell. In particular, a bottom electrode has a material selected for lattice matching characteristics. This material may be created from a relatively inexpensive metal oxide which is processed to adopt a conductive, but difficult-to-produce oxide state, with specific crystalline form; to provide one example, specific materials are disclosed that are compatible with the growth of rutile phase titanium dioxide (TiO | 04-18-2013 |
| 20130102120 | METHODS OF MANUFACTURING PHASE-CHANGE MEMORY DEVICE AND SEMICONDUCTOR DEVICE - Methods of manufacturing a phase-change memory device and a semiconductor device are provided. The method of manufacturing the phase-change memory device includes forming a switching device layer, an ohmic contact layer, and a hard mask layer on a semiconductor substrate, patterning the hard mask layer to form a hard mask pattern, etching the ohmic layer and the switching layer using the hard mask pattern to form a pattern structure including an ohmic contact pattern, a switching device pattern, and the hard mask pattern, selectively oxidizing a surface of the pattern structure, forming an insulating layer to bury the pattern structure, and selectively removing the hard mask pattern other than the oxidized surface thereof to form a contact hole. | 04-25-2013 |
| 20130102121 | Oxygen Diffusion Barrier Comprising Ru - A method for forming a MIM capacitor structure includes the steps of obtaining a base structure provided with a recess, the recess exposing a conductive bottom electrode plug; selectively growing Ru on the bottom electrode plug, based on a difference in incubation time of Ru growth on the bottom electrode plug compared to the base structure material; oxidizing the selectively grown Ru; depositing a Ru-comprising bottom electrode over the oxidized Ru; forming a dielectric layer on the Ru-comprising bottom electrode; and—forming a conductive top electrode over the dielectric layer. | 04-25-2013 |
| 20130102122 | SEMICONDUCTOR PACKAGE AND METHOD FOR MAKING THE SAME - The present invention relates to a semiconductor package and a method for making the same. The method includes the steps of: (a) providing a base material; (b) forming a first metal layer on the base material, wherein the first metal layer comprises a first inductor and a first lower electrode; (c) forming a first dielectric layer and a first upper electrode on the first lower electrode, wherein the first dielectric layer is disposed between the first upper electrode and the first lower electrode, and the first upper electrode, the first dielectric layer and the first lower electrode form a first capacitor; and (d) forming a first protective layer, so as to encapsulate the first inductor and the first capacitor. | 04-25-2013 |
| 20130109147 | Methods of Forming Metal Oxide and Memory Cells | 05-02-2013 |
| 20130115748 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming a mold layer over a substrate, wherein the mold layer includes a first sacrificial layer and a second sacrificial layer that are stacked, forming an insulation layer pattern that has an etch selectivity to the first sacrificial layer and the second sacrificial layer on the mold layer, etching the mold layer using the insulation layer pattern as an etch barrier to form storage node holes, forming a storage node conductive layer over a substrate structure including the insulation layer pattern and the mold layer that has been etched, performing a storage node isolation process that simultaneously forms storage nodes and forming the insulation layer pattern to a first thickness, and removing the first sacrificial layer and the second sacrificial layer. | 05-09-2013 |
| 20130122678 | ADSORPTION SITE BLOCKING METHOD FOR CO-DOPING ALD FILMS - A method for doping a dielectric material by pulsing a first dopant precursor, purging the non-adsorbed precursor, pulsing a second precursor, purging the non-adsorbed precursor, and pulsing a oxidant to form an intermixed layer of two (or more) metal oxide dielectric dopant materials. The method may also be used to form a blocking layer between a bulk dielectric layer and a second electrode layer. The method improves the control of the composition and the control of the uniformity of the dopants throughout the thickness of the doped dielectric material. | 05-16-2013 |
| 20130122679 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The semiconductor device has an insulation layer formed over a semiconductor substrate, a conductor plug | 05-16-2013 |
| 20130130463 | MANUFACTURING METHOD OF CHARGING CAPACITY STRUCTURE - A method of manufacturing a charging capacity structure includes steps of: forming a first oxide layer, a support layer and a second oxide layer on a substrate in sequence; forming a plurality of etching holes on the surface of the second oxide layer in a matrix to run through the substrate that are spaced from each other at a selected distance; forming a plurality of pillar layers in the etching holes; removing the second oxide layer by etching; forming an etching protection layer on the surfaces of the support layer and pillar tubes that is formed at a thickness one half of the spaced distance between the etching holes such that the pillar tubes at diagonal locations form a self-calibration hole; and finally removing the first oxide layer from the self-calibration hole by etching. Through the self-calibration hole, the invention needn't to provide extra photoresists to form holes. | 05-23-2013 |
| 20130130464 | PLASMA PROCESSING OF METAL OXIDE FILMS FOR RESISTIVE MEMORY DEVICE APPLICATIONS - In some embodiments, the present invention discloses plasma processing at interfaces of an ALD metal oxide film with top and bottom electrodes to improve the ReRAM device characteristics. The interface processing can comprise an oxygen inhibitor step with a bottom polysilicon electrode to prevent oxidation of the polysilicon layer, enhancing the electrical contact of the metal oxide film with the polysilicon electrode. The interface processing can comprise an oxygen enrichment step with a top metal electrode to increase the resistivity of the metal oxide layer, providing an integrated current limiter layer. | 05-23-2013 |
| 20130130465 | METHODS OF FORMING INTEGRATED CIRCUIT CAPACITORS HAVING COMPOSITE DIELECTRIC LAYERS THEREIN CONTAINING CRYSTALLIZATION INHIBITING REGIONS - Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers. | 05-23-2013 |
| 20130130466 | Methods of Forming Electrical Components and Memory Cells - Some embodiments include methods of forming electrical components. First and second exposed surface configurations are formed over a first structure, and material is then formed across the surface configurations. The material is sub-divided amongst two or more domains, with a first of the domains being induced by the first surface configuration, and with a second of the domains being induced by the second surface configuration. A second structure is then formed over the material. The first domains of the material are incorporated into electrical components. The second domains may be replaced with dielectric material to provide isolation between adjacent electrical components, or may be utilized as intervening regions between adjacent electrical components. | 05-23-2013 |
| 20130130467 | RESIST FEATURE AND REMOVABLE SPACER PITCH DOUBLING PATTERNING METHOD FOR PILLAR STRUCTURES - A method of making a memory array is provided that includes forming a layer over a substrate, forming features over the layer, forming sidewall spacers on each of the features, filling spaces between adjacent sidewall spacers with filler features, removing the sidewall spacers to leave the features and the filler features, and etching the layer using the features and the filler features as a mask to form pillar shaped nonvolatile memory cells. Numerous other aspects are provided. | 05-23-2013 |
| 20130143379 | LEAKAGE REDUCTION IN DRAM MIM CAPACITORS - A method for reducing the leakage current in DRAM MIM capacitors comprises forming a multi-layer dielectric stack from an amorphous highly doped material, an amorphous high band gap material, and a lightly or non-doped material. The highly doped material will remain amorphous (<30% crystalline) after an anneal step. The high band gap material will remain amorphous (<30% crystalline) after an anneal step. The lightly or non-doped material will become crystalline (≧30% crystalline) after an anneal step. The high band gap material is formed between the amorphous highly doped material and the lightly or non-doped material and provides an intermediate barrier to conduction through the multi-layer dielectric stack. | 06-06-2013 |
| 20130143380 | METHODS OF FORMING A PHASE CHANGE LAYER AND METHODS OF FABRICATING A PHASE CHANGE MEMORY DEVICE INCLUDING THE SAME - A phase change structure includes a first phase change material layer pattern and a second phase change material layer pattern. The first phase change material layer pattern may partially fill a minute structure, and the second phase change material layer pattern may fully fill the minute structure. The first phase change material layer pattern may include a first phase change material, and the second phase change material layer pattern may include a second phase change material having a composition substantially different from a composition of the first phase change material. | 06-06-2013 |
| 20130143381 | ELECTRIC CIRCUIT CHIP AND METHOD OF MANUFACTURING ELECTRIC CIRCUIT CHIP - An electric circuit chip includes: a substrate made of glass or a semiconductor; and a circuit which is disposed in an inside of the substrate, has a first end portion and a second end portion exposed at specific surfaces of the substrate, and includes a spiral inductor. | 06-06-2013 |
| 20130149833 | Methods of Manufacturing Semiconductor Devices - A method of manufacturing a semiconductor device, the method including: preparing a semiconductor substrate including a mold layer and a support layer disposed on the mold layer; forming multiple holes that pass through the mold layer and the support layer; forming multiple bottom electrodes in the holes; exposing at least a portion of the bottom electrodes by removing at least a portion of the mold layer; removing a portion of the bottom electrodes from an exposed surface of the bottom electrodes; and sequentially forming a dielectric layer and a top electrode layer on the bottom electrodes. | 06-13-2013 |
| 20130149834 | Methods Of Forming Memory Cells, And Methods Of Patterning Chalcogenide-Containing Stacks - Some embodiments include methods of forming memory cells. Chalcogenide is formed over a plurality of bottom electrodes, and top electrode material is formed over the chalcogenide. Sacrificial material is formed over the top electrode material. A plurality of memory cell structures is formed by etching through the sacrificial material, top electrode material and chalcogenide. Each of the memory cell structures has a cap of the sacrificial material thereover. The etching forms polymeric residue over the sacrificial material caps, and damages chalcogenide along sidewalls of the structures. The sacrificial material is removed with an HF-containing solution, and such removes the polymeric residue off of the memory cell structures. After the sacrificial material is removed, the sidewalls of the structures are treated with one or both of H | 06-13-2013 |
| 20130157434 | PHASE CHANGE MEMORY APPARATUS AND FABRICATION METHOD THEREOF - A phase change memory apparatus is provided that includes a first electrode of a bar type having a trench formed on an active region of a semiconductor substrate, a second electrode formed in a bottom portion of the trench, and a bottom electrode contact formed on the second electrode. | 06-20-2013 |
| 20130164901 | Method of Making Capacitor With a Sealing Liner and Semiconductor Device Comprising Same - Generally, the subject matter disclosed herein relates to various methods of making a capacitor with a sealing liner and a semiconductor device including such a capacitor. In one example, the method includes forming a layer of insulating material, forming a capacitor opening in the layer of insulating material, forming a sealing liner on the sidewalls of the capacitor opening and forming a first metal layer in the capacitor opening and on the sealing liner by performing a process using a precursor having a minimum particle size, wherein the sealing liner is made of a material having an opening size that is less than the minimum particle size of the precursor. | 06-27-2013 |
| 20130164902 | Methods Of Forming Capacitors - A method of forming capacitors includes forming support material over a substrate. A first capacitor electrode is formed within individual openings in the support material. A first etching is conducted only partially into the support material using a liquid etching fluid to expose an elevationally outer portion of sidewalls of individual of the first capacitor electrodes. A second etching is conducted into the support material using a dry etching fluid to expose an elevationally inner portion of the sidewalls of the individual first capacitor electrodes. A capacitor dielectric is formed over the outer and inner portions of the sidewalls of the first capacitor electrodes. A second capacitor electrode is formed over the capacitor dielectric. | 06-27-2013 |
| 20130164903 | METHOD FOR FABRICATING CAPACITOR OF SEMICONDUCTOR DEVICE - A method for fabricating a capacitor of a semiconductor device includes sequentially forming an etch-stop layer and a mold layer over a substrate, sequentially forming a support layer and a hard mask pattern over the mold layer, forming a storage node hole by etching the support layer and the mold layer using the hard mask pattern as an etch barrier, forming a barrier layer on the sidewall of the mold layer inside the storage node hole, etching the etch-stop layer under the storage node hole, forming a storage node inside the storage node hole, and removing the hard mask pattern, the mold layer, and the barrier layer. | 06-27-2013 |
| 20130164904 | INDUCTOR STRUCTURES FOR INTEGRATED CIRCUIT DEVICES - An IC device ( | 06-27-2013 |
| 20130171797 | METHOD FOR FORMING MULTI-COMPONENT LAYER, METHOD FOR FORMING MULTI-COMPONENT DIELECTRIC LAYER AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method of forming a multi-component dielectric layer on the surface of a substrate by atomic layer deposition includes injecting a cocktail source of a plurality of sources at least having a cyclopentadienyl ligand, wherein the cocktail source is adsorbed on a surface of a substrate by injecting the cocktail source, performing a first purge process to remove a non-adsorbed portion of the cocktail source, injecting a reactant to react with the adsorbed cocktail source, wherein a multi-component layer is formed by the reaction between the reactant and the absorbed cocktail source, and performing a second purge process to remove reaction byproducts and an unreacted portion of the reactant. | 07-04-2013 |
| 20130171798 | METHOD OF MANUFACTURING PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE - A method of manufacturing a phase-change random access memory device. The method includes forming a word line on a semiconductor substrate, forming a switching element material and a hard mask material on the word line, etching the switching element material and the hard mask material to form a hole exposing the word line, forming an insulating material on a sidewall and a bottom of the hole, removing the hard mask material; and forming a heater material on the switching element material. The hard mask material has different etch selectivity from the insulating material. | 07-04-2013 |
| 20130178038 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - An FeRAM is produced by a method including the steps of forming a lower electrode layer, forming a first ferroelectric film on the lower electrode layer, forming on the first ferroelectric film a second ferroelectric film in an amorphous state containing iridium inside, thermally treating the second ferroelectric film in an oxidizing atmosphere to crystallize the second ferroelectric film and to cause iridium in the second ferroelectric film to diffuse into the first ferroelectric film, forming an upper electrode layer on the second ferroelectric film, and processing each of the upper electrode layer, the second ferroelectric film, the first ferroelectric film, and the lower electrode layer to form the capacitor structure. With such a structure, the inversion charge amount in a ferroelectric capacitor structure is improved without increasing the leak current pointlessly, and a high yield can be assured, thereby realizing a highly reliable FeRAM. | 07-11-2013 |
| 20130189823 | Profile Engineered Thin Film Devices and Structures - The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or dielectric precursor. The smooth and/or dome-shaped cross-sectional profile allows for smooth topological transitions without sharp steps, preventing feature discontinuities during deposition and allowing for more complete step coverage of subsequently deposited structures. The inventive profile allows for both the uniform growth of oxide layers by thermal oxidation, and substantially uniform etching rates of the structures. Such oxide layers may have a uniform thickness and provide substantially complete coverage of the underlying electrically active feature. Uniform etching allows for an efficient method of reducing a critical dimension of an electrically active structure by simple isotropic etch. | 07-25-2013 |
| 20130203232 | MANUFACTURING METHOD OF RANDOM ACCESS MEMORY - A manufacturing method of a random access memory includes the following steps: providing a semiconductor structure having an array region and a peripheral region; forming a plurality of first trenches in the array region, and concurrently, a plurality of second trenches on the peripheral region; forming a polysilicon layer to cover the array region and the peripheral region, and the first and the second trenches are filled up with the polysilicon layer; planarizing the polysilicon layer so the remaining polysilicon layer only resides in the first and the second trenches; forming a conductive layer on the semiconductor structure; patterning the conductive layer to form a plurality of landing pads on the array region, and a plurality of bit line units on the peripheral region; and forming a plurality of capacitor units which is in electrical connection to the landing pads. | 08-08-2013 |
| 20130230961 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FORMING THE SAME - According to example embodiments of inventive concepts, method of forming a semiconductor memory devices includes sequentially forming a first mold layer, a first support layer, a second mold layer, and a second support layer on a substrate, forming lower electrodes penetrating the second support layer, the second mold layer, the first support layer, and the first mold layer on the substrate, patterning the second support layer to form a second support pattern including an opening, removing the second mold layer to expose portions of sidewalls of the lower electrodes, and etching the exposed sidewalls of the lower electrodes. | 09-05-2013 |
| 20130244394 | METHOD FOR FABRICATING CAPACITOR WITH HIGH ASPECT RATIO - A method for fabricating a capacitor includes: forming a first silicon layer over a semiconductor substrate, where the first silicon layer is doped with a dopant; forming an undoped second silicon layer over the first silicon layer; forming an opening by etching the second silicon layer and the first silicon layer; forming a storage node in the opening; and removing the first silicon layer and the second silicon layer. | 09-19-2013 |
| 20130260527 | METHOD OF FORMING A METAL CHALCOGENIDE MATERIAL AND METHODS OF FORMING MEMORY CELLS INCLUDING SAME - A method of forming a metal chalcogenide material. The method comprises exposing a metal to a solution comprising a chalcogenide element source compound and an acid. Methods of forming memory cells including the metal chalcogenide material are also disclosed. | 10-03-2013 |
| 20130280879 | Method for Producing a Conductor Line - A method for producing a rounded conductor line of a semiconductor component is disclosed. In that method, a partially completed semiconductor component is provided. The partially completed semiconductor component has a bottom side and a top side spaced distant from the bottom side in a vertical direction. Also provided is an etchant. On the top side, a dielectric layer is arranged. The dielectric layer has at least two different regions that show different etch rates when they are etched with the etchant. Subsequently, a trench is formed in the dielectric layer such that the trench intersects each of the different regions. Then, the trench is widened by etching the trench with the etchant at different etch rates. By filling the widened trench with an electrically conductive material, a conductor line is formed. | 10-24-2013 |
| 20130280880 | PHASE-CHANGE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME - A phase-change memory device with improved deposition characteristic and a method of fabricating the same are provided. The phase-change memory device includes a semiconductor substrate having a phase-change area, a first material-rich first phase-change layer forming an inner surface of the phase-change area and comprised of a hetero compound of the first material and a second material, and a second phase-change layer formed on a surface of the first phase-change layer to fill the phase-change area. | 10-24-2013 |
| 20130280881 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A semiconductor device including a substrate; a bottom electrode on the substrate; a first dielectric layer on the bottom electrode, the first dielectric layer including a first metal oxide including at least one of Hf, Al, Zr, La, Ba, Sr, Ti, and Pb; a second dielectric layer on the first dielectric layer, the second dielectric layer including a second metal oxide including at least one of Hf, Al, Zr, La, Ba, Sr, Ti, and Pb, wherein the first metal oxide and the second metal oxide are different materials; a third dielectric layer on the second dielectric layer, the third dielectric layer including a metal carbon oxynitride; and an upper electrode on the third dielectric layer. | 10-24-2013 |
| 20130295743 | NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a nonvolatile memory device includes a selection element layer and a nanomaterial aggregate layer. The selection element layer includes silicon. The nanomaterial aggregate layer is stacked on the selection element layer. The nanomaterial aggregate layer includes a plurality of micro conductive bodies and fine particles dispersed in a plurality of gaps between the micro conductive bodies. At least a surface of the fine particle is made of an insulating material other than silicon oxide. | 11-07-2013 |
| 20130309832 | MOS CAPACITORS WITH A FINFET PROCESS - Methods for capacitor fabrication include doping a capacitor region of a semiconductor layer in a semiconductor-on-insulator substrate; partially etching the semiconductor layer to produce a first terminal layer comprising doped semiconductor fins on a remaining base of doped semiconductor; forming a dielectric layer over the first terminal layer; and forming a second terminal layer over the dielectric layer in a finFET process. | 11-21-2013 |
| 20130309833 | Decoupling Composite Capacitor in a Semiconductor Wafer - According to an exemplary embodiment, a method for fabricating a decoupling composite capacitor in a wafer that includes a dielectric region overlying a substrate includes forming a through-wafer via in the dielectric region and the substrate. The through-wafer via includes a through-wafer via insulator covering a sidewall and a bottom of a through-wafer via opening and a through-wafer via conductor covering the through-wafer via insulator. The method further includes thinning the substrate, forming a substrate backside insulator, forming an opening in the substrate backside insulator to expose the through-wafer via conductor, and forming a backside conductor on the through-wafer via conductor, such that the substrate backside conductor extends over the substrate backside insulator, thereby forming the decoupling composite capacitor. The substrate forms a first decoupling composite capacitor electrode and the through-wafer via conductor and substrate backside conductor form a second decoupling composite capacitor electrode. | 11-21-2013 |
| 20130323901 | CAPACITIVE ELEMENT, MANUFACTURING METHOD OF THE SAME, SOLID-STATE IMAGING DEVICE, AND IMAGING APPARATUS - A capacitive element, includes: an active region parted by an element isolation region formed in a semiconductor substrate; a first electrode formed of a diffusion layer in the active region; an insulating layer formed on the first electrode; and a second electrode formed on a planar surface of the first electrode via the insulating layer, wherein the second electrode is formed within the active region and within the first electrode in a planar layout. | 12-05-2013 |
| 20130323902 | Methods of Forming a Plurality of Capacitors - A method of forming a plurality of capacitors includes providing a plurality of capacitor electrodes, an elevationally inner insulative retaining material received laterally about the capacitor electrodes, an elevationally outer insulative retaining material received laterally about the capacitor electrodes, a first material received laterally about the capacitor electrodes elevationally inward of the inner insulative retaining material, and a second material received laterally about the capacitor electrodes elevationally between the inner and outer insulative retaining materials. Openings are anisotropically etched to extend through the outer insulative retaining material and the second material. After the anisotropic etching, remaining of the second material is isotropically etched through the openings from being received laterally about the capacitor electrodes between the inner and outer insulative retaining materials. The isotropic etching of the second material is conducted selectively relative to the capacitor electrodes and the inner and outer insulative retaining materials. The capacitor electrodes are ultimately incorporated into a plurality of capacitors. | 12-05-2013 |
| 20130337625 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The present invention provides a method for manufacturing a semiconductor device including a metal compound film formation process based on an atomic layer deposition (ALD) with repeating a plurality of cycles in which a supply time of a metallic source gas at the first time of the cycles is longer than a supply time of the source gas at the second time or later of the cycles, the ALD including, as one cycle, supplying the metallic source gas to adsorb a metallic source onto a foundation; purging the metallic source gas from a film-forming space; supplying a reactant gas to convert the metallic source into a corresponding metal compound; and purging the reactant gas. | 12-19-2013 |
| 20130337626 | Monolithic Group III-V and Group IV Device - According to one disclosed embodiment, a method for fabricating a monolithic integrated composite device comprises forming a group III-V semiconductor body over a group IV semiconductor substrate, forming a trench in the group III-V semiconductor body, and forming a group IV semiconductor body in the trench. The method also comprises fabricating at least one group IV semiconductor device in. the group IV semiconductor body, and fabricating at least one group III-V semiconductor device in the group III-V semiconductor body. In one embodiment, the method further comprises planarizing an upper surface of the III-V semiconductor body and an upper surface of the group IV semiconductor body to render those respective upper surfaces substantially co-planar. In one embodiment, the method further comprises fabricating at least one passive device in a defective region of said group IV semiconductor body adjacent to a side-wall of the trench. | 12-19-2013 |
| 20130344674 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A LAMINATED STRUCTURE COMPRISING A BORON-DOPED SILICON GERMANIUM FILM AND A METAL FILM - A semiconductor device has memory cell portions and compensation capacitance portions on a single substrate. The memory cell portion and the compensation capacitance portion have mutually different planar surface areas. The memory cell portion and the compensation capacitance portion include capacitance plate electrodes of the same structure. The capacitance plate electrode has a laminated structure including a boron-doped silicon germanium film and a metal film. | 12-26-2013 |
| 20130344675 | INTEGRATED DECOUPLING CAPACITOR EMPLOYING CONDUCTIVE THROUGH-SUBSTRATE VIAS - A capacitor in a semiconductor substrate employs a conductive through-substrate via (TSV) as an inner electrode and a columnar doped semiconductor region as an outer electrode. The capacitor provides a large decoupling capacitance in a small area, and does not impact circuit density or a Si3D structural design. Additional conductive TSV's can be provided in the semiconductor substrate to provide electrical connection for power supplies and signal transmission therethrough. The capacitor has a lower inductance than a conventional array of capacitors having comparable capacitance, thereby enabling reduction of high frequency noise in the power supply system of stacked semiconductor chips. | 12-26-2013 |
| 20140004678 | METHOD FOR FABRICATING CAPACITOR OF SEMICONDUCTOR DEVICE | 01-02-2014 |
| 20140004679 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE | 01-02-2014 |
| 20140017872 | METHOD FOR FABRICATING A METAL-INSULATOR-METAL CAPACITOR - A method for fabricating a metal-insulator-metal capacitor (MIMCap) is disclosed. A first metal layer is provided on top of an oxide layer. A nitride layer is then deposited on the first metal layer. The nitride layer and the first metal layer are etched to form a MIMCap metal layer. The gaps among the MIMCap metal layer are filled with a plasma oxide, and the excess plasma oxide is polished using the nitride layer a polish stop. After removing the nitride layer, a dielectric layer and a second metal layer are deposited on the MIMCap metal layer. Finally, the dielectric layer and the second metal layer are etched to form a set of MIMCap structures. | 01-16-2014 |
| 20140030863 | METHODS OF FORMING CAPACITORS - A method of forming capacitors includes providing first capacitor electrodes within support material. The first capacitor electrodes contain TiN and the support material contains polysilicon. The polysilicon-containing support material is dry isotropically etched selectively relative to the TiN-containing first capacitor electrodes using a sulfur and fluorine-containing etching chemistry. A capacitor dielectric is formed over sidewalls of the first capacitor electrodes and a second capacitor electrode is formed over the capacitor dielectric. Additional methods are disclosed. | 01-30-2014 |
| 20140065784 | METHODS OF FABRICATING A SEMICONDUCTOR DEVICE WITH CAPACITORS USING MOLD STRUCTURE AND PROTECTION LAYER - A method of fabricating a semiconductor device with capacitors may include forming a mold structure on a lower structure, patterning the mold structure to form a plurality of holes exposing the lower structure, forming a protection layer on sidewalls of the mold structure exposed by the holes, forming lower electrodes in the holes provided with the protection layer, removing the mold structure to expose the protection layer, removing the protection layer to expose sidewalls of the lower electrodes, and sequentially forming a dielectric film and an upper electrode on the lower electrodes. | 03-06-2014 |
| 20140065785 | SEMICONDUCTOR DEVICES INCLUDING A SUPPORT FOR AN ELECTRODE AND METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING A SUPPORT FOR AN ELECTRODE - Semiconductor devices are provided. Each of the semiconductor devices may include a plurality of electrodes. Moreover, each of the semiconductor devices may include a supporting pattern connected to sidewalls of the plurality of electrodes. Related methods of forming semiconductor devices are also provided. For example, the methods may include forming the supporting pattern before forming the plurality of electrodes. | 03-06-2014 |
| 20140065786 | Large Dimension Device and Method of Manufacturing Same in Gate Last Process - An integrated circuit device and methods of manufacturing the same are disclosed. In an example, integrated circuit device includes a capacitor having a doped region disposed in a semiconductor substrate, a dielectric layer disposed over the doped region, and an electrode disposed over the dielectric layer. At least one post feature embedded in the electrode. | 03-06-2014 |
| 20140113427 | PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A phase-change random access memory (PCRAM) device includes a semiconductor substrate; switching elements formed on the semiconductor substrate; a plurality of phase-change structures formed on the switching elements; and heat absorption layers buried between the plurality of phase-change structures, wherein the plurality of phase-change structures are insulated from the heat absorption layers. | 04-24-2014 |
| 20140120683 | CAPACITOR OF SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Capacitor of a semiconductor device, and a method of fabricating the same, include sequentially forming a mold structure and a polysilicon pattern over a semiconductor substrate, patterning the mold structure using the polysilicon pattern as an etch mask to form lower electrode holes penetrating the mold structure, forming a protection layer covering a surface of the polysilicon pattern, forming lower electrodes in the lower electrode holes provided with the protection layer, removing the polysilicon pattern and the protection layer to expose upper sidewalls of the lower electrodes, removing the mold structure to expose lower sidewalls of the lower electrodes, and sequentially forming a dielectric and an upper electrode covering the lower electrodes. | 05-01-2014 |
| 20140120684 | Methods of Forming Capacitors - A method of forming capacitors includes providing first capacitor electrodes within support material. The first capacitor electrodes contain TiN and the support material contains polysilicon. The polysilicon-containing support material is dry isotropically etched selectively relative to the TiN-containing first capacitor electrodes using a sulfur and fluorine-containing etching chemistry. A capacitor dielectric is formed over sidewalls of the first capacitor electrodes and a second capacitor electrode is formed over the capacitor dielectric. Additional methods are disclosed. | 05-01-2014 |
| 20140127875 | INTEGRATED DECOUPLING CAPACITOR UTILIZING THROUGH-SILICON VIA - A semiconductor device may include a through substrate via (TSV) conductive structure that may extend vertically through two or more layers of the semiconductor device. The TSV conductive structure may be coupled to a first voltage supply. The semiconductor device may include substrate layer. The substrate layer may include a first dopant region and a second dopant region. The first dopant region may be coupled to a second voltage supply. The second dopant region may be in electrical communication with the TSV conductive structure. The semiconductor device may include a first metal layer and a first insulator layer disposed between the substrate layer and the first metal layer. The first metal layer may laterally contact the TSV conductive structure. The first and second voltage supply may be adapted to create a capacitance at a junction between the first dopant region and the second dopant region. | 05-08-2014 |
| 20140134821 | METHOD FOR FABRICATING CAPACITOR HAVING RUTILE TITANIUM OXIDE DIELECTRIC FILM - A method for fabricating a capacitor includes: (1) forming a bottom electrode on a substrate; (2) forming a template layer on the bottom electrode; (3) performing a plurality of atomic layer deposition (ALD) cycles by using water vapor as an oxidant thereby depositing a first TiO2 layer on the template layer; and (4) performing ozone pulse and purge step to transform entire thickness of the first TiO2 layer into rutile phase. | 05-15-2014 |
| 20140154858 | AREA-EFFICIENT CAPACITOR USING CARBON NANOTUBES - An on-chip decoupling capacitor is disclosed. One or more carbon nanotubes are coupled to a first electrode of the capacitor. A dielectric skin is formed on the one or more carbon nanotubes. A metal coating is formed on the dielectric skin. The dielectric skin is configured to electrically isolate the one or more carbon nanotubes from the metal coating. | 06-05-2014 |
| 20140162427 | METHOD OF FORMING A FINE PATTERN OF A SEMICONDUCTOR DEVICE - A method of forming a fine pattern includes forming first line mask patterns on a mask layer to extend along a direction, forming second line mask patterns to extend along a diagonal direction with respect to the first line mask patterns, anisotropically etching the mask layer exposed by the first and second line mask patterns to form elliptical openings, and isotropically etching the mask layer provided with the openings to form a mask pattern with enlarged openings. | 06-12-2014 |
| 20140187015 | Methods to Improve Leakage for ZrO2 Based High K MIM Capacitor - A first electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the first electrode layer contains a conductive base layer and conductive metal oxide layer. A second electrode layer for a Metal-Insulator-Metal (MIM) DRAM capacitor is formed wherein the second electrode layer contains a conductive base layer and conductive metal oxide layer. In some embodiments, both the first electrode layer and the second electrode layer contain a conductive base layer and conductive metal oxide layer. | 07-03-2014 |
| 20140187016 | High Work Function, Manufacturable Top Electrode - Provided are MIM DRAM capacitors and methods of forming thereof. A MIM DRAM capacitor may include an electrode layer formed from a high work function material (e.g., greater than about 5.0 eV). This layer may be used to reduce the leakage current through the capacitor. The capacitor may also include another electrode layer having a high conductivity base portion and a conductive metal oxide portion. The conductive metal oxide portion serves to promote the growth of the high k phase of the dielectric layer. | 07-03-2014 |
| 20140187017 | PROCESS OF PREPARING A GAP FILLER AGENT, A GAP FILLER AGENT PREPARED USING SAME, AND A METHOD FOR MANUFACTURING SEMICONDUCTOR CAPACITOR USING THE GAP FILLER AGENT - A method of preparing a gap filler agent includes adding a halosilane to a basic solvent, and, to the basic solvent and the halosilane, adding ammonia in an amount of about 50 to about 70 parts by weight based on 100 parts by weight of the halosilane at a rate of about 1 g/hr to about 15 g/hr. | 07-03-2014 |
| 20140199819 | METHOD OF FABRICATING CAPACITOR STRUCTURE - A method of fabricating a capacitor structure includes the following steps. Firstly, a substrate is provided. A first conductive layer, a first insulation layer, a second conductive layer and a second insulation layer are sequentially formed over the substrate. A hard mask material layer is formed on the second insulation layer. Then, the hard mask material layer is defined with a photo resist pattern, so that a hard mask is formed. After the photo resist pattern is removed, the second conductive layer is defined with the hard mask, so that a first electrode of the capacitor structure is formed. | 07-17-2014 |
| 20140235027 | SILICON CARRIER SPACE TRANSFORMER AND TEMPORARY CHIP ATTACH BURN-IN VEHICLE FOR HIGH DENSITY CONNECTIONS - A silicon carrier space transformer assembly includes one or more silicon structures, which provide space transformer scaling to permit interconnection for fine pitch input/output interconnections with a semiconductor die or wafer, and fine pitch test probe tips connected to the one or more silicon structures. | 08-21-2014 |
| 20140242772 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A semiconductor device includes a dielectric layer in which zirconium, hafnium, and a IV group element are mixed. A method for fabricating a capacitor includes forming a bottom electrode, forming the dielectric layer and forming a top electrode over the dielectric layer. | 08-28-2014 |
| 20140242773 | PHASE CHANGE MEMORY DEVICE HAVING SELF-ALIGNED BOTTOM ELECTRODE AND FABRICATION METHOD THEREOF - A semiconductor memory device and a fabrication method thereof capable of improving electric contact characteristic between an access device and a lower electrode are provided. The semiconductor memory device includes an access device formed in a pillar shape on a semiconductor substrate, a first conductive layer formed over the access device, a protection layer formed on an edge of the first conductive layer to a predetermined thickness, and a lower electrode connected to the first conductive layer. | 08-28-2014 |
| 20140273391 | INDUCTIVE ELEMENT WITH INTERRUPTER REGION AND METHOD FOR FORMING - A semiconductor device structure a semiconductor substrate having a first conductivity type and a top surface. A plurality of first doped regions is at a first depth below the top surface arranged in a checkerboard fashion. The first doped regions are of a second conductivity type. A dielectric layer is over the top surface. An inductive element is over the dielectric layer, wherein the inductive element is over the first doped regions. | 09-18-2014 |
| 20140273392 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor integrated circuit device includes a lower electrode formed on a substrate, a first dielectric layer formed of a metal nitride layer, a metal oxynitride layer, or a combination thereof, on the lower electrode, a second dielectric layer formed on the first dielectric layer that includes a zirconium oxide layer, and an upper electrode formed on the second dielectric layer. | 09-18-2014 |
| 20140273393 | HIGH DENSITY THREE-DIMENSIONAL INTEGRATED CAPACITORS - A capacitor can include a substrate having a first surface, a second surface remote from the first surface, and a through opening extending between the first and second surfaces, first and second metal elements, and a capacitor dielectric layer separating and insulating the first and second metal elements from one another at least within the through opening. The first metal element can be exposed at the first surface and can extend into the through opening. The second metal element can be exposed at the second surface and can extend into the through opening. The first and second metal elements can be electrically connectable to first and second electric potentials. The capacitor dielectric layer can have an undulating shape. | 09-18-2014 |
| 20140308794 | SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming an insulation layer over a substrate; forming an open portion in the insulation layer; forming a sacrificial spacer over sidewalls of the open portion; forming, over the sacrificial spacer, a first conductive pattern in a lower section of the open portion; forming an ohmic contact layer over the first conductive pattern; forming an air gap by removing the sacrificial spacer; capping the air gap by forming a barrier layer over the ohmic contact layer; and forming a second conductive pattern over the barrier layer to fill an upper section of the open portion. | 10-16-2014 |
| 20140308795 | METHOD OF MANUFACTURING A SEMICONDUCTOR COMPONENT AND STRUCTURE - A semiconductor component and methods for manufacturing the semiconductor component that includes a three dimensional helically shaped common mode choke. In accordance with embodiments, a transient voltage suppression device may be coupled to the monolithically integrated common mode choke. | 10-16-2014 |
| 20140315367 | RINSE LIQUID FOR INSULATING FILM AND METHOD OF RINSING INSULATING FILM - A rinse liquid for an insulation layer, the rinse liquid including a solvent represented by the following Chemical Formula 1: | 10-23-2014 |
| 20140315368 | PROCESS FOR FORMING A CAPACITOR STRUCTURE WITH RUTILE TITANIUM OXIDE DIELECTRIC FILM - A process of forming a capacitor structure includes providing a substrate. Next, a first electrode is deposited onto the substrate. Later, a water-based ALD process is performed to deposit a transitional amorphous TiO | 10-23-2014 |
| 20140349461 | METHOD FOR USING METAL BILAYER - A method for using a metal bilayer is disclosed. First, a bottom electrode is provided. Second, a dielectric layer which is disposed on and is in direct contact with the lower electrode is provided. Then, a metal bilayer which serves as a top electrode in a capacitor is provided. The metal bilayer is disposed on and is in direct contact with the dielectric layer. The metal bilayer consists of a noble metal in direct contact with the dielectric layer and a metal nitride in direct contact with the noble metal. | 11-27-2014 |
| 20140357044 | METAL-INSUALTOR-METAL (MIM) DEVICE AND METHOD OF FORMATION THEREROF - In a method of fabricating a metal-insulator-metal (MIM) device, initially, a first electrode is provided. An oxide layer is provided on the first electrode, and a protective layer is provided on the oxide layer. An opening through the protective layer is provided to expose a portion of the oxide layer, and a portion of the first electrode underlying the exposed portion of the oxide layer is oxidized. A second electrode is provided in contact with the exposed portion of the oxide layer. in alternative embodiments, the initially provided oxide layer may be eliminated, and spacers of insulating material may be provided in the opening. | 12-04-2014 |
| 20140357045 | eFUSE AND METHOD OF FABRICATION - An improved eFuse and method of fabrication is disclosed. A cavity is formed in a substrate, which results in a polysilicon line having an increased depth in the area of the fuse, while having a reduced depth in areas outside of the fuse. The increased depth reduces the chance of the polysilicon line entering the fully silicided state. The cavity may be formed with a wet or dry etch. | 12-04-2014 |
| 20140377928 | METHOD FOR FINFET INTEGRATED WITH CAPACITOR - The present disclosure provides methods to fabricate a semiconductor structure that includes a semiconductor substrate having a first region and a second region; a shallow trench isolation (STI) feature formed in the semiconductor substrate. The STI feature includes a first portion disposed in the first region and having a first thickness T1 and a second portion disposed in the second region and having a second thickness T2 greater than the first depth, the first portion of the STI feature being recessed from the second portion of the STI feature. The semiconductor structure also includes a plurality of fin active regions on the semiconductor substrate; and a plurality of conductive features disposed on the fin active regions and the STI feature, wherein one of the conductive features covers the first portion of the STI feature in the first region. | 12-25-2014 |
| 20150017778 | Capacitor in Post-Passivation Structures and Methods of Forming the Same - A device includes a metal pad and a passivation layer having a portion overlapping the metal pad. A capacitor includes a bottom capacitor electrode underlying the passivation layer, wherein the bottom capacitor includes the metal pad. The capacitor further includes a top capacitor electrode over the portion of the passivation layer; and a capacitor insulator including the portion of the passivation layer. | 01-15-2015 |
| 20150017779 | SEMICONDUCTOR DEVICE HAVING STACKED STORAGE NODES OF CAPACITORS IN CELL REGION SEPARATED FROM PERIPHERAL REGION - Methods of fabricating a semiconductor device are provided. The method includes forming a first mold layer on a in a cell region and a peripheral region, forming first storage nodes penetrating the first mold layer in the cell region and a first contact penetrating the first mold layer in the peripheral region, forming a second mold layer on the first mold layer, forming second storage nodes that penetrate the second mold layer to be connected to respective ones of the first storage nodes, removing the second mold layer in the cell and peripheral regions and the first mold layer in the cell region to leave the first mold layer in the peripheral region, and forming a second contact that penetrates a first interlayer insulation layer to be connected to the first contact. Related devices are also provided. | 01-15-2015 |
| 20150031184 | METHODS OF MANUFACTURING A PACKAGE - A method of manufacturing a package may include: providing a first device having a first redistribution layer (RDL) and an insulator layer disposed over the first RDL; and forming a first micro-bump line over the insulator layer of the first device. The first micro-bump line may extend laterally over a surface of the insulator layer facing away from the first RDL, and a first inductor of the package comprises the first RDL and the first micro-bump line. | 01-29-2015 |
| 20150044848 | HIGH VOLTAGE HYBRID POLYMERIC-CERAMIC DIELECTRIC CAPACITOR - An integrated circuit includes isolation capacitors which include a silicon dioxide dielectric layer and a polymer dielectric layer over the layer of silicon dioxide. The silicon dioxide dielectric layer and the polymer dielectric layer extend across the integrated circuit. Top plates of the isolation capacitors have bond pads for wire bonds or bump bonds. Bottom plates of the isolation capacitors are connected to components of the integrated circuit. Other bond pads are connected to components in the integrated circuit through vias through the silicon dioxide dielectric layer and the polymer dielectric layer. | 02-12-2015 |
| 20150056778 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device includes: a multilayer wiring layer located over a substrate and in which multiple wiring layers configured by a wiring and an insulating layer are stacked; a memory circuit which is formed in a memory circuit region in the substrate and has a capacitance element embedded in a concave part located in the multilayer wiring layer; a logic circuit which is formed in a logic circuit region in the substrate; an upper part coupling wiring which is stacked over the capacitance element configured by a lower part electrode, a capacitor insulating film and an upper part electrode; and a cap layer which is formed on the upper surface of the wiring configuring the logic circuit. The upper surface of the upper part coupling wiring and the upper surface of the cap film are provided on the same plane. | 02-26-2015 |
| 20150056779 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate divided into a cell region and a peripheral circuit region defined in a first direction, wherein the peripheral circuit region is divided into a first region and a second region defined in a second direction substantially orthogonal to the first direction; gate lines formed over the semiconductor substrate in the cell region and arranged in the second direction; and a capacitor including lower electrodes over the semiconductor substrate, a dielectric layer and an upper electrode, wherein the lower electrodes in the first and second regions, separated from each other in the first direction and coupled to each other in the first region, the dielectric layer is formed along surfaces of the lower electrodes in the second region, and the upper electrode is formed over the dielectric layer. | 02-26-2015 |
| 20150079756 | Semiconductor Device and Fabrication Method Thereof - The semiconductor device fabrication method of the present invention includes: laminating a plurality of amorphous silicon films on a semiconductor substrate, forming through-holes that pass through the plurality of amorphous silicon films, and subjecting the plurality of amorphous silicon films | 03-19-2015 |
| 20150093873 | INDUCTOR DEVICE AND FABRICATION METHOD - Various embodiments provide inductor devices and fabrication methods. An exemplary inductor device can include a plurality of planar spiral wirings isolated by a dielectric layer. The planar spiral wirings can be connected by conductive pads formed over the dielectric layer and by conductive plugs formed in the dielectric layer. In one embodiment, a third planar spiral wiring can be formed over a second planar spiral wirings that is formed over a first planar spiral wiring. The third planar spiral wiring can be configured in parallel with the first third planar spiral wiring. The second planar spiral wiring can be configured in series with the first and third planar spiral wirings configured in parallel. | 04-02-2015 |
| 20150093874 | METHODS OF FORMING CAPACITORS AND SEMICONDUCTOR DEVICES INCLUDING A RUTILE TITANIUM DIOXIDE MATERIAL - Methods of forming a capacitor including forming a titanium nitride material within at least one aperture defined by a support material, forming a ruthenium material within the at least one aperture over the titanium nitride material, and forming a first conductive material over the ruthenium material within the at least one aperture. The titanium nitride material may be oxidized to a titanium dioxide material. A second conductive material may be formed over a surface of the titanium dioxide material. A semiconductor device may include at least one capacitor, wherein a major longitudinal portion of the at least one capacitor is not surrounded by a solid material. The capacitor may include a first electrode; a ruthenium oxide material laterally adjacent the first electrode; a rutile titanium dioxide material laterally adjacent the ruthenium oxide material; and a second electrode laterally adjacent the rutile titanium dioxide material. | 04-02-2015 |
| 20150093875 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein, semiconductor memory elements formed over the semiconductor substrate in the cell region, an interlayer insulating layer formed over the semiconductor substrate in the peripheral circuit region, first conductive layers substantially vertically passing through the interlayer insulating layer, and arranged in a matrix, and second conductive layers coupling the first conductive layers in rows or columns, each pair of the second conductive layers and the first conductive layers coupled to the each pair of the second conductive layers, respectively, forming electrodes of a capacitor. | 04-02-2015 |
| 20150111360 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a first conductive layer on a substrate, partially removing the first conductive layer and an upper portion of the substrate to form a recess, forming a second conductive layer pattern to fill the recess, forming a third conductive layer on the second conductive layer pattern and the first conductive layer, and patterning the third conductive layer and the second conductive layer pattern to form a bit line structure and a bit line contact, respectively. | 04-23-2015 |
| 20150126013 | SEMICONDUCTOR DEVICE INCLUDING AIR GAPS AND METHOD FOR FABRICATING THE SAME - Disclosed are a semiconductor device capable of reducing parasitic capacitance between adjacent conductive structures and a method for fabricating the same. The semiconductor device includes a plurality of bit line structures each comprising a first contact plug formed over a substrate and a bit line formed over the first contact plug. A spacer structure having air gaps is formed on sidewalls of the first contact plug and on sidewalls of the bit line. An plug isolation layer is formed between the plurality of bit line structures. The isolation layer includes an opening. A second contact plug is formed in the opening and a memory element is formed over the second contact plug. | 05-07-2015 |
| 20150132916 | METHOD FOR FABRICATING CAPACITOR - A method for fabricating a capacitor includes: forming a storage node contact plug over a substrate; forming an insulation layer having an opening exposing a surface of the storage node contact plug over the storage contact plug; forming a conductive layer for a storage node over the insulation layer and the exposed surface of the storage node contact plug through two steps performed at different temperatures; performing an isolation process to isolate parts of the conductive layer; and sequentially forming a dielectric layer and a plate electrode over the isolated conductive layer. | 05-14-2015 |
| 20150140772 | USING MULTI-LAYER MIMCAPS WITH DEFECTIVE BARRIER LAYERS ASSELECTOR ELEMENT FOR A CROSS BAR MEMORY ARRAY - Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a low band gap dielectric layer disposed between two higher band gap dielectric layers. The high band gap dielectric layers can be doped with doping materials to form traps at energy levels higher than the operating voltage of the memory device. | 05-21-2015 |
| 20150140773 | METHODS OF FORMING INSULATIVE ELEMENTS - Methods of forming an insulative element are described, including forming a first metal oxide material having a first dielectric constant, forming a second metal oxide material having a second dielectric constant different from the first, and heating at least portions of the structure to crystallize at least a portion of at least one of the first dielectric material and the second dielectric material. Methods of forming a capacitor are described, including forming a first electrode, forming a dielectric material with a first oxide and a second oxide over the first electrode, and forming a second electrode over the dielectric material. Structures including dielectric materials are also described. | 05-21-2015 |
| 20150140774 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device comprises forming a first etch stop layer over a first dielectric layer. The method also comprises forming a first trench in the first etch stop layer and the first dielectric layer. The method further comprises filling the first trench with a conductive material. The method additionally comprises forming a second etch stop layer over the first etch stop layer. The method also comprises forming a second dielectric layer over the second etch stop layer. The method further comprises forming a second trench to expose the conductive material. The second trench is formed having a depth less than a total thickness of the first etch stop layer, the second etch stop layer and the second dielectric layer. The method additionally comprises depositing a first metal layer over sidewalls of the second trench and in contact with the conductive material. | 05-21-2015 |
| 20150311090 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming a first layer above a semiconductor substrate, implanting in a surface of the first layer, at least one kind of ions of an element contained in the first layer, and applying microwave to the first layer in which at least one kind of the ions are implanted. | 10-29-2015 |
| 20150311276 | SEMICONDUCTOR DEVICES HAVING SELF-ALIGNED CONTACT PADS AND METHODS OF MANUFACTURING THE SAME - A semiconductor device includes a substrate having a field area that defines active areas, gate trenches in the substrate and extending in a first direction, a buried gate in a respective gate trench, gate capping fences in a respective gate trench over a respective buried gate, the gate capping fences protruding from top surfaces of the active areas and extending in the first direction, bit line trenches in the gate capping fences, a respective bit line trench crossing the gate capping fences and extending in a second direction perpendicular to the first direction, an insulator structure on inner walls of a respective bit line trench, bit lines and bit line capping patterns stacked on the insulator structures in a respective bit line trench, contact pads self-aligned with the gate capping fences and on the substrate between the adjacent bit lines, and a lower electrode of a capacitor on a respective contact pad. | 10-29-2015 |
| 20150348919 | RECONFIGURABLE MULTI-STACK INDUCTOR - A reconfigurable multi-stack inductor formed within a semiconductor structure may include a first inductor structure located within a first metal layer of the semiconductor structure, a first ground shielding structure located within the first metal layer that is electrically isolated from and circumferentially bounds the first inductor structure, and a second inductor structure located within a second metal layer of the semiconductor structure, whereby the second inductor structure is electrically coupled to the first inductor structure. A second ground shielding structure located within the second metal layer is electrically isolated from and circumferentially bounds the second inductor structure, whereby the first and second inductor generate a first inductance value based on the first ground shielding structure and second ground shielding structure being coupled to ground, and the first and second inductor generate a second inductance value based on the first ground shielding structure and second ground shielding structure electrically floating. | 12-03-2015 |
| 20150371891 | SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming an insulation layer over a substrate; forming an open portion in the insulation layer; forming a sacrificial spacer over sidewalls of the open portion; forming, over the sacrificial spacer, a first conductive pattern in a lower section of the open portion; forming an ohmic contact layer over the first conductive pattern; forming an air gap by removing the sacrificial spacer; capping the air gap by forming a barrier layer over the ohmic contact layer; and forming a second conductive pattern over the barrier layer to fill an upper section of the open portion. | 12-24-2015 |
| 20150371895 | METHOD FOR MANUFACTURING SMEICONDUCTOR DEVICE - In one embodiment, a first insulating film is formed with a recess portion left therein in a contact hole, and the contact hole is surrounded by a first line pattern and a second line pattern, the first line pattern and the second line pattern having different heights. The recess portion is filled so as to form a first mask film, and the first insulating film except for the recess portion is etched back so as to be removed, thereby forming a second contact hole. After that, a conductive material is implanted in the second contact hole, and the top surface of the first line pattern having a low height is exposed, thereby forming a contact plug. | 12-24-2015 |
| 20160005644 | SURFACE TREATMENT METHOD, SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE - Provided are methods of surface treatment, semiconductor devices and methods of forming the semiconductor device. The methods of forming the semiconductor device include forming a first oxide layer and a second oxide layer on a substrate. The first and second oxide layers are patterned to form a contact hole exposing the substrate. A sidewall of the first oxide layer exposed by the contact hole reacts with HF to form a first reaction layer and a sidewall of the second oxide layer exposed by the contact hole reacts with NH | 01-07-2016 |
| 20160020213 | METHODS OF FORMING POSITIONED LANDING PADS AND SEMICONDUCTOR DEVICES INCLUDING THE SAME - A method of forming a DRAM can include forming a plurality of transistors arranged in a first direction on a substrate and forming a bit line structure that extends in the first direction, where the bit line structure being electrically coupled to the plurality of transistors at respective locations in the first direction. A plurality of first landing pads an be formed at alternating ones of the respective locations having a first position in a second direction on the substrate. A plurality of second landing pads can be formed at intervening ones of the respective locations between the alternating ones of the respective locations, where the intervening ones of the respective locations having a second position in the second direction on the substrate wherein second position is shifted in the second direction relative to the first position. | 01-21-2016 |
| 20160027787 | PADS INCLUDING CURVED SIDES AND RELATED ELECTRONIC DEVICES, STRUCTURES, AND METHODS - An electronic device may include a substrate, and a plurality of spaced apart pads on the substrate. Each of the pads may includes first, second, third, and fourth sides, the first and third sides may be opposite sides that are substantially straight, and the second and fourth sides may be opposite sides that are curved. Related methods, devices, and structures are also discussed. | 01-28-2016 |
| 20160027865 | MEMORY DEVICES INCLUDING CAPACITOR STRUCTURES HAVING IMPROVED AREA EFFICIENCY - Semiconductor structures including a plurality of conductive structures having a dielectric material therebetween are disclosed. The thickness of the dielectric material spacing apart the conductive structures may be adjusted to provide optimization of capacitance and voltage threshold. The semiconductor structures may be used as capacitors, for example, in memory devices. Various methods may be used to form such semiconductor structures and capacitors including such semiconductor structures. Memory devices including such capacitors are also disclosed. | 01-28-2016 |
| 20160049409 | SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a plurality of first conductive structures formed over a substrate, second conductive structures each formed between neighboring first conductive structures of the first conductive structures, air gaps each formed between the second conductive structures and the neighboring first conductive structures thereof, third conductive structures each capping a portion of the air gaps, and capping structures each capping the other portion of the air gaps. | 02-18-2016 |
| 20160064386 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A method of fabricating semiconductor devices may include forming a mold structure on a lower layer, the mold structure including an etch stop layer doped at a first impurity concentration, a lower mold layer doped at a second impurity concentration, and an undoped upper mold layer. The method may include forming a trench exposing the lower layer in the mold structure using dry etching, extending a width of the trench in the etch stop layer using wet etching, and forming a first conductive pattern in the extended width trench, wherein an etch rate of the etch stop layer with respect to the dry etching may be smaller than an etch rate of the lower mold layer with respect to the dry etching, and an etch rate of the etch stop layer with respect to the wet etching may be proportional to the first impurity concentration. | 03-03-2016 |
| 20160079189 | HIGH DENSITY THREE-DIMENSIONAL INTEGRATED CAPACITORS - A capacitor can include a substrate having a first surface, a second surface remote from the first surface, and a through opening extending between the first and second surfaces, first and second metal elements, and a capacitor dielectric layer separating and insulating the first and second metal elements from one another at least within the through opening. The first metal element can be exposed at the first surface and can extend into the through opening. The second metal element can be exposed at the second surface and can extend into the through opening. The first and second metal elements can be electrically connectable to first and second electric potentials. The capacitor dielectric layer can have an undulating shape. | 03-17-2016 |
| 20160126189 | Programmable Devices and Methods of Manufacture Thereof - Programmable devices, methods of manufacture thereof, and methods of programming devices are disclosed. In one embodiment, a programmable device includes a link and at least one first contact coupled to a first end of the link. The at least one first contact is adjacent a portion of a top surface of the link and at least one sidewall of the link. The programmable device includes at least one second contact coupled to a second end of the link. The at least one second contact is adjacent a portion of the top surface of the link and at least one sidewall of the link. | 05-05-2016 |
| 20160148991 | PRECISION INTRALEVEL METAL CAPACITOR FABRICATION - A method for fabricating, within an integrated circuit (IC), a capacitor that includes a first plate formed within a recess of a metal layer that includes a second plate of the capacitor is disclosed. The method may include forming the second plate of the capacitor by creating, in a top surface of the metal layer, the recess having at least one side and a bottom and depositing a conformal dielectric film onto the at least one side and the bottom of the recess. The method may also include forming the first plate of the capacitor by filling a portion of the recess that is not filled by the conformal dielectric film with an electrically conductive material that is electrically insulated, by the conformal dielectric film, from the second plate. | 05-26-2016 |
| 20160163638 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A method for manufacturing a semiconductor device includes forming a first conductor pattern and a second conductor pattern running side by side with each other, including forming a first portion of the first conductor pattern and a second portion of the second conductor pattern by patterning using a first mask, and forming a second portion of the first conductor pattern and a first portion of the second conductor pattern by patterning using a second mask. A first inter-conductor capacity is formed by the first portion of the first conductor pattern and the first portion of the second conductor pattern. A second inter-conductor capacity is formed by the second portion of the first conductor pattern and the second portion of the second conductor pattern. | 06-09-2016 |
| 20160172433 | SURFACE TREATMENT METHOD FOR SEMICONDUCTOR DEVICE | 06-16-2016 |
| 20160379969 | Patterned Wafer and Method of Making the Same - A patterned wafer used for production of passive-component chip bodies includes a peripheral end portion and at least one passive-component unit that including a connecting portion, a breaking line, and a plurality of spaced apart chip bodies. The connecting portion is connected to the peripheral end portion and is spaced apart from the chip bodies by a tab-accommodating space along a first direction. The breaking line has a plurality of connecting tabs that are spaced apart from one another and that are disposed in the tab-accommodating space. Each of the connecting tabs interconnects the connecting portion and a respective one of the chip bodies. A method for making the patterned wafer is also disclosed. | 12-29-2016 |
