| Entries |
| Document | Title | Date |
|---|
| 20080199978 | System and method for film stress and curvature gradient mapping for screening problematic wafers - A method of testing a wafer after a current top layer is formed over the wafer. Stress data is collected for the wafer after forming the current top layer. The stress data is derived from changes in wafer curvature. The stress data includes: stress-xx in an x direction and stress-yy in a y direction for each area of a set of finite areas on the wafer, the stress-xx and stress-yy both being derived from wafer-curvature-change-xx in the x direction for each area of the set of finite areas and from wafer-curvature-change-yy in the y direction for each area of the set of finite areas; and the stress-xy being derived from wafer-curvature-change-xy, wherein wafer-curvature-change-xy is a change in wafer twist in the x-y plane for each area of the set of finite areas. A stress gradient vector (and/or its norm) is calculated and used to evaluate the investigating single or multiple accumulated layer. | 08-21-2008 |
| 20080206902 | STRESS MEASUREMENTS DURING LARGE-MISMATCH EPITAXIAL PROCESSES - A substrate is disposed within a processing chamber. A nitrogen precursor and a group-III precursor are flowed into the processing chamber. A layer is deposited over the substrate with a thermal chemical-vapor-deposition process at an elevated temperature within the processing chamber using the nitrogen precursor and the group-III precursor. Light beams are directed to a surface of the layer and light spots corresponding to reflections of the light beams are received from the surface at a position-sensitive detector. Positions of the light spots on the position-sensitive detector are determined from photocurrent induced in a photodiode in the position-sensitive detector. A curvature of the layer is determined from the positions of the light spots. | 08-28-2008 |
| 20080206903 | ADAPTIVE THRESHOLD WAFER TESTING DEVICE AND METHOD THEREOF - Techniques for testing a semiconductor wafer are disclosed. One technique includes measuring a parameter for each of the semiconductor dies in a region of the wafer and determining an adaptive threshold for the region based on the measured parameters. The parameter measured for each die in the region is then compared to the adaptive threshold to determine a qualification status for each die. Accordingly, the semiconductor dies of the wafer are qualified based on an adaptive threshold that varies according to the wafer region under test. This allows for detection of dies whose parameters vary significantly from other dies in a region, providing for detection of potentially faulty dies whose parameter measurements otherwise meet a fixed threshold set for the entire wafer, such as a Single Threshold Test Limit (STL) expectation for the wafer. | 08-28-2008 |
| 20080220545 | SYSTEM AND METHOD FOR TESTING AND PROVIDING AN INTEGRATED CIRCUIT HAVING MULTIPLE MODULES OR SUBMODULES - In an integrated circuit having a plurality of modules and/or submodules that each perform a substantially same function, defective modules and/or submodules are determined by creating a test signature from an input test pattern. The output of each module and/or submodule is compared with the test signature and defective modules to identify defective modules and/or submodules. The identity of defective modules/submodules is stored on the integrated circuit for subsequent use by a customer. Integrated circuits having one or more defective modules/submodules are sold to customers with full disclosure of which modules/submodules are defective, thereby improving the yield associated with the product. Pricing of the product is discounted for products with less than full functionality. | 09-11-2008 |
| 20080227227 | DYNAMIC TEMPERATURE BACKSIDE GAS CONTROL FOR IMPROVED WITHIN-SUBSTRATE PROCESS UNIFORMITY - A method and apparatus are provided to control the radial or non-radial temperature distribution across a substrate during processing to compensate for non-uniform effects, including radial and angular non-uniformities arising from system variations, or process variations, or both. The temperature is controlled, preferably dynamically, by flowing backside gas differently across different areas on a wafer supporting chuck to vary heat conduction across the wafer. Backside gas flow, of helium, for example, is dynamically varied across the chuck to control the uniformity of processing of the wafer. Ports in the support are grouped, and gas to or from the groups is separately controlled by different valves responsive to a controller that controls gas pressure in each of the areas to spatially and preferably dynamically control wafer temperature to compensate for system and process non-uniformities. | 09-18-2008 |
| 20080233663 | SINGULATED BARE DIE TESTING - There is testing of individual dice prior to their inclusion in a multi-chip package. A wafer is sawn into individual dice and the dice are placed onto a die tray. If the tray is not full, then dice can be added that originate from other wafers. Contacts perform diagnostic tests upon the dice to determine if individual dice function as expected. Mapping talkes place to distinguish between dice that passed the diagnostic test and those that did not. Multiple tests can take place in series, where various forms of consolidation and mapping takes place. Passing dice can become part of a multi-chip package while failing dice can be re-screened or scrapped. | 09-25-2008 |
| 20080268556 | Plate With An Indicator For Discerning Among Pre-Identified Probe Holes In The Plate - Disclosed is a system and method for providing an effective means for making it easy to identify which holes in an interface plate are to be populated with probes and which are to be left empty. This identification of holes or apertures in a plate is used most commonly an electrical probe testing plates where a probe array is set up and inserted though the plate. The problem is that it is very difficult to double check to see if all probes are installed. With a two-tone color identifier (or other techniques disclosed herein) it is easy to visually or machine read the probe plate for probe installation errors. The method employs coating the plate with a colorant and ablating colorant adjacent holes, which are either populated or empty, the difference being easy to spot. | 10-30-2008 |
| 20080280380 | Fluid Storage and Dispensing System Including Dynamic Fluid Monitoring of Fluid Storage and Dispensing Vessel - A monitoring system ( | 11-13-2008 |
| 20080280381 | Method of forming a fine pattern of a semiconductor device using a resist reflow measurement key - In a resist reflow measurement key, and method of fabricating a fine pattern of a semiconductor device using the same, the resist reflow measurement key includes a first reflow key including a plurality of first pattern elements each having a first pattern with a first radius of curvature located on a first side of a first center line and a second pattern with a second radius of curvature located on a second side of the first center line, and a second reflow key including a plurality of second pattern elements each having a third pattern with a third radius of curvature located on a first side of a second center line and a fourth pattern with a fourth radius of curvature located on a second side of the second center line, the second reflow key being formed on a same plane of a substrate as the first reflow key. | 11-13-2008 |
| 20080299683 | ESTIMATING YIELD FLUCTUATION FOR BACK-END PLANNING - A method for production planning includes receiving a first order quantity of a first device. A first yield estimate of the first device from a production line is determined. The first yield estimate is adjusted based on a first confidence factor associated with the first order quantity. A dispatch quantity for processing in the production line is determined based on the first order quantity and the adjusted first yield estimate. | 12-04-2008 |
| 20080299684 | METHOD AND SYSTEM FOR REMOVING EMPTY CARRIERS FROM PROCESS TOOLS BY CONTROLLING AN ASSOCIATION BETWEEN CONTROL JOBS AND CARRIER - By providing an under-specified specification for designating a destination carrier in a respective control job or control message, a high degree of flexibility in determining the destination of processed substrates may be obtained, thereby also allowing the removal of a source carrier for enhancing load port availability in complex semiconductor facilities. | 12-04-2008 |
| 20080311688 | Method and Apparatus for Creating a Gate Optimization Evaluation Library - The invention can provide a method of processing a substrate using Gate-Optimization processing sequences and evaluation libraries that can include gate-etch procedures, COR-etch procedures, and evaluation procedures. | 12-18-2008 |
| 20080318347 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In the semiconductor device manufacturing method of the present invention, first, the emissivity of a wafer placed in a chamber is measured. Then, the fluctuation rate of a wafer physical quantity that fluctuates in association with the given thermal energy is calculated based on an estimate expression, which are obtained in advance, presenting the relationship between the thermal energy quantity emitted from the heat source for heating the wafer, wafer emissivity and the wafer physical quantity fluctuation rate and on the measured emissivity. Subsequently, the processing time for the physical quantity to be a specific value is calculated based on the calculated fluctuation rate. Then, the thermal process is conducted for the calculated processing time. | 12-25-2008 |
| 20090017564 | METHOD TO DETECT AND PREDICT METAL SILICIDE DEFECTS IN A MICROELECTRONIC DEVICE DURING THE MANUFACTURE OF AN INTEGRATED CIRCUIT - The present invention provides a method detecting metal silicide defects in a microelectronic device. The method comprises positioning ( | 01-15-2009 |
| 20090029490 | Method of fabricating an electronic device - It has been found that for silicon integrated circuits having capacitor structures or other p-n junctions structure at a technology node of 32 nm or smaller, photovoltaic induced corrosion of copper in the metallization stack is a significant issue. Thus processing conditions or device configurations are employed that preclude such corrosion. In one embodiment photovoltaic induced corrosion is monitored to prevent completion of devices with corrosion defects. | 01-29-2009 |
| 20090053837 | Wafer boat for semiconductor testing - In accordance with one embodiment of the invention, a method and apparatus are provided for testing a wafer while the wafer is disposed in a wafer carrier. The test results can be utilized to adjust the manufacturing process and thereby increase processing yield. | 02-26-2009 |
| 20090061543 | METHOD FOR CALIBRATING AN INSPECTION TOOL - Provided is a method for manufacturing a semiconductor device. The method, in one embodiment, includes calibrating an inspection tool configured to obtain a measurement of a semiconductor feature, including: 1) providing a test structure comprising a substrate having a trench therein, and a post feature located over the substrate adjacent the trench. The post feature, in this embodiment, includes a second layer positioned over a first layer, wherein the first layer has a notch or bulge in a sidewall thereof; 2) finding a location of the notch or bulge relative to a different known point of the test structure using a probe of the inspection tool; and 3) calculating a dimension of the probe using the relative locations of the notch or bulge and the different known point. | 03-05-2009 |
| 20090061544 | TRAJECTORY BASED CONTROL OF PLASMA PROCESSING - A method of controlling a plasma processing according to trajectories connecting start and stop values of parameters controlling the plasma processing, for example, gas flow and power supplied to generate the plasma. The trajectories maybe based on equations including at least time as a variable. At set times within the processing, the values of the parameters are updated according to the predetermined trajectories. Sensors associated with the chamber may also adjust the trajectories, provide variables to the equations, and/or define the trajectories. | 03-05-2009 |
| 20090068770 | TACTILE SURFACE INSPECTION DURING DEVICE FABRICATION OR ASSEMBLY - Processes for inspecting a surface during device fabrication include contacting the surface with a tactile sensor. The tactile sensor is an electroluminescent tactile sensor array or a current electrode sensor array or a capacitive sensor array. The sensor is configured to convert local stress resulting from contact with the surface into light intensity and/or modulation in local current density. Both the light intensity and current density are linearly proportional to the local stress. The image stress provided by the sensor can then be captured by focusing the light intensity onto a suitable detector to provide a topographical image of the surface. Current density can alternatively be directly sensed via high resolution electrode array. | 03-12-2009 |
| 20090075404 | BALL FILM FOR INTEGRATED CIRCUIT FABRICATION AND TESTING - According to one embodiment of the invention, a method of testing ball grid array packages includes providing a substrate, providing a ball film that includes a plurality of metal balls movably contained within respective slots of a thin film, coupling the metal balls to the substrate, and removing the thin film from the metal balls. | 03-19-2009 |
| 20090081817 | PATTERNING METHOD - A patterning method is provided. In the patterning method, a film is formed on a substrate and a pre-layer information is measured. Next, an etching process is performed to etch the film. The etching process includes a main etching step, an etching endpoint detection step, an extension etching step and an over etching step. An extension etching time for performing the extension etching step is set within 10 seconds based on a predetermined correlation between an extension etching time and the pre-layer information, so as to achieve a required film profile. | 03-26-2009 |
| 20090117673 | FAILURE DETECTING METHOD, FAILURE DETECTING APPARATUS, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A failure detecting method has inputting a foreign substance inspection map created by foreign substance inspection for a wafer surface after each processing process in a wafer processing process, inputting a die sort map created by a die sort test after the wafer processing process, setting a plurality of region segments in the wafer, setting a region number for each of the region segments, calculating foreign substance density in each of the region segments, based on the foreign substance inspection map, and plotting the foreign substance density, using the region numbers, to calculate a foreign substance inspection map waveform characteristic amount, calculating failure density in each of the region segments, based on the die sort map, and plotting the failure density, using the region numbers, to calculate a die sort map waveform characteristic amount, calculating similarity between the foreign substance inspection map waveform characteristic amount and the die sort map waveform characteristic amount, and identifying a processing process that is a cause of failure occurrence, based on the similarity. | 05-07-2009 |
| 20090124027 | Structure and Method for Placement, Sizing and Shaping of Dummy Structures - A material layer on a substrate being processed, e.g. to form chips, includes one or more functional structures. In order to control pattern density during fabrication of the chip, dummy fill structures of different sizes and shapes are added to the chip at different distances from the functional structures of the material layer. In particular, the placement, size and shape of the dummy structures are determined as a function of a distance to, and density of, the functional structures of the material layer. | 05-14-2009 |
| 20090130784 | Method for determining the position of the edge bead removal line of a disk-like object - A method for determining the position of an edge bead removal line of a disk-like object having an edge area and an alignment mark on the edge area is disclosed, wherein the edge area including the edge bead removal line is imaged on a line-by-line basis, an intensity profile I of the imaged edge area including the edge bead removal line is obtained with a camera on a line-by-line basis, and the edge area and the alignment mark are detected, wherein the local intensity maxima I′ | 05-21-2009 |
| 20090137068 | Method and Computer Program Product for Wafer Manufacturing Process Abnormalities Detection - A method for wafer manufacturing process abnormalities detection, the method includes: generating a classifier in response to compression based similarities between relevant wafer manufacturing process information of pairs of wafers; and utilizing the classifier to detect wafer manufacturing process abnormalities. | 05-28-2009 |
| 20090148965 | Method and apparatuses for high pressure gas annealing - Novel methods and apparatuses for annealing semiconductor devices in a high pressure gas environment. According to an embodiment, the annealing vessel has a dual chamber structure, and potentially toxic, flammable, or otherwise reactive gas is confined in an inner chamber which is protected by pressures of inert gas contained in the outer chamber. The incoming gas delivery system and exhaust gas venting system are likewise protected by various methods. Embodiments of the present invention can be used, for example, for high-K gate dielectric anneal, post metallization sintering anneal, and forming gas anneal in the semiconductor manufacturing process. | 06-11-2009 |
| 20090155933 | Manufacturing Method of Display Device - To suppress the occurrence of image quality irregularities in a liquid crystal display device having a TFT substrate which is manufactured by performing steps a plurality of times in such a manner that one region is divided into a plurality of exposure regions, and the plurality of exposure regions is exposed. In a manufacturing method of a display device which performs, for a preliminarily determined one region on a surface of an insulation substrate, an exposure/development step including a step of exposing a formed film made of a photosensitive material and a step of developing an exposed film made of the photosensitive material a plurality of times, said each exposure step is performed such that said one region is divided into the plurality of exposure regions by a boundary line which has no overlapping portion and is not aligned with a boundary line between the exposure regions in the exposure step for at least one time out of other exposure steps, and the whole of said one region is exposed by individually exposing the respective exposure regions. | 06-18-2009 |
| 20090155934 | DEPOSITION APPARATUS AND DEPOSITION METHOD - A deposition apparatus includes: a first electrode for placing a processing object; a second electrode for generating plasma with the first electrode, the second electrode being opposed to the first electrode; and a heat flow control heat transfer part for drawing heat from the processing object to generate a heat flow from a central area to a peripheral area of the processing object. | 06-18-2009 |
| 20090155935 | BACK SIDE WAFER DICING - Systems and methods for scribing a semiconductor wafer with reduced or no damage or debris to or on individual integrated circuits caused by the scribing process. The semiconductor wafer is scribed from a back side thereof. In one embodiment, the back side of the wafer is scribed following a back side grinding process but prior to removal of back side grinding tape. Thus, debris generated from the scribing process is prevented from being deposited on a top surface of the wafer. To determine the location of dicing lanes or streets relative to the back side of the wafer, the top side of the wafer is illuminated with a light configured to pass through the grinding tape and the wafer. The light is detected from the back side of the wafer, and the streets are mapped relative to the back side. The back side of the wafer is then cut with a saw or laser. | 06-18-2009 |
| 20090186426 | Plasma Doping Method and Apparatus Employed in the Same - A plasma doping method and a plasma doping apparatus, having a superior in-plane uniformity of an amorphous layer formed on a sample surface, are provided. | 07-23-2009 |
| 20090197354 | SYSTEM AND METHOD FOR MONITORING MANUFACTURING PROCESS - A system and method for monitoring a manufacturing process are provided. A wafer is provided. Process parameters of a manufacturing machine are in-situ measured and recorded if the wafer is processed in the manufacturing machine. A wafer measured value of the wafer is measured after the wafer has been processed. The process parameters are transformed into a process summary value. A two dimensional orthogonal chart with a first axis representing the wafer measured value and a second axis representing the process summary value is provided. The two dimensional orthogonal chart includes a close-loop control limit. A visualized point representing the wafer measured value and the process summary value is displayed on the two dimensional orthogonal chart. | 08-06-2009 |
| 20090197355 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING SYSTEM - A method for manufacturing a semiconductor device that controls the influence of a thickness of a stopper film even if there is a change in the thickness of the stopper film by measuring the thickness prior to etching to a predetermined thickness. | 08-06-2009 |
| 20090197356 | Substrate positioning on a vacuum chuck - We have discovered a method of using the vacuum chuck/heater upon which a substrate wafer is positioned to determine whether the wafer is properly placed on the vacuum chuck. The method employs measurement of a rate of increase in pressure in a confined space beneath the substrate. Because the substrate is not hermetically sealed to the upper surface of the vacuum chuck/heater apparatus, pressure from the processing chamber above the substrate surface tends to leak around the edges of the substrate and into the space beneath the substrate which is at a lower pressure. A pressure sensing device, such as a pressure transducer is in communication with a confined volume present beneath the substrate. The rate of pressure increase in the confined volume is measured. If the substrate is well positioned on the vacuum chuck/heater apparatus, the rate of pressure increase in the confined volume beneath the substrate is slow. If the substrate is not well positioned on the vacuum chuck/heater apparatus, the rate of pressure increase is more rapid. | 08-06-2009 |
| 20090197357 | HIGH-TEMPERATURE ION IMPLANTATION APPARATUS AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES USING HIGH-TEMPERATURE ION IMPLANTATION - A semiconductor device fabrication apparatus includes a load lock chamber, a loading assembly in the load lock chamber, and an ion implantation target chamber that is hermetically connected to the load lock chamber. The load lock chamber is configured to store a plurality of wafer plates. Each wafer plate respectively includes at least one semiconductor wafer thereon. The ion implantation target chamber is configured to implant an ion species into a semiconductor wafer on a currently loaded wafer plate. The loading assembly is also configured to load a next one of the plurality of wafer plates from the load lock chamber into the ion implantation target chamber. The loading assembly may be configured to load the next wafer plate from the load lock chamber into the ion implantation target chamber while substantially maintaining a current temperature within the ion implantation target chamber and/or without depressurizing the ion implantation target chamber. Related methods and devices are also discussed. | 08-06-2009 |
| 20090215203 | MONITORING OF TEMPERATURE VARIATION ACROSS WAFERS DURING PROCESSING - A method of measuring temperature across wafers during semiconductor processing includes the step of providing a correlation between a peak wafer temperature during a processing step and a change in wafer surface charge or surface potential following the processing step. A first wafer to be characterized for its peak temperature spatial distribution during the processing step is processed through the processing step. The wafer surface charge or surface potential at a plurality of locations on the first wafer are measured following the processing step. A peak temperature spatial distribution for the first wafer is then determined based on the correlation and the wafer surface charge or surface potential measured in the measuring step. | 08-27-2009 |
| 20090221103 | FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In the fabrication of a semiconductor integrated circuit device, a 2D-3D inspection technique for solder printed on a substrate is provided which permits easy preparation of data and easy visual confirmation of a defective portion. In a substrate inspecting step, first, a 3D inspection is performed, followed by execution of 2D inspection, whereby a 2D picked-up image of the portion of a pad determined to be defective can be displayed on a larger scale simultaneously with the end of inspection, thereby providing an environment for efficient visual confirmation of the defect. Further, by subjecting a raw substrate to measurement at the time of preparing inspection data, a relation between an original height measurement reference generated automatically by the inspection system and the height of a pad upper surface is checked, whereby it is possible to measure the height and volume of printed solder based on the pad upper surface. | 09-03-2009 |
| 20090246891 | MARK FORMING METHOD AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A mark forming method includes forming a first mask layer on a semiconductor substrate; forming at least three first patterns having periodicity on the first mask layer; forming a second mask layer on the first mask layer having the first patterns formed thereon; and forming an opening in the second mask layer to cover at least two patterns on ends of the at least three first patterns, thereby forming a mark composed of exposed ones of the first patterns. | 10-01-2009 |
| 20090258445 | MULTI-VARIABLE REGRESSION FOR METROLOGY - A method for assessing metrology tool accuracy is described. Multi-variable regression is used to define the accuracy of a metrology tool such that the interaction between different measurement parameters is taken into account. A metrology tool under test (MTUT) and a reference metrology tool (RMT) are used to measure a set of test profiles. The MTUT measures the test profiles to generate a MTUT data set for a first measurement parameter. The RMT measures the test profiles to generate RMT data sets for the first measurement parameter, and at least a second measurement parameter. Multi-variable regression is then performed to generate a best-fit plane for the data sets. The coefficient of determination (R | 10-15-2009 |
| 20090280582 | Design Methodology for MuGFET ESD Protection Devices - A method for manufacturing a MuGFET ESD protection device having a given layout by means of a given manufacturing process, the method comprising selecting multiple interdependent layout and process parameters of which a first set are fixed by said manufacturing process and a second set are variable, selecting multiple combinations of possible layout and process parameter values which meet predetermined ESD constraints; determining an optimum value for at least one other parameter in view of a predetermined design target apart from the predetermined ESD constraints; determining values for fin width (W | 11-12-2009 |
| 20090286334 | PROCESS FOR TREATMENT OF SEMICONDUCTOR WAFER USING WATER VAPOR CONTAINING ENVIRONMENT - A process is provided for treating a semiconductor wafer at a target wafer temperature. This process includes the following steps: | 11-19-2009 |
| 20090298205 | Pattern verifying method, pattern verifying device, program, and manufacturing method of semiconductor device - An overlapping margin of a second pattern for a first pattern is corrected for at least one of the first pattern and the second pattern (S | 12-03-2009 |
| 20090305440 | Method for Treatment of Samples for Auger Electronic Spectrometer (AES) in the Manufacture of Integrated Circuits - A method for analyzing a sample for the manufacture of integrated circuits, e.g. MOS transistors, application specific integrated circuits, memory devices, microprocessors, system on a chip. The method includes providing an integrated circuit chip, which has a surface area with at least one region of interest, e.g., bond pad. The method includes covering a first portion of the surface area including the region of interest using a blocking material. The method also forms a metal layer on a second portion of the surface area, while the blocking material protects the first portion. The method removes the blocking material to expose the first portion of the surface area including the region of interest. The method also subjects the metal layer to a voltage differential to draw away one or more charged particles from the first portion of the surface area. The method also subjects the surface area including the region of interest to spectrometer analysis. | 12-10-2009 |
| 20090317925 | EVALUATION METHOD OF SEMICONDUCTOR DEVICE - A technology for analyzing and evaluating of a change of impurity content distribution at the heat treatment of electrodeposited copper film. There is provided a method of evaluating a semiconductor device, comprising providing an electrodeposited copper film formed while causing the deposition current to transit between the first state of current density and the second state of current density so as to attain a desired impurity content distribution and carrying out analysis and evaluation of any impurity diffusion from a change of impurity content distribution in the electrodeposited copper film between before and after heat treatment. | 12-24-2009 |
| 20090325324 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE AND MANUFACTURING APPARATUS FOR SEMICONDUCTOR DEVICE - A manufacturing method for a semiconductor device including: determining pattern dependency of a radiation factor of an element forming surface of one wafer having a predetermined pattern formed on the wafer; determining a heating surface of the wafer, based on the pattern dependency of the radiation factor; holding the one wafer having the determined heating surface and another wafer having a determined heating surface, spaced at a predetermined distance in such a manner that non-heating surfaces of the one wafer and the another wafer oppose to each other; and heating the each heating surface of the one wafer and the another wafer. | 12-31-2009 |
| 20100022033 | PROCESS FOR WAFER TEMPERATURE VERIFICATION IN ETCH TOOLS - A blank wafer is placed in an etch chamber. A layer is deposited over the blank wafer, comprising providing a deposition gas, forming the deposition gas into a deposition plasma, and stopping the deposition gas. The blank wafer with the deposited layer is removed from the etch chamber. The thickness of the deposited layer is measured. Wafer temperature accuracy is calculated from the measured thickness of the deposited layer. The etch chamber is compensated according to the calculated wafer temperature accuracy. A wafer with an etch layer over the wafer and a patterned mask over the etch layer is placed into the etch chamber. The etch layer is etched in the etch chamber. | 01-28-2010 |
| 20100029021 | METHODS FOR REAL-TIME CONTAMINATION, ENVIRONMENTAL, OR PHYSICAL MONITORING OF A PHOTOMASK - Methods for real-time contamination, environmental, or physical monitoring of a photomask. An attribute of a photomask is monitored using a sensor of an electronics package attached to the photomask. The methods further include generating one or more sensor signals relating to the monitored attribute with the sensor and transmitting the one or more sensor signals from the electronics package to a control system. | 02-04-2010 |
| 20100035367 | FILM THICKNESS PREDICTION METHOD, LAYOUT DESIGN METHOD, MASK PATTERN DESIGN METHOD OF EXPOSURE MASK, AND FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT - A film thickness prediction method of predicting a film thickness of a second processed layer after planarization includes the steps of: creating first to third actual measurement databases; obtaining a reference film thickness of a second processed layer formed on a region in which no circuit pattern exists; segmenting a first processed layer to be formed on a substrate into grid-like meshes, and obtaining a pattern area ratio occupied by a circuit pattern to be formed on a first processed layer in each mesh and further obtaining a circumferential length of the circuit pattern in each mesh; obtaining an initial thickness of the second processed layer in each mesh; and predicting the film thickness of the second processed layer after planarization from an initial film thickness predicted value and an amount of planarization H | 02-11-2010 |
| 20100047933 | SUBSTRATE, SUBSTRATE INSPECTING METHOD AND METHODS OF MANUFACTURING AN ELEMENT AND A SUBSTRATE - A substrate inspection method allowing inspection of all a plurality of substrates each provided at its surface with a plurality of layers by determining quality of the plurality of layers as well as methods of manufacturing the substrate and an element using the substrate inspection method are provided. The substrate inspection method includes a step of preparing the substrate provided at its main surface with the plurality of layers, a film forming step, a local etching step, and an inspection step or a composition analysis step. In the step, a concavity is formed in a region provided with an epitaxial layer of the main surface of the substrate by removing at least partially the epitaxial layer. In the inspection step, the inspection is performed on the layer exposed in the concavity. | 02-25-2010 |
| 20100055808 | SUBSTRATE PROCESSING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A substrate processing apparatus for executing a predetermined process on a substrate loaded into a process chamber by running a recipe containing a plurality of steps is provided. The recipe includes a process step of processing the substrate, and a leak check step executed before the process step to check whether a leak occurs inside the process chamber, and the substrate processing apparatus includes a main control unit configured to execute the process step while keeping an error that occurs in the leak check step. | 03-04-2010 |
| 20100062549 | PATTERN CORRECTING METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND PATTERN CORRECTING PROGRAM - A side of a correction target pattern is divided into a plurality of segments. A space between each of the divided segments or an imaginary segment extended from both the ends of the segment to outer sides and a side of an adjacent pattern adjacent to the segment is measured. An overlapping distance between each of the divided segments or the imaginary segment extended from both the ends of the segment to the outer sides and the side of the adjacent pattern is measured. A shift amount of the segment is corrected based on the overlapping distance. | 03-11-2010 |
| 20100075442 | SEMICONDUCTOR WAFER PROCESSING APPARATUS, REFERENCE ANGULAR POSITION DETECTION METHOD, AND SEMICONDUCTOR WAFER - [Problems] To provide a semiconductor wafer processing apparatus and reference angular position detection method able to suitably detect a reference angular position for a semiconductor wafer for which a reference angular position is set and a semiconductor wafer for which a reference angular position is suitably set. | 03-25-2010 |
| 20100093114 | METHOD OF SEARCHING FOR KEY SEMICONDUCTOR OPERATION WITH RANDOMIZATION FOR WAFER POSITION - A method of searching for the key semiconductor operation with randomization for wafer position, comprising: recording the wafer position and the wafer yields of a plurality of wafer ID respectively corresponding to a plurality of semiconductor operations; establishing a matrix model which describes the matrix set for wafer yields of the plurality of wafer ID; analyzing the matrix model, further computing the matrix set for wafer yields of the wafer ID, thereby acquiring the weightings of the randomized wafer positions in such semiconductor operations; and searching for a key semiconductor operation among the plurality of semiconductor operations; herein, by using a local regression model to estimate the wafer position effect, computing the weighting of the position effect in each semiconductor operation based on the estimated position effect and the randomized wafer yield, higher weighting thereof indicates the key semiconductor operation having greater position effect in the aforementioned semiconductor process. | 04-15-2010 |
| 20100093115 | ETCH TOOL PROCESS INDICATOR METHOD AND APPARATUS - A method for providing a process indicator for an etching chamber is provided. A wafer with a blanket etch layer is provided into the etching chamber. A blanket etch is performed on the blanket etch layer. A blanket deposition layer is deposited over the blanket etch layer after performing the blanket etch has been completed. A thickness of the blanket etch layer and a thickness of the blanket deposition layer is measured. The measured thicknesses are used to determine a process indicator. | 04-15-2010 |
| 20100112731 | ELECTRIC DEVICE HAVING NANOWIRES, MANUFACTURING METHOD THEREOF, AND ELECTRIC DEVICE ASSEMBLY - An electric device having a plurality of nanowires, in which at least one of the nanowires is cut or changed in its electric characteristics so as to have a desired characteristic value of the electric device. | 05-06-2010 |
| 20100120177 | Feature Dimension Control in a Manufacturing Process - A method for manufacturing a semiconductor device is disclosed including determining a dimension or other physical characteristic of a pattern in a layer of material that is disposed on a workpiece, and etching the layer of material using information that is related to the dimension. A system is also disclosed for manufacturing a semiconductor device including a first etch system configured to etch a layer to define a pattern in the layer, and a second etch system configured to measure a physical characteristic of the pattern, determine an etch control parameter based on the physical characteristic, and etch the layer in accordance with the etch control parameter. | 05-13-2010 |
| 20100129940 | VIBRATION MONITORING OF ELECTRONIC SUBSTRATE HANDLING SYSTEMS - An electronic device substrate handling system. The system comprises an electronic device fabrication tool and a mechanical handling structure. The fabrication tool is configured to hold at least one substrate on a mounting body of the tool. The mechanical handling structure is configured to actuate the substrate such that the substrate is transferred to or from the mounting body. The system further comprises a vibration monitor coupled to at least one of the mechanical handling structure, or, the tool. The vibration monitor is configured to measure vibrations of the mechanical handling structure, or, the tool, while said mechanical handling structure is actuating said substrate. The vibration monitor is also configured to convert the measured vibrations into a time-dependent electrical signal. | 05-27-2010 |
| 20100136715 | Screening of Silicon Wafers Used in Photovoltaics - A method for screening silicon-based wafers used in the photovoltaic industry is provided herewith. | 06-03-2010 |
| 20100136716 | Manufacturing apparatus for semiconductor device and manufacturing method for semiconductor device - A manufacturing apparatus for a semiconductor device, treating a SiN film formed on a wafer with phosphoric acid solution, including a processing bath to store phosphoric acid solution provided for treatment of the wafer, a control unit for calculating integrated SiN etching amount of the phosphoric acid solution, determining necessity of quality adjustment of the phosphoric acid solution, based on correlation between the integrated SiN etching amount calculated and etching selectivity to oxide film, and calculating a quality adjustment amount of the phosphoric acid solution as needed, and also including a mechanism to adjust the quality of the phosphoric acid solution based on the quality adjustment amount calculated. | 06-03-2010 |
| 20100136717 | APPARATUS AND METHOD TO INSPECT DEFECT OF SEMICONDUCTOR DEVICE - An apparatus and method to inspect a defect of a semiconductor device. The amount of secondary electrons generated due to a scanning electron microscope (SEM) may depend on the topology of a pattern of a semiconductor substrate. The amount of secondary electrons emitted from a recess of an under layer is far smaller than that of secondary electrons emitted from a projection of a top layer. Since the recess is darker than the projection, a ratio of a value of a secondary electron signal of the under layer to a value of a secondary electron signal of the top layer may be increased in order to improve a pattern image used to inspect a defect in the under layer. To do this, a plurality of conditions under which electron beams (e-beams) are irradiated may be set, at least two may be selected out of the set conditions, and the pattern may be scanned under the selected conditions. Thus, secondary electron signals may be generated according to the respective conditions and converted into image data so that various pattern images may be displayed on a monitor. Scan information on the pattern images may be automatically stored in a computer storage along with positional information on a predetermined portion of the semiconductor substrate. When calculation conditions are input to a computer, each of scan information on the pattern images may be calculated to generate a new integrated pattern image. | 06-03-2010 |
| 20100144065 | METHOD FOR RECYCLING/RECLAIMING A MONITOR WAFER - The invention provides a method for recycling/reclaiming a monitor or test wafer and a method for testing an integrated circuit manufacturing process. After a monitor wafer has been used for testing one or more semiconductor wafer processing steps to determine adequacy for use with production wafers, deposited materials and other residues from the tested processing steps are removed, and the stripped wafer is subjected to a thermal anneal to repair defects in its surface and return it to a reusable condition. | 06-10-2010 |
| 20100144066 | SYSTEM AND METHOD FOR RECYCLING A GAS USED TO DEPOSIT A SEMICONDUCTOR LAYER - A system for recycling includes a processing chamber, a reclamation reservoir and a mixing reservoir. The processing chamber is configured to receive a deposition gas deposited onto a semiconductor layer. The processing chamber has an exhaust to discharge an unused portion of the deposition gas as an effluent gas. The reclamation reservoir is in fluid communication with the processing chamber. The reclamation reservoir is configured to receive and store the effluent gas from the processing chamber. The mixing reservoir is in fluid communication with the reclamation reservoir and the processing chamber. The mixing reservoir is configured to mix the effluent gas with a virgin gas to form a recycled deposition gas. The mixing reservoir supplies the recycled deposition gas to the processing chamber to deposit an additional portion of the semiconductor layer. | 06-10-2010 |
| 20100144067 | CIRCUIT AND METHOD FOR INTERCONNECTING STACKED INTEGRATED CIRCUIT DIES - Signals are routed to and from identical stacked integrated circuit dies by selectively coupling first and second bonding pads on each of the dies to respective circuits fabricated on the dies through respective transistors. The transistors connected to the first bonding pads of an upper die are made conductive while the transistors connected to the second bonding pads of the upper die are made non-conductive. The transistors connected to the second bonding pads of a lower die are made conductive while the transistors connected to the first bonding pads of the lower die are made non-conductive. The second bonding pads of the upper die are connected to the second bonding pads of the lower die through wafer interconnects extending through the upper die. Signals are routed to and from the circuits on the first and second dies through the first and second bonding pads, respectively. | 06-10-2010 |
| 20100151597 | METHOD FOR SMOOTHING WAFER SURFACE AND APPARATUS USED THEREFOR - Disclosed is a method for smoothing the surface of at least one side of a wafer which is obtained by slicing a semiconductor ingot. In this method, a fluid is applied according to projections of the wafer surface, thereby reducing the projections. Alternatively, a fluid is applied over the wafer surface, thereby smoothing the entire surface of the wafer while reducing the projections in the wafer surface. | 06-17-2010 |
| 20100159618 | Assembly of ordered carbon shells on semiconducting nanomaterials - In some embodiments of the invention, encapsulated semiconducting nanomaterials are described. In certain embodiments the nanostructures described are semiconducting nanomaterials encapsulated with ordered carbon shells. In some aspects a method for producing encapsulated semiconducting nanomaterials is disclosed. In some embodiments applications of encapsulated semiconducting nanomaterials are described. | 06-24-2010 |
| 20100167428 | METHOD AND SYSTEM FOR DETERMINING SEMICONDUCTOR CHARACTERISTICS - Method and system for determining semiconductor characteristics. In a specific embodiment, the present invention provides a method for determining one or more characteristics of a partially processed integrated circuit. The method includes a step for providing a substrate material. The method further includes a step for forming at least one opening within the substrate material. The opening can be characterized by an opening characteristic that includes a depth and an opening width associated with an unknown volume. The method includes a step for providing fill material. Additionally, the method includes a step for processing the fill material to cause a first portion of the fill material to enter the opening and occupy an entirety of the unknown volume associated with the opening characteristic while a second portion of the fill material remains outside of the unknown volume. Moreover, the method includes a step for processing the second portion of the fill material using one or more processes to determine a spatial characteristic associated with the unknown volume. | 07-01-2010 |
| 20100167429 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device estimates the level of erosion generated in CMP of a plug by using a monitoring pattern that defines uniformly a hole array size (split a) and the length (split b) of the space between arrays. | 07-01-2010 |
| 20100197049 | DOPING APPARATUS, DOPING METHOD, AND METHOD FOR FABRICATING THIN FILM TRANSISTOR - It is an object of the present invention to provide a doping apparatus, a doping method, and a method for fabricating a thin film transistor that can carry out doping to the carrier concentration which is optimum for obtaining the desired electric characteristic non-destructively and in an easy manner. In accordance with the present invention, an electric characteristic of a semiconductor element (threshold voltage in a transistor and the like) is correctly and precisely monitored by using a contact angle, and is controlled by controlling a doping method. In addition, the present invention can be momentarily acquired information by in-situ monitoring the characteristic and can be fed back without a time lag. | 08-05-2010 |
| 20100216261 | METHOD FOR IDENTIFYING AN INCORRECT POSITION OF A SEMICONDUCTOR WAFER DURING A THERMAL TREATMENT - An incorrect position of a semiconductor wafer during thermal treatment in a process chamber heated by means of infrared emitters and transmissive to infrared radiation is identified, wherein the semiconductor wafer lies in a circular pocket of a rotating susceptor and is held at a predetermined temperature with the aid of the infrared emitters and a control system, and wherein thermal radiation is measured by a pyrometer, an amplitude of the fluctuations of the measurement signal is determined and an incorrect position of the semiconductor wafer is assumed if the amplitude exceeds a predetermined maximum value. The pyrometer is oriented such that the measurement spot detected by the pyrometer lies partly on the semiconductor wafer and partly outside the semiconductor wafer on the susceptor so that it is possible to identify an eccentric position of the semiconductor wafer within the pocket of the susceptor. | 08-26-2010 |
| 20100233830 | METHOD FOR MONITORING FABRICATION PARAMETER - A method for monitoring fabrication parameters comprises steps of: obtaining a normal parameter variance curve and a comparing parameter variance curve; defining a plurality of normal parameter points on the normal parameter variance curve; defining a plurality of comparing parameter points on the comparing parameter variance curve; finding out the corresponding comparing parameter points nearest to the normal parameter points; calculating the distances between the normal parameter points and the corresponding comparing parameter points thereof; summing up the distances so as to receive a total distance; and determining whether or not the total distance exceeds a limit. Via this arrangement, when fabrication parameter of tool is abnormal, it can be efficiently and immediately determined. | 09-16-2010 |
| 20100248397 | High temperature susceptor having improved processing uniformity - A susceptor configured to be coupled to a material processing system is described. The susceptor comprises a substrate support comprising a central portion and an edge portion, wherein the central portion has a support surface configured to receive and support a substrate, and the edge portion extends beyond a peripheral edge of the substrate. The susceptor further comprises an edge reflector coupled to the edge portion of the substrate support and configured to partially or fully shield the peripheral edge of the substrate from radiative exchange with an outer region of the material processing system. | 09-30-2010 |
| 20100248398 | E-CHUCK FOR AUTOMATED CLAMPED FORCE ADJUSTMENT AND CALIBRATION - The present disclosure provides a semiconductor manufacturing method. The method includes performing a first process to a wafer; measuring the wafer for wafer data after the first process; securing the wafer on an E-chuck in a processing chamber; collecting sensor data from a sensor embedded in the E-chuck; adjusting clamping forces to the E-chuck based on the wafer data and the sensor data; and thereafter performing a second process to the wafer secured on the E-chuck in the processing chamber. | 09-30-2010 |
| 20100279436 | Inspection Method For Integrated Circuit Manufacturing Processes - The present disclosure provides a method for manufacturing integrated circuit devices including an electron beam inspection. The method includes forming a silicide region on a substrate. In an embodiment, the silicide region is formed to provide contact to a device feature such as a source or drain region. An electron beam scan is then performed on the substrate. The electron beam scan includes a first scan and a second scan. The first scan includes a lower landing energy than the second scan. In an embodiment, the first scan provides a dark silicide image analysis and a bright image analysis. In an embodiment, the second scan provides a dark silicide image analysis. The method continues to form a conductive plug after performing the electron beam scan. | 11-04-2010 |
| 20100279437 | CONTROLLING EDGE EMISSION IN PACKAGE-FREE LED DIE - Light emitting diode (LED) structures are fabricated in wafer scale by mounting singulated LED dies on a carrier wafer or a stretch film, separating the LED dies to create spaces between the LED dies, applying a reflective coating over the LED dies and in the spaces between the LED dies, and separating or breaking the reflective coating in the spaces between the LED dies such that some reflective coating remains on the lateral sides of the LED die. Portions of the reflective coating on the lateral sides of the LED dies may help to control edge emission. | 11-04-2010 |
| 20100279438 | APPARATUS AND METHOD OF IN-SITU IDENTIFICATION FOR CONTAMINATION CONTROL IN SEMICONDUCTOR FABRICATION - An apparatus is provided that includes a load port for receiving a container that houses a wafer and a detector disposed proximate the load port such that the detector detects a metal characteristic of the wafer. The detected metal characteristic indicates whether the wafer is at a proper location. Also, provided is a method for use in semiconductor manufacture that includes providing a container that houses a wafer, receiving the container in a load port, detecting a metal characteristic of the wafer, and determining whether the wafer is at a proper location based on the detected metal characteristic of the wafer. | 11-04-2010 |
| 20100285614 | SEMICONDUCTOR WAFER METROLOGY APPARATUS AND METHOD - A semiconductor wafer metrology technique comprising performing atmospheric buoyancy compensated weighing of a wafer, in which the wafer is weighed in a substantially upright condition. A vertical or near vertical wafer orientation causes the surface area in the direction of a force (weight) sensor to be reduced compared with a horizontal wafer orientation. Hence, the electrostatic force components acting in the same direction as the wafer weight force component is reduced. | 11-11-2010 |
| 20100297785 | MANUFACTURE OF DEFECT CARDS FOR SEMICONDUCTOR DIES - A method for producing a defect card for individual dies located on a wafer, comprising: producing first and second defect cards, where the defective individual dies whose adjoining individual dies form an environment having a defect density up to a first value (δ | 11-25-2010 |
| 20100323460 | DEFECT INSPECTING METHOD - A defect inspecting method includes: forming, in a first air pressure state, a film, which covers one opening of two openings provided on an upper surface of a substrate, on a tubular contact hole formed on the substrate in manufacturing a semiconductor device and formed in a tubular shape by connecting two cylindrical contact holes on bottom surface sides thereof, both ends of the tubular shape being opened in the openings; exposing the substrate covered with the film in a second air pressure state; and observing whether the film is deformed to thereby inspect whether the part of the tubular shape is blocked. | 12-23-2010 |
| 20110008916 | Proximity Head Heating Method and Apparatus - Provided is an apparatus and a method for heating fluid in a proximity head. A method for semiconductor wafer processing, includes providing liquid to a proximity head including a heating portion, heating the liquid within the heating portion of the proximity head and delivering the heated liquid to a surface of a semiconductor wafer for use in a wafer processing operation including forming a meniscus between the proximity head and the surface of the semiconductor wafer. | 01-13-2011 |
| 20110020959 | HUMIDITY CONTROL AND METHOD FOR THIN FILM PHOTOVOLTAIC MATERIALS - A method for processing a thin film photovoltaic module. The method includes providing a plurality of substrates, each of the substrates having a first electrode layer and an overlying absorber layer composed of copper indium gallium selenide (CIGS) or copper indium selenide (CIS) material. The absorber material comprises a plurality of sodium bearing species. The method maintains the plurality of substrates in a controlled environment after formation of at least the absorber layer through one or more processes up to a lamination process. The controlled environment has a relative humidity of less than 10% and a temperature ranging from about 10 Degrees Celsius to about 40 Degrees Celsius. The method subjects the plurality of substrates to a liquid comprising water at a temperature from about 10 Degrees Celsius to about 80 Degrees Celsius to process the plurality of substrates after formation of the absorber layer. The plurality of substrates having the absorber layer is subjected to an environment having a relative humidity of greater than about 10% to a time period of less then four hours. | 01-27-2011 |
| 20110020960 | METHOD FOR FABRICATING MICRO AND NANOSTRUCTURES IN A MATERIAL - A method to determine minimum etch mask dosage or thickness as a function of etch depth or maximum etch depth as a function of etch mask implantation dosage or thickness, for fabricating structures in or on a substrate through etch masking via addition or removal of a masking material and subsequent etching. | 01-27-2011 |
| 20110045615 | Manufacturing method of semiconductor device - A manufacturing method of a semiconductor device using a semiconductor manufacturing unit comprising a reaction chamber, a substrate mounting stage, and a high frequency power supply coupled to the substrate mounting stage, a blocking capacitor interposed between the substrate mounting stage and the high-frequency power supply to continuously perform a plurality of dry etching processing with respect to the same substrate in the same reaction chamber, the method includes: disposing a substrate on a substrate mounting stage, and applying high-frequency powers to the substrate mounting stage while introducing a fluorocarbon-based first gas to perform a first dry etching processing with respect to the substrate, the substrate including an organic material film and a silicon compound film sequentially deposited on a surface thereof and a resist film patterned on the silicon compound film, the first dry etching processing including processing the silicon compound film with the resist film being used as a mask; and stopping application of one of the high-frequency powers, thereby reducing a bias voltage generated to the substrate while introducing a second gas after the first dry etching processing to remove a fluorocarbon-based deposition in the reaction chamber and perform a second dry etching processing with respect to the substrate. | 02-24-2011 |
| 20110076789 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS - To reduce the number of photomasks for forming an ion injection mask, then reduce a manufacturing cost of a semiconductor device, accurately control a shape and a position of an ion implantation region into a substrate, and improve a manufacturing yield of the semiconductor device. A manufacturing method of a semiconductor device comprises the steps of: forming an alignment mark on a substrate; forming a second resist pattern on the substrate on which the alignment mark is formed; forming a first ion implantation region by injecting a first ion into an exposure surface of the substrate; forming a thin film on the second resist pattern and on the first ion implantation region; forming a thin film pattern that covers an outer edge of the first ion implantation region by reducing a prescribed portion of the thin film; forming a second ion implantation region by injecting a second ion into the exposure surface of the first ion implantation region; and removing the thin film pattern and the second resist pattern. | 03-31-2011 |
| 20110086442 | COPPER CONTAMINATION DETECTION METHOD AND SYSTEM FOR MONITORING COPPER CONTAMINATION - A method of monitoring copper contamination. The method includes method, comprising: (a) ion-implanting an N-type dopant into a region of single-crystal silicon substrate, the region abutting a top surface of the substrate; (c) activating the N-type dopant by annealing the substrate at a temperature of 500° C. or higher in an inert atmosphere; (c) submerging, for a present duration of time, the substrate into an aqueous solution, the aqueous solution to be monitored for copper contamination; and (d) determining an amount of copper adsorbed from the aqueous solution by the region of the substrate. | 04-14-2011 |
| 20110086443 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A manufacturing yield of a semiconductor device (capacitive micromachined ultrasonic transducer) is increased. A plurality of first chips | 04-14-2011 |
| 20110097824 | METHOD OF CREATING AN EXTREMELY THIN SEMICONDUCTOR-ON- INSULATOR (ETSOI) LAYER HAVING A UNIFORM THICKNESS - A method for creating an extremely thin semiconductor-on-insulator (ETSOI) layer having a uniform thickness includes: measuring a thickness of a semiconductor-on-insulator (SOI) layer at a plurality of locations; determining a removal thickness at each of the plurality of locations; and implanting ions at the plurality of locations. The implanting is dynamically based on the removal thickness at each of the plurality of locations. The method further includes oxidizing the SOI layer to form an oxide layer, and removing the oxide layer. | 04-28-2011 |
| 20110097825 | Methods For Reducing Recrystallization Time for a Phase Change Material - A method for reducing recrystallization time for a phase change material of a memory cell element in conjunction with the manufacture of a memory cell device can be carried out as follows. A phase change material, a buffer layer material and a cladding layer material are selected. The buffer layer material is deposited on the substrate, the phase change material is deposited on the buffer layer, and the cladding layer material is deposited on the phase change material to form a memory cell element. The thickness of the phase change material is preferably less than 30 nm and more preferably less than 10 nm. The recrystallization time of the phase change material of the memory cell element is determined. If the recrystallization time is not less than a length of time X, these steps are repeated while changing at least one of the selected materials and material thicknesses. | 04-28-2011 |
| 20110117683 | CHIP QUALITY DETERMINATION METHOD AND MARKING MECHANISM USING SAME - A chip quality determination method includes the steps of (a) determining the continuity of defective chips in at least four directions of an X-axis and a Y-axis on a wafer based on the wafer test result of determining the acceptability of chips arranged in a matrix in the four directions on the wafer, and dividing the defective chips into one or more defective groups so that successive ones of the defective chips are in the same defective group; (b) calculating a quality determination index of each of one or more determination target wafer periphery neighboring chips among wafer periphery neighboring chips located within a predetermined range from the periphery of the wafer based on the distance from a corresponding one of the defective groups; and (c) determining the quality of the determination target wafer periphery neighboring chips by comparing the quality determination indexes thereof with a preset threshold. | 05-19-2011 |
| 20110124134 | END-CUT FIRST APPROACH FOR CRITICAL DIMENSION CONTROL - A method for fabricating a semiconductor device is disclosed. The method includes forming at least one material layer over a substrate; performing an end-cut patterning process to form an end-cut pattern overlying the at least one material layer; transferring the end-cut pattern to the at least one material layer; performing a line-cut patterning process after the end-cut patterning process to form a line-cut pattern overlying the at least one material layer; and transferring the line-cut pattern to the at least one material layer. | 05-26-2011 |
| 20110129947 | Method For Improving Performance Of A Substrate Carrier - A method of modifying a substrate carrier to improve process performance includes depositing material or fabricating devices on a substrate supported by a substrate carrier. A parameter of layers deposited on the substrate is then measured as a function of their corresponding positions on the substrate carrier. The measured parameter of at least some devices fabricated on the substrate or a property of the deposited layers is related to a physical characteristic of substrate carrier to obtain a plurality of physical characteristics of the substrate carrier corresponding to a plurality of positions on the substrate carrier. The physical characteristic of the substrate carrier is then modified at one or more of the plurality of corresponding positions on the substrate carrier to obtain desired parameters of the deposited layers or fabricated devices as a function of position on the substrate carrier. | 06-02-2011 |
| 20110177626 | Method Of Determining An Amount of Impurities That A Contaminating Material Contributes To High Purity Silicon And Furnace For Treating High Purity Silicon - A method of determining an amount of impurities that a contaminating material contributes to high purity silicon comprises the step of partially encasing a sample of high purity silicon in the contaminating material. The sample encased in the contaminating material is heated within a furnace. A change in impurity content of the high purity silicon is determined after the step of heating, compared to an impurity content of the high purity silicon prior to the step of heating. A furnace for heat treating high purity silicon comprises a housing that defines a heating chamber. The housing is at least partially formed from low contaminant material that contributes less than 400 parts per trillion of impurities to the high purity silicon during heating at annealing temperatures for a sufficient period time to anneal the high purity silicon, and the furnace contributes an average of less than 400 parts per trillion of impurities to the high purity silicon under the same heating conditions. | 07-21-2011 |
| 20110183445 | METHOD FOR MANUFACTURING SOI SUBSTRATE - An insulating layer is formed over a surface of a semiconductor wafer to be the bond substrate and irradiation with accelerated ions is performed, so that an embrittlement region is formed inside the wafer. Next, this semiconductor wafer and a base substrate such as a glass substrate or a semiconductor wafer are attached to each other. Then, the semiconductor wafer is divided at the embrittlement region by heat treatment, whereby an SOI substrate is manufactured in which a semiconductor layer is provided over the base substrate with the insulating layer interposed therebetween. Before this SOI substrate is manufactured, heat treatment is performed on the semiconductor wafer at 1100° C. or higher under a non-oxidizing atmosphere such as an argon gas atmosphere or a mixed atmosphere of an oxygen gas and a nitrogen gas. | 07-28-2011 |
| 20110183446 | Method of manufacturing a semiconductor device - The invention aims to provide substrate treatment equipment that can automatically collect a substrate in a normal condition without needing manual operation. The equipment includes a substrate holder for holding substrates in a multistage manner and a substrate transfer unit for transferring the substrates into the substrate holder, wherein a substrate holding condition of the substrate holder is sensed by a sensing section. The sensing section has photo-sensors, and sensing waveforms sensed by the photo-sensors are compared with a normal waveform. A control section is provided, which controls a substrate transfer unit such that substrates other than at least a substrate that was determined to be abnormal are transferred by the unit. | 07-28-2011 |
| 20110201136 | COMBINATORIAL EVALUATION OF DRY SEMICONDUCTOR PROCESSES - Combinatorial evaluation of dry semiconductor processes is described, including rotating a mask comprising a plurality of apertures, wherein the mask is positioned between a dry semiconductor processing source and the substrate, and performing a dry semiconductor process through the apertures of the mask at a plurality of intervals during the rotating the mask to combinatorially create a plurality of processed regions on the substrate, wherein the apertures of the mask are arranged in such a way that the plurality of processed regions have different geometries relative to the processing source, and analyzing the processed regions to determine effects of time and geometry on the processed regions. | 08-18-2011 |
| 20110207246 | METHODS FOR REDUCING THE WIDTH OF THE UNBONDED REGION IN SOI STRUCTURES - The disclosure relates to preparation of silicon on insulator structures with reduced unbonded regions and to methods for producing such wafers by minimizing the roll-off amount (ROA) of the handle and donor wafers. Methods for polishing wafers are also provided. | 08-25-2011 |
| 20110207247 | METHOD OF CORRECTING OVERLAY AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD USING THE SAME - A method of correcting an overlay includes setting a reference map having information relating to predetermined positions of a substrate. An overlay value is measured at each of the predetermined positions to obtain a plurality of overlay measurement values. The plurality of overlay measurement values is applied to a polar coordinate function to calculate a correlation coefficient of the polar coordinate function. The polar coordinate function uses coordinate values of the predetermined positions as parameters. | 08-25-2011 |
| 20110223694 | METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A wafer WF is mounted in a substrate holder, and the substrate holder is placed in a film forming furnace. The film forming furnace is evacuated by a vacuum pump through a gas discharge part to remove remaining oxygen as completely as possible. Then, a temperature in the film forming furnace is heated to a range of 800° C. to 950° C. under reduced pressure while an inert gas such as Ar or helium (He) is being introduced through a gas introduction part. When the temperature reaches this temperature range, an inflow of the inert gas is stopped. Vaporized ethanol is introduced as a source gas into the film forming furnace through the gas introduction part, thus forming a graphite film on an entire surface of the wafer WF. | 09-15-2011 |
| 20110229989 | LARGE SCALE METHOD AND FURNACE SYSTEM FOR SELENIZATION OF THIN FILM PHOTOVOLTAIC MATERIALS - A method for fabricating a copper indium diselenide semiconductor film is provided using substrates having a copper and indium composite structure. The substrates are placed vertically in a furnace and a gas including a selenide species and a carrier gas are introduced. The temperature is increased from about 350° C. to about 450° C. to initiate formation of a copper indium diselenide film from the copper and indium composite on the substrates. | 09-22-2011 |
| 20110250708 | METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DIODE ARRAYS AND SYSTEM FOR ELIMINATING DEFECTS IN ORGANIC LIGHT EMITTING DIODE ARRAYS - A method for manufacturing an organic light emitting diode (OLED) array is provided that includes applying an energizing signal to at least one of the OLED pixels in the array. The energizing signal exceeds a threshold level. The method also includes reducing the energizing signal and identifying an OLED in the array that continues to remain energized. The method further includes irradiating the identified OLED to degrade the organic material in the OLED. A method of performing quality control in a manufacturing process of an OLED array is provided. The method includes determining an intensity, a time and a wavelength of radiation sufficient to render an OLED of the OLED array inoperative by degrading organic material in the OLED. A system of performing quality control in a manufacturing process of an OLED array is provided. A computer-readable medium having stored thereon computer-executable instructions is provided. | 10-13-2011 |
| 20110256645 | MULTIPLE PRECURSOR SHOWERHEAD WITH BY-PASS PORTS - A method and apparatus that may be utilized for chemical vapor deposition and/or hydride vapor phase epitaxial (HVPE) deposition are provided. In one embodiment, the apparatus a processing chamber that includes a showerhead with separate inlets and channels for delivering separate processing gases into a processing volume of the chamber without mixing the gases prior to entering the processing volume. In one embodiment, the showerhead includes one or more cleaning gas conduits configured to deliver a cleaning gas directly into the processing volume of the chamber while by-passing the processing gas channels. In one embodiment, the showerhead includes a plurality of metrology ports configured to deliver a cleaning gas directly into the processing volume of the chamber while by-passing the processing gas channels. As a result, the processing chamber components can be cleaned more efficiently and effectively than by introducing cleaning gas into the chamber only through the processing gas channels. | 10-20-2011 |
| 20110275169 | SEMICONDUCTOR NANOCRYSTAL PROBES FOR BIOLOGICAL APPLICATIONS AND PROCESS FOR MAKING AND USING SUCH PROBES - A semiconductor nanocrystal compound and probe are described. The compound is capable of linking to one or more affinity molecules. The compound comprises (1) one or more semiconductor nanocrystals capable of, in response to exposure to a first energy, providing a second energy, and (2) one or more linking agents, having a first portion linked to the one or more semiconductor nanocrystals and a second portion capable of linking to one or more affinity molecules. One or more semiconductor nanocrystal compounds are linked to one or more affinity molecules to form a semiconductor nanocrystal probe capable of bonding with one or more detectable substances in a material being analyzed, and capable of, in response to exposure to a first energy, providing a second energy. Also described are processes for respectively: making the semiconductor nanocrystal compound; making the semiconductor nanocrystal probe; and treating materials with the probe. | 11-10-2011 |
| 20110275170 | SYSTEM FOR CONCURRENT TEST OF SEMICONDUCTOR DEVICES - A tool to aid a test engineer in creating a concurrent test plan. The tool may quickly map test system resources to specific pins to satisfy the requirements of a concurrent test. The tool may project test time when such a mapping is possible. When a mapping is not possible, the tool may inform its user, including making suggestions of additional resources that could allow the test system to perform the test or suggestions for other variations in input parameters that would allow a mapping. The tool employs an assignment process in which groups of associated pins are identified, along with associated resource requirements for each group. Groups of test system resources that collectively fulfill a higher level requirement are identified and the assignment is made by mapping resource sets to resource groups, using ordering and matching heuristics to reduce processing time. | 11-10-2011 |
| 20110281378 | ULTRASONIC SYSTEM FOR MEASURING GAS VELOCITY - A system and method for measuring the velocity of gas flow between multiple plasma deposition chambers is provided. A passage atmospherically linking two plasma processing chambers conducts a gas flow therebetween due to differential pressures within the respective chambers. The gas flow velocity is measured by a linear or non-linear ultrasonic energy acoustic path between two transducers located exteriorly to the chambers using the difference in transit time in a forward and reverse direction due to the velocity of gas in the passage. The pressure of process gas in one or more chambers is adjustable based on the measured velocity of gas flow in the passage. | 11-17-2011 |
| 20110294234 | THIN FILM SOLAR FABRICATION PROCESS, ETCHING METHOD, DEVICE FOR ETCHING, AND THIN FILM SOLAR DEVICE - Methods and devices for etching a device precursor are provided. For example, a method includes: providing a substrate, determining a temperature associated with the substrate, and etching a metal oxide layer of the substrate, wherein the etching is controlled based on the determined temperature. | 12-01-2011 |
| 20110294235 | METHOD OF FORMING A SEMICONDUCTOR DEVICE - A method of forming a semiconductor device includes the following processes. A groove is formed in a semiconductor substrate. A first film is formed in a device-formation region and a non-device-formation region of a semiconductor substrate. The first film is patterned to form a second film in the device-formation region and a monitoring pattern in the non-device-formation region. First and second structures are formed over the second film and the monitoring pattern respectively. The first structure has substantially the same pattern defined in a horizontal direction as the second structure. The first and second structures are polished. | 12-01-2011 |
| 20110294236 | Semiconductor device and method of manufacturing it - A method of manufacturing a semiconductor device capable of largely increasing the yield and a semiconductor device manufactured by using the method is provided. After a semiconductor layer is formed on a substrate, as one group, a plurality of functional portions with at least one parameter value different from each other is formed in the semiconductor layer for every unit chip area. Then, a subject that is changed depending on the parameter value is measured and evaluated and after that, the substrate is divided for every chip area so that a functional portion corresponding with a given criterion as a result of the evaluation is not broken. Thereby, at least one functional portion corresponding with a given criterion can be formed by every chip area by appropriately adjusting each parameter value. | 12-01-2011 |
| 20110300646 | PATTERN FORMING METHOD, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, AND TEMPLATE MANUFACTURING METHOD - In the pattern forming method according to the embodiment, second templates are manufactured by an imprint technology using first templates manufactured by applying a predetermined misalignment distribution for each shot on a first substrate by an exposure apparatus. Then, an upper-layer-side pattern is formed by an imprint technology using a second template in which an inter-layer misalignment amount between a lower-layer-side pattern already formed above a second substrate and the upper-layer-side pattern to be formed above the second substrate becomes equal to or lower than a predetermined reference value. | 12-08-2011 |
| 20110300647 | METHOD FOR MANUFACTURING SEMICONDUCTOR CHIPS FROM A SEMICONDUCTOR WAFER - A method for manufacturing semiconductor chips from a semiconductor wafer, including the steps of: fastening, on a first support frame, a second support frame having outer dimensions smaller than the outer dimensions of the first frame and greater than the inner dimensions of the first frame; arranging the wafer on a surface of a film stretched on the second frame; carrying out wafer processing operations by using equipment capable of receiving the first frame; separating the second frame from the first frame and removing the first frame; and carrying out wafer processing operations by using equipment capable of receiving the second frame. | 12-08-2011 |
| 20110312107 | METHOD AND DEVICE FOR MEASURING TEMPERATURE DURING DEPOSITION OF SEMICONDUCTOR - Provided is a method and a device for measuring a temperature which can recognize the temperature of a semiconductor layer directly with high precision when the semiconductor layer is formed by deposition. The quantity of laser light transmitted a semiconductor layer is monitored by a photodetector by using laser light having a wavelength As at which the transmittance of light changes abruptly when the temperature of the semiconductor layer reaches Ts during or after deposition. When heat being given to the semiconductor layer is changed, the quantity of laser light monitored by the photodetector changes abruptly when the temperature of the semiconductor layer reaches Ts at a time A, B or C. Consequently, the fact that the temperature of the semiconductor layer reached Ts at a time A, B or C can be recognized exactly, and an error in temperature information observed by a device for measuring temperature variations can be calibrated, for example. | 12-22-2011 |
| 20120009692 | System and Method of Dosage Profile Control - A system and method for controlling a dosage profile is disclosed. An embodiment comprises separating a wafer into components of a grid array and assigning each of the grid components a desired dosage profile based upon a test to compensate for topology differences between different regions of the wafer. The desired dosages are decomposed into directional dosage components and the directional dosage components are translated into scanning velocities of the ion beam for an ion implanter. The velocities may be fed into an ion implanter to control the wafer-to-beam velocities and, thereby, control the implantation. | 01-12-2012 |
| 20120021540 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a plurality of semiconductor integrated circuits bonded to a structure body in which a fibrous body is impregnated with an organic resin. The plurality of semiconductor integrated circuits are provided at openings formed in the structure body and each include a photoelectric conversion element, a light-transmitting substrate which has stepped sides and in which the width of the projected section on a first surface side is smaller than that of a second surface, a semiconductor integrated circuit portion provided on the second surface of the light-transmitting substrate, and a chromatic color light-transmitting resin layer which covers the first surface and part of side surfaces of the light-transmitting substrate. The plurality of semiconductor integrated circuits include the chromatic color light-transmitting resin layers of different colors. | 01-26-2012 |
| 20120028378 | METHOD FOR FORMING PATTERN AND A SEMICONDUCTOR DEVICE - According to one embodiment, a pattern forming method comprises transferring a pattern formed in a surface of a template to a plurality of chip areas in a semiconductor substrate under different transfer conditions. Furthermore, the transferring the pattern formed in the surface of the template to the plurality of chip areas in the semiconductor substrate under the different transfer conditions comprises transferring the pattern formed in the surface of the template to the semiconductor substrate at least twice under each identical transfer condition. Moreover, the pattern forming method comprises dividing each of the plurality of chip areas into a plurality of areas, determining an optimum condition for each set of corresponding divided areas in the plurality of chip areas, and transferring the pattern onto the semiconductor substrate using the optimum transfer condition determined for each divided area. | 02-02-2012 |
| 20120028379 | METHODS AND APPARATUSES FOR CONTROLLING GAS FLOW CONDUCTANCE IN A CAPACITIVELY-COUPLED PLASMA PROCESSING CHAMBER - Apparatuses are provided for controlling flow conductance of plasma formed in a plasma processing apparatus that includes an upper electrode opposite a lower electrode to form a gap therebetween. The lower electrode is adapted to support a substrate and coupled to a RF power supply. Process gas injected into the gap is excited into the plasma state during operation. The apparatus includes a ground ring that concentrically surrounds the lower electrode and has a set of slots formed therein, and a mechanism for controlling gas flow through the slots. | 02-02-2012 |
| 20120045852 | AUTOTUNED SCREEN PRINTING PROCESS - Embodiments of the invention generally provide apparatus and methods of screen printing a pattern on a substrate. In one embodiment, a patterned layer is printed onto a surface of a substrate along with a plurality of alignment marks. The locations of the alignment marks are measured with respect to a feature of the substrate to determine the actual location of the patterned layer. The actual location is compared with the expected location to determine the positional error of the patterned layer placement on the substrate. This information is used to adjust the placement of a patterned layer onto subsequently processed substrates. | 02-23-2012 |
| 20120058577 | METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR ELEMENT | 03-08-2012 |
| 20120070915 | METHOD FOR COPPER HILLOCK REDUCTION - A method of forming interconnects in integrated circuits includes providing a semiconductor substrate and forming a copper interconnect structure that is formed overlying a barrier layer within a thickness of an interlayer dielectric layer. The copper interconnect structure has a first stress characteristic. The method further loads the semiconductor substrate including the copper interconnect structure into a deposition chamber that contains an inert environment. The semiconductor substrate including the copper interconnect structure is annealed in the inert environment for a period of time to cause the copper interconnect structure to have a second stress characteristic. The semiconductor substrate is maintained in the deposition chamber while an etch stop layer is deposited thereon. The method further deposits an inner-metal dielectric layer overlying the etch stop layer, wherein the annealing reduces copper hillock defects resulting from at least the first stress characteristic. | 03-22-2012 |
| 20120077290 | METHOD OF ETCHING SURFACE LAYER PORTION OF SILICON WAFER AND METHOD OF ANALYZING METAL CONTAMINATION OF SILICON WAFER - An aspect of the present invention relates to a method of etching a surface layer portion of a silicon wafer comprising: positioning the silicon wafer within a sealed vessel containing a mixed acid A of hydrofluoric acid and sulfuric acid so that the silicon wafer is not in contact with mixed acid A; introducing a solution B in the form of nitric acid containing nitrogen oxides into the sealed vessel and causing solution B to mix with mixed acid A; and vapor phase decomposing the surface layer portion of the silicon wafer within the sealed vessel within which mixed acid A and solution B have been mixed. | 03-29-2012 |
| 20120100641 | ETCHING APPARATUS AND ETCHING METHOD - According to an embodiment, an etching apparatus includes a reaction chamber, a vacuum pump connected to the reaction chamber through the gate valve, a holding unit which holds a processing subject, an etching gas supply unit, a heating unit, and a sublimation amount determining unit. The etching gas supply unit supplies an etching gas which forms a reaction product by reacting with the processing subject to the reaction chamber. The heating unit heats the processing subject to an equal or higher temperature than temperature at which the reaction product will be sublimated. The sublimation amount determining unit monitors a predetermined physical amount which changes depending on the degree of sublimation of the reaction product during the sublimation process using the heating unit, in which the physical amount is used as a sublimation-amount-dependent change value which changes over time. | 04-26-2012 |
| 20120129278 | DRY ETCHING METHOD - A dry etching method includes a first step and a second step. The first step includes generating a first plasma from a gas mixture, which includes an oxidation gas and a fluorine containing gas, and performing anisotropic etching with the first plasma on a silicon layer to form a recess in the silicon layer. The second step includes alternately repeating an organic film forming process whereby an organic film is deposited on the inner surface of the recess with a second plasma, and an etching process whereby the recess covered with the organic film is anisotropically etched with the first plasma. When an etching stopper layer is exposed from a part of the bottom surface of the recess formed in the first step, the first step is switched to the second step. | 05-24-2012 |
| 20120135547 | FABRICATING METHOD AND TESTING METHOD OF SEMICONDUCTOR DEVICE AND MECHANICAL INTEGRITY TESTING APPARATUS - A fabricating method and a testing method of a semiconductor device and a mechanical integrity testing apparatus are provided. An object includes a wafer, an insulating layer, and a plurality of conductive posts is provided. A surface of the wafer has a plurality of first blind holes outside chip regions and a plurality of second blind holes inside the chip regions. The insulating layer is between the conductive posts and the walls of the first blind holes and between the conductive posts and the walls of the second blind holes. A mechanical integrity test is performed to test a binding strength between the insulating layer, the conductive posts, and the walls of the first blind holes. The conductive posts in the chip regions are electrically connected to an element after the conductive posts in the first blind holes are qualified in the mechanical integrity test. | 05-31-2012 |
| 20120142123 | ALGAINN-BASED LASERS PRODUCED USING ETCHED FACET TECHNOLOGY - A process for fabricating AlGaInN-based photonic devices, such as lasers, capable of emitting blue light employs etching to form device waveguides and mirrors, preferably using a temperature of over 500° C. and an ion beam in excess of 500 V in CAIBE. | 06-07-2012 |
| 20120149134 | METHODS AND APPARATUS FOR THINNING, TESTING AND SINGULATING A SEMICONDUCTOR WAFER - A wafer translator is provided with a patterned layer of wafer bonding thermoset plastic and is removably attached with a wafer so as to form a wafer/wafer translator pair. The wafer translator acts as a mechanical support during a thinning process as well as during a wafer dicing operation. The singulated integrated circuits are then removed from the wafer translator. In some embodiments, wafer level testing of the integrated circuits on the wafer is performed subsequent to the wafer thinning process but before the wafer and wafer translator are separated. In other embodiments, wafer level testing of the integrated circuits on the wafer is performed subsequent to the wafer dicing operation but before the diced wafer and wafer translator are separated. | 06-14-2012 |
| 20120149135 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD THAT ALLOWS REWORK RATE IN MANUFACTURING STEP TO DECREASE - A semiconductor device manufacturing method includes: forming a first pattern in a first film to be processed on a semiconductor substrate; measuring a first distance, which is a dimension in a predetermined direction in the first pattern; forming a second film to be processed on the first pattern; forming a second pattern in a photoresist formed on the second film to be processed; and measuring a second distance, which is a dimension in a predetermined direction in the second pattern. Whether or not the second pattern is defective is determined based on either the first distance or a value calculated from the first and second distances. | 06-14-2012 |
| 20120164760 | COMPLETE RECRYSTALLIZATION OF SEMICONDUCTOR WAFERS - The instant disclosure relates to a device and method for recrystallising a silicon wafer or a wafer comprising at least one silicon layer. The silicon wafer or the at least one silicon layer of the wafer is totally molten. | 06-28-2012 |
| 20120190137 | CROSS SECTION OBSERVATION METHOD - Provided is a cross section observation method, including the steps of: forming a marker layer at a base material, the marker layer having a conductivity different from that of another portion of the base material; forming a sample, by performing treatment on the base material at which the marker layer is formed; and detecting secondary electrons generated by emitting electrons to a cross section of the sample. | 07-26-2012 |
| 20120190138 | SEMICONDUCTOR MANUFACTURING APPARATUS AND SEMICONDUCTOR SUBSTRATE BONDING METHOD - According to one embodiment, semiconductor manufacturing apparatus includes a first member that holds a first semiconductor substrate; a second member that holds a second semiconductor substrate in a state where a bonding surface of the second semiconductor substrate faces a bonding surface of the first semiconductor substrate; a distance detecting unit that detects a distance between the bonding surface of the first semiconductor substrate and the bonding surface of the second semiconductor substrate; an adjusting unit that adjusts the distance between the bonding surface of the first semiconductor substrate and the bonding surface of the second semiconductor substrate to a predetermined value by moving at least one of the first and second members based on a detection result of the distance detecting unit; and a third member that forms the bonding start point between the first semiconductor substrate and the second semiconductor substrate. | 07-26-2012 |
| 20120196387 | SUBSTRATE PROCESSING METHOD - The present invention provides a substrate processing method to process a substrate including at least a process layer, an intermediate layer, and a mask layer which are stacked in this order. The mask layer includes an aperture configured to expose a portion of the intermediate layer. The substrate processing method includes a material deposition step of depositing a material on a side surface of the aperture and exposing a portion of the process layer by etching the exposed portion of the intermediate layer by plasma generated from a deposit gas, and an etching step of etching the exposed portion of the process layer. | 08-02-2012 |
| 20120202302 | SEMICONDUCTOR DEVICE MANUFACTURING SYSTEM AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Certain embodiments provide a semiconductor device manufacturing system including processing devices used in processing processes, a wafer transfer device, a processing characteristic measuring unit, a device characteristic measuring unit, data server, and an analysis server. The wafer transfer device conveys the wafer to the processing devices such that a direction of the wafer differs according to each processing process. The data server stores data. The data include processing characteristic data that is the processing characteristic of the wafer for each processing process measured by the processing characteristic measuring unit, the direction of the wafer for each processing process, and device characteristic data that is the device characteristic of the wafer measured by the device characteristic measuring unit. The analysis server specifies a cause process that causes the device characteristic data to be obtained based on the correlation between the processing characteristic data and the device characteristic data. | 08-09-2012 |
| 20120214259 | OXYGEN DIFFUSION EVALUATION METHOD OF OXIDE FILM STACKED BODY - Experience shows that, in a material containing oxygen as a main component, an excess or deficiency of trace amounts of oxygen with respect to a stoichiometric composition, or the like affects properties of the material. An oxygen diffusion evaluation method of an oxide film stacked body includes the steps of: measuring a quantitative value of one of oxygen isotopes of a substrate including a first oxide film and a second oxide film which has an existence proportion of an oxygen isotope different from an existence proportion of an oxygen isotope in the first oxide film in a depth direction, by secondary ion mass spectrometry; and evaluating the one of the oxygen isotopes diffused from the first oxide film to the second oxide film. | 08-23-2012 |
| 20120214260 | Semiconductor Surface Modification - Methods, systems, and devices associated with surface modifying a semiconductor material are taught. One such method includes providing a semiconductor material having a target region and providing a dopant fluid layer that is adjacent to the target region of the semiconductor material, where the dopant fluid layer includes at least one dopant. The target region of the semiconductor material is lased so as to incorporate the dopant or to surface modify the semiconductor material. During the surface modification, the dopant in the dopant fluid layer is actively replenished. | 08-23-2012 |
| 20120225502 | PLASMA ETCHING METHOD AND COMPUTER-READABLE STORAGE MEDIUM - A plasma etching method includes a preparation process for performing a plasma etching process using a processing gas including a first processing gas containing carbon (C) and fluorine (F), a ratio (C/F) of the first processing gas having a first value, and obtaining a residual amount of the mask layer corresponding to a variation point where a variation amount of the bowing CD is increased; a first plasma etching process using the processing gas including the first processing gas until a residual amount of the mask layer reaches the variation point; and a second plasma etching process performed after the first plasma etching process. The second plasma etching process is performed by using a processing gas including at least a second processing gas containing carbon (C) and fluorine (F), and a ratio (C/F) of the second processing gas is smaller than the first value. | 09-06-2012 |
| 20120231561 | REMOVAL OF METAL - Methods of removing metal from a portion of a substrate are useful in integrated circuit fabrication. Methods include exposing the substrate to an oxidizing environment comprising at least one oxidizing agent and at least one reducing agent, and exposing the substrate to a reducing environment comprising at least one reducing agent and at least one oxidizing agent. | 09-13-2012 |
| 20120231562 | SEMICONDUCTOR MANUFACTURING APPARATUS, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING ELECTRONIC DEVICE - A semiconductor manufacturing apparatus includes: a treatment chamber treating a treated film of a wafer using a desired chemical fluid; a film thickness measurement unit measuring an initial film thickness of the treated film before treatment and a final film thickness of the treated film after treatment; and a main body controlling unit calculating a treatment speed of the chemical fluid from the initial film thickness, the final film thickness, and a chemical fluid treatment time taken from the initial film thickness to the final film thickness to calculate a chemical fluid treatment time for a wafer to be treated next from the calculated treatment speed. | 09-13-2012 |
| 20120238042 | Device for Releasably Receiving a Semiconductor Chip - A device is disclosed for releasably receiving a singulated semiconductor chip having a first main surface and a second main surface opposite the first main surface. The device includes a support structure. At least one elastic element is arranged on the support structure. Electrical contact elements are arranged on the at least one elastic element and adapted to be contacted to the first main surface of the semiconductor chip. A foil is adapted to be arranged over the second main surface of the semiconductor chip. | 09-20-2012 |
| 20120238043 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - With the stage kept in an as-heated state, the semiconductor wafer is placed over the stage (step S | 09-20-2012 |
| 20120244646 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND ADJUSTING APPARATUS - According to embodiments, there is provided a manufacturing method of a semiconductor device includes forming a semiconductor thin film on a substrate; processing the thin film to a predetermined shape; executing an ion implantation process on the thin film processed to the predetermined shape; executing an anneal treatment on the thin film on which the ion implantation process has been executed to create a resistor element; and adjusting both or any one of a process condition of the ion implantation process and a treatment condition of the anneal treatment based on at least any one of a film forming condition and a film formation result of the forming and a film process result of the processing. | 09-27-2012 |
| 20120264238 | PROGRAM CONTROLLED DICING OF A SUBSTRATE USING A PULSED LASER BEAM - A substrate is diced using a program-controlled pulsed laser beam apparatus having an associated memory for storing a laser cutting strategy file. The file contains selected combinations of pulse rate Δt, pulse energy density E and pulse spatial overlap to machine a single layer or different types of material in different layers of the substrate while restricting damage to the layers and maximising machining rate to produce die having predetermined die strength and yield. The file also contains data relating to the number of scans necessary using a selected combination to cut through a corresponding layer. The substrate is diced using the selected combinations. Gas handling equipment for inert or active gas may be provided for preventing or inducing chemical reactions at the substrate prior to, during or after dicing. | 10-18-2012 |
| 20120270341 | METHOD AND SYSTEM FOR LARGE SCALE MANUFACTURE OF THIN FILM PHOTOVOLTAIC DEVICES USING MULTI-CHAMBER CONFIGURATION - A method for large scale manufacture of photovoltaic devices includes loading a substrate into a load lock station and transferring the substrate in a controlled ambient to a first process station. The method includes using a first physical deposition process in the first process station to cause formation of a first conductor layer overlying the surface region of the substrate. The method includes transferring the substrate to a second process station, and using a second physical deposition process in the second process station to cause formation of a second layer overlying the surface region of the substrate. The method further includes repeating the transferring and processing until all thin film materials of the photovoltaic devices are formed. In an embodiment, the invention also provides a method for large scale manufacture of photovoltaic devices including feed forward control. | 10-25-2012 |
| 20120276663 | EQUIPMENT AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to an embodiment, equipment for manufacturing a semiconductor device includes a first block, a plurality of stamp pins, a second block and a plurality of springs. The first block includes a plurality of first through-holes penetrating from a first major surface to a second major surface. The stamp pins are inserted into each of the first through-holes from the first major surface, each of the stamp pins having an end projected from the second major surface and being capable of moving forward and backward in the insertion direction. The second block has a plurality of second through-holes with an inner diameter larger than an inner diameter of the first through-holes, the second through-holes being disposed so as to overlap with the first through-holes; and the springs are disposed in each of the second through-holes, for biasing the stamp pins in the insertion direction. | 11-01-2012 |
| 20120282714 | SUSCEPTOR WITH BACKSIDE AREA OF CONSTANT EMISSIVITY - Methods and apparatus for providing constant emissivity of the backside of susceptors are described. Provided is a method comprising: providing a susceptor in a deposition chamber, the susceptor comprising a susceptor plate and a layer comprising an oxide, a nitride, an oxynitride, or combinations thereof, the layer being stable in the presence of the reactive process gases; and locating the wafer on a support surface of the susceptor plate. The method can further comprise selectively depositing an epitaxial layer or a non-epitaxial layer on a surface of the wafer. The method can also further comprise selectively etching to maintain the oxide, nitride, oxynitride, or combinations thereof layer. | 11-08-2012 |
| 20120301977 | SILICON CARRIER STRUCTURE AND METHOD OF FORMING SAME - A silicon carrier structure for electronic packaging includes a base substrate, a silicon carrier substrate disposed on the base substrate, a memory chip disposed on the silicon carrier substrate, a microprocessor chip disposed on the silicon carrier substrate, an input/output chip disposed on the silicon carrier substrate, and a clocking chip disposed on the silicon carrier substrate. | 11-29-2012 |
| 20120301978 | METHOD FOR PRODUCING PHOTOELECTRIC CONVERSION DEVICE AND LIGHT BEAM IRRADIATION PROCESSING APPARATUS - There is provided a method for producing a photoelectric conversion device in which an object to be processed is processed by directing a light beam to a position determined based on information including temperature information and distortion information acquired in advance. There is also provided a light beam irradiation processing apparatus including a control portion capable of controlling a light beam generating portion and a drive portion in such a manner that a light beam can be directed to a position determined based on information including temperature information acquired by a temperature information acquiring portion and distortion information stored therein. | 11-29-2012 |
| 20120315712 | Method for Detecting Embedded Voids in a Semiconductor Substrate - A method for detecting embedded voids present in a structure formed in or on a semiconductor substrate is described. The method includes performing a processing step P | 12-13-2012 |
| 20120322171 | Apparatus and Method for Making an Absorbing layer of a Solar Cell - An apparatus for making an absorbing layer of a compound solar cell includes a transportation unit, a coating unit, a heat treatment unit, a measurement unit and a control unit. The transportation unit transports a substrate-based laminate. The coating unit provides coating liquid on the substrate-based laminate. The heat treatment unit treats the coated substrate-based laminate with heat to form a film. The measurement unit measures the film and provides correction parameters to the coating unit. The control unit controls the transportation unit, the coating unit, the heat treatment unit and the measurement unit. | 12-20-2012 |
| 20120322172 | METHOD FOR MONITORING THE REMOVAL OF POLYSILICON PSEUDO GATES - The present invention discloses a method for monitoring the removal of a polycrystalline silicon dummy gate, comprising the steps of: forming a polycrystalline silicon dummy gate structure on a surface of a wafer; determining a measurement target and an error range of mass of the wafer; and measuring the mass of the wafer by a mass measurement tool after polycrystalline silicon dummy gate removal to determine whether the polycrystalline silicon dummy gate has been completely removed. According to the measurement method of the present invention, the full wafer may be quickly and accurately measured without requiring a specific test structure, to effectively monitor and determine whether the polysilicon dummy gate is thoroughly removed, meanwhile said measurement method gives feedback directly, quickly and accurately without causing any damage to the wafer. | 12-20-2012 |
| 20120322173 | METHOD AND SYSTEM FOR ISOLATED AND DISCRETIZED PROCESS SEQUENCE INTEGRATION/US - A system for processing a semiconductor substrate is provided. The system includes a mainframe having a plurality of modules attached thereto. The modules include processing modules, storage modules, and transport mechanisms. The processing modules may include combinatorial processing modules and conventional processing modules, such as surface preparation, thermal treatment, etch and deposition modules. In one embodiment, at least one of the modules stores multiple masks. The multiple masks enable in-situ variation of spatial location and geometry across a sequence of processes and/or multiple layers of a substrate to be processed in another one of the modules. A method for processing a substrate is also provided. | 12-20-2012 |
| 20130011939 | Techniques Providing Semiconductor Wafer Grouping In A Feed Forward Process - A method for processing a plurality of semiconductor wafers includes acquiring a process parameter measurement for each of the semiconductor wafers, associating each of the semiconductor wafers with one of a plurality of groups based on a respective process parameter measurement for each of the semiconductor wafers, where each respective group corresponds to a respective recipe, and for each one of the groups, processing ones of the semiconductor wafers associated with that group together according to a respective recipe. | 01-10-2013 |
| 20130011940 | METHOD OF REDUCING DAMAGE TO AN ELECTRON BEAM INSPECTED SEMICONDUCTOR SUBSTRATE, AND METHODS OF INSPECTING A SEMICONDUCTOR SUBSTRATE - Methods for reducing electron beam induced damage on semiconductor substrates employ compositions such as small chain organic solvents and non-neutral pH solutions to reduce or eliminate charge imbalances on semiconductor substrates caused by electron beam inspection of the semiconductor substrates. Damage to semiconductor substrates by electron beam inspection processes may also be reduced by generating or otherwise forming passivation films on a semiconductor substrate following electron beam inspection. | 01-10-2013 |
| 20130017628 | TEMPERATURE DETECTING APPARATUS, SUBSTRATE PROCESSING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICEAANM KOSUGI; TetsuyaAACI ToyamaAACO JPAAGP KOSUGI; Tetsuya Toyama JPAANM UENO; MasaakiAACI ToyamaAACO JPAAGP UENO; Masaaki Toyama JPAANM YAMAGUCHI; HidetoAACI ToyamaAACO JPAAGP YAMAGUCHI; Hideto Toyama JP - A temperature detecting apparatus is provided which is capable of suppressing disconnection of a thermocouple wire or positional deviation of a thermocouple junction portion caused by change over time. The temperature detecting apparatus includes: an insulation rod installed to extend in a vertical direction and including a through-hole in vertical direction; a thermocouple wire inserted in the through-hole of the insulation rod, the thermocouple wire including a thermocouple junction portion at an upper end thereof and an angled portion at a lower end of the insulation rod; and a buffer area installed below the insulation rod and configured to suppress a restriction of a horizontal portion of the angled portion upon heat expansion, wherein an upper portion of the thermocouple wire or a middle portion in the vertical direction are supported by the insulation rod. | 01-17-2013 |
| 20130052758 | REMOVING ALUMINUM NITRIDE SECTIONS - Approaches for substantially removing bulk aluminum nitride (AlN) from one or more layers epitaxially grown on the bulk AlN are discussed. The bulk AlN is exposed to an etchant during an etching process. During the etching process, the thickness of the bulk AlN can be measured and used to control etching. | 02-28-2013 |
| 20130052759 | VERTICAL SOLID-STATE TRANSDUCERS HAVING BACKSIDE TERMINALS AND ASSOCIATED SYSTEMS AND METHODS - Vertical solid-state transducers (“SSTs”) having backside contacts are disclosed herein. An SST in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the SST, a second semiconductor material at a second side of the SST opposite the first side, and an active region between the first and second semiconductor materials. The SST can further include first and second contacts electrically coupled to the first and second semiconductor materials, respectively. A portion of the first contact can be covered by a dielectric material, and a portion can remain exposed through the dielectric material. A conductive carrier substrate can be disposed on the dielectric material. An isolating via can extend through the conductive carrier substrate to the dielectric material and surround the exposed portion of the first contact to define first and second terminals electrically accessible from the first side. | 02-28-2013 |
| 20130065329 | Superior Integrity of High-K Metal Gate Stacks by Preserving a Resist Material Above End Caps of Gate Electrode Structures - When forming high-k metal gate electrode structures in a semiconductor device on the basis of a basic transistor design, undue exposure of sensitive materials at end portions of the gate electrode structures of N-channel transistors may be avoided, for instance, prior to and upon incorporating a strain-inducing semiconductor material into the active region of P-channel transistors, thereby contributing to superior production yield for predefined transistor characteristics and performance. | 03-14-2013 |
| 20130065330 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING SAME - In manufacturing an LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by a voltage-application test in an environment of high temperature (e.g., from 85 to 130° C.) and high humidity (e.g., about 80% RH). It has been found that separation of a titanium nitride anti-reflection film from an upper film and generation of cracks in the titanium nitride film at an upper surface edge part of the aluminum-based bonding pad applied with a positive voltage in the test is caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film. These problems are addressed by removing the titanium nitride film over the pad in a ring or slit shape at peripheral area of the aluminum-based bonding pad. | 03-14-2013 |
| 20130084657 | Plasma Density Control - A first embodiment is a method for semiconductor processing. The method comprises forming a component on a wafer in a chamber; determining a non-uniformity of the plasma in the chamber, the determining being based at least in part on the component on the wafer; and providing a material on a surface of the chamber corresponding to the non-uniformity. The forming the component includes using a plasma. The material can have various shapes, compositions, thicknesses, and/or placements on the surface of the chamber. Other embodiments include a chamber having a material on a surface to control a plasma uniformity. | 04-04-2013 |
| 20130084658 | Separation of Semiconductor Devices from a Wafer Carrier - In accordance with an embodiment of the present invention, a semiconductor device is manufactured by arranging a plurality of semiconductor devices on a frame with an adhesive foil. The plurality of semiconductor devices is attached to the adhesive foil. The plurality of semiconductor devices is removed from the frame with the adhesive foil using a carbon dioxide snow jet and/or a laser process. | 04-04-2013 |
| 20130084659 | Testing Process for Semiconductor Devices - In accordance with an embodiment of the present invention, a method of manufacturing a semiconductor device includes providing a wafer having a top surface and an opposite bottom surface. The top surface has a plurality of dicing channels. The wafer has a plurality of dies adjacent the top surface. Each die of the plurality of dies is separated by a dicing channel of the plurality of dicing channels from another die of the plurality of dies. Trenches are formed in the wafer from the top surface. The trenches are oriented along the plurality of dicing channels. After forming the trenches, the plurality of dies is tested to identify first dies to be separated from remaining dies of the plurality of dies. After testing the plurality of dies, the wafer is subjected to a grinding process from the back surface. The grinding process separates the wafer into the plurality of dies. | 04-04-2013 |
| 20130084660 | PROCESS FOR ENHANCING IMAGE QUALITY OF BACKSIDE ILLUMINATED IMAGE SENSOR - A method of forming an image sensor device includes forming a light sensing region at a front surface of a silicon substrate and a patterned metal layer there over. Thereafter, the method also includes performing an ion implantation process to the back surface of the silicon substrate and performing a green laser annealing process to the implanted back surface of the silicon substrate. The green laser annealing process uses an annealing temperature greater than or equal to about 1100° C. for a duration of about 100 to about 400 nsec. After performing the green laser annealing process, a silicon polishing process is performed on the back surface of the silicon substrate. | 04-04-2013 |
| 20130089936 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A plurality of SiC semiconductor chips are mounted on a mounting substrate (S | 04-11-2013 |
| 20130095578 | APPARATUS AND METHOD FOR THE PRODUCTION OF PHOTOVOLTAIC MODULES - Embodiments of the invention may provide a system for the production of photovoltaic modules that comprises at least a first work line having a plurality of positioning stations in which a series of first processing operations are performed and a second work line consisting of at least a positioning station in which at least a second processing operation is performed. The process sequence may include, for example, printing a layer material used to form one or more electric contacts on a base layer, and then positioning photovoltaic cells and various layers of insulating material in a desired orientation over the base layer to form a photovoltaic module. | 04-18-2013 |
| 20130102092 | POLYCRYSTALLINE SILICON ROD AND METHOD FOR MANUFACTURING POLYCRYSTALLINE SILICON ROD - The length of the polycrystalline silicon rod ( | 04-25-2013 |
| 20130109110 | METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE | 05-02-2013 |
| 20130122613 | Localized CMP to Improve Wafer Planarization - To provide improved planarization, techniques in accordance with this disclosure include a CMP station that utilizes localized planarization on a wafer. This localized planarization, which is often carried out in a localized planarization station downstream of a CMP station, applies localized planarization to less than the entire face of the wafer to correct localized non-planar features. Other systems and methods are also disclosed. | 05-16-2013 |
| 20130130410 | METHOD FOR METAL CORRELATED VIA SPLIT FOR DOUBLE PATTERNING - A method of via patterning mask assignment for a via layer using double patterning technology, the method includes determining, using a processor, if a via of the via layer intercepts an underlying or overlaying metal structure assigned to a first metal mask. If the via intercepts the metal structure assigned to the first metal mask, assigning the via to a first via mask, wherein the first via mask aligns with the first metal mask. Otherwise, assigning the via to a second via mask, wherein the second via mask aligns with a second metal mask different from the first metal mask. | 05-23-2013 |
| 20130137196 | METHOD FOR MONITORING DEVICES IN SEMICONDUCTOR PROCESS - The invention provides a method for monitoring devices in semiconductor process comprising: Step a, designing a sampling plan with fixed sample size before the beginning of the semiconductor process; Step b, determining whether to sample the wafers according to the sampling plan and dispatching the wafers to be sampled to each process device before the beginning of the process step, wherein the process device is used for performing the process step; Step c, performing the process step; Step d, sampling the wafers according to the sampling plan, and performing in-line inspection to the sampled wafers according to the sampling results; Step e, repeating Step b to Step d until all the process steps are completed; Step f, performing e-test to all the wafers. According to the method, the potential risk during the semiconductor process can be minimized through the coordination of the sampling plan and the dynamic risk flag. | 05-30-2013 |
| 20130149800 | Method of Controlling Semiconductor Device Fabrication - A semiconductor wafer fabrication metrology method in which process steps are characterised by a change in wafer mass, whereby during fabrication mass is used as a measurable parameter to implement statistical process control on the one or more of process steps. In one aspect, the shape of a measured mass distribution is compared with the shape of a predetermined characteristic mass distribution to monitor the process. An determined empirical relationship between a control variable of the process and the characteristic mass change may enable differences between the measured mass distribution and characteristic mass distribution to provide information about the control variable. In another aspect, the relative position of an individual measured wafer mass change in a current distribution provides information about individual wafer problems independently from general process problems. | 06-13-2013 |
| 20130157389 | Multiple-Patterning Overlay Decoupling Method - A method for fabricating a semiconductor device is disclosed. An exemplary method includes forming a first structure in a first layer by a first exposure and determining placement information of the first structure. The method further includes forming a second structure in a second layer overlying the first layer by a second exposure and determining placement information of the second structure. The method further includes forming a third structure including first and second substructures in a third layer overlying the second layer by a third exposure. Forming the third structure includes independently aligning the first substructure to the first structure and independently aligning the second substructure to the second structure | 06-20-2013 |
| 20130164864 | TOOL CUTTING METHOD FOR WORKPIECE HAVING A PLURALITY OF LED CHIPS SEALED BY SEALING MEMBER - A tool cutting method which includes a correlation table preparing step of preparing a correlation table indicating the correlation between the brightness of light emitted from LED chips and the thickness of a sealing member, a brightness measuring step of measuring the brightness of light emitted from the LED chips by applying a voltage to the LED chips, a calculating step of calculating the thickness of the sealing member corresponding to the desired thickness from the brightness measured in the brightness measuring step and the correlation table, and a cutting step of cutting the sealing member by using a tool cutting unit after performing the calculating step to reduce the thickness of the sealing member to a finished thickness providing the desired brightness of light emitted from the LED chips. | 06-27-2013 |
| 20130171747 | FABRICATING METHOD OF SEMICONDUCTOR DEVICE - A fabricating method and a testing method of a semiconductor device and a mechanical integrity testing apparatus are provided. An object includes a wafer, an insulating layer, and a plurality of conductive posts is provided. A surface of the wafer has a plurality of first blind holes outside chip regions and a plurality of second blind holes inside the chip regions. The insulating layer is between the conductive posts and the walls of the first blind holes and between the conductive posts and the walls of the second blind holes. A mechanical integrity test is performed to test a binding strength between the insulating layer, the conductive posts, and the walls of the first blind holes. The conductive posts in the chip regions are electrically connected to an element after the conductive posts in the first blind holes are qualified in the mechanical integrity test. | 07-04-2013 |
| 20130171748 | METHOD OF TESTING A SEMICONDUCTOR DEVICE AND SUCTIONING A SEMICONDUCTOR DEVICE IN THE WAFER STATE - A semiconductor device has an alignment mark which can be recognized by a conventional wafer prober. A redistribution layer connects electrodes of the semiconductor device to electrode pads located in predetermined positions of the redistribution layer. Metal posts configured to be provided with external connection electrodes are formed on the electrode pads of the redistribution layer. A mark member made of the same material as the metal posts is formed on the redistribution layer. The mark member serves as an alignment mark located in a predetermined positional relationship with the metal posts. | 07-04-2013 |
| 20130189802 | SUBSTRATE HOLDER, LITHOGRAPHIC APPARATUS, AND DEVICE MANUFACTURING METHOD - A substrate holder for use in a lithographic apparatus. The substrate holder comprises a main body, a plurality of burls and a heater and/or a temperature sensor. The main body has a surface. The plurality of burls project from the surface and have end surfaces to support a substrate. The heater and/or temperature sensor is provided on the main body surface. The substrate holder is configured such that when a substrate is supported on the end surfaces, a thermal conductance between the heater and/or temperature sensor and the substrate is greater than a thermal conductance between the heater and/or temperature sensor and the main body surface. | 07-25-2013 |
| 20130196456 | Method for Stressing a Thin Pattern and Transistor Fabrication Method Incorporating Said Method - A method for stressing a pattern having a pattern surface, in a layer of semiconductive material that can be silicon on the surface of a stack of layers generated on the surface of a substrate, said stack comprising at least one stress layer of alloy Si | 08-01-2013 |
| 20130196457 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In some aspects of the invention, a circuit pattern of a front surface structure is formed in a front surface of a semiconductor wafer and an alignment mark is formed on the front surface of a semiconductor wafer. A transparent supporting substrate is attached to the front surface of the semiconductor wafer by a transparent adhesive. Then, a resist is applied onto a rear surface of the semiconductor wafer. Then, the semiconductor wafer is mounted on a stage of an exposure apparatus, with the supporting substrate down. Then, the alignment mark formed on the front surface of the semiconductor wafer is recognized by a camera, and the positions of the semiconductor wafer and a photomask are aligned with each other. Then, the resist is patterned. Then, a circuit pattern is formed in the rear surface of the semiconductor wafer. | 08-01-2013 |
| 20130203188 | HYBRID METROLOGY FOR SEMICONDUCTOR DEVICES - Methods and systems are provided for fabricating and measuring physical features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves forming a first feature of the semiconductor device structure on a substrate of semiconductor material, obtaining a first measurement for the semiconductor device structure from a first metrology tool, obtaining a second measurement of the first feature of the semiconductor device structure from a second metrology tool, and determining a hybrid measurement for the first feature based at least in part on the first measurement and the second measurement. | 08-08-2013 |
| 20130217155 | PATTERN FORMING METHOD, PATTERN FORMING APPARATUS, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a pattern forming method using a template containing a pattern that has at least one recess section or protrusion section to transfer the shape of the pattern to a resin layer on a substrate, is provided. The method includes a process for coating the resin on the substrate, a process for making the hardness of the first portion as a portion of the resin higher than the hardness of the second portion as the portion other than the first portion, and a process in which the portion other than the pattern of the template makes contact with the first portion, in a state where a gap is maintained between the template and the resin, the shape of the pattern is transferred to the second portion, and the resin is cured. Embodiments of an apparatus for pattern forming are also provided. | 08-22-2013 |
| 20130217156 | METHOD, MASK AND SYSTEM FOR MANUFACTURING SOLAR CELL - A method of manufacturing a solar cell according to an aspect includes detecting a positioning pattern that includes at least a part of an ion implantation pattern in which an ion is implanted into a predetermined region of a solar cell substrate, and performing relative positioning between a process unit and the solar cell substrate, wherein the process unit executes a predetermined process based on the detected positioning pattern when the predetermined process is executed to the solar cell substrate. | 08-22-2013 |
| 20130230933 | METHODS FOR FABRICATING THIN FILM SOLAR CELLS - A method for fabricating a thin-film solar cell. The method includes rolling a flexible substrate prepared with a metalized surface out of a roll to move linearly with a speed. The method further includes forming a back-electrode film overlying the metalized surface moving with the speed. Additionally, the method includes forming a stack of films comprising at least copper, gallium, and indium overlying the back-electrode film and forming a Se-alloy layer overlying the stack of films. Furthermore, the method includes depositing a Se—Na bearing film overlying the Se-alloy layer from a vacuum evaporator having at least two sources. Moreover, the method includes performing a thickness measurement in real time for the back-electrode film, the stack of films, and the Se-alloy layer on the flexible substrate moving with the speed to control the Se-alloy layer in a thickness of 10-100 nm corresponding to the Se—Na film in a thickness of 1-3 microns. | 09-05-2013 |
| 20130244349 | IMPURITY ANALYSIS DEVICE AND METHOD - According to one embodiment, an impurity analysis method comprises performing vapor-phase decomposition on a silicon-containing film formed on a substrate, heating the substrate at a first temperature after vapor phase decomposition, heating the substrate at a second temperature higher than the first temperature after heating at the first temperature, to remove a silicon compound deposited on the surface of the silicon-containing film, dropping a recovery solution onto the substrate surface after heating at the second temperature and moving the substrate surface, to recover metal into the recovery solution, and drying the recovery solution, to perform X-ray fluorescence spectrometry on a dried mark. | 09-19-2013 |
| 20130252350 | SYSTEM AND METHOD FOR GENERATING CARE AREAS FOR DEFECT INSPECTION - A method of generating care areas is disclosed. An artwork file of a layout of a product is provided and a cell tree of the layout is formed. The cell tree includes a plurality of cells of the layout arranged in a hierarchical order. The method also includes defining care areas in the artwork file of the layout. | 09-26-2013 |
| 20130252351 | FILM-FORMING FORMULATIONS FOR SUBSTRATE PRINTING - Film-forming formulations are provided that satisfy a plurality of criteria for inkjet printing, thermal printing, or both. Criteria for film-forming formulations are also provided for selecting vehicles, combinations of vehicles, and film-forming materials, based upon viscosity, surface tension, solubility, and properties of printed films formed by such formulations. Film-forming formulations useful in the fabrication of organic light emitting devices (OLEDs) are provided including formulations useful for the fabrication of OLED hole transport layers, hole injection layers, electron transport layers, electron injection layers, and emissive layers, of an OLED. Methods of evaluating formulations for suitability in inkjet printing, thermal printing, or both, are also provided. | 09-26-2013 |
| 20130252352 | DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A display substrate includes a transistor, a black matrix and a color spacer. The transistor is connected to a gate line, and a data line crossing the gate line. The black matrix includes a first light-blocking portion covering the gate line and the data line, and a second light-blocking portion covering a channel of the transistor. The second light-blocking portion has a thickness which is smaller than a thickness of the first light-blocking portion. The color spacer is disposed on the second light-blocking portion. | 09-26-2013 |
| 20130252353 | VAPOR DEPOSITION METHOD, VAPOR DEPOSITION DEVICE AND ORGANIC EL DISPLAY DEVICE - A coating film ( | 09-26-2013 |
| 20130267045 | SHOWER HEAD APPARATUS AND METHOD FOR CONTROLLIGN PLASMA OR GAS DISTRIBUTION - An apparatus comprises: a shower head having a supply plenum for supplying the gas to the chamber and a vacuum manifold fluidly coupled to the supply plenum; and at least one vacuum system fluidly coupled to the vacuum manifold of the shower head. | 10-10-2013 |
| 20130267046 | METHOD FOR FABRICATION OF A SEMICONDUCTOR DEVICE AND STRUCTURE - A method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a first metal layer overlaying the first transistors and providing at least one connection to the first transistors, then processing a second metal layer overlaying the first metal layer, then processing a second layer of second transistors overlaying the second metal layer, wherein the second metal layer is connected to provide power to at least one of the second transistors. | 10-10-2013 |
| 20130267047 | Topography-Aware Lithography Pattern Check - The present disclosure provides a method. The method includes obtaining an integrated circuit (IC) layout. The method includes providing a polishing process simulation model. The method includes performing a lithography pattern check (LPC) process to the IC layout. The LPC process is performed at least in part using the polishing process simulation model. The method includes detecting, in response to the LPC process, possible problem areas on the IC layout. The method includes modifying the polishing process simulation model. The method includes repeating the performing the LPC process and the detecting the possible problem areas using the modified polishing process simulation model. | 10-10-2013 |
| 20130267048 | Structure and Method for Placement, Sizing and Shaping of Dummy Structures - A chip includes a number a plurality of functional areas of a layer and a number of dummy structures within the layer. The dummy structures are spaced from the functional areas. Each dummy structure has a size that is a function of the size and density of the functional areas. | 10-10-2013 |
| 20130273671 | Apparatus and Method for Endpoint Detection During Electronic Sample Preparation - A method for detecting an endpoint during removal of material from an electronic device includes while removing material from an electronic device-under-test (DUT) using a tip driven by a spindle, applying an input signal to the DUT via the tip and using an output signal received from one of the DUT and a mounting plate to which the DUT is attached to determine an endpoint for removal of material. | 10-17-2013 |
| 20130280824 | APPARATUS AND METHOD FOR MEASURING RADIATION ENERGY DURING THERMAL PROCESSING - Embodiments of the present invention provide apparatus and method for reducing heating source radiation influence in temperature measurement during thermal processing. In one embodiment of the present invention, background radiant energy, such as an energy source of a thermal processing chamber, is marked within a selected spectrum, a characteristic of the background is then determined by measuring radiant energy at a reference wavelength within the selected spectrum and a comparing wavelength just outside the selected spectrum. | 10-24-2013 |
| 20130280825 | PEELING SYSTEM, PEELING METHOD, AND COMPUTER STORAGE MEDIUM - A peeling system includes: a carry-in/carry-out station that loads/unloads substrates to be processed, support substrates, or stacked substrates in which these are made to adhere; a peeling process station that carries out prescribed processing on substrates to be processed, support substrates and stacked substrates; and a transport station provided between the carry-in/carry-out station and the peeling process station. The peeling process station has a peeling device that peels the stacked substrates, a first washing apparatus that washes peeled substrates to be processed, and a second washing apparatus that washes the peeled support substrates. The pressure inside the transport station is a positive pressure in relation to the pressure inside the peeling device, the pressure inside the first washing apparatus, and the pressure inside the second washing apparatus. The pressure inside a transport apparatus is a positive pressure in relation to the pressure inside the peeling device and the pressure inside the first washing apparatus. | 10-24-2013 |
| 20130288400 | System and Method for Aligning Substrates for Multiple Implants - A system and method are disclosed for aligning substrates during successive process steps, such as ion implantation steps, is disclosed. Implanted regions are created on a substrate. After implantation, an image is obtained of the implanted regions, and a fiducial is provided on the substrate in known relation to at least one of the implanted regions. A thermal anneal process is performed on the substrate such that the implanted regions are no longer visible but the fiducial remains visible. The position of the fiducial may be used in downstream process steps to properly align pattern masks over the implanted regions. The fiducial also may be applied to the substrate before any ion implanting of the substrate is performed. The position of the fiducial with respect to an edge or a corner of the substrate may be used for aligning during downstream process steps. Other embodiments are described and claimed. | 10-31-2013 |
| 20130288401 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes: forming a first layer and a second layer in this order on a nitride semiconductor layer on a first main surface side of a substrate, the first and second layers having one of first and second arrangements, the first arrangement having the first layer of any of Au, V and Ta and the second layer of Ni, the second arrangement having the first layer of any of Ti, TiW, Al, W, Mo, Nb, Pt, Ta and V and the second layer of Au; forming a mask on a second main surface side of the substrate, the mask having an opening; applying an etching process to the substrate and the nitride semiconductor layer exposed in the opening of the mask; and determining an endpoint of the etching process by confirming elimination of the first layer in the opening of the mask. | 10-31-2013 |
| 20130288402 | ORGANIC EL DEVICE MANUFACTURING METHOD AND APPARATUS - An organic EL device manufacturing method includes a vapor deposition step of supplying a substrate, and while moving the substrate with a side thereof, on which an electrode layer is not provided, in contact with a surface of a can roller that rotates, discharging an evaporated organic layer forming material from a nozzle of a vapor deposition source to form an organic layer over a side of the substrate on which the electrode layer is provided, wherein the vapor deposition step is performed while, using a distance measuring section capable of measuring a first distance to the substrate supported by the can roller, and a position adjusting section capable of adjusting a second distance between the nozzle of the vapor deposition source and a surface of the substrate, control is performed by the position adjusting section so that the second distance is constant. | 10-31-2013 |
| 20130295698 | LITHOGRAPHIC TARGETS FOR UNIFORMITY CONTROL - A photo mask having a first set of patterns and a second set of patterns is provided in which the first set of patterns correspond to a circuit pattern to be fabricated on a wafer, and the second set of patterns have dimensions such that the second set of patterns do not contribute to the circuit pattern that is produced using a lithography process based on the first set of patterns under a first exposure condition. The critical dimension distribution of the photo mask is determined based on the second set of patterns that do not contribute to the circuit pattern produced using the lithography process based on the first set of patterns under the first exposure condition. | 11-07-2013 |
| 20130302918 | PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD - A plasma processing apparatus for processing an object to be processed using a plasma. The apparatus includes a processing chamber defining a processing cavity for containing an object to be processed and a process gas therein, a microwave radiating antenna having a microwave radiating surface for radiating a microwave in order to excite a plasma in the processing cavity, and a dielectric body provided so as to be opposed to the microwave radiating surface, in which the distance D between the microwave radiating surface and a surface of the dielectric body facing away from the microwave radiating surface, which is represented with the wavelength of the microwave being a distance unit, is determined to be in the range satisfying the inequality 0.7×n/4≦D≦1.3×n/4 (n being a natural number). | 11-14-2013 |
| 20130309785 | ROTATIONAL ABSORPTION SPECTRA FOR SEMICONDUCTOR MANUFACTURING PROCESS MONITORING AND CONTROL - Methods and apparatus for semiconductor manufacturing process monitoring and control are provided herein. In some embodiments, apparatus for substrate processing may include a process chamber for processing a substrate in an inner volume of the process chamber; a radiation source disposed outside of the process chamber to provide radiation at a frequency of about 200 GHz to about 2 THz into the inner volume via a dielectric window in a wall of the vacuum process chamber; a detector to detect the signal after having passed through the inner volume; and a controller coupled to the detector and configured to determine the composition of species within the inner volume based upon the detected signal. | 11-21-2013 |
| 20130316471 | Test Line Placement to Improve Die Sawing Quality - A semiconductor wafer structure includes a plurality of dies, a first scribe line extending along a first direction, a second scribe line extending along a second direction and intersecting the first scribe line, wherein the first and the second scribe lines have an intersection region. A test line is formed in the scribe line, wherein the test line crosses the intersection region. Test pads are formed in the test line and only outside a free region defined substantially in the intersection region. | 11-28-2013 |
| 20130323860 | SUBSTRATE SUPPORT PROVIDING GAP HEIGHT AND PLANARIZATION ADJUSTMENT IN PLASMA PROCESSING CHAMBER - A semiconductor substrate support for use in a plasma processing apparatus comprises a chuck body having a plenum and three radially extending bores extending between the plenum and an outer periphery of the chuck body, wherein the chuck body is sized to support a semiconductor substrate having a diameter of at least 450 mm. The semiconductor substrate support further comprises three tubular support arms which include a first section extending radially outward from the outer periphery of the chuck body, and a second section extending vertically from the first section. The tubular support arms provide a passage therethrough which communicates with a respective bore in the chuck body. The second section of each tubular support aim is configured to engage with a respective actuation mechanism outside the chamber operable to effect vertical translation and planarization of the chuck body in the interior of a plasma processing chamber. | 12-05-2013 |
| 20130323861 | PROCESS OF TREATING DEFECTS DURING THE BONDING OF WAFERS - The invention concerns a process of preparing a thin layer to be transferred onto a substrate having a surface topology and, therefore, variations in altitude or level, in a direction perpendicular to a plane defined by the thin layer, this process comprising the formation on the thin layer of a layer of adhesive material, the thickness of which enables carrying out a plurality of polishing steps of its surface in order to eliminate any defect or void or almost any defect or void, in preparation for an assembly via a molecular kind of bonding with the substrate. | 12-05-2013 |
| 20130330845 | GAS CLUSTER ION BEAM PROCESS FOR OPENING CONFORMAL LAYER IN A HIGH ASPECT RATIO CONTACT VIA - A method for patterning a layer at a bottom of a high aspect ratio feature of a substrate is described. The method includes providing the substrate having a first layer with a feature pattern overlying a second layer. The feature pattern is characterized with an initial critical dimension (CD), an initial corner profile, and an aspect ratio of 5:1 or greater. The method further includes etching through at least a portion of the second layer at the bottom of the feature pattern to extend the feature pattern at least partially into the second layer while retaining a final CD within a threshold of the initial CD and a final corner profile within a threshold of the initial corner profile using a gas cluster ion beam (GCIB) etching process. | 12-12-2013 |
| 20140024144 | INTEGRATED CIRCUIT DIE AND METHOD OF MAKING - Integrated circuit dies and methods of making dies are disclosed. An embodiment of a die includes at least one transistor gate, wherein the gate has an area. A conductor is connected to the gate, and wherein the conductor has an area. The area of the conductor is proportional to the area of the gate raised to a power, wherein the power is a function of the failure rate of the gate. | 01-23-2014 |
| 20140030827 | UNDERFILL ADHESION MEASUREMENTS AT A MICROSCOPIC SCALE - Methods and systems to method to determine an adhesion force of an underfill material to a chip assembled in a flip-chip module are provided. A method includes forming a flip-chip module including a chip connected to a substrate with a layer of underfill material adhered to the chip and the substrate. The method also includes forming a block from the layer of underfill material. The method further includes measuring a force required to shear the block from a surface of the flip-chip module. | 01-30-2014 |
| 20140038318 | PATTERN FORMING METHODS AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - According to one embodiment, a pattern forming method includes forming a self-assembled material on a plurality of first patterns, forming a plurality of second patterns by heating the self-assembled material and causing microphase separation of the self-assembled material, the second patterns corresponding to the first patterns, and calculating positional deviations of respective positions of the second patterns from positions of the corresponding first patterns. When at least one of the positional deviations is larger than a predetermined value, the self-assembled material is adjusted. | 02-06-2014 |
| 20140057371 | HIGH PRODUCTIVITY COMBINATORIAL WORKFLOW FOR POST GATE ETCH CLEAN DEVELOPMENT - Combinatorial workflow is provided for evaluating cleaning processes after forming a gate structure of transistor devices, to provide optimized process conditions for gate stack formation, including metal gate stack using high-k dielectrics. NMOS and PMOS transistor devices are combinatorially fabricated on multiple regions of a substrate, with each region exposed to a different cleaning chemical and process. The transistor devices are then characterized, and the data are compared to categorize the potential damages of different cleaning chemicals and processes. Optimized chemicals and processes can be obtained to satisfy desired device requirements. | 02-27-2014 |
| 20140065734 | METHOD AND SYSTEM FOR DETERMINING OVERLAP PROCESS WINDOWS IN SEMICONDUCTORS BY INSPECTION TECHNIQUES - The formation of overlap areas in sophisticated semiconductor devices is a critical aspect which may not be efficiently evaluated on the basis of conventional measurement and design strategies. For this reason, the present disclosure provides measurement techniques and systems in which overlying device patterns are transformed into the same material layer, thereby forming a combined pattern which is accessible by well-established defect inspection techniques. Upon geometrically modulating some of these combined patterns, a systematic evaluation of overlap process windows may be accomplished. | 03-06-2014 |
| 20140065735 | IMPRINT APPARATUS, IMPRINT METHOD, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - An imprint apparatus according to embodiments includes a stage, a dropping unit that drops resist, an imprinting unit that presses a circuit pattern of a template against the resist on a transfer target substrate, an underlying position detecting unit, a correcting unit, and a dropping position control unit. The underlying position detecting unit detects a position of an underlying pattern on the transfer target substrate. The correcting unit corrects a dropping position of the resist on a basis of a position of the underlying pattern. The dropping position control unit causes the resist to be dropped onto a dropping position after correction on the transfer target substrate on the basis of corrected dropping position. | 03-06-2014 |
| 20140065736 | DEVICE CORRELATED METROLOGY (DCM) FOR OVL WITH EMBEDDED SEM STRUCTURE OVERLAY TARGETS - Aspects of the present disclosure describe a target for use in measuring a relative position between two substantially coplanar layers of a device. The target includes periodic structures in first and second layers. Differences in relative position of the first and the second layers between the first and second periodic structures and the respective device-like structure can be measured to correct the relative position of the first and the second layers between the first and second periodic structures. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. | 03-06-2014 |
| 20140073069 | ETCHING METHOD, ETCHING APPARATUS AND CHEMICAL SOLUTION - An etching method according to an embodiment, includes performing etching on a material having tungsten (W) as a main component by using as an etchant a chemical solution having hydrogen peroxide as a main component. The chemical solution contains 12 ppm or more and 100,000 ppm or less of W. | 03-13-2014 |
| 20140087490 | Method and Apparatus for Improving Particle Performance - A method for combinatorially processing a substrate is provided. The method includes providing a substrate disposed on a substrate support. The method further includes rigidly locking a top portion of a sleeve to a bottom portion of a process head of a combinatorial processing device, where the combinatorial processing device is operable to concurrently process different regions of the substrate differently. The method includes raising the substrate and the substrate support to contact a sealing surface of the sleeve with a surface of the substrate and combinatorially processing the different regions of the substrate. | 03-27-2014 |
| 20140106478 | SLIT VALVE UNIT AND FILM FORMING APPARATUS HAVING THE SAME - There is provided a slit valve unit including: a body disposed on an outer side of a process chamber and having an entrance connected to an opening of the process chamber; a slit valve provided in an internal space of the body and selectively opening and closing the entrance; a plurality of packing members provided along the circumference of the entrance on an inner side of the body and tightly attached to the slit valve when the slit valve shields the entrance; and a connection pipe having one end exposed between the plurality of packing members on the inner side of the body so as to be connected to an airtight space formed among the plurality of packing members, the body, and the slit valve, and the other end exposed to the outer side of the body, the connection pipe penetrating the body. | 04-17-2014 |
| 20140106479 | End-Cut First Approach For Critical Dimension Control - A method for fabricating a semiconductor device is disclosed. The method includes forming at least one material layer over a substrate; performing an end-cut patterning process to form an end-cut pattern overlying the at least one material layer; transferring the end-cut pattern to the at least one material layer; performing a line-cut patterning process after the end-cut patterning process to form a line-cut pattern overlying the at least one material layer; and transferring the line-cut pattern to the at least one material layer. | 04-17-2014 |
| 20140127836 | SYSTEMS AND METHODS OF LOCAL FOCUS ERROR COMPENSATION FOR SEMICONDUCTOR PROCESSES - A system and method of compensating for local focus errors in a semiconductor process. The method includes providing a reticle and applying, at a first portion of the reticle, a step height based on an estimated local focus error for a first portion of a wafer corresponding to the first portion of the reticle. A multilayer coating is formed over the reticle and an absorber layer is formed over the multilayer coating. A photoresist is formed over the absorber layer. The photoresist is patterned, an etch is performed of the absorber layer and residual photoresist is removed. | 05-08-2014 |
| 20140127837 | THIN FILM DEPOSITION APPARATUS AND METHOD OF DEPOSITING THIN FILM USING THE SAME - A thin film deposition apparatus and a method of depositing a thin film using the thin film deposition apparatus, the thin film deposition apparatus including a chamber having a substrate and a mask mounted therein; a deposition source, the deposition source supplying a deposition gas to the substrate; and a mask measuring unit, the mask measuring unit measuring a status of the mask within the chamber. | 05-08-2014 |
| 20140134759 | METHOD OF FORMING A PATTERN - An embodiment of a method of forming a substrate pattern including forming a bottom layer and an overlying middle layer on the substrate. A photo resist pattern is formed on the middle layer. An etch coating layer is deposited on the photo resist pattern. The etch coating layer and the photo resist pattern are used as a masking element to pattern at least one of the middle layer and the bottom layer. The substrate is etched to form the substrate pattern using the at least one of the patterned middle layer and the patterned bottom layer as a masking element. The substrate pattern may be used as an element of an overlay measurement process. | 05-15-2014 |
| 20140134760 | DEVICES AND METHODS FOR EMBEDDING SEMICONDUCTORS IN PRINTED CIRCUIT BOARDS - Methods and devices for embedding semiconductors in printed circuit boards (PCBs) are provided. In one example, a method of manufacturing a PCB having a die assembly embedded therein includes removing a release film from an adhesive layer of the die assembly. The method also includes disposing the die assembly on a first layer of the PCB such that the adhesive layer contacts the first layer of the PCB. The method includes disposing a second layer of the PCB over the first layer such that the die assembly is within an intermediate portion between the first layer and the second layer. The method also includes filling the intermediate portion with resin and subjecting the PCB to a press cycle to cure the resin. | 05-15-2014 |
| 20140141541 | LOADING PORT, SYSTEM FOR ETCHING AND CLEANING WAFERS AND METHOD OF USE - A loading port includes a housing and a plurality of stations defined in the housing configured to receive a front opening universal pod (FOUP). The loading port further includes a connector configured to receive an inert gas. At least one of the plurality of stations is configured to deliver the inert gas to the FOUP to purge an interior of the FOUP of moisture. A system including the loading port and a method of using the system are also described. | 05-22-2014 |
| 20140141542 | METHODS FOR DEPOSITING FILMS ON SENSITIVE SUBSTRATES - Methods and apparatus to form films on sensitive substrates while preventing damage to the sensitive substrate are provided herein. In certain embodiments, methods involve forming a bilayer film on a sensitive substrate that both protects the underlying substrate from damage and possesses desired electrical properties. Also provided are methods and apparatus for evaluating and optimizing the films, including methods to evaluate the amount of substrate damage resulting from a particular deposition process and methods to determine the minimum thickness of a protective layer. The methods and apparatus described herein may be used to deposit films on a variety of sensitive materials such as silicon, cobalt, germanium-antimony-tellerium, silicon-germanium, silicon nitride, silicon carbide, tungsten, titanium, tantalum, chromium, nickel, palladium, ruthenium, or silicon oxide. | 05-22-2014 |
| 20140170782 | SCANNER OVERLAY CORRECTION SYSTEM AND METHOD - A method includes performing a semiconductor fabrication process on a plurality of substrates. The plurality of substrates are divided into a first subset and a second subset. A rework process is performed on the second subset of the plurality of substrates but not on the first subset. A respective mean value of at least one exposure parameter for a lithography process is computed for each respective one of the first and second subsets of the plurality of substrates. A scanner overlay correction and a mean correction are applied to expose a second plurality of substrates on which the rework process has been performed. The mean correction is based on the computed mean values. | 06-19-2014 |
| 20140170783 | MASK ALIGNMENT SYSTEM FOR SEMICONDUCTOR PROCESSING - A mask alignment system for providing precise and repeatable alignment between ion implantation masks and workpieces. The system includes a mask frame having a plurality of ion implantation masks loosely connected thereto. The mask frame is provided with a plurality of frame alignment cavities, and each mask is provided with a plurality of mask alignment cavities. The system further includes a platen for holding workpieces. The platen may be provided with a plurality of mask alignment pins and frame alignment pins configured to engage the mask alignment cavities and frame alignment cavities, respectively. The mask frame can be lowered onto the platen, with the frame alignment cavities moving into registration with the frame alignment pins to provide rough alignment between the masks and workpieces. The mask alignment cavities are then moved into registration with the mask alignment pins, thereby shifting each individual mask into precise alignment with a respective workpiece. | 06-19-2014 |
| 20140179030 | Dissolution Rate Monitor - A multiple channel site-isolated reactor system and method are described. The system contains a reactor block with a plurality of reactors. Input lines are coupled to each reactor to provide a fluid to the respective reactors. A sealing element associated with each reactor contacts a surface of a substrate disposed below the reactor block, which defines isolated regions on the surface of the substrate. A dissolution rate monitor extends into each reactor to monitor a rate of real-time dissolution of one or more layers on the surface of the substrate when it is disposed proximate to the surface of the substrate. | 06-26-2014 |
| 20140186976 | LIGHT EMITTING DEVICE WITH PLANAR CURRENT BLOCK STRUCTURE - The present disclosure discloses a method of manufacturing a light-emitting device comprising the steps of providing a light-emitting wafer having a semiconductor stacked structure and an alignment mark, sensing the alignment mark, and separating the light-emitting wafer into a plurality of light-emitting diodes and removing the alignment mark accordingly. | 07-03-2014 |
| 20140186977 | METHOD FOR CALCULATING WARPAGE OF BONDED SOI WAFER AND METHOD FOR MANUFACTURING BONDED SOI WAFER - A method for calculating a warpage of a bonded SOI wafer includes: assuming that the epitaxial growth SOI wafer is a silicon single crystal wafer having the same dopant concentration as dopant concentration of the bond wafer; calculating a warpage A that occurs at the time of performing the epitaxial growth relative to the assumed silicon single crystal wafer; calculating a warpage B caused due to a thickness of the BOX layer of the epitaxial growth SOI wafer; determining a measured value of a warpage of the base wafer before bonding as a warpage C; and calculating a sum of the warpages (A+B+C) as the warpage of the bonded SOI wafer. | 07-03-2014 |
| 20140199791 | Method and System for Universal Target Based Inspection and Metrology - Universal target based inspection drive metrology includes designing a plurality of universal metrology targets measurable with an inspection tool and measurable with a metrology tool, identifying a plurality of inspectable features within at least one die of a wafer using design data, disposing the plurality of universal targets within the at least one die of the wafer, each universal target being disposed at least proximate to one of the identified inspectable features, inspecting a region containing one or more of the universal targets with an inspection tool, identifying one or more anomalistic universal targets in the inspected region with an inspection tool and, responsive to the identification of one or more anomalistic universal targets in the inspected region, performing one or more metrology processes on the one or more anomalistic universal metrology targets with the metrology tool. | 07-17-2014 |
| 20140242733 | REFLECTIVE MASK, METHOD OF MONITORING THE SAME, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, provided is a reflective mask having a substrate, a reflection layer that reflects EUV light formed above the substrate, and an absorption layer that absorbs the EUV light formed above the reflection layer. The reflective mask further includes a monitor pattern monitoring an attachment amount of contamination attached during exposure. | 08-28-2014 |
| 20140248720 | DEVICE FOR DETERMINING THE TEMPERATURE OF A SUBSTRATE - An apparatus for determining the temperature of a substrate, in particular of a semiconductor wafer during a heating thereof by means of a first radiation source is described. Furthermore, an apparatus and a method for thermally treating substrates are described, in which the substrate is heated by means of at least one first radiation source. The apparatus comprises a first grating structure having grating lines, which are opaque with respect to a substantial portion of the radiation of the first radiation source, wherein the grating structure is arranged between the first radiation source and the substrate, and a drive unit for moving the first grating structure. Furthermore, a first radiation detector is provided, which is directed directly onto the surface of the substrate facing the grating structure, and a device for determining radiation emitted by the substrate due to its own temperature and for determining the temperature of the substrate on the basis of the radiation detected by the first radiation detector. | 09-04-2014 |
| 20140256066 | Radiofrequency Adjustment for Instability Management in Semiconductor Processing - Methods, systems, and computer programs are presented for reducing chamber instability while processing a semiconductor substrate. One method includes an operation for identifying a first recipe with steps having an operating frequency equal to the nominal frequency of a radiofrequency (RF) power supply. Each step is analyzed with the nominal frequency, and the analysis determines if any step produces instability at the nominal frequency. The operating frequency is adjusted, for one or more of the steps, when the instability in the one or more steps exceeds a threshold. The adjustment acts to find an approximate minimum level of instability. A second recipe is constructed after the adjustment, such that at least one of the steps includes a respective operating frequency different from the nominal frequency. The second recipe is used to etch the one or more layers disposed over the substrate in the semiconductor processing chamber. | 09-11-2014 |
| 20140256067 | Structure and Method for E-Beam In-Chip Overlay Mark - The present disclosure provides an integrated circuit structure that includes a semiconductor substrate having a first region and a second region having an area less than about 10 micron×10 micron; a first material layer over the semiconductor substrate and patterned to have a first circuit feature in the first region and a first mark in the second region; and a second material layer over the first material layer and patterned to have a second circuit feature in the first region and a second mark in the second region. The first mark includes first mark features oriented in a first direction, and second mark features oriented in a second direction perpendicular to the first direction. The second mark includes third mark features oriented in the first direction, and fourth mark features oriented in the second direction. | 09-11-2014 |
| 20140273299 | SYSTEMS AND METHODS FOR FABRICATING SEMICONDUCTOR DEVICE STRUCTURES USING DIFFERENT METROLOGY TOOLS - Methods and systems are provided for fabricating and measuring physical features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves obtaining a first measurement of a first attribute of the semiconductor device structure from a first metrology tool, obtaining process information pertaining to fabrication of one or more features of the semiconductor device structure by a first processing tool, and determining an adjusted measurement for the first attribute based at least in part on the first measurement in a manner that is influenced by the process information. | 09-18-2014 |
| 20140273300 | Method for Forming ReRAM Chips Operating at Low Operating Temperatures - Forming a resistive memory structure at a temperature well above the operating temperature can reduce the forming voltage and create a defect distribution with higher stability and lower programming voltages. The forming temperature can be up to 200 C above the operating temperature. The memory chip can include an embedded heater in the chip package, allowing for a chip forming process after packaging. | 09-18-2014 |
| 20140273301 | MOVEABLE AND ADJUSTABLE GAS INJECTORS FOR AN ETCHING CHAMBER - An apparatus for increasing the uniformity in a critical dimension of chemical vapor deposition and etching during substrate processing, comprising a plurality of gas injectors for admitting a processing gas into an etching chamber. Each gas injector of the plurality of gas injectors is disposed along a track within the etching chamber and moveable along the track. Further, each gas injector is coupled with a throttling valve or nozzle to permit adjustment of processing gas flow rate. A method for increasing the uniformity in a critical dimension of chemical vapor deposition and etching during substrate processing includes performing a chemical deposition or etch using the plurality of moveable and adjustable gas injectors and measuring the critical dimension uniformity. Adjustments to the location of at least one gas injector or the processing gas flow rate to at least one gas injector are made to increase critical dimension uniformity. | 09-18-2014 |
| 20140273302 | Fine Temperature Controllable Wafer Heating System - Disclosed are a method and a system for processing wafers in fabricating a semiconductor device where disposing chemicals and wafer heating are needed for chemical reaction. A wafer is placed above a wafer heater such that a second surface faces the wafer heater, and heated from the second surface. A chemical layer is formed on an opposing first surface. The wafer heater is sized and configured to be capable of heating the entire second surface, and adapted to produce a locally differential temperature profile if needed. During heating, an actual temperature profile on the wafer may be monitored and transmitted to a computing system, which may generate a target temperature profile and control the wafer heater to adjust local temperatures on the wafer according to the target temperature profile. A supplemental heater for heating the chemicals may be used for finer control of the wafer temperature. | 09-18-2014 |
| 20140273303 | System and Method for an Etch Process with Silicon Concentration Control - The present disclosure provides one embodiment of an etch system. The etch system includes a tank designed to hold an etch solution for etching; a silicon monitor configured to measure silicon concentration of the etch solution; a drain module coupled to the tank and being operable to drain the etch solution; and a supply module being operable to fill in the tank with a fresh etch solution. | 09-18-2014 |
| 20140273304 | METHODS FOR REDUCING ETCH NONUNIFORMITY IN THE PRESENCE OF A WEAK MAGNETIC FIELD IN AN INDUCTIVELY COUPLED PLASMA REACTOR - Methods and apparatus for plasma-enhanced substrate processing are provided herein. In some embodiments, a method is provided for processing a substrate in a process chamber having a plurality of electromagnets disposed about the process chamber to form a magnetic field within the process chamber at least at a substrate level. In some embodiments, the method includes determining a first direction of an external magnetic field present within the process chamber while providing no current to the plurality of electromagnets; providing a range of currents to the plurality of electromagnets to create a magnetic field within the process chamber having a second direction opposing the first direction; determining a desired magnitude in the second direction of the magnetic field over the range of currents; and processing a substrate in the process chamber using a plasma while statically providing the magnetic field at the desired magnitude. | 09-18-2014 |
| 20140295582 | Controlling the Device Performance by Forming a Stressed Backside Dielectric Layer - A device includes a p-type metal-oxide-semiconductor (PMOS) device and an n-type metal-oxide-semiconductor (NMOS) device at a front surface of a semiconductor substrate. A first dielectric layer is disposed on a backside of the semiconductor substrate. The first dielectric layer applies a first stress of a first stress type to the semiconductor substrate, wherein the first dielectric layer is overlying the semiconductor substrate and overlapping a first one of the PMOS device and the NMOS device, and is not overlapping a second one of the PMOS device and the NMOS device. A second dielectric layer is disposed on the backside of the semiconductor substrate. The second dielectric layer applies a second stress to the semiconductor substrate, wherein the second stress is of a second stress type opposite to the first stress type. The second dielectric layer overlaps a second one of the PMOS device and the NMOS device. | 10-02-2014 |
| 20140302621 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - A semiconductor device manufacturing method is disclosed by which electron beam irradiation is accomplished at a low cost while exhibiting uniform characteristics. A wafer stack consisting of multiple stacked wafers is irradiated with an electron beam from both the front surface and reverse surface. As such, a semiconductor device manufacturing method is provided whereby the electrical characteristics are extremely uniform between wafers, and costs are reduced by reducing the number of electron beam irradiations. | 10-09-2014 |
| 20140315332 | System and Method for Increasing Productivity of Combinatorial Screening - The present invention provides systems and methods for simultaneous, parallel and/or rapid serial testing of material parameters or other parameters of the result of a process. The testing is typically used for screening different methods or materials to select those methods or materials with desired properties. A reactor structure used to form the materials may consist of an array of small isolated reaction chambers that overlie the substrate so that the substrate forms a bottom surface of each isolated reaction chamber. Test structures are formed on the substrate, where the location of each test structure corresponds to an isolated reaction chamber area of the reaction structure. Test structures are used to measure certain parameters, such as by probing contact pads for each test structure, or such testing may be performed in-situ during processing. | 10-23-2014 |
| 20140322832 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - According to example embodiments of inventive concepts, a method of fabricating a semiconductor device includes: forming a preliminary stack structure, the preliminary stack structure defining a through hole; forming a protection layer and a dielectric layer in the through hole; forming a channel pattern, a gapfill pattern, and a contact pattern in the through hole; forming an offset oxide on the preliminary stack structure; measuring thickness data of the offset oxide; and scanning the offset oxide using a reactive gas cluster ion beam. The scanning the offset oxide includes setting a scan speed based on the measured thickness data of the offset oxide, and forming a gas cluster. | 10-30-2014 |
| 20140322833 | IRRADIATION APPARATUS FOR IRRADIATING CHARGED PARTICLE BEAM, METHOD FOR IRRADIATION OF CHARGED PARTICLE BEAM, AND METHOD FOR MANUFACTURING ARTICLE - An apparatus includes an optical system configured to irradiate a substrate with a charged particle beam, a control unit configured to control an irradiation position of the charged particle beam, and a first measurement unit and a second measurement unit each configured to measure a surface position of the substrate. The first measurement unit and the second measurement unit have different characteristics in terms of charging. The control unit controls the irradiation position of the charged particle beam based on values measured by the first measurement unit and the second measurement unit. | 10-30-2014 |
| 20140329341 | BONDING METHOD, BONDING APPARATUS AND BONDING SYSTEM - A bonding method according to an exemplary embodiment of the present disclosure includes a first holding processing, a second holding processing, a temporary bonding processing, a temperature increasing processing and a main bonding processing. In the first holding processing, a target substrate is held. In the second holding processing, a glass substrate held by electrostatic adsorption. In the temporary bonding processing, the target substrate and the glass substrate are temporarily bonded with a pressing force lower than a predetermined pressing force at a temperature lower than a predetermined temperature. In the temperature increasing processing, while releasing the electrostatic adsorption of the glass substrate at the same time as or after the temporary bonding, the temperature is increased to the predetermined temperature. In the main bonding processing, a main bonding of the target substrate and the glass substrate is performed with the predetermined pressing force. | 11-06-2014 |
| 20140342473 | SEMICONDUCTOR PROCESSING METHOD - A method for detecting metal contamination from a film-forming process causing interface traps is described. The film-forming process is performed to form a dielectric film on a wafer. An annealing treatment is performed to reduce the interface traps between the wafer and the dielectric film. Thereafter, the bulk recombination lifetime (BRLT) of the wafer is measured to estimate the amount of the metal contamination. | 11-20-2014 |
| 20140342474 | TEMPERATURE DETECTING APPARATUS, SUBSTRATE PROCESSING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A temperature detecting apparatus is provided which is capable of suppressing disconnection of a thermocouple wire or positional deviation of a thermocouple junction portion caused by change over time. The temperature detecting apparatus includes: an insulation rod installed to extend in a vertical direction and including a through-hole in vertical direction; a thermocouple wire inserted in the through-hole of the insulation rod, the thermocouple wire including a thermocouple junction portion at an upper end thereof and an angled portion at a lower end of the insulation rod; and a buffer area installed below the insulation rod and configured to suppress a restriction of a horizontal portion of the angled portion upon heat expansion, wherein an upper portion of the thermocouple wire or a middle portion in the vertical direction are supported by the insulation rod. | 11-20-2014 |
| 20140363904 | METHOD FOR EVALUATING SILICON SINGLE CRYSTAL AND METHOD FOR MANUFACTURING SILICON SINGLE CRYSTAL - The present invention provides a method for evaluating silicon single crystal wherein an amount Δ[C] of carriers generated due to oxygen donors produced when a heat treatment is performed to the silicon single crystal is calculated and evaluated, the amount Δ[C] being calculated from oxygen concentration [Oi] in the silicon single crystal, a temperature T of the heat treatment, a time t of the heat treatment, and an oxygen diffusion coefficient D(T) at the temperature T by using the following relational expression: | 12-11-2014 |
| 20140370626 | METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DISPLAY DEVICE USING ORGANIC LAYER DEPOSITION APPARATUS - A method of manufacturing an organic light-emitting display device is provided. An alignment master member is loaded on a moving unit. An organic layer deposition assembly is pre-aligned to the alignment master member. After the pre-aligning of the organic layer deposition assembly, a substrate is loaded on the moving unit. The organic layer deposition assembly is aligned to the substrate positioned as is after the loading of the substrate. An organic layer is formed on the substrate while the moving unit is moving along the moving direction. While the moving unit is moving along the moving direction, the organic layer deposition assembly is adjusted so that an interval between the organic layer deposition assembly and part of the substrate is maintained as substantially constant. The part of the substrate receives a deposition material emitted from the organic layer deposition assembly to form the organic layer. | 12-18-2014 |
| 20140377888 | METHOD OF DETECTING AND MEASURING CONTACT ALIGNMENT SHIFT RELATIVE TO GATE STRUCTURES IN A SEMICONDCUTOR DEVICE - The present invention provides a method of detecting and measuring the alignment shift of the contacts relative to the gate structures. The method comprises: designing a test model array having different test model regions on the substrate; forming second conductivity type doped well regions, gate structures, and first conductivity type doped active regions in each of the test model regions; forming contacts in each of the test model region; scanning the test model array by an electron-beam inspector to obtain light-dark patterns of the contacts; and detecting and measuring the alignment shift of the contacts relative to the gate structures according to the light-dark patterns of the contacts and the critical dimensions of the transistors in the test model regions. | 12-25-2014 |
| 20140377889 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method which eliminates the possibility that when a film is processed several times, a thin photoresist film is made over a pattern used as an alignment mark, etc. and the pattern is exposed from the photoresist film and removed in a processing step, in order to improve the reliability of a semiconductor device. Patterns used as alignment marks, etc. are linear trenches as openings in a conductive film made over a semiconductor substrate, thereby preventing the photoresist film over the conductive film from flowing toward the openings in the conductive film. | 12-25-2014 |
| 20150011025 | ENHANCED SELENIUM SUPPLY IN COPPER INDIUM GALLIUM SELENIDE PROCESSES - A system for depositing selenium on a substrate comprises includes a substrate carrier including a body, means for holding the substrate, and a plurality of selenium vapor outlets formed in the body to direct a flux of selenium vapor onto the substrate. A selenium supply container provides selenium vapor to the selenium vapor outlets. At least one temperature sensor is coupled to the substrate carrier to sense temperature of the substrate. A heat source is positioned to heat the substrate. A controller is coupled to the temperature sensor and the heat source. | 01-08-2015 |
| 20150011026 | PROCESSING METHOD, PROCESSING APPARATUS, LITHOGRAPHY APPARATUS, AND METHOD OF MANUFACTURING ARTICLE - The present invention provides a processing method of processing a first signal obtained by detecting an alignment mark including a plurality of mark elements to obtain a position of the alignment mark, the method including steps of performing filtering to the first signal to generate a second signal, and obtaining the position of the alignment mark based on the second signal, wherein the filtering uses a plurality of filters by which a plurality of weights are respectively given to the plurality of mark elements, all of the plurality of weights being not the same for obtaining the position. | 01-08-2015 |
| 20150017747 | METHOD FOR FORMING A SOLAR CELL WITH A SELECTIVE EMITTER - A method for producing a solar cell with a selective emitter is disclosed. A semiconductor substrate ( | 01-15-2015 |
| 20150024518 | METHOD OF FORMING A SELECTIVELY ADJUSTABLE GATE STRUCTURE - The present disclosure relates to a method of forming a gate structure that can be selectively adjusted to reduce critical-dimension (CD) variations. In some embodiments, the method is performed by forming a gate structure having a first length over a semiconductor substrate. The first length of the gate structure is measured and compared to a target length. If the first length differs from the target length by an amount that is greater than a threshold value, the first length is adjusted to converge upon the target length. By selectively adjusting the length of the gate structure, critical-dimension (CD) variations can be reduced, thereby increasing yield and reducing cost. | 01-22-2015 |
| 20150024519 | METHOD FOR PRODUCING ORGANIC ELECTROLUMINESCENT ELEMENT - A method for producing an organic electroluminescent element including: a first producing process of stacking at least a first electrode layer, a dielectric layer, and a second electrode layer on a substrate in this order, the organic electroluminescent element having a light-emitting portion that is in contact with an inner surface of a concave portion formed to penetrate the dielectric layer; measuring a temperature distribution of the organic electroluminescent element while causing the light-emitting portion to emit light by applying a voltage to the first electrode layer and the second electrode layer of the organic electroluminescent element produced in the first producing process, and obtaining temperature irregularity information of the organic electroluminescent element; and a second producing process of adjusting concave portion density on the basis of the temperature irregularity information, and reducing temperature irregularity of the organic electroluminescent element. | 01-22-2015 |
| 20150024520 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND MANUFACTURING DEVICE - A marker which is a reference of a coordinate position defining a region of a chip that is manufactured in a semiconductor substrate is formed. A crystal defect on the semiconductor substrate is detected. The coordinate position of the detected crystal defect is detected on the basis of the marker. Therefore, it is possible to detect the position of a semiconductor chip including the crystal defect among the semiconductor chips manufactured on the semiconductor substrate. As a result, it is possible to easily detect the position of the semiconductor device including the position of the crystal defect on the semiconductor substrate. | 01-22-2015 |
| 20150031148 | Shadow Mask for Patterned Deposition on Substrates - A method for performing a physical vapor deposition (PVD) on a substrate is disclosed, comprising placing a substrate on a susceptor disposed below one or more PVD guns and below a plasma shield assembly having a bellows and a shadow mask coupled to a bottom side of the bellows, lowering the bellows toward the substrate to place the shadow mask in contact with the substrate; and depositing a material on an isolated region on the substrate through the shadow mask. In one implementation, the shadow mask may include a plate having openings in the shape of individual dies on the substrate, and a layer having openings in the shape of features patterned on the substrate, wherein the layer is coupled to a bottom surface of the plate by an epoxy. | 01-29-2015 |
| 20150037912 | METHOD FOR MANUFACTURING TRANSISTOR - A hydrogen barrier layer is selectively provided over an oxide semiconductor layer including hydrogen and hydrogen is selectively desorbed from a given region in the oxide semiconductor layer by conducting oxidation treatment, so that regions with different conductivities are formed in the oxide semiconductor layer. After that, a channel formation region, a source region, and a drain region can be formed with the use of the regions with different conductivities formed in the oxide semiconductor layer. | 02-05-2015 |
| 20150037913 | MILLIMETER WAVE WAFER LEVEL CHIP SCALE PACKAGING (WLCSP) DEVICE AND RELATED METHOD - Various embodiments include wafer level chip scale package (WLCSP) structures and methods of tuning such structures. In some embodiments, the WLCSP structure includes: a printed circuit board (PCB) trace connection including at least one PCB ground connection connected with a PCB ground plane; a set of ground solder balls each contacting the printed circuit board trace connection; a set of chip pads contacting each of the ground solder balls in the set of ground solder balls; a chip ground plane connecting the set of chip pads; and a signal interconnect interposed between two of the set of ground solder balls, the signal interconnect including: a signal trace connection electrically isolated from the PCB ground plane; a signal ball contacting the signal PCB trace connection; a chip pad contacting the signal ball, and a signal trace connection on a chip contacting the chip pad. | 02-05-2015 |
| 20150044786 | Alignment Systems and Wafer Bonding Systems and Methods - Alignment systems, and wafer bonding alignment systems and methods are disclosed. In some embodiments, an alignment system for a wafer bonding system includes means for monitoring an alignment of a first wafer and a second wafer, and means for adjusting a position of the second wafer. The alignment system includes means for feeding back a relative position of the first wafer and the second wafer to the means for adjusting the position of the second wafer before and during a bonding process for the first wafer and the second wafer. | 02-12-2015 |
| 20150050755 | METROLOGY MARKS FOR BIDIRECTIONAL GRATING SUPERPOSITION PATTERNING PROCESSES - Cut spacer reference marks, targets having such cut spacer reference marks, and methods of making the same by forming spacer gratings around grating lines on a first layer, and fabricating a template mask that extends across and perpendicular to such spacer gratings. Cut spacer gratings are etched into a second layer using the template mask to superimpose at least a portion of the spacer gratings of the first layer into the second layer. | 02-19-2015 |
| 20150056724 | INTEGRATED CIRCUIT LAYOUT AND METHOD WITH DOUBLE PATTERNING - The present disclosure provides one embodiment of a method for an integrated circuit (IC). The method includes forming a mandrel pattern on a substrate by a first lithography process; forming a first spacer pattern on sidewalls of the mandrel pattern; removing the mandrel pattern; forming a second spacer pattern on sidewalls of the first spacer pattern; removing the first spacer pattern; and etching the substrate using the second spacer pattern as an etch mask. | 02-26-2015 |
| 20150064812 | METHOD OF FORMING A SEMICONDUCTOR DEVICE EMPLOYING AN OPTICAL PLANARIZATION LAYER - A method for the manufacture of a semiconductor device is provided, including the steps of providing a semiconductor substrate including a first area separated from a second area by a first isolation region, wherein the second area includes an intermediate transistor comprising a gate electrode, forming an oxide layer over the first and second areas, forming an organic planarization layer (OPL) over the oxide layer, forming a mask layer over the OPL in the first area without covering the OPL in the second area, and etching the OPL with the mask layer being present to expose the oxide layer over the gate electrode of the transistor. | 03-05-2015 |
| 20150087085 | DEVICE FOR DETERMINING THE TEMPERATURE OF A SUBSTRATE - An apparatus and a method for determining the temperature of a substrate, in particular of a semiconductor substrate during the heating thereof by means of at least one first radiation source are disclosed. A determination of the temperature is based on detecting first and second radiations, each comprising radiation emitted by the substrate due to its own temperature and radiation emitted by the first radiation, which is reflected at the substrate and at least one of a drive power of the first radiation source and the radiation intensity of the first radiation source. | 03-26-2015 |
| 20150087086 | METHOD FOR PRODUCING IMAGE PICKUP APPARATUS, AND METHOD FOR PRODUCING SEMICONDUCTOR APPARATUS - A method for producing an image pickup apparatus includes: a process of fabricating a plurality of image pickup chips by cutting an image pickup chip substrate where light receiving sections and electrode pads are formed; a process of fabricating a joined wafer by bonding the image pickup chips to a glass wafer; a process of filling a gap between the plurality of image pickup chips with a sealing member; a process of machining the joined wafer to reduce a thickness; a process of forming through-hole vias; a process of forming an insulating layer that covers the image pickup chips; a process of forming through-hole interconnections; a process of forming external connection electrodes, each of which is connected to each of the through-hole interconnections; and a process of cutting the joined wafer. | 03-26-2015 |
| 20150104888 | SYSTEM FOR DETERMINING PRESENCE OF ABNORMALITY OF HEATER FOR SEMICONDUCTOR THIN FILM DEPOSITION APPARATUS - The present invention relates, in general, to an apparatus for determining the presence of abnormality of a heater for a semiconductor thin film deposition apparatus, such as an aluminum or ceramic heater and, more particularly, to a technique for monitoring a phenomenon occurring in an apparatus during a semiconductor thin film deposition process and a phenomenon occurring in a heater, thereby determining the presence of abnormality of the heater. The present invention also relates to a technique for measuring, in real time, a thickness of a thin film deposited by driving of a heater during a thin film deposition process in a chamber, thereby determining the presence of abnormality of a wafer and the presence of abnormality of the heater, based on the measurement result. | 04-16-2015 |
| 20150111316 | METHOD FOR DETECTING DEFECTS IN A DIFFUSION BARRIER LAYER - A method of providing a semiconductor structure comprising a diffusion barrier layer and a seed layer, the seed layer comprising an alloy of copper and a metal other than copper, depositing an electrically conductive material on the seed layer, performing an annealing process, wherein at least a first portion of the metal other than copper diffuses away from a vicinity of the diffusion barrier layer through the electrically conductive material, and wherein, in case of a defect in the diffusion barrier layer, a second portion of the metal other than copper indicative of the defect remains in a vicinity of the defect, measuring a distribution of the metal other than copper in at least a portion of the semiconductor structure, and determining, from the measured distribution of the metal other than copper, if the second portion of the metal other than copper is present. | 04-23-2015 |
| 20150125969 | INSPECTION METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - First, a product to be inspected is prepared. The product to be inspected includes a substrate and a first film formed on the substrate. TDS is performed while the temperature of the product to be inspected is raised to 1,000° C. or higher, and the quality of the product to be inspected is determined by checking for the presence or absence of a peak at 1,000° C. or higher. Meanwhile, the substrate is, for example, a semiconductor substrate such as a silicon substrate. In addition, the rate of temperature rise is, for example, equal to or higher than 40° C./min and equal to or lower than 80° C./min. The upper limit of the temperature of TDS is, for example, 1,300° C. | 05-07-2015 |
| 20150125970 | SYSTEMS AND METHODS OF AUTOMATICALLY DETECTING FAILURE PATTERNS FOR SEMICONDUCTOR WAFER FABRICATION PROCESSES - A system and method of automatically detecting failure patterns for a semiconductor wafer process is provided. The method includes receiving a test data set collected from testing a plurality of semiconductor wafers, forming a respective wafer map for each of the wafers, determining whether each respective wafer map comprises one or more respective objects, selecting the wafer maps that are determined to comprise one or more respective objects, selecting one or more object indices for selecting a respective object in each respective selected wafer map, determining a plurality of object index values in each respective selected wafer map, selecting an object in each respective selected wafer map, determining a respective feature in each of the respective selected wafer, classifying a respective pattern for each of the respective selected wafer maps and using the respective wafer fingerprints to adjust one or more parameters of the semiconductor fabrication process. | 05-07-2015 |
| 20150132866 | Silicon Wafer Coated With A Passivation Layer - Production of a silicon wafer coated with a passivation layer. The coated silicon wafer may be suitable for use in photovoltaic cells which convert energy from light impinging on the front face of the cell into electrical energy. | 05-14-2015 |
| 20150132867 | SEMICONDUCTOR PROCESS - The present disclosure relates to a semiconductor process, which includes: (a) providing a semiconductor element; (b) attaching the semiconductor element to a carrier by an adhesive layer, so that the adhesive layer is sandwiched between the semiconductor element and the carrier; and (c) cutting the semiconductor element to form a plurality of semiconductor units. Thereby, the gaps between the semiconductor units are fixed after the cutting process, so as to facilitate testing the semiconductor units. | 05-14-2015 |
| 20150140692 | ADVANCED PROCESS CONTROL METHOD FOR CONTROLLING WIDTH OF SPACER AND DUMMY SIDEWALL IN SEMICONDUCTOR DEVICE - An advanced process control (APC) method for controlling a width of a spacer in a semiconductor device includes: providing a semiconductor substrate; providing a target width of a gate; forming the gate on the semiconductor substrate, in which the gate has a measured width; depositing a dielectric layer covering the gate, in which the dielectric layer has a measured thickness; providing a target width of the spacer; determining a trim time of the dielectric layer based on the target width of the gate, the measured width of the gate, the target width of the spacer, and the measured thickness of the dielectric layer; and performing a trimming process on the dielectric layer for the determined trim time to form the spacer. | 05-21-2015 |
| 20150140693 | MISALIGNMENT/ALIGNMENT COMPENSATION METHOD, SEMICONDUCTOR LITHOGRAPHY SYSTEM, AND METHOD OF SEMICONDUCTOR PATTERNING - A misalignment/alignment compensation method for a lithography process includes the steps of: obtaining misalignment data associated with an alignment mark disposed on a substrate; and obtaining a compensation parameter by performing asymmetry compensation calculation on at least one of a first directional component of the misalignment data, which is associated with a first direction, and a second directional component of the misalignment data, which is associated with a second direction. | 05-21-2015 |
| 20150140694 | GAS SUPPLY DEVICE, FILM FORMING APPARATUS, GAS SUPPLY METHOD, AND STORAGE MEDIUM - A gas supply device for intermittently supplying raw material gas into a film forming process unit that includes a raw material container for accommodating a raw material, a carrier gas supply unit for supplying carrier gas to evaporate the raw material, a raw material gas supply path for supplying the raw material gas and the carrier gas into the film forming process unit, a flow rate detector, a flow rate regulating valve, a raw material supply and block unit for supplying and blocking the raw material gas into the film forming process unit, and a control unit for outputting a control signal for intermittently supplying the raw material gas into the film forming process unit. | 05-21-2015 |
| 20150140695 | METHOD AND SYSTEM FOR DETERMINING OVERLAP PROCESS WINDOWS IN SEMICONDUCTORS BY INSPECTION TECHNIQUES - The formation of overlap areas in sophisticated semiconductor devices is a critical aspect which may not be efficiently evaluated on the basis of conventional measurement and design strategies. For this reason, the present disclosure provides measurement techniques and systems in which overlying device patterns are transformed into the same material layer, thereby forming a combined pattern which is accessible by well-established defect inspection techniques. Upon geometrically modulating some of these combined patterns, a systematic evaluation of overlap process windows may be accomplished. | 05-21-2015 |
| 20150294916 | METHOD OF DETECTING AN ASYMMETRIC PORTION OF AN OVERLAY MARK AND METHOD OF MEASURING AN OVERLAY INCLUDING THE SAME - A method of detecting an asymmetric portion of an overlay mark includes forming a plurality of virtual overlay marks having a plurality of virtual asymmetric portions. The virtual asymmetric portions may have different sizes with respect to a reference model profile of a reference overlay mark. Virtual information with respect to each virtual overlay mark may be obtained. The virtual information of the virtual overlay marks may be compared with actual information of an actual overlay mark to identify virtual information of the virtual overlay mark corresponding to the actual information of the actual overlay mark. Thus, measuring the overlay of the actual overlay mark may be performed under than the actual asymmetric portion may be excluded from the actual overlay mark, so that the overlay may be accurately measured. As a result, errors may not be generated in a correcting process to a layer using the accurate overlay | 10-15-2015 |
| 20150303119 | METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A silicon carbide substrate having a main surface angled off in an off direction relative to a {0001} plane is prepared. A protruding first alignment mark is formed on the main surface of the silicon carbide substrate. A second alignment mark is formed on the first alignment mark by forming a silicon carbide epitaxial layer on the first alignment mark. The first alignment mark includes a first region and a second region, the second region being in contact with the first region and extending from the first region in the off direction. The second alignment mark includes a first portion formed on the first region and a second portion formed on the second region. An alignment step includes the step of capturing an image of the first portion while not including the second portion, and recognizing an edge of the first portion based on the image. | 10-22-2015 |
| 20150325502 | SEMICONDUCTOR DEVICE WITH STEP PORTION HAVING SHEAR SURFACES - A semiconductor device includes a source electrode pad formed to a front surface of a semiconductor chip and a metal clip (metal plate) to which a lead is electrically connected. The metal clip includes a chip-connecting portion electrically connected to the source electrode pad via a conductive bonding material, a lead-connecting portion electrically connected to the lead via a conductive bonding material, and an intermediate portion positioned between the chip-connecting portion and the lead-connecting portion. Further, between the intermediate portion and the chip-connecting portion, a step portion, which has shear surfaces disposed to face each other, is provided interposing a joining portion. | 11-12-2015 |
| 20150338276 | CALIBRATION CURVE FORMATION METHOD, IMPURITY CONCENTRATION MEASUREMENT METHOD, AND SEMICONDUCTOR WAFER MANUFACTURING METHOD - According to an embodiment, a method of forming a calibration curve is provided. The method includes ion-implanting different doses of an impurity into a plurality of first samples, measuring an intensity of photoluminescence deriving from the impurity by a photoluminescence spectroscopy for the first samples and a second sample made of the same semiconductor. Based on the amount of implanted impurity, the intensity of the photoluminescence, and a concentration of the impurity contained in the second sample measured by a method other than the photoluminescence spectroscopy, a calibration curve is formed. | 11-26-2015 |
| 20150340242 | COMPOSITE SUBSTRATE OF GALLIUM NITRIDE AND METAL OXIDE - The present invention discloses a novel composite substrate which solves the problem associated with the quality of substrate surface. The composite substrate has at least two layers comprising the first layer composed of Ga | 11-26-2015 |
| 20150340270 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE - Provided is a semiconductor device that suppresses the occurrence of defects due to photocorrosion. A method for manufacturing the semiconductor device includes the steps of: forming an insulating layer with a concave portion over a substrate; forming a conductive film over the insulating film and the inside of the concave portion; polishing and removing the conductive film positioned over the insulating layer; and cleaning the insulating layer in a light-shielded state. Between the step of polishing and the step of cleaning, or after the step of cleaning, the substrate SUB is moved by detecting the presence or absence of the substrate SUB in the light-shielded state using an infrared sensor. | 11-26-2015 |
| 20150345022 | Apparatus And Methods For Injector To Substrate Gap Control - Described are apparatus and methods for processing a semiconductor wafer in which the gap between the wafer surface and the gas distribution assembly remains uniform and of known thickness. The wafer is positioned within a susceptor assembly and the assembly is lifted toward the gas distribution assembly using actuators. The wafer can be lifted toward the gas distribution assembly by creating a fluid bearing below and/or above the wafer. | 12-03-2015 |
| 20150352686 | CHEMICAL MECHANICAL POLISHING (CMP) PLATFORM FOR LOCAL PROFILE CONTROL - A localized chemical mechanical polishing (CMP) platform is provided. A table is configured to support a workpiece with a to-be-polished surface. A polishing pad is spaced from the table with a width less than about half that of the table. The polishing pad is configured to individually polish rough regions of hillocks or valleys on the to-be-polished surface. A slurry distribution system is configured to apply slurry to an interface between the polishing pad and the workpiece. A cleaning system is configured to clean the workpiece in situ on the table. A drying system is configured to dry the workpiece in situ on the table. A method for CMP with local profile control and a system with local profile control are also provided. | 12-10-2015 |
| 20150357249 | SUBSTRATE ETCHING APPARATUS AND SUBSTRATE ANALYSIS METHOD - The present invention provides an etching apparatus suitable for etching polysilicon on a substrate or bulk silicon constituting the substrate. The present invention relates to an etching apparatus including a gas-flow adjusting means that allows etching gas to flow from a periphery of a substrate to substantially a center of the substrate, and relates to a technology capable of etching polysilicon or bulk silicon at a uniform thickness on an entire substrate surface. In addition, the gas-flow adjusting means is installed in a vertically movable manner, and an etching speed can be controlled by an adjustment of the gas-flow adjusting means. | 12-10-2015 |
| 20150380245 | POLYSILICON MANUFACTURING METHOD THAT ENHANCES HOMOGENEITY OF POLYSILICON LAYER - The present invention provides a polysilicon manufacturing method that enhances homogeneity of a polysilicon layer, including (1) forming a amorphous silicon layer ( | 12-31-2015 |
| 20160005662 | LOCALIZED STRESS MODULATION FOR OVERLAY AND EPE - Embodiments of the disclosure provide apparatus and methods for localized stress modulation for overlay and edge placement error (EPE) using electron or ion implantation. In one embodiment, a process for correcting overlay error on a substrate generally includes performing a measurement process in a metrology tool on a substrate to obtain a substrate distortion or an overlay error map, determining doping parameters to correct overlay error or substrate distortion based on the overlay error map, and providing a doping recipe to a doping apparatus based on the doping parameters determined to correct substrate distortion or overlay error. Embodiments may also provide performing a doping treatment process on the substrate using the determined doping repair recipe, for example, by comparing the overlay error map or substrate distortion with a database library stored in a computing system. | 01-07-2016 |
| 20160005915 | METHOD AND APPARATUS FOR INHIBITING LIGHT-INDUCED DEGRADATION OF PHOTOVOLTAIC DEVICE - A method for inhibiting light-induced degradation of a photovoltaic device includes steps of: a) subjecting the photovoltaic device to an illumination treatment using a light having a wavelength not less than 300 nm to heat the photovoltaic device in the absence of ambient light; and b) maintaining the temperature of the photovoltaic device above an annealing temperature of the photovoltaic device for at least 0.5 minute. An apparatus for inhibiting light-induced degradation of a photovoltaic device is also disclosed. | 01-07-2016 |
| 20160020149 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Provided are a semiconductor device and a method for fabricating the same. The semiconductor device includes a substrate including a circuit region and a scribe lane region, an active fin protruding from the substrate in the circuit region, a first gate structure extending over the active fin in the circuit region, and a second gate structure formed in the scribe lane region. | 01-21-2016 |
| 20160020156 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - The trench has, in a cross-sectional view, a first corner portion which is an intersection between a first sidewall surface and a bottom portion and a second corner portion which is an intersection between a second sidewall surface and the bottom portion. A first layer has a second-conductivity-type region. In a cross-sectional view, the second-conductivity-type region is arranged to intersect with a line which passes through any of the first corner portion and the second corner portion and is in parallel to a <0001> direction of a silicon carbide crystal forming the silicon carbide layer. A ratio calculated by dividing SP by ST is not lower than 20% and not higher than 130%, where ST represents a total area of the trenches in a boundary surface between the first layer and a second layer and SP represents a total area of the second-conductivity-type regions in a plan view. | 01-21-2016 |
| 20160027649 | ADVANCED PROCESS CONTROL METHOD FOR CONTROLLING WIDTH OF SPACER AND DUMMY SIDEWALL IN SEMICONDUCTOR DEVICE - An advanced process control (APC) method for controlling a width of a spacer in a semiconductor device includes: providing a semiconductor substrate; providing a target width of a gate; forming the gate on the semiconductor substrate, in which the gate has a measured width; depositing a dielectric layer covering the gate, in which the dielectric layer has a measured thickness; providing a target width of the spacer; determining a trim time of the dielectric layer based on the target width of the gate, the measured width of the gate, the target width of the spacer, and the measured thickness of the dielectric layer; and performing a trimming process on the dielectric layer for the determined trim time to form the spacer. | 01-28-2016 |
| 20160027696 | WAFER PROCESSING METHOD - A wafer has a substrate, a functional layer and division lines. The wafer is held on a chuck table with a protective member attached to the front side of the functional layer in contact with the chuck table. The height of the back side of the wafer is detected in a Z direction along each division line while moving the chuck table in an X direction. An X coordinate is recorded for each division line, as well as a corresponding Z coordinate. A cutting blade is positioned on the back side of the wafer and moved in the Z direction according to the recorded X and Z coordinates while moving the chuck table in the X direction to thereby form a cut groove having a depth not reaching the functional layer, with a part of the substrate left between the bottom of the cut groove and the functional layer. | 01-28-2016 |
| 20160027739 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING ALIGNMENT MARKS TO ALIGN LAYERS - A method of manufacturing a semiconductor device includes forming a first alignment mark trench in a first material layer on a substrate. A first alignment mark via may then be formed by etching a second material layer that is underneath the first material layer, where the first alignment mark via is positioned to communicate with the first alignment mark trench. Then, a trench-via-merged-type first alignment mark may be formed by filling the first alignment mark trench and the first alignment mark via with a light reflection material layer. | 01-28-2016 |
| 20160041136 | FLUID STORAGE AND DISPENSING SYSTEM INCLUDING DYNAMIC FLUID MONITORING OF FLUID STORAGE AND DISPENSING VESSEL - A monitoring system for monitoring fluid in a fluid supply vessel during operation including dispensing of fluid from the fluid supply vessel. The monitoring system includes (i) one or more sensors for monitoring a characteristic of the fluid supply vessel or the fluid dispensed therefrom, (ii) a data acquisition module operatively coupled to the one or more sensors to receive monitoring data therefrom and responsively generate an output correlative to the characteristic monitored by the one or more sensors, and (iii) a processor and display operatively coupled with the data acquisition module and arranged to process the output from the data acquisition module and responsively output a graphical representation of fluid in the fluid supply vessel, billing documents, usage reports, and/or resupply requests. | 02-11-2016 |
| 20160055288 | METHOD OF DETECTING FOCUS SHIFT IN LITHOGRAPHY PROCESS, METHOD OF ANALYZING ERROR OF TRANSFERRED PATTERN USING THE SAME AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE METHODS - A method of detecting focus shift in a lithography process, a method of analyzing an error of a transferred pattern using the same, and a method of manufacturing a semiconductor device using the methods are provided. The focus shift detecting method of a lithography process comprises generating a first contour band of a mask pattern between a first focus and a second focus, generating a second contour of the mask pattern between the first focus and a third focus, and determining whether focus shift of the mask pattern occurs using an intersection of the first contour band and the second contour band. | 02-25-2016 |
| 20160064262 | SEMICONDUCTOR MANUFACTURING APPARATUS, SEMICONDUCTOR MANUFACTURING SYSTEM, AND SEMICONDUCTOR MANUFACTURING METHOD - The semiconductor manufacturing apparatus includes a film forming part and a control part. The film forming part forms a stacked film on a semiconductor substrate. The stacked film has a lower layer and an upper layer on the lower layer. The control part controls the film forming part. The control part controls the film forming part to form the upper layer film in which an inclination of a film thickness is inverted with respect to that of the lower layer film. | 03-03-2016 |
| 20160079179 | MARK FORMING METHOD, MARK DETECTING METHOD, AND DEVICE MANUFACTURING METHOD - A mark forming method includes: exposing a wafer with a mask image to form first and second resist marks that have different shapes than one another based on a portion of the mask image; applying a polymer layer that contains a block copolymer to the wafer by spin-coating; forming self-assembled regions in the applied polymer layer; selectively removing a portion of the self-assembled regions; and forming first and second wafer marks on the wafer using the first and second resist marks. This makes it possible to form the marks when forming circuit patterns using self-assembly of a block copolymer. | 03-17-2016 |
| 20160107887 | METHODOLOGY AND SYSTEM FOR WAFER-LEVEL TESTING OF MEMS PRESSURE SENSORS - A method for testing a plurality of pressure sensors on a device wafer includes placing a diaphragm of one of the pressure sensors on the device wafer in proximity to a nozzle of a test system. A pneumatic pressure stimulus is applied to the diaphragm via an outlet of the nozzle and a cavity pressure is measured within a cavity associated with the pressure sensor in response to application of the pneumatic pressure stimulus. The pneumatic pressure stimulus within the cavity corresponds to the pressure applied to the diaphragm. Methodology is executed to test the strength and/or stiffness of the diaphragm. Additionally, the methodology and test system can be utilized to determine an individual calibration factor for each pressure sensor on the device wafer. | 04-21-2016 |
| 20160111282 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - It is an object to provide an oxide semiconductor which is suitable for use in a semiconductor device. Alternatively, it is another object to provide a semiconductor device using the oxide semiconductor. Provided is a semiconductor device including an In—Ga—Zn—O based oxide semiconductor layer in a channel formation region of a transistor. In the semiconductor device, the In—Ga—Zn—O based oxide semiconductor layer has a structure in which crystal grains represented by InGaO | 04-21-2016 |
| 20160111296 | SUBSTRATE PROCESSING APPARATUS, LINKED PROCESSING SYSTEM, AND SUBSTRATE PROCESSING METHOD - A substrate processing apparatus comprises: a substrate holding unit configured to hold and rotate a substrate; an etching unit configured to etch a surface of a substrate by discharging a processing liquid to the substrate rotated by the substrate holding unit; and a control unit configured to control an etching amount by the etching unit. In the substrate processing apparatus, the control unit controls an etching amount at each position on the surface of the substrate based on information upon a characteristic of a surface processing to be performed on the substrate by a post-processing apparatus which is configured to perform a post-processing after a substrate processing by the substrate processing apparatus. | 04-21-2016 |
| 20160118294 | METHOD OF PRODUCING BONDED WAFER - Method of producing bonded wafer including thin film on base wafer, including: implanting at least one gas ion selected from hydrogen ion and rare gas ion into bond wafer from surface of bond wafer to form layer of implanted ion; bonding surface from which ion is implanted into bond wafer and surface of base wafer directly or through insulator film; and then performing heat treatment to separate part of bond wafer along layer of implanted ion, wherein before bond wafer and base wafer are bonded, thickness of bond wafer and base wafer is measured, and combination of bond wafer and base wafer is selected such that difference in thickness between the wafers is less than 5 μm, and selected bond and base wafers are bonded. This method can inhibit variation in thickness in marble pattern that occurs in thin film and produce bonded wafer including thin film with uniform thickness. | 04-28-2016 |
| 20160126085 | METHOD AND DEVICE FOR TREATING A SUBSTRATE SURFACE - A method for treatment of a substrate surface of a substrate by applying a liquid to the substrate surface, the liquid which has been applied to the substrate surface being heated by a heating area which is located above the substrate surface, wherein the temperature of the liquid is kept constant by moving the heating area up and down. Furthermore the invention relates to a corresponding device. | 05-05-2016 |
| 20160148826 | DEVICE AND METHOD FOR ALIGNING SUBSTRATES - A method for alignment and contact-making of a first substrate with a second substrate using several detection units as well as a corresponding device. | 05-26-2016 |
| 20160178679 | CAPACITANCE MONITORING USING X-RAY DIFFRACTION | 06-23-2016 |
| 20160181120 | Laser annealing systems and methods with ultra-short dwell times | 06-23-2016 |
| 20160189972 | WAFER POLISHING APPARATUS AND METHOD - A wafer polishing apparatus capable of maintaining a drive ring in a flat state and a wafer polishing method are provided. | 06-30-2016 |
| 20160190024 | SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD AND RECORDING MEDIUM RECORDING SUBSTRATE PROCESSING PROGRAM - A substrate processing apparatus includes at least one process module configured to process first substrates. A position detector is configured to detect first positions of the first substrates. A control unit is configured to control the position detector so as to measure a second position of a second substrate selected from the first substrates to be processed in a same process module depending on a measurement interval set for the same process module. | 06-30-2016 |
| 20160190291 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A transistor with superior electric characteristics is manufactured. An oxide insulating film is formed over a substrate, an oxide semiconductor film is formed over the oxide insulating film, heat treatment is then conducted at a temperature at which hydrogen contained in the oxide semiconductor film is desorbed and part of oxygen contained in the oxide insulating film is desorbed, then the heated oxide semiconductor film is etched into a predetermined shape to form an island-shaped oxide semiconductor film, a pair of electrodes is formed over the island-shaped oxide semiconductor film, a gate insulating film is formed over the pair of electrodes and the island-shaped oxide semiconductor film, and a gate electrode is formed over the gate insulating film. | 06-30-2016 |
| 20160202620 | MEASUREMENT APPARATUS, LITHOGRAPHY APPARATUS, AND METHOD OF MANUFACTURING ARTICLE | 07-14-2016 |
| 20160204041 | METHOD OF INSPECTING SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE SAME | 07-14-2016 |
| 20180024536 | SUBSTRATE PROCESSING APPARATUS AND RECORDING MEDIUM | 01-25-2018 |
| 20180025929 | SYSTEMS AND METHODS FOR SENSING PROCESS PARAMETERS DURING SEMICONDUCTOR DEVICE FABRICATION | 01-25-2018 |
| 20180025953 | INSPECTING METHOD FOR INSPECTING INFLUENCE OF INSTALLATION ENVIRONMENT UPON PROCESSING APPARATUS | 01-25-2018 |
| 20190146347 | MASKLESS EXPOSURE METHOD, MASKLESS EXPOSURE APPARATUS AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME | 05-16-2019 |
| 20190148178 | GAS DELIVERY SYSTEM FOR HIGH PRESSURE PROCESSING CHAMBER | 05-16-2019 |
| 20190148246 | AUTOMATIC OPTIMIZATION OF MEASUREMENT ACCURACY THROUGH ADVANCED MACHINE LEARNING TECHNIQUES | 05-16-2019 |
