Entries |
Document | Title | Date |
20080199980 | METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - An object is to prevent a breakage of a membrane probe and a wafer to be tested in a probe testing using a membrane probe with styluses formed by a manufacturing technology for a semiconductor integrated circuit device. | 08-21-2008 |
20080206905 | TECHNIQUE FOR PATTERNING DIFFERENTLY STRESSED LAYERS FORMED ABOVE TRANSISTORS BY ENHANCED ETCH CONTROL STRATEGIES - During the patterning of stressed layers having different types of intrinsic stress, the effects of the deposition of a silicon dioxide based etch indicator material between the first and second dielectric layers may be significantly reduced by a controlled etch on the basis of optical measurement data indicating the etch rate and, thus, the performance of the respective etch process. In other cases, highly efficient etch indicator species may be incorporated into the stressed dielectric layers or may be formed on a surface portion thereof with reduced layer thickness, thereby providing an enhanced endpoint detection signal without creating the negative effects of silicon dioxide based indicator layers. In one illustrative embodiment, a stressed silicon, nitrogen and carbon-containing layer may be combined with a stressed silicon and nitrogen-containing layer, wherein the carbon species provides a prominent endpoint detection signal. | 08-28-2008 |
20080206906 | Method of manufacturing nitride semiconductor device including SiC substrate and apparatus for manufacturing nitride semiconductor device - Excitation light is irradiated onto a GaN layer on a silicon carbide substrate constituting a layered product that is set on a stage. Then light is emitted from a defective part caused by a structural defect of the silicon carbide substrate out of the GaN layer. By using this light luminescence phenomena, a position of a defective part of the silicon carbide substrate can be detected. | 08-28-2008 |
20080213926 | METHOD FOR EVALUATING A SEMICONDUCTOR SUBSTRATE - A method for evaluating a semiconductor substrate is provided that can evaluate even a thin semiconductor substrate or a substrate with untreated surfaces, can evaluate a large quantity of semiconductor substrates for solar cells in a short time and can be used as in-line inspection in a production process of solar cells or the like. The method for evaluating a semiconductor substrate comprises a step of immersing a semiconductor substrate in an etching solution filled in a container, a step of irradiating the substrate being immersed in the etching solution with light via the etching solution to cause the substrate to emit photoluminescence, and a step of observing the emitted photoluminescence. | 09-04-2008 |
20080220546 | METHOD FOR SIMULATING DEPOSITION FILM SHAPE AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE - A deposition film shape simulation method for calculating a thickness of a thin-film formed by supplying deposition species on a substrate surface, includes: changing a parameter to be used in the calculation depending on the thickness of the deposited thin-film. | 09-11-2008 |
20080227228 | Measurement of Overlay Offset in Semiconductor Processing - A method of semiconductor manufacturing including forming an overlay offset measurement target including a first feature on a first layer and a second feature on a second layer. The first feature and the second feature have a first predetermined overlay offset. The target is irradiated. The reflectivity of the irradiated target is determined. An overlay offset for the first layer and the second layer is calculated using the determined reflectivity. | 09-18-2008 |
20080233664 | Semiconductor integrated circuit production method and device - A semiconductor integrated circuit production method prepares an SOI layer thickness database that correlates measurement data of each SOI layer thickness with each SOI substrate identification data. The production method extracts the measurement data for each SOI substrate from the SOI layer thickness database, and carries out layer thickness adjustment surface treatment for the SOI substrates based on these data. A semiconductor integrated circuit production device includes an SOI layer thickness database storage unit for storing the SOI layer thickness database, and a layer thickness adjustment conditions control unit for extracting the measurement data for each SOI substrate from the SOI layer thickness database and deciding conditions for the layer thickness adjustment surface treatment based on these data. The semiconductor integrated circuit production device also includes a surface treatment unit that adjusts SOI layer thickness by carrying out the surface treatment on the SOI layers in accordance with the decided conditions. | 09-25-2008 |
20080241974 | Determining photoresist parameters using optical metrology - To generate a simulated diffraction signal, one or more values of one or more photoresist parameters, which characterize behavior of photoresist when the photoresist undergoes processing steps in a wafer application, are obtained. One or more values of one or more profile parameters are derived using the one or more values, of the one or more photoresist parameters. The one or more profile parameters characterize one or more geometric features of the structure. A simulated diffraction signal is generated using the one or more values of the one or more profile parameters. The simulated diffraction signal characterizes behavior of light diffracted from the structure. The generated simulated diffraction signal is associated with the one or more values of the one or more photoresist parameters. The generated simulated diffraction signal, the one or more values of the one or more photoresist parameters, and the association between the generated simulated diffraction signal and the one or more values of the one or more photoresist parameters are stored. | 10-02-2008 |
20080241975 | Automated process control using optical metrology and photoresist parameters - To control a photolithography cluster using optical metrology, a structure is fabricated on a wafer using the photolithography cluster. A measured diffraction signal off the structure is obtained. The measured diffraction signal is compared to a simulated diffraction signal. The simulated diffraction signal is associated with one or more values of one or more photoresist parameters. The one or more photoresist parameters characterize behavior of photoresist when the photoresist undergoes processing steps in the photolithography cluster. The simulated diffraction signal was generated using one or more values of one or more profile parameters. The one or more values of the one or more profile parameters used to generate the simulated diffraction signal were derived from the one or more values of the one or more photoresist parameters associated with the simulated diffraction signal. If the measured diffraction signal and the simulated diffraction signal match, then one or more values of one or more photoresist parameters used in the photolithography cluster are determined to be the one or more values of the one or more photoresist parameters associated with the matching simulated diffraction signal. One or more process parameters or equipment settings of the photolithography cluster are adjusted based on the one or more values of the one or more photoresist parameters. | 10-02-2008 |
20080268557 | METHOD FOR MEASURING A THIN FILM THICKNESS - A method for measuring a thin film thickness is provided. The method includes the following steps: providing a plurality of structures, each including a semiconductor substrate, a thin film, and a metal layer; measuring resistances of the metal layers of the plurality of structures and thicknesses of the thin films of the plurality of structures to obtain a plurality of resistance values and a plurality of corresponding thickness values; establishing a thickness-resistance table based on the plurality of resistance values and thickness values; providing a structure to be tested including a semiconductor substrate, a thin film, and a metal layer; and measuring resistance of the metal layer of the structure to be tested to determine a thickness value of the thin film of the structure to be tested according to the thickness-resistance table. | 10-30-2008 |
20080274568 | Reticle and method of fabricating semiconductor device - Dicing lines extending longitudinally and transversely, and chip areas surrounded by the dicing lines are formed in a resist mask. Critical-dimension patterns are formed in the dicing lines so as to be paired while placing the center line thereof in between. The dimensional measurement of the resist film having these patterns formed therein is made under a CD-SEM, by specifying a measurement-target chip area out of a plurality of chip areas, and by specifying a position of a critical-dimension pattern on the left thereof. Then, the distance of two linear portions configuring the critical-dimension pattern is measured, wherein a portion at a point of measurement on the measurement-target chip area side as viewed from the center line of the dicing line is measured. | 11-06-2008 |
20080274569 | Method for forming semiconductor ball grid array package - A method for forming a semiconductor package provides a ball grid array, BGA, formed on a package substrate. The apices of the solder balls of the BGA are all at the same height, even if the package substrate is non-planar. Different solder ball pad sizes are used and tailored to compensate for non-planarity of the package substrate that may result from thermal warpage. Larger size solder ball pads are formed at relatively-high locations on the package substrate. An equal amount of solder is formed on each of the solder ball pads to produce solder balls having different heights and coplanar apices. | 11-06-2008 |
20080280382 | Wafer-level test module for testing image sensor chips, the related test method and fabrication - A wafer-level test module is disclosed to include a base layer having multiple first apertures spaced from one another at a pitch corresponding to the pitch of the image sensor chips of an integrated circuit wafer, a cover layer having second apertures respectively axially aimed at the first apertures, and an optical layer sandwiched between the base layer and the cover layer having multiple optical lenses of which the optical axes pass through the first apertures and the second apertures, so that when one image capturing device of the image sensor chips of an integrated circuit wafer is adjusted to the image plane of one of the optical lenses and the wafer-level test module is set in alignment with the integrated circuit wafer horizontally and vertically, then the effective test light can be simultaneously projected onto the image capturing devices of the respective image sensor chips through the wafer-level test module to achieve an effective wafer-level test on multiple image sensor chips of the integrated circuit wafer accurately and rapidly. | 11-13-2008 |
20080293169 | LITHOGRAPHY EVALUATING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND PROGRAM MEDIUM - A lithography evaluating method comprises preparing a substrate, the substrate including a semiconductor substrate and a wiring structure including at least one wiring layer formed on the semiconductor substrate, partitioning the substrate into a plurality of regions to be evaluated, and obtaining a value of property relating to the wiring structure previously, and evaluating proximity effect on each of the plurality of regions to be evaluated based on the value of the property relating to the wiring structure. | 11-27-2008 |
20080293170 | METHOD FOR EVALUATING A GATE INSULATION FILM CHARACTERISTIC FOR USE IN A SEMICONDUCTOR DEVICE - A gate insulating film | 11-27-2008 |
20080299686 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device, includes; measuring a within-wafer distribution of a physical quantity; and etching the wafer so that the physical quantity get close to constant within the wafer. Alternatively, a method for manufacturing a semiconductor device, includes, measuring a within-wafer distribution of a physical quantity of at least one of a plurality of semiconductor layers provided in a wafer; determining a within-wafer distribution of etching amount for the at least one of the plurality of semiconductor layers based on the measured within-wafer distribution of the physical quantity; and etching the at least one of the plurality of semiconductor layers based on the determined within-wafer distribution of the etching amount so that the etching amount is locally varied within the wafer. | 12-04-2008 |
20080318350 | Apparatus for improving incoming and outgoing wafer inspection productivity in a wafer reclaim factory - An apparatus and method for inspecting wafers at a reclaim factory is described. Embodiments of the invention describe an apparatus in which a wafer ID and wafer thickness may be simultaneously measured. A wafer is placed onto a sloped surface and positioned by aligning a notch in the wafer with a pin located on the surface, and by propping the wafer against a pair of laterally opposite restraints. In one embodiment, a foot-switch is used to trigger the simultaneous wafer ID and wafer thickness measurements. | 12-25-2008 |
20080318351 | METHOD OF SETTING RECIPES OF A DEFECT TEST - In a method of setting recipes of a defect test, a laser intensity map of a sample is obtained. The laser intensity map is then area-scanned to obtain average laser intensity. Recipes are set based on the average laser intensity. Thus, a laser power set in a defect detector may be constant regardless of inspectors so that the defect detector may have improved defect detection reliability. | 12-25-2008 |
20090023230 | METHODS AND APPARATUS FOR DEPOSITING AN ANTI-REFLECTION COATING - Systems, methods, and apparatus are provided for depositing an anti-reflection film on a substrate. A substrate is transported to a metrology tool. A characteristic of the substrate is measured, via the metrology tool. A recipe for an anti-reflection film is determined, based on the measured characteristic. The substrate is transported from the metrology tool to a process chamber. The recipe is employed to form an anti-reflection film on the substrate within the process chamber. Numerous other aspects are provided. | 01-22-2009 |
20090023231 | Semiconductor Device Manufacturing Method and Method for Reducing Microroughness of Semiconductor Surface - Surface treatment is performed with a liquid, while shielding a semiconductor surface from light. When the method is employed for surface treatment in wet processes such as cleaning, etching and development of the semiconductor surface, increase of surface microroughness can be reduced. Thus, electrical characteristics and yield of the semiconductor device are improved. | 01-22-2009 |
20090035882 | METHOD AND APPARATUS FOR AFFECTING SURFACE COMPOSITION OF CIGS ABSORBERS FORMED BY TWO-STAGE PROCESS - A method and system to modify a surface composition of thin film Group IBIIIA VIA solar cell absorbers having non-uniformly distributed Group IIIA materials or graded materials, such as Indium (In), gallium (Ga) and aluminum (Al). The graded materials distribution varies between the surface and the bottom of the absorber layer such that a molar ratio of (Ga+Al)/(Ga+Al+In) is the highest at the bottom of the absorber layer and the lowest at the surface of the absorber. Within the bulk of the absorber, the molar ratio gradually changes between the bottom and the surface of the absorber. In one embodiment, the surface composition of a graded absorber layer may be modified by removing a top portion or slice of the absorber layer, where the molar ratio is low so as to expose the inner portions of the absorber layer having a higher molar ratio of graded materials. | 02-05-2009 |
20090061545 | Edge Removal Of Silicon-On-Insulator Transfer Wafer - A silicon-on-insulator transfer wafer having a front surface with a circumferential lip around a circular recess is polished. In one version, the circular recess on the front surface of the wafer is masked by filling the recess with spin-on-glass. The front surface of the wafer is exposed to an etchant to preferentially etch away the circumferential lip, while the circular recess is masked by the spin-on-glass. The spin-on glass is removed, and the front surface of the transfer wafer is polished. Other methods of removing the circumferential lip include applying a higher pressure to the circumferential lip in a polishing process, and directing a pressurized fluid jet at the base of the circumferential lip. | 03-05-2009 |
20090075407 | ELECTRONIC DEVICE AND METHOD FOR PRODUCING THE SAME - A microelectronic device and a method for producing the device can overcome the disadvantages of known electronic devices composed of carbon molecules, and can deliver performance superior to the known devices. An insulated-gate field-effect transistor includes a multi-walled carbon nanotube ( | 03-19-2009 |
20090098668 | Method and Apparatus to Facilitate Testing of Printed Semiconductor Devices - A printing platform receives ( | 04-16-2009 |
20090098669 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS - A semiconductor device manufacturing method and a semiconductor device manufacturing apparatus which enable to detect an etching end-point with high accuracy are provided. In etching of a lower layer formed on a semiconductor wafer using a mask which comprises a plurality of patterns extending in a predetermined direction (line-and-space patterns) and contains at least one of a metal layer and an electrically-conductive metal compound layer, the surface of the semiconductor wafer is irradiated with inspection light, the etching is performed while monitoring the intensity of the polarized light component perpendicular to the predetermined extending direction of the line-and-space patterns and the etching is terminated at the time the intensity of the polarized light component reaches a reflected light intensity corresponding to a desired remaining thickness of the lower layer. | 04-16-2009 |
20090124028 | Imaging device and method for a bonding apparatus - An imaging device and method of a bonding apparatus in which the imaging device includes: a high-magnification optical system having first and second high-magnification optical paths that extend to multiple imaging planes through a high-magnification lens and have different optical path lengths from the high-magnification lens to the respective imaging planes correspondingly to multiple subject imaging ranges which are at different distances from the high-magnification lens; and a low-magnification optical system having a low-magnification optical path that extends to an imaging plane through a low-magnification lens and having a field of view wider than those of the high-magnification optical paths. The imaging elements on the respective imaging planes in the high-magnification optical system are adapted to image semiconductor chips, while the imaging element on the imaging plane in the low-magnification optical system is adapted to image a lead frame. | 05-14-2009 |
20090170223 | METHODS FOR CALIBRATING A PROCESS FOR GROWING AN EPITAXIAL SILICON FILM AND METHODS FOR GROWING AN EPITAXIAL SILICON FILM - Methods are provided for calibrating a process for growing an epitaxial silicon-comprising film and for growing an epitaxial silicon-comprising film. One method comprises epitaxially growing a first silicon-comprising film on a first silicon substrate that has an adjacent non-crystalline-silicon structure that extends from said first silicon substrate. The step of epitaxially growing uses hydrochloric acid provided at a first hydrochloric acid flow rate for a first time period. A morphology of the first film relevant to the adjacent non-crystalline-silicon structure is analyzed and a thickness of the first film is measured. The first flow rate is adjusted to a second flow rate based on the morphology of the first film. The first time period is adjusted to a second time period based on the second flow rate and the thickness. A second silicon-comprising film on a second silicon substrate is epitaxially grown for the second time period using the second flow rate. | 07-02-2009 |
20090176321 | TEMPLATE FOR FORMING SOLDER BUMPS, METHOD OF MANUFACTURING THE TEMPLATE AND METHOD OF INSPECTING SOLDER BUMPS USING THE TEMPLATE - A template for forming solder bumps includes a transparent substrate on which a plurality of cavities is formed at an upper surface portion thereof, and a light-reflective layer and a protective layer formed on a lower surface of the transparent substrate. When a nozzle makes close contact with the template to inject a molten solder into the cavities, damage to the template may be prevented by the light-reflective layer and the protective layer, and thus the lifetime of the template may be increased. An inspection process on the solder bumps, which are formed in the cavities of the template, may be easily performed by analyzing light reflected by the light-reflective layer. | 07-09-2009 |
20090186427 | CHARACTERIZING FILMS USING OPTICAL FILTER PSEUDO SUBSTRATE - A system and method of characterizing a parameter of an ultra thin film, such as a gate oxide layer. A system is disclosed that includes a structure having a pseudo substrate positioned below an ultra thin film, wherein the pseudo substrate includes an optical mirror for enhancing an optical response; and a system for characterizing the ultra thin film by applying a light source to the ultra thin film and analyzing the optical response. | 07-23-2009 |
20090186428 | METHOD FOR CONSTRUCTING MODULE FOR OPTICAL CRITICAL DIMENSION (OCD) AND MEASUREING METHOD OF MODULE FOR OPTICAL CRITICAL DIMENSION USING THE MODULE - An optical critical dimension measuring method, applicable in measuring a pattern, that includes a plurality of polysilicon layers, of a device, is provided. The method includes obtaining a real curve corresponding to the to-be-measured device. Then, determining whether an ion implantation process has been performed on the polysilicon layers, a different module is selected. A correlation process is performed according to the selected module to generate a theoretical curve that correlates with the real curve to obtain a plurality of parameters corresponding to the theoretical curve. | 07-23-2009 |
20090186429 | Method for correcting a mask pattern, system for correcting a mask pattern, program, method for manufacturing a photomask and method for manufacturing a semiconductor device - A computer implemented method for correcting a mask pattern includes: predicting a displacement of a device pattern by using a mask pattern to form the device pattern and a variation of a process condition; determinating an optical proximity correction value so that the displacement falls within a displacement tolerance of the device pattern; and correcting the mask pattern using the optical proximity correction value. | 07-23-2009 |
20090191651 | POSITIONING APPARATUS, EXPOSURE APPARATUS, AND METHOD OF MANUFACTURING DEVICE - A positioning apparatus comprises a detector which detects the mark and outputs a mark signal and a controller. The controller includes a calculating unit which calculates position data of the mark based on the mark signal, a processing unit which calculates a parameter representing a displacement of the object, based on the mark signal and the position data of the mark, and a positioning controller which controls the positioning of the object, based on the position information of the object corrected by using the parameter calculated by said processing unit. The processing unit calculates a feature value, calculates a degree of influence that the feature value exerts on a displacement of the mark, corrects the calculated position data of the mark based on the calculated degree of influence, and statistically calculates the corrected position data of the mark, thereby calculating a parameter representing a displacement of the object. | 07-30-2009 |
20090197358 | Method for making COP evaluation on single-crystal silicon wafer - An evaluation area of an evaluation object wafer is concentrically divided in a radial direction, an upper limit value to the number of COPs is set in each divided evaluation segment, and an acceptance determination of the single-crystal silicon wafer is made using the upper limit value as a criterion. Thereby, a quantitative and objective COP evaluation can be made, and a proper determination is made based on a clear criterion. The evaluation method of the present invention can sufficiently deal with automation of the COP evaluation (inspection) and the higher-quality wafer in the near future, and the evaluation method can be widely applied to production of the single-crystal silicon wafer and production of a semiconductor device. | 08-06-2009 |
20090197359 | METHODS FOR EVALUATING AND MANUFACTURING SEMICONDUCTOR WAFER - A method for evaluating a shape change of a semiconductor wafer is provided. The method comprises acquiring unconstrained shape data of shape data of the semiconductor wafer being placed on a reference surface in a unconstrained state; acquiring constrained shape data of shape data of the semiconductor wafer being constrained along the reference surface in a constrained state; and comparing the unconstrained shape data and the constrained shape data. A method for manufacturing the semiconductor wafer utilizing a result of the evaluation of the wafer is also provided. | 08-06-2009 |
20090203156 | METHODS FOR ACCURATELY MEASURING THE THICKNESS OF AN EPITAXIAL LAYER ON A SILICON WAFER - Methods for measuring thickness of an epitaxial layer of a wafer. An example method applies photoresist over the epitaxial layer, and then portions of the photoresist within a sacrificial region of the wafer are removed. Next, the epitaxial layer is isotropically etched through the removed portions of the photoresist until a portion of the silicon handle layer is exposed. The remaining photoresist layer is removed. Then, the silicon handle layer is anisotropically etched to form a well. Profile information of the epitaxial layer and the etched handle layer generated. Next, the thickness of the epitaxial layer is determined based on the profile information. The acceptability of the epitaxial layer may be determined based on the determined thickness of the epitaxial layer. If the epi layer is acceptable, then the geometry of devices that are to be etched into the epitaxial layer are determined based on the determined thickness. | 08-13-2009 |
20090215205 | SHOWER HEAD STRUCTURE FOR PROCESSING SEMICONDUCTOR - A shower head structure disposed in a device | 08-27-2009 |
20090221105 | MANUFACTURING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In mass production of CMIS integrated circuit devices or the like, electric characteristics, such as Vth (threshold voltage) or the like, disadvantageously vary due to variations in gate length of the MISFET. This problem has become serious because of a short channel effect. In order to solve the problem, various kinds of feed-forward techniques have been studied in which a subsequent variation factor process is regulated to be reversed with respect to variations in a previous variation factor process so as to cause these variation factors to cancel each other out. Since the feed-back technique has an effect of the cancellation process over the entire system, the technique can be relatively easily applied to a product with a single type of MISFE, but is difficult to be applied to a product equipped with a plurality of types of MISFETs. The invention is adapted to adjust the amount of halo implantation by multivariate analysis based on the result of a patterning step of the gate electrode and a film forming step of an offset spacer. | 09-03-2009 |
20090233385 | Plasma Doping Method and Plasma Doping Apparatus - Before a plasma doping process is performed, there is generated a plasma of a gas containing an element belonging to the same group in the periodic table as the primary element of a silicon substrate | 09-17-2009 |
20090239315 | METHOD AND SYSTEM FOR PROCESSING TEST WAFER IN PHOTOLITHOGRAPHY PROCESS - A method and a system for processing a test wafer in a photolithography process are provided for processing an i | 09-24-2009 |
20090246893 | SEMICONDUCTOR INTEGRATED CIRCUIT MANUFACTURING PROCESS EVALUATION METHOD - A method for evaluating a process of manufacturing a semiconductor integrated circuit including a deposition step and a polishing step after the deposition step, the method includes: dividing the semiconductor integrated circuit into a plurality of areas; determining a deposition height after the deposition step for each of the areas; and determining a risk value for each of the areas on the basis of a difference in the deposition height between each of the areas and its adjacent areas. | 10-01-2009 |
20090246894 | Fabrication and Test Methods and Systems - Methods and systems for fabricating and testing semiconductor devices are disclosed. In one embodiment, a method of forming a material includes providing a first workpiece, forming a material on the first workpiece using a first process condition, and measuring a defect state of the material using a test that utilizes a monochromatic light source. If the defect state is below a predetermined value, the material is formed on at least one second workpiece using the first process condition. | 10-01-2009 |
20090258446 | PATTERN VERIFICATION METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND RECORDING MEDIA - A pattern verification method according to an embodiment includes, dividing a pattern data region or a pattern formation region formed based on the pattern data to a plurality of unit regions, calculating a pattern area ratio with respect to each unit region, calculating differences in the amount of the pattern area ratio between each unit region and adjacent unit regions thereto, setting the number or density of measurement point with respect to each unit region to the pattern of the pattern data region or the pattern formation region according to the difference in the amount of pattern area ratio, measuring the pattern size at each measurement point, and verifying whether the size measurement value is within a predetermined range or not. | 10-15-2009 |
20090269864 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE BY CONSIDERING THE EXTINCTION COEFFICIENT DURING ETCHING OF AN INTERLAYER INSULATING FILM - The present invention is directed to a method for manufacturing a semiconductor device by forming an ultraviolet radiation absorbing film of a silicon-rich film above a semiconductor substrate, measuring an extinction coefficient of the ultraviolet radiation absorbing film of a silicon-rich film for ultraviolet radiation, and etching the ultraviolet radiation absorbing film of a silicon-rich film under an etching condition using an oxygen gas flow rate corresponding to the extinction coefficient. | 10-29-2009 |
20090291511 | METHOD OF FORMING SEMICONDUCTOR THIN FILM AND SEMICONDUCTOR THIN FILM INSPECTION APPARATUS - A method of forming a semiconductor thin film includes the steps of: forming an amorphous semiconductor thin film on a substrate; forming a crystalline semiconductor thin film partially in each element region by applying laser light to the amorphous semiconductor thin film to selectively perform a heating process on the amorphous semiconductor thin film, thereby crystallizing the amorphous semiconductor thin film in a region irradiated with the laser light; and inspecting the crystallinity degree of the crystalline semiconductor thin film. The step of inspecting includes the steps of determining a contrast between the luminance of a crystallized region and the luminance of a non-crystallized region by applying light to the crystalline semiconductor thin film and the amorphous semiconductor thin film, and performing screening of the crystalline semiconductor thin film on the basis of the determined contrast. | 11-26-2009 |
20090291512 | SEMICONDUCTOR DEVICE PATTERN VERIFICATION METHOD, SEMICONDUCTOR DEVICE PATTERN VERIFICATION PROGRAM, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - Information on a transfer pattern created from a design pattern corresponding to a pattern to be formed on a substrate is acquired as pattern transfer information. The design pattern is compared with the transfer pattern and, on the basis of the feature quantity obtained from the comparison, the pattern transfer information and the design pattern are classified. A threshold value is set for the feature quantity and, on the basis of the threshold value, the pattern transfer information and the design pattern are further classified. Then, verification is conducted to see if the transfer pattern satisfies the threshold value. | 11-26-2009 |
20090291513 | OVERLAY MARKS, METHODS OF OVERLAY MARK DESIGN AND METHODS OF OVERLAY MEASUREMENTS - An overlay mark for determining the relative shift between two or more successive layers of a substrate and methods for using such overlay mark are disclosed. In one embodiment, the overlay mark includes at least one test pattern for determining the relative shift between a first and a second layer of the substrate in a first direction. The test pattern includes a first set of working zones and a second set of working zones. The first set of working zones are disposed on a first layer of the substrate and have at least two working zones diagonally opposed and spatially offset relative to one another. The second set of working zones are disposed on a second layer of the substrate and have at least two working zones diagonally opposed and spatially offset relative to one another. The first set of working zones are generally angled relative to the second set of working zones thus forming an “X” shaped test pattern. | 11-26-2009 |
20090298206 | METHOD AND APPARATUS TO MINIMIZE STRESS DURING REFLOW PROCESS - Utilizing an appropriately configured laser interferometer, the warpage of a silicon chip can be easily monitored during the solder reflow attachment process in an effort to determine the amount of stress encountered by the chip. Warpage measurements can then be continuously monitored throughout the process and related data can be stored to easily suggest the level of warpage generated by various processing parameters. By dynamically monitoring warpage in conjunction with processing parameters, a correlation can be established between the various parameters chosen, and resulting warpage. Based upon this correlation, the evaluators can easily identify those parameters which produce minimum stress, thus avoiding potential for breakage and damage during reflow operations. | 12-03-2009 |
20090298207 | METHOD FOR BONDING WAFERS - The invention relates to a method for bonding wafers along their corresponding surfaces. | 12-03-2009 |
20090298208 | METHOD OF FORMING SEMICONDUCTOR THIN FILM AND INSPECTION DEVICE OF SEMICONDUCTOR THIN FILM - A method of forming a semiconductor thin film includes: a step of forming an amorphous semiconductor thin film over a transparent substrate; a step of forming a crystalline semiconductor thin film by irradiating the amorphous semiconductor thin film with laser light to provide heat treatment and thereby crystallizing the amorphous semiconductor thin film; and an inspection step of inspecting the crystalline semiconductor thin film. The inspection step includes a step of obtaining a transmission image of the crystalline semiconductor thin film by irradiating the crystalline semiconductor thin film with light from a rear side of the transparent substrate and taking an image, and a screening step of performing screening of the crystalline semiconductor thin film based on the obtained transmission image. | 12-03-2009 |
20090305441 | NEXT GENERATION SCREEN PRINTING SYSTEM - Embodiments of the present invention provide an apparatus and method for processing substrates using a multiple screen printing chamber processing system that has an increased system throughput, improved system uptime, and improved device yield performance, while maintaining a repeatable and accurate screen printing process on the processed substrates. In one embodiment, the multiple screen printing chamber processing system is adapted to perform a screen printing process within a portion of a crystalline silicon solar cell production line in which a substrate is patterned with a desired material, and then processed in one or more subsequent processing chambers. | 12-10-2009 |
20090325326 | Apparatus and method for manufacturing semiconductor devices through layer material dimension analysis - Apparatus and method for manufacturing a semiconductor device through a layer material dimension analysis increase productivity. The method includes performing a semiconductor manufacturing process of at least one reference substrate and at least one target substrate in a semiconductor process device, detecting a reference spectrum and a reference profile for the reference substrate, determining a relation function between the detected reference spectrum and reference profile, detecting a real-time spectrum of the target substrate, and determining in real time a real-time profile of the target substrate processed in the semiconductor process device by using the detected real-time spectrum as a variable in the determined relation function. | 12-31-2009 |
20100009472 | Edge Exclusion Zone Patterning For Solar Cells And The Like - The edge profile (and optionally the physical and electrical characteristics) of a wafer is determined. Useful regions of the wafer in an edge exclusion zone may then be identified. A customized grid array layout is created specific to that wafer from an analysis of the edge profile, for example having a grid array with interconnection lines located within the useful portions of the edge exclusion zone. This working file is then used by a system, such as a digital lithography system, to form the grid array on the surface of the wafer. The grid array is specific to that wafer. Various aspects of the grid array may also be controlled in the process. For example, the line width, inter-line spacing, and position of the lines comprising the grid array are configurable on a wafer-by-wafer basis. | 01-14-2010 |
20100015735 | OBSERVATION METHOD OF WAFER ION IMPLANTATION DEFECT - An analysis method of wafer ion implant is presented, the steps of the method comprises: (a) cleave a wafer for analysis, and (b) from these pieces of wafers determine which ones are wafer with defect and set an insulator on the wafer with defect, (c) finally, use scanning electron microscope to observe whether the ion implant on the wafer with defect was correct or not. Whereby, engineers can take less time to analyze whether the ion implant of the wafer is correct or not with 100% repeatability. | 01-21-2010 |
20100015736 | METHOD OF FABRICATING A CHIP - A method of fabricating a chip may include the step of providing a first electrical part. The method may also include the step of forming a shell with the first electrical part embedded in a first side portion of the shell and a cavity in a second side portion of the shell. The method may include the step of testing the embedded first electrical part to determine whether the first electrical part is defective or functional. The method may also include the steps of providing a second electrical part, inserting the second electrical part within the cavity of the shell second side portion, establishing electrical communication between the first and second electrical parts if a test result of the first electrical part indicates that the first electrical part is functional, and finishing the chip. Also, the method may include the step of rejecting the first electrical part if the test result of the first electrical part indicates that the first electrical part is defective. | 01-21-2010 |
20100022036 | METHOD FOR FORMING PATTERN, AND TEMPLATE - According to an aspect of the present invention, there is provided a template including: a template substrate; patterns for forming device patterns on a wafer substrate; and a charging monitoring pattern, a size of the charging monitoring pattern being equal to a largest pattern in the patterns for forming the device patterns. | 01-28-2010 |
20100022037 | METHOD FOR FABRICATING CMOS IMAGE SENSOR - A method for fabricating a CMOS image sensor includes developing a semiconductor substrate provided with metal pads with tetramethylammonium hydroxide (TMAH), to etch the metal pads. In accordance with the method, it is possible to realize normal output of materials, which were previously scrapped due to problems including pad corrosion, appearance defects and bonding pad issues which may occur in the process of fabricating CMOS image sensors. As a result, advantageously, it is possible to reduce wafer scrap and improve product yield. | 01-28-2010 |
20100029024 | PLASMA PROCESSING METHOD - The invention provides a plasma processing method capable of reducing the damage applied to the low-k film or the underlayer. The method uses a plasma processing apparatus comprising gas supply means | 02-04-2010 |
20100035368 | Lead frame, method of manufacturing the same, and method of manufacturing semiconductor device - A lead frame is provided that includes a base metal, a plated layer provided on a part of the surface of the base metal, and a thermal history monitor portion that discolors under heat load applied thereto, provided at another part of the base metal surface. A method of manufacturing a semiconductor device includes an assembly process including mounting a semiconductor chip on the lead frame, performing a wire bonding process thereby connecting the semiconductor chip and the lead frame, and encapsulating with a resin the wire-bonded semiconductor chip and the lead frame, and then performing an appearance check after the assembly process to inspect whether the thermal history monitor portion has discolored under heat load applied through the assembly process, thereby deciding whether an abnormality has emerged through the thermal history. | 02-11-2010 |
20100035369 | METHOD FOR METAL GATE QUALITY CHARACTERIZATION - Measuring the amount of unreacted polysilicon gate material in a fully silicided (FUSI) nickel silicide gate process for metal oxide semiconductor (MOS) transistors in an integrated circuit (IC) to guide process development and monitor IC production requires a statistically significant sample size and an economical procedure. A method is disclosed which includes a novel deprocessing sequence of oxidizing the nickel followed by removing the nickel silicide by acid etching, acquiring an SEM image of a deprocessed area encompassing a multitude of gates, forming a quantifiable mask of the original gate area in the SEM image, forming a quantifiable image of the unreacted polysilicon area in the SEM image, and computing a fraction of unreacted polysilicon. | 02-11-2010 |
20100068832 | METHOD FOR THE PROTECTION OF INFORMATION IN MULTI-PROJECT WAFERS - A method for the protection of the information in a multi-project wafer (MPW) is provided. First, a substrate is provided. There are a first die and a second die on the substrate. Second, a first wafer process is performed on the substrate. The first wafer process includes performing a wafer procedure by using a non-destructive energy source and destroying the first die by using a destructive energy source. Later, a second wafer process is performed to finish the second die. | 03-18-2010 |
20100068833 | System of testing semiconductor devices, a method for testing semiconductor devices, and a method for manufacturing semiconductor devices - A system of testing semiconductor devices includes a classification module configured to classify a plurality of lots into a plurality of groups; an apparatus assignment module configured to assign a plurality of testing apparatuses to each of the groups; and a test recipe creation module configured to create a test recipe to test defects in a second group other than a first group specified in the groups, the test recipe including a definition of testing positions in the second group defined by a rule different from the first group. | 03-18-2010 |
20100068834 | DAMAGE EVALUATION METHOD OF COMPOUND SEMICONDUCTOR MEMBER, PRODUCTION METHOD OF COMPOUND SEMICONDUCTOR MEMBER, GALLIUM NITRIDE COMPOUND SEMICONDUCTOR MEMBER, AND GALLIUM NITRIDE COMPOUND SEMICONDUCTOR MEMBRANE - A method of evaluating damage of a compound semiconductor member, comprising: a step of performing spectroscopic ellipsometry measurement on a surface of the compound semiconductor member; and a step of evaluating damage on the surface of the compound semiconductor member, using a spectrum in a wavelength band containing a wavelength corresponding to a bandgap of the compound semiconductor member, in a spectrum of an optical constant obtained by the spectroscopic ellipsometry measurement. | 03-18-2010 |
20100075443 | TEMPLATE INSPECTION METHOD AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE - A template inspection method for performing defect inspection of a template, by bringing a pattern formation surface of a template used to form a pattern close to a first fluid coated on a flat substrate, filling the first fluid into a pattern of the template, and by performing optical observation of the template in a state that the first fluid is sandwiched between the template and the substrate, wherein a difference between an optical constant of the first fluid and an optical constant of the template is larger than a difference between an optical constant of air and the optical constant of the template. | 03-25-2010 |
20100087018 | METHOD FOR FORMING DUAL DAMASCENE STRUCTURE - A method for forming a dual damascene structure is disclosed. First a substrate is provided. There are an etching stop layer and an interlayer dielectric layer disposed on the substrate in order. The interlayer dielectric layer has a thickness A. Second, the interlayer dielectric layer is patterned to form a first opening. Later, a photo resist layer with a thickness B is formed on the interlayer dielectric layer. Then, the photo resist layer is patterned by a light source to construct a patterned photo resist layer. Later, the interlayer dielectric layer is again patterned by the patterned photo resist to pattern the interlayer dielectric layer to construct a second opening on the first opening by means of a light source and the photo resist layer so as to form a dual damascene structure. The light source has a periodic parameter C so that (A+B)/C≈X/2, where X is an odd number. | 04-08-2010 |
20100093116 | DIMENSION PROFILING OF SIC DEVICES - There is provided a method for dimension profiling of a semiconductor device. The method involves incorporating a feature comprising a detectable element into the device, and thereafter detecting the detectable element to determine a dimension of the feature. This information can be used for the determination of a dimension of buried channels, and also for end-point detection of CMP processes. | 04-15-2010 |
20100105155 | DIGITAL TRIMMING IN A MICROELECTRONIC DEVICE - Digital trimming logic is included in a microelectronic device of a type that produces an output signal in response to an input signal and a threshold signal. Trimming logic values are produced in response to a clock signal that is applied to the device in a trimming mode. The clock signal can be applied to a device pin that is used in normal operation to provide an output signal, thus allowing the pin to serve a dual function. The trimming logic changes the trimming logic value in response to the clock signal until the trimming logic value reaches a trim value at which the threshold signal is substantially equal to the input signal. The trimming logic then stores the trim value in a non-volatile memory and enters a locked mode in which further trimming is prevented and the device is ready for normal operation. | 04-29-2010 |
20100112732 | NOVEL PROCESS FOR CONTROLLING SHALLOW TRENCH ISOLATION STEP HEIGHT - A method for fabricating an integrated circuit with improved uniformity among the step heights of isolation regions is disclosed. The method comprises providing a substrate having one or more trenches; filling the one or more trenches; performing a chemical mechanical polishing on the one or more filled trenches, wherein each of the one or more filled trenches comprises a thickness; measuring the thickness of each of the one or more filled trenches; determining, based on the measured thickness of each of the one or more filled trenches, an amount of time to perform an etching process; and performing the etching process for the determined amount of time. | 05-06-2010 |
20100112733 | MEASURING DEVICE, EXPOSURE APPARATUS, AND DEVICE MANUFACTURING METHOD - A measuring device configured to measure a wave aberration of an optical system to be measured includes a reflection optical element for reflecting light, having passed through a mask and the optical system to be measured, into the optical system to be measured, and a detector for detecting an interference fringe of light having passed through pinholes and openings. The mask has at least three pinhole-opening pairs, each including one pinhole and one opening having a larger diameter than the pinhole that are arranged point-symmetrically, the three pinhole-opening pairs having the common center of symmetry. The light to be measured formed in two of the three pairs is made to interfere with the reference light formed in the remaining pair, or, the light to be measured formed in one of the three pairs is made to interfere with the reference light formed in the other two pairs. | 05-06-2010 |
20100120178 | Process Control Methods and Systems - A process control method includes setting first through fourth conditions, forming a first pattern by performing a first process on a semiconductor wafer, measuring the first pattern using a first measuring equipment to obtain a first result, comparing the first result with the first condition, forming a second pattern by performing a second process on the semiconductor wafer, comparing a period of the second process with the second condition, measuring the second pattern using a second measuring equipment to obtain a second result, comparing the second result with the third condition, forming a third pattern by performing a third process on the semiconductor wafer, measuring the third pattern using the a second measuring equipment to obtain a third result, and comparing the third result with the fourth condition. | 05-13-2010 |
20100129941 | PROCESSING METHOD FOR UNIFORMIZING FILM THICKNESS DISTRIBUTION OF LAYER HAVING PREDETERMINED FILM THICKNESS FORMED ON SURFACE OF SILICON WAFER AND PROCESSING METHOD FOR UNIFORMIZING THICKNESS DISTRIBUTION OF SILICON WAFER - In order to uniformize a film thickness distribution of a layer (e.g., an SOI layer) having predetermined film thickness formed on a surface of a silicon wafer, a processing method includes an oxidation step of forming a natural oxide film on a surface of the SOI layer and an etching step of removing, with etching liquid, the natural oxide film formed in a local thick film portion of the SOI layer while leaving a part (e.g., 1 Å to 2 Å) of the thickness. Since a main surface of the SOI layer is converted into the natural oxide film, the natural oxide film can be easily etched with hydrofluoric acid and etching processing can be locally performed. Therefore, the film thickness distribution of the SOI layer can be accurately uniformized by subjecting the thick film portion of the SOI layer to the etching processing. | 05-27-2010 |
20100129942 | NONDESTRUCTIVE TESTING METHOD FOR OXIDE SEMICONDUCTOR LAYER AND METHOD FOR MAKING OXIDE SEMICONDUCTOR LAYER - A nondestructive testing method for an oxide semiconductor layer includes the steps of applying excitation light to an amorphous or polycrystalline target oxide semiconductor layer to be tested and measuring an intensity of photoluminescence in a wavelength region longer than a wavelength corresponding to a bandgap energy among light emitted from the target oxide semiconductor layer; and estimating a film property of the target oxide semiconductor layer on the basis of measurement results. | 05-27-2010 |
20100136718 | METHODS AND APPARATUS FOR ALIGNING A SET OF PATTERNS ON A SILICON SUBSTRATE - A method of aligning a set of patterns on a substrate, the substrate including a substrate surface, is disclosed. The method includes depositing a set of silicon nanoparticles on the substrate surface, the set of nanoparticles including a set of ligand molecules including a set of carbon atoms, wherein a first set of regions is formed where the silicon nanoparticles are deposited and the remaining portions of the substrate surface define a second set of regions. The method also includes densifying the set of silicon nanoparticles into a thin film wherein a set of silicon-organic zones are formed on the substrate surface, wherein the first set of regions has a first reflectivity value and the second set of regions has a second reflectivity value. The method further includes illuminating the substrate surface with an illumination source, wherein the ratio of the second reflectivity value to the first reflectivity value is greater than about 1.1. | 06-03-2010 |
20100167431 | LASER PROCESSING APPARATUS - A laser processing apparatus which achieves both shorter TAT and reduction in processing defects. In the apparatus, a laser radiation section, an undulation measurement section for measuring undulation of a substrate or a film thickness measuring section for measuring the thickness of a thin film formed on the substrate, and an optical inspection section for optically inspecting grooves formed by laser-processing the thin film on the substrate are fixed so that their positional relationship is kept constant. | 07-01-2010 |
20100190274 | RTP SPIKE ANNEALING FOR SEMICONDUCTOR SUBSTRATE DOPANT ACTIVATION - A semiconductor substrate has a plurality of active device patterns. At least some of the active device patterns comprise doped regions. The substrate has a plurality of surface regions, including the active device patterns and un-patterned regions, with respectively different reflectances for light in a near infrared wavelength. A first difference is determined, between a largest reflectance at the near infrared wavelength and a smallest reflectance at the near infrared wavelength. A second infrared wavelength is determined, for which a second difference between a largest reflectances a smallest reflectance is substantially less than the first difference at the near infrared wavelength. A rapid thermal processing (RTP) spike annealing dopant activation step is performed on the substrate using a second light source providing light at the second wavelength. | 07-29-2010 |
20100190275 | SCRIBING DEVICE AND METHOD OF PRODUCING A THIN-FILM SOLAR CELL MODULE - A laser scribing device is provided which comprises at least a laser light source. The laser light source may generate a laser beam for scribing cell lines to form a patterned solar cell module. Furthermore, the laser may emit a light beam for generating a light spot on the surface of the solar cell module. The light beam may be modulated compared with the light beam used for the scribing process. By means of the light spot a particular region of the active area of the solar cell module may be illuminated, and the voltage V | 07-29-2010 |
20100190276 | METHOD AND APPARATUS FOR IRRADIATING LASER - A laser irradiation process includes: scanning a substrate with laser having a predetermined lasing frequency at different irradiation intensities to form a plurality of first irradiation areas corresponding to the irradiation intensities; illuminating the first irradiation areas to reflected light receive from the first irradiation areas; determining microcrystallization intensity based on the received reflected light; and determining irradiation intensity based on the thus determined microcrystallization intensity. The laser irradiation process uses the irradiation intensity for irradiating a polycrystalline film in a product semiconductor device. | 07-29-2010 |
20100197050 | METHOD OF FORMING SEMICONDUCTOR THIN FILM AND INSPECTION DEVICE OF SEMICONDUCTOR THIN FILM - A method of forming a semiconductor thin film includes the steps of: forming an amorphous semiconductor thin film on a substrate; partially forming a crystalline semiconductor thin film for each element region by irradiating laser light to the amorphous semiconductor thin film to selectively perform a heating treatment on the amorphous semiconductor thin film, and crystallizing an amorphous semiconductor thin film corresponding to an irradiation region; and inspecting crystallinity of the crystalline semiconductor thin film. The inspection step includes the steps of obtaining an optical step based on an optical phase difference between a crystallized region and an uncrystallized region by irradiating light to the crystalline semiconductor thin film and the amorphous semiconductor thin film, and evaluating one or both of sorting of the crystalline semiconductor thin film and control of crystallinity of the crystalline semiconductor thin film, based on the obtained optical step. | 08-05-2010 |
20100197051 | METROLOGY AND INSPECTION SUITE FOR A SOLAR PRODUCTION LINE - Embodiments of the present invention generally relate to a system used to form solar cell devices using processing modules adapted to perform one or more processes in the formation of the solar cell devices. In one embodiment, the system is adapted to form thin film solar cell devices by accepting a large unprocessed substrate and performing multiple deposition, material removal, cleaning, sectioning, bonding, and various inspection and testing processes to form multiple complete, functional, and tested solar cell devices that can then be shipped to an end user for installation in a desired location to generate electricity. In one embodiment, the system provides inspection of solar cell devices at various levels of formation, while collecting and using metrology data to diagnose, tune, or improve production line processes during the manufacture of solar cell devices. | 08-05-2010 |
20100216262 | METHOD FOR PRODUCING BONDED WAFER - Bonded wafers are produced by a method including a step (S | 08-26-2010 |
20100216263 | Method and Apparatus for Measuring Process Parameters of a Plasma Etch Process - Method and apparatus for measuring process parameters of a plasma etch process. A method for detecting at least one process parameter of a plasma etch process being performed on a semiconductor wafer. The method comprises the steps of detecting light being generated from the plasma during the etch process, filtering the detected light to extract modulated light; and processing the detected modulated light to determine at least one process parameter of the etch process. | 08-26-2010 |
20100233832 | Method of manufacturing silicon carbide seminconductor device - In a method of manufacturing a silicon carbide semiconductor device, a trench and a thickness measurement section are formed in a surface of a semiconductor substrate made of silicon carbide. The thickness measurement section includes a plurality of grooves and a protruding portion provided between the grooves so as to have a predetermined width. When an epitaxial layer made of silicon carbide is grown, a thickness of the epitaxial layer formed on the surface of the semiconductor substrate is measured by calculating a difference in height between a surface of the epitaxial layer formed on a portion of the surface of the semiconductor substrate different from the thickness measurement section and a top surface of the protruding portion. The predetermined width is less than a surface migration amount of atoms during growth of the epitaxial layer. | 09-16-2010 |
20100240155 | Auto Feedback Apparatus for Laser Marking - A method of manufacturing integrated circuits includes measuring a reflectivity value of a wafer. An optimum energy level for laser marking the wafer is determined using the reflectivity value. A laser beam having the optimum energy level is then emitted to make laser marks on the wafer. | 09-23-2010 |
20100261298 | CURVATURE REDUCTION FOR SEMICONDUCTOR WAFERS - A method for reducing curvature of a wafer having a semiconductor surface. One or more process steps are identified at which wafers exhibit the largest curvature, and/or wafer curvature that may reduce die yield. A crystal damaging process converts at least a portion of the semiconductor surface into at least one amorphous surface region After or contemporaneously with the crystal damaging, the amorphous surface region is recrystallized by recrystallization annealing that anneals the wafer for a time ≦5 seconds at a temperature sufficient for recrystallization of the amorphous surface region. A subsequent photolithography step is facilitated due to the reduction in average wafer curvature provided by the recrystallization. | 10-14-2010 |
20100267172 | Formation of Shallow Trench Isolation Using Chemical Vapor Etch - A method includes measuring a depth of a shallow trench isolation (STI) region below a surface of a substrate. The STI region is filled with an oxide material. The substrate has a nitride layer above the surface. A thickness of the nitride layer is measured. A first chemical vapor etch (CVE) of the oxide material is performed, to partially form a recess in the STI region. The first CVE removes an amount of the oxide material less than the thickness of the nitride layer. The nitride layer is removed by dry etching. A remaining height of the STI region is measured after removing the nitride. A second CVE of the oxide material in the STI region is performed, based on the measured depth and the remaining height, to form at least one fin having a desired fin height above the oxide in the STI region without an oxide fence. | 10-21-2010 |
20100267173 | Fiber Laser Substrate Processing - Embodiments of the present invention pertain to substrate processing equipment and methods incorporating light sources which provide independent control of light pulse duration, shape and repetition rate. Embodiments further provide rapid increases and decreases in intensity of illumination. | 10-21-2010 |
20100267174 | LED Substrate Processing - Embodiments of the present invention pertain to substrate processing equipment and methods incorporating light emitting diodes (LEDs) for thermally processing substrates. Such light sources offer a variety of advantages including higher efficiency and more rapid response times. Pulse widths are selectable down to under a millisecond but can be for long pulses up to and exceeding a second. LEDs are preferable to tungsten-halogen lamps even in circumstances that allow longer processing times, since LEDs produce light with greater than 50% efficiency and tungsten-halogen lamps operate with less than 5% efficiency. | 10-21-2010 |
20100273278 | BURN-IN METHOD FOR SURFACE EMITTING SEMICONDUCTOR LASER DEVICE - A burn-in method includes applying a stress current for applying thermal stress to a surface-emitting semiconductor laser, measuring an operation characteristic of the surface-emitting semiconductor laser to which the stress current is applied, and making a pass/fail decision on the surface-emitting semiconductor laser on the basis of the operation characteristic measured. | 10-28-2010 |
20100279440 | NITRIDE SEMICONDUCTOR WAFER AND METHOD OF PROCESSING NITRIDE SEMICONDUCTOR WAFER - Nitride semiconductor wafers which are produced by epitaxially grown nitride films on a foreign undersubstrate in vapor phase have strong inner stress due to misfit between the nitride and the undersubstrate material. A GaN wafer which has made by piling GaN films upon a GaAs undersubstrate in vapor phase and eliminating the GaAs undersubstrate bends upward due to the inner stress owing to the misfit of lattice constants between GaN and GaAs. Ordinary one-surface polishing having the steps of gluing a wafer with a surface on a flat disc, bringing another surface in contact with a lower turntable, pressing the disc, rotating the disc, revolving the turntable and whetting the lower surface, cannot remedy the inherent distortion. The Distortion worsens morphology of epitaxial wafers, lowers yield of via-mask exposure and invites cracks on surfaces. Nitride crystals are rigid but fragile. Chemical/mechanical polishing has been requested in vain. Current GaN wafers have roughened bottom surfaces, which induce contamination of particles and fluctuation of thickness. | 11-04-2010 |
20100279441 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE BY CONSIDERING THE EXTINCTION COEFFICIENT DURING ETCHING OF AN INTERLAYER INSULATING FILM - The present invention is directed to a method for manufacturing a semiconductor device by forming an ultraviolet radiation absorbing film of a silicon-rich film above a semiconductor substrate, measuring an extinction coefficient of the ultraviolet radiation absorbing film of a silicon-rich film for ultraviolet radiation, and etching the ultraviolet radiation absorbing film of a silicon-rich film under an etching condition using an oxygen gas flow rate corresponding to the extinction coefficient. | 11-04-2010 |
20100285615 | FABRICATION METHOD OF SEMICONDUCTOR DEVICE - A technique is provided which can exactly recognize a chip to be picked up when picking up the chip from a wafer sheet in a process of die bonding a thin chip. A camera is coupled to one end of a lens barrel, an objective lens is attached to an opposite end of the lens barrel, and an image of a main surface of a chip is photographed through the objective lens. A surface-emitting lighting unit, a diffusing plate and a half mirror are internally provided between the lens barrel and the chip. Further, another lens barrel having a coaxial drop lighting function of radiating light to the main surface of the chip along the same optical axis as that of the camera is disposed. | 11-11-2010 |
20100291714 | METHOD AND SYSTEM FOR THE IN-SITU DETERMINATION OF THE MATERIAL COMPOSITION OF OPTICALLY THIN LAYERS - A system and method for in situ determination of a material composition of optically thin layers deposited from a vapor phase onto a substrate includes irradiating the substrate with incoherent light of at least three different wavelengths, optically detecting in a spatially resolved manner a reflection intensity of a diffuse or a direct light scattering emanating from a deposited layer outside of a total reflection, concurrently providing numerical values of the detected reflection intensity to an optical layer model based on general line transmission theory, ascertaining values for the optical layer parameters of the deposited layer from the optical layer model for the at least three different wavelengths by numerically adapting the optical layer model to a time characteristic of the detected reflection intensities, and quantitatively determining a material composition of the deposited layer from the ascertained values by comparing the ascertained values to standard values. | 11-18-2010 |
20100297786 | Method for Manufacturing Compound Semiconductor and Apparatus for Manufacturing the Same - The present invention provides a method for manufacturing a compound semiconductor, which can improve a quality of each of thin film layers constituting a laminate structure. | 11-25-2010 |
20100297787 | SYSTEM AND METHOD FOR BACKSIDE CIRCUIT EDITING ON FULL THICKNESS SILICON DEVICE - A system for accessing circuitry on a flip chip circuit device with active circuitry and full-thickness bulk silicon includes a moveable surface for supporting and locating the circuit device in a plane, an infrared (IR) imaging device located at a defined perpendicular distance from a surface of the bulk silicon, the surface of the bulk silicon parallel to the plane and a milling chamber configured to direct an etchant and a focused ion beam to the surface of the bulk silicon, resulting in a gas-enhanced milling process that creates a milled cavity in the bulk silicon. The system produces an IR reflective material located at a base of the cavity, wherein the circuit device is located within a field of view of the IR imaging device such that the IR reflective material is brought into focus by moving the IR imaging device an adjustable distance perpendicular to the surface of the bulk silicon, and where the adjustable perpendicular distance is indicative of a depth of the cavity. | 11-25-2010 |
20100297788 | ARRANGEMENTS AND METHODS FOR IMPROVING BEVEL ETCH REPEATABILITY AMONG SUBSTRATES - A method, performed in connection with bevel etching of a substrate, for improving bevel-etch repeatability among substrates, is disclosed. The method includes providing an optical arrangement and ascertaining at least one bevel edge characteristic of a bevel edge of said substrate. The method also includes deriving at least one compensation factor from said at least one bevel edge characteristic, said at least one compensation factor pertaining to an adjustment in a bevel etch process parameter. The method further includes performing said bevel etching utilizing said at least one compensation factor. | 11-25-2010 |
20100297789 | METHOD FOR PRODUCING SEMICONDUCTOR OPTICAL DEVICE - A method for producing a semiconductor optical device, includes the steps of: (a) forming a semiconductor region on a substrate, the substrate including first and second areas; the first area including device sections (b) forming a first mask on the semiconductor region, the first mask including first patterns periodically arranged in the first area and a second pattern provided in the second area; (c) forming a plurality of periodic structures in each of the device sections and a monitoring structure in the second area by using the first mask, the periodic structures respectively corresponding to the first patterns, the monitoring structure corresponding to the second pattern; (d) measuring a shape of the monitoring structure; (e) selecting a desired periodic structure from the plurality of periodic structures on a basis of a result of measuring the shape of the monitoring structure; (f) forming a second mask including a pattern on the desired periodic structure; and (g) forming stripe mesas including the desired periodic structure by using the second mask. | 11-25-2010 |
20100297790 | METHOD FOR PRODUCING SEMICONDUCTOR DEVICES - The present invention provides a method for producing semiconductor devices by which the fraction defective upon division into chips is reduced and the yield is enhanced. | 11-25-2010 |
20100304507 | METHOD OF PRODUCING A STRUCTURE BY LAYER TRANSFER - The invention relates to a method of producing a semiconductor structure by transferring a layer of a donor substrate to a receiver substrate, with the creation of an embrittlement zone in the donor substrate to define the transfer layer, and the treatment of the surface of one of the substrates to increase the bonding strength between them, followed by the direct wafer bonding of the substrates and the detachment of the donor substrate at the embrittlement zone to form the semiconductor structure, in which the surface of the receiver substrate, except for a peripheral crown, is covered with the transferred layer. The treatment of the substrate surface is controlled so that the bonding strength between the substrates is lower in a peripheral area than in a central area. The peripheral area has a width at least equal to the that of the crown and less than 10 mm. | 12-02-2010 |
20100304508 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - The semiconductor device of the present invention includes a first insulating film on a substrate having a first region and a second region, a light shielding film formed in the first region and an interconnect film formed in the second region in the first insulating film and a second insulating film having a first concave portion above the light shielding film in the first region and an interconnect hole having a via hole and a second concave portion in the second region in the second insulating film on the first insulating film, wherein an area of the light shielding film is overlapping an area of the first plurality of concave portions. | 12-02-2010 |
20100317129 | COMPOSITION CONTROL FOR PHOTOVOLTAIC THIN FILM MANUFACTURING - The present invention relates to methods and apparatus for providing composition control to thin compound semiconductor films for radiation detector and photovoltaic applications. In one aspect of the invention, there is provided a method in which the molar ratio of the elements in a plurality of layers are detected so that tuning of the multi-element layer can occur to obtain the multi-element layer that has a predetermined molar ratio range. In another aspect of the invention, there is provided a method in which the thickness of a sub-layer and layers thereover of Cu, In and/or Ga are detected and tuned in order to provide tuned thicknesses that are substantially the same as pre-determined thicknesses. | 12-16-2010 |
20100323461 | Lithographic Method and Arrangement - A method is described for obtaining information for use in modeling of a lithographic process. A pattern feature is formed on a target portion of a substrate by projecting a beam of radiation onto the target portion of the substrate. For that target portion the lithographic process is characterized by one or both of a first property that varies in a first direction along a surface of the substrate, and a second property that varies in a second direction along a surface of the substrate. A property of the pattern feature is measured. Using the measured property of the pattern feature and at least one of the first and second properties, information is obtained for use in modeling the process. The lithographic process may be or include the projection of the beam of radiation onto the surface of the substrate. | 12-23-2010 |
20110003403 | TESTING METHOD OF SURFACE-EMITTING LASER DEVICE AND TESTING DEVICE THEREOF - A method of performing a wafer level burn-in test for a plurality of surface-emitting laser devices formed on a wafer includes causing a plurality of contact electrodes arranged in a same plane with a pitch same as that of the surface-emitting laser devices being electrically connected to each other to have contact with pad electrodes of the surface-emitting laser devices, respectively, and applying a current to second electrodes of the surface-emitting laser devices and the contact electrodes. The wafer level burn-in test is performed while heating the wafer at a predetermined temperature. Laser lights emitted from the surface-emitting laser devices are monitored during the wafer level burn-in test. | 01-06-2011 |
20110008917 | HIGH-POWER OPTICAL BURN-IN - Semiconductor lasers are aged to identify weak or flawed devices, resulting in improved reliability of the remaining devices. The lasers can be aged using a high-power optical burn-in that includes providing a high drive current to the lasers for a period of time, and maintaining the ambient temperature of the lasers at a low temperature. After the high-power optical burn-in, the output of the lasers can be measured to determine if the lasers are operating within specifications. Those that are not can be discarded, while those that are can be further aged using a high-temperature thermal burn-in that includes providing a drive current to the lasers while maintaining the ambient temperature of the lasers at a high-temperature. | 01-13-2011 |
20110027917 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - To provide a manufacturing method of a semiconductor device capable of placing a larger number of alignment marks for lithography and PCM and at the same time, preventing information leakage from the PCM. In a portion of a first scribe region sandwiched between first semiconductor chip regions, a first region and a second region are placed in parallel to each other. The first region is equipped with at least one monitor selected from a first monitor for electrically evaluating at least either one of an active element (such as transistor) and a passive element (such as resistor or capacitor), a second monitor for dimensional control, and a third monitor for measuring film thickness. In the second region, an alignment mark for lithography is placed. In the cutting step, the first region is cut off. | 02-03-2011 |
20110027918 | INSPECTION METHOD AND MANUFACTURING METHOD OF LIGHT-EMITTING DEVICE - In a light-emitting element provided with a thick layer of a plurality of EL layers which are partitioned by a charge generation layer between a pair of electrodes, a portion which a conductive foreign substance enters between the pair of electrodes emits stronger light at a voltage lower than a voltage required when a normal portion starts emitting light. In a light-emitting element provided with a plurality of EL layers which are partitioned by a charge generation layer between a pair of electrodes, a voltage may be applied thereto in the forward direction. Then, an abnormal light-emission portion may be detected because the portion emits light at a luminance of 1 (cd/m | 02-03-2011 |
20110027919 | Measurement and control of strained devices - A method that includes measuring stress on at least one of a monitor substrate, a production substrate, and a proxy device on a production substrate to produce stress data, measuring shape on at least one of a proxy device on a production substrate and a production device on a production substrate to produce shape data, and inputting the stress data and the shape data into an elastic deformation calculation to determine a stress value for a production device. | 02-03-2011 |
20110033957 | INTEGRATED THIN FILM METROLOGY SYSTEM USED IN A SOLAR CELL PRODUCTION LINE - Embodiments of the present invention generally relate to systems, apparatuses, and methods used to form solar cell devices using processing modules adapted to perform one or more processes in the formation of the solar cell devices. In one embodiment, the system provides an inline inspection system of solar cell devices within a solar cell production line while collecting and using metrology data to diagnose, tune, or improve production line processes during manufacture of solar cell devices. In one embodiment, the inspection system provides an on-the-fly characterization module positioned downstream from one or more processing tools wherein the characterization module is configured to measure on-the-fly one or more properties of one or more photovoltaic layers formed on a substrate surface and a system controller in communication with the characterization module and the one or more processing tools, where the system controller is configured to analyze information received from the characterization module. | 02-10-2011 |
20110033958 | METHOD FOR FORMING OXIDE FILM ON SILICON WAFER - The present invention provides a method for forming an oxide film on a silicon wafer, comprising: measuring surface roughness of the silicon wafer and/or crystallinity in a surface layer portion of the silicon wafer in advance; adjusting oxidizing conditions for the silicon wafer based on the measurement value; and forming the oxide film on the silicon wafer under the adjusted oxidizing conditions. As a result, there can be provided the method for forming an oxide film by which the oxidizing conditions can be adjusted based on a state of the surface and/or the surface layer of the silicon wafer before forming the oxide film and even an ultrathin oxide film can be thereby accurately formed. | 02-10-2011 |
20110039356 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND APPARATUS FOR MANUFACTURING SAME - A method for manufacturing a semiconductor device includes: irradiating a growth substrate with laser light to focus the laser light into a prescribed position inside a crystal for a semiconductor device or inside the growth substrate, the crystal for the semiconductor device being formed on a first major surface of the growth substrate; moving the laser light in a direction parallel to the first major surface; and peeling off a thin layer including the crystal for the semiconductor device from the growth substrate, a wavelength of the laser light being longer than an absorption end wavelength of the crystal for the semiconductor device or the growth substrate, the laser light being irradiated inside a crystal for the semiconductor device or inside the growth substrate. | 02-17-2011 |
20110065216 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE OR APPARATUS, AND APPARATUS FOR MANUFACTURING THE SAME - A method for manufacturing a semiconductor device or apparatus having at least a semiconductor as a component, characterized by including irradiating the semiconductor with light having a longer wavelength than the absorption edge wavelength of the semiconductor to change the threshold voltage of the semiconductor device or apparatus, and checking the threshold voltage of the semiconductor device or apparatus, after or during irradiation with the light, to determine whether the threshold voltage is in a predetermined range, during manufacturing the semiconductor device or apparatus. | 03-17-2011 |
20110070667 | METHOD OF PROCESSING SUBSTRATE AND METHOD OF MANUFACTURING SUBSTRATE FOR USE IN LIQUID EJECTION HEAD - A substrate processing method includes preparing a substrate, a first mask adjacent to a first surface of the substrate and including a first light transmitting portion allowing light to be transmitted therethrough, a condenser adjacent to the first surface, a second mask including a second light transmitting portion, and a photo detecting member including a photo detecting portion detecting light having passed through the second light transmitting portion, the condenser condensing light having passed through the first light transmitting portion toward the second light transmitting portion, the second light transmitting portion allowing the light condensed by the condenser to be transmitted therethrough, and forming a recess in the substrate by laser beam irradiation from a direction opposite to the first surface. When an intensity of the laser beam detected by the photo detecting portion is at or above a specific intensity, the irradiation of the laser beam is stopped. | 03-24-2011 |
20110070668 | METHODS OF SELECTIVELY REMOVING LUMINOUS MATERIAL FROM A LIGHT EMITTING DEVICE BASED ON MEASURED OUTPUT THEREOF - A light emitting apparatus is provided that includes a light emitting device and luminous material thereon. Light output of the light emitting apparatus is measured. Some of the luminous material is selectively removed from the light emitting device based on the output of the light emitting apparatus that was measured, so that luminous material that remains on the light emitting device after the selective removing continues to be optically excited by light that is generated by the light emitting device. In measuring, a frequency spectrum of the light emitting apparatus may be measured, and the light emitting apparatus may emit white light after the selectively removing. | 03-24-2011 |
20110070669 | METHODS OF SELECTIVELY APPLYING LUMINOUS MATERIAL TO LIGHT EMITTING DEVICES BASED ON MEASURED OUTPUT THEREOF - A light emitting apparatus is fabricated by measuring light output of a semiconductor light emitting device, and selectively applying luminous material to the light emitting device based on the measured output of the light emitting device. An amount of luminous material, different compositions of luminous material and/or different doping levels of luminous material may be selectively applied based on the measured output of the light emitting device. | 03-24-2011 |
20110081734 | METHOD AND ARRANGEMENT FOR PRODUCING AN N-SEMICONDUCTIVE INDIUM SULFIDE THIN LAYER - A method of producing, at atmospheric pressure, an n-type semiconductive indium sulfide thin film on a substrate using an indium-containing precursor, hydrogen sulfide as a reactive gaseous precursor, and an inert carrier gas stream includes cyclically repeating first and second steps so as to produce an indium sulfide thin film of a desired thickness. The first method phase includes converting the indium-containing precursor to at least one of a dissolved and a gaseous phase, heating the substrate to a temperature in a range of 100° C. to 275° C., directing the indium containing precursor onto the substrate and supplying hydrogen sulfide to the indium-containing precursor in a mixing zone in an amount so as to provide an absolute concentration of hydrogen sulfide that is greater than zero and no greater than 1% by volume. The indium concentration of the indium-containing precursor is set so as to produce a compact In(OH | 04-07-2011 |
20110086444 | PROCESS FOR PRODUCING SUBSTRATES FREE OF PATTERNS USING AN ALPHA STEPPER TO ENSURE RESULTS - The present disclosure provides a method for making an integrated circuit. The method comprises processing a first surface of a substrate to create the integrated circuit and grinding a second surface of the substrate to remove material until the substrate is substantially close to a desire thickness. The method also includes performing a wet etch process over the second surface of the substrate and performing a chemical mechanical polishing (CMP) process over the second surface of the substrate to remove a pattern on the substrate. The second surface of the substrate is examined with a metrological instrument to determine if the second surface is substantially smooth; if the second surface is not substantially smooth, the steps of performing the CMP process and examining the second surface with the metrological instrument are repeated until the second surface is substantially smooth. | 04-14-2011 |
20110097827 | PATTERN FORMATION METHOD AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - In one embodiment, a pattern formation method is disclosed. The method can place a liquid resin material on a workpiece substrate. The method can press a template against the resin material and measuring distance between a lower surface of a projection of the template and an upper surface of the workpiece substrate. The template includes a pattern formation region and a circumferential region around the pattern formation region. A pattern for circuit pattern formation is formed in the pattern formation region and the projection is formed in the circumferential region. The method can form a resin pattern by curing the resin material in a state of pressing the template. In addition, the method can separate the template from the resin pattern. | 04-28-2011 |
20110097828 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, includes providing a mark above a main surface on a semiconductor substrate, separating the semiconductor substrate into a plurality of semiconductor elements by cutting the semiconductor substrate, determining a reference semiconductor element on the basis of a coordinate data indicating coordinates of the mark and coordinates of all of the semiconductor elements on the semiconductor substrate, and picking-out the semiconductor elements on the basis of the coordinate data using a pick-out apparatus. The providing operation includes forming a protective coat onto the main surface of the semiconductor substrate, irradiating a point on the main surface of the semiconductor substrate with a laser beam through the protective coat, and eliminating the protective coat from the main surface of the semiconductor substrate. | 04-28-2011 |
20110097829 | METHOD FOR INSPECTION OF DEFECTS ON A SUBSTRATE - A method for inspection of defects on a substrate includes positioning a probe of a scanning probe microscopy (SPM) over and spaced apart from a substrate, includes scanning the substrate by changing a relative position of the probe with respect to the substrate on a plane spaced apart from and parallel to the substrate, and includes measuring a value of an induced current generated via the probe in at least two different regions of the substrate. The value of the induced current is variable according to at least a shape and a material of the substrate. The method further includes determining whether a defect exists by comparing the values of the induced currents measured in the at least two different regions of the substrate. | 04-28-2011 |
20110104830 | APPARATUS FOR INSPECTION WITH ELECTRON BEAM, METHOD FOR OPERATING SAME, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE USING FORMER - A substrate inspection apparatus | 05-05-2011 |
20110129948 | Optical alignment methods for forming LEDs having a rough surface - A method of aligning a wafer when lithographically fabricating a light-emitting diode (LED). The method includes forming on the wafer at least one roughened alignment mark having a root-mean-square (RMS) surface roughness σ | 06-02-2011 |
20110129949 | METHOD FOR GROWTH OF DILUTE-NITRIDE MATERIALS USING AN ISOTOPE FOR ENHANCING THE SENSITIVITY OF RESONANT NUCLEAR REATION ANALYSIS - In certain desirable embodiments, the present invention relates to the use of | 06-02-2011 |
20110143463 | VAPOR DEPOSITION METHOD AND VAPOR DEPOSITION APPARATUS - According to one embodiment, a vapor deposition method is disclosed for forming a nitride semiconductor layer on a substrate by supplying a group III source-material gas and a group V source-material gas. The method can deposit a first semiconductor layer including a nitride semiconductor having a compositional proportion of Al in group III elements of not less than 10 atomic percent by supplying the group III source-material gas from a first outlet and by supplying the group V source-material gas from a second outlet. The method can deposit a second semiconductor layer including a nitride semiconductor having a compositional proportion of Al in group III elements of less than 10 atomic percent by mixing the group III and group V source-material gases and supplying the mixed group III and group V source-material gases from at least one of the first outlet and the second outlet. | 06-16-2011 |
20110177628 | LIGHT EMITTING DEVICE FABRICATING APPARATUS AND LIGHT EMITTING DEVICE FABRICATING METHOD USING THE SAME - Provided is a light emitting device fabricating apparatus, which includes a light emitting device, first and second contact parts, a power source part, a loading plate, and a chamber. The first and second contact parts are connected to the light emitting device to apply a first current to the light emitting device. The power source part supplies power to the first and second contact parts. The loading plate supports and heats the light emitting device. The chamber accommodates the light emitting device, the first and second contact parts, and the loading plate, and has a vacuum state or oxygen atmosphere. | 07-21-2011 |
20110195531 | APPARATUS AND METHOD FOR EVALUATING OPTICAL PROPERTIES OF LED AND METHOD FOR MANUFACTURING LED DEVICE - An optical property evaluation apparatus includes: a light conversion filter converting light emitted from an LED chip or a bare LED package, which is to be evaluated, into a different wavelength of light, and emitting a specific color of light; and an optical property measurement unit receiving the specific color of light emitted from the light conversion filter and measuring the optical properties of the received light. | 08-11-2011 |
20110201138 | MASK VERIFYING METHOD, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, AND COMPUTER PROGRAM PRODUCT - According to a mask verifying method of the embodiment, a difference between an actual dimension of a mask pattern and a simulation dimension is calculated as a computational estimated value. Moreover, a difference between an actual dimension of the mask pattern that is actually measured and a dimension on pattern data is calculated as an actually-measured difference. Then, it is verified whether a mask pattern dimension passes or fails based on the calculated value. When calculating the computational estimated value, a model function, which is set based on each correspondence relationship between an actual dimension and a mask simulation dimension of a test pattern, which includes a plurality of types of pattern ambient environments, to the mask pattern. | 08-18-2011 |
20110212550 | METHODS FOR DETECTING METAL PRECIPITATES IN A SEMICONDUCTOR WAFER - Methods are disclosed for monitoring the amount of metal contamination imparted during wafer processing operations such as polishing and cleaning. The methods include subjecting a silicon-on-insulator structure to the semiconductor process, precipitating metal contamination in the structure and delineating the metal contaminants. | 09-01-2011 |
20110217794 | MICROELECTRONIC WORKPIECE PROCESSING SYSTEMS AND ASSOCIATED METHODS OF COLOR CORRECTION - Several embodiments of semiconductor systems and associated methods of color corrections are disclosed herein. In one embodiment, a method for producing a light emitting diode (LED) includes forming an (LED) on a substrate, measuring a base emission characteristic of the formed LED, and selecting a phosphor based on the measured base emission characteristic of the formed LED such that a combined emission from the LED and the phosphor at least approximates white light. The method further includes introducing the selected phosphor onto the LED via, for example, inkjet printing. | 09-08-2011 |
20110217795 | SEMICONDUCTOR MANUFACTURING APPARATUS AND SEMICONDUCTOR MANUFACTURING METHOD - According to one embodiment, a first substrate and a second substrate are pressed from an opposite surface of a joint surface of the second substrate such that a joint surface of the first substrate and the joint surface of the second substrate are in contact with each other. The second substrate is restrained by a member to provide a gap between the joint surfaces. It is determined, based on a temporal change of a joint interface calculated based on an image imaged from the opposite surface side of the joint surface, whether joining is normally performed. | 09-08-2011 |
20110217796 | ETCHING METHOD AND APPARATUS - An etching method capable of controlling the film thickness of a hard mask layer uniformly is provided. A plasma etching is performed on a native oxide film by using an etching gas containing, for example, CF | 09-08-2011 |
20110237005 | Layout Testing Method and Wafer Manufacturing Method - A product layout testing method includes testing and correcting one or more patterns of a product layout, detecting and correcting electrical characteristic changes of transistors of the product layout, and testing whether a product characteristic predicted from the product layout is equal to that predicted from a designed circuit view. Weak points with respect to the pattern may be detected and corrected, electrical characteristic changes depending on layout parameters may be detected and corrected, and whether a circuit operation depending on parasitic components is normal may be checked. | 09-29-2011 |
20110263052 | METHOD OF REMOVING CONTAMINATIONS - A method of removing contaminations includes providing a wafer, performing an inspection or a measuring step to the wafer, and performing a baking step to re-vaporize and remove contaminations from the wafer after the inspection or measuring step. | 10-27-2011 |
20110281379 | METHODS OF FORMING CONDUCTIVE LAYER PATTERNS USING GAS PHASE CLEANING PROCESS AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - Methods of forming conductive patterns include forming a conductive layer including a metal element on a substrate. The conductive layer is partially etched to generate a residue including an oxide of the metal element and to form a plurality of separately formed conductive layer patterns. A cleaning gas is inflowed onto the substrate including the conductive layer pattern. The metal compound is evaporated to remove the metal element contained in the residue and to form an insulating interface layer on the conductive layer pattern and a surface portion of the substrate through a reaction of a portion of the cleaning gas and oxygen. The residue may be removed from the conductive layer pattern to suppress generation of a leakage current. | 11-17-2011 |
20110294239 | SUB-RESOLUTION ASSIST FEATURE ARRANGING METHOD AND COMPUTER PROGRAM PRODUCT AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - According to a sub-resolution assist feature arranging method in embodiments, it is selected which of a rule base and a model base is set for which pattern region on pattern data corresponding to a main pattern as a type of the method of arranging the sub-resolution assist feature for improving resolution of the main pattern formed on a substrate. Then, the sub-resolution assist feature by the rule base is arranged in a pattern region set as the rule base and the sub-resolution assist feature by the model base is arranged in a pattern region set as the model base. | 12-01-2011 |
20110294240 | LIGHT-EMITTING DEVICE, LIGHT-EMITTING SYSTEM INCLUDING THE SAME, AND FABRICATING METHOD THEREOF - A light-emitting device having improved light conversion efficiency, a light-emitting system including the same, and fabricating methods of the light-emitting device and the light-emitting system, are provided. The light-emitting device includes one or more light-emitting elements arranged on one surface of a substrate, and a phosphor layer disposed inside or on the substrate to a predetermined thickness and partially wavelength-converts the light emitted from the one or more light-emitting elements into light having different wavelength, wherein a light conversion efficiency of the phosphor layer is maximized when the phosphor layer has the predetermined thickness. | 12-01-2011 |
20120003761 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE AND FABRICATION SYSTEM OF SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device and a fabrication system of the semiconductor device are provided. The method includes sequentially forming a film to be etched and a dielectric film and measuring a thickness of the dielectric film, forming a photoresist film on the dielectric film, performing a lithography process using the measured thickness of the dielectric film to form a photoresist film pattern, and etching the dielectric film and the film to be etched using the photoresist film pattern. | 01-05-2012 |
20120009693 | System and method for cleaning a charging wafer surface - A system and method for processing a wafer includes a charge neutralization system. The wafer processing system includes a wafer measuring device that can measure characteristics of a surface of the semiconductor wafer. One or more wafer processing stations perform a chemical mechanical polish (CMP) process on the wafer surface. A desica cleaning station can clean and dry the semiconductor wafer. The wafer processing system further includes a charge neutralizing device that can alter a surface charge of the wafer surface. | 01-12-2012 |
20120009694 | APPARATUS AND METHOD FOR MONITORING PRECURSOR FLUX - An apparatus and method for monitoring precursor flux is disclosed herein. The apparatus comprises an optical cell configured for electromagnetic radiation spectroscopy and has a precursor reservoir or deposition chamber configured to provide a flow of a vapor deposition precursor therethrough, a first inner window sealing a first optical opening in the precursor reservoir or deposition chamber, a first outer window in optical communication with the first inner window, a first vacuum chamber disposed between the first inner window and the first outer window, a second inner window sealing a second optical opening in the precursor reservoir or deposition chamber, a second outer window in optical communication with the second inner window, a second vacuum chamber disposed between the second inner window and the second outer window. Each window being disposed to be in optical communication with one another, a electromagnetic radiation or light source, and an optical detector. A method of monitoring precursor flux comprises directing electromagnetic radiation through an outer window, a vacuum chamber, a first inner window, a volume within a cell body, and out of the cell body through a second inner window; and receiving the electromagnetic radiation from the second inner window with a sensor and sensing at least one parameter of a gas within the cell body. | 01-12-2012 |
20120015459 | Thermal Leveling for Semiconductor Devices - A semiconductor device and a method of manufacturing are provided. In some embodiments, a backside annealing process such that a first heat source is placed along a backside of the substrate. In other embodiments, the first heat source is used in combination with an anti-reflection dielectric (ARD) layer is deposited over the substrate. In yet other embodiments, a second heat source is placed along a front side of the substrate in addition to the first heat source placed on the backside of the substrate. In yet other embodiments, a heat shield may be placed between the substrate and the second heat source on the front side of the substrate. In yet further embodiments, a single heat source may be used on the front side of the substrate in combination with the ARD layer. A reflectivity scan may be performed to determine which anneal stage (RTA or MSA or both) to place thermal leveling solution. | 01-19-2012 |
20120015460 | System and Method for Estimating Field Curvature - Projection systems and methods with mechanically decoupled metrology plates according to embodiments of the present invention can be used to characterize and compensate for misalignment and aberration in production images due to thermal and mechanical effects. Sensors on the metrology plate measure the position of the metrology plate relative to the image and to the substrate during exposure of the substrate to the production image. Data from the sensors are used to adjust the projection optics and/or substrate dynamically to correct or compensate for alignment errors and aberration-induced errors. Compared to prior art systems and methods, the projection systems and methods described herein offer greater design flexibility and relaxed constraints on mechanical stability and thermally induced expansion. In addition, decoupled metrology plates can be used to align two or more objectives simultaneously and independently. | 01-19-2012 |
20120015461 | System Metrology Core - Projection systems and methods with mechanically decoupled metrology plates according to embodiments of the present invention can be used to characterize and compensate for misalignment and aberration in production images due to thermal and mechanical effects. Sensors on the metrology plate measure the position of the metrology plate relative to the image and to the substrate during exposure of the substrate to the production image. Data from the sensors are used to adjust the projection optics and/or substrate dynamically to correct or compensate for alignment errors and aberration-induced errors. Compared to prior art systems and methods, the projection systems and methods described herein offer greater design flexibility and relaxed constraints on mechanical stability and thermally induced expansion. In addition, decoupled metrology plates can be used to align two or more objectives simultaneously and independently. | 01-19-2012 |
20120034714 | WAFER-LEVEL LIGHT EMITTING DIODE STRUCTURE, LIGHT EMITTING DIODE CHIP, AND METHOD FOR FORMING THE SAME - A method for fabricating a wafer-level light emitting diode structure is provided. The method includes: providing a substrate, wherein a first semiconductor layer, a light emitting layer, and a second semiconductor layer are sequentially disposed on the substrate; subjecting the first semiconductor layer, the light emitting layer, and the second semiconductor layer with a patterning process to form a first depressed portion, a second depressed portion, a stacked structure disposed on the second depressed portion and a remained first semiconductor layer disposed on the depressed portion, wherein the stacked structure comprises a patterned second semiconductor layer, a patterned emitting layer, and a patterned first semiconductor layer; forming a first electrode on the remained first semiconductor layer of the first depressed portion; and forming a second electrode correspondingly disposed on the patterned second semiconductor layer of the second depressed portion. | 02-09-2012 |
20120034715 | Methods of fabricating a light-emitting device - Methods of fabricating of a light-emitting device are provided, the methods include forming a plurality of light-emitting units on a substrate, measuring light characteristics of the plurality of light-emitting units, respectively, depositing a phosphor layer on the plurality of light-emitting units using a printing method, and cutting the substrate to separate the plurality of light-emitting units into unit by unit. The phosphor layer is adjustably deposited according to the measured light characteristics of the plurality of light-emitting units. | 02-09-2012 |
20120045854 | INSPECTING METHOD, TEMPLATE MANUFACTURING METHOD, SEMICONDUCTOR INTEGRATED CIRCUIT MANUFACTURING METHOD, AND INSPECTING SYSTEM - According to one embodiment, a template for manufacturing a memory cell array comprising a relievable area and a redundant area replaceable with the relievable area is to be inspected. First, based on a defect position of a defect-detected template and position information on a relievable area, a decision is made as to whether the detected defect is positioned within the relievable area. A decision is made as to whether the number of defect-detected relievable areas exceeds the preset permissible number. When the detected defect is positioned outside the relievable area or when the number of defect-detected relievable areas exceeds the permissible number, a notification that the template has failed the inspection is output. | 02-23-2012 |
20120045855 | POSITION-SENSITIVE METROLOGY SYSTEM - A metrology system for analyzing a semiconductor device on a substrate can include a metrology sensor. | 02-23-2012 |
20120064643 | Methods and System for On-Chip Decoder for Array Test - The present invention provides devices capable of testing the electrical performance of thin-film transistor backplane arrays and methods for their use. | 03-15-2012 |
20120070916 | MOVABLE INJECTORS IN ROTATING DISC GAS REACTORS - A system and method for uniform deposition of material layers on wafers in a rotating disk chemical vapor deposition reaction system is provided, wherein one or more substrates are rotated on a carrier about an axis while maintaining surfaces of the one or more substrates substantially perpendicular to the axis of rotation and facing in an upstream direction along the axis of rotation. During rotating a first gas is discharged in the downstream direction towards the one or more substrates from a first set of gas inlets. A second gas is discharged in the downstream direction towards the one or more substrates from at least one movable gas injector, and the at least one movable gas inlet is moved with a component of motion in a radial direction towards or away from the axis of rotation. | 03-22-2012 |
20120070917 | APPARATUS AND METHOD FOR MOUNTING SEMICONDUCTOR LIGHT EMITTING ELEMENT - When bump electrodes | 03-22-2012 |
20120083054 | METHODS AND APPARATUS FOR ALIGNING A SET OF PATTERNS ON A SILICON SUBSTRATE - The disclosure relates to a method of aligning a set of patterns on a substrate, which includes depositing on the substrate's surface a set of silicon nanoparticles, which includes a set of ligand molecules including a set of carbon atoms. The method involves forming a first set of regions where the nanoparticles are deposited, while the remaining portions of the substrate surface define a second set of regions. The method also includes densifying the set of nanoparticles into a thin film to form a set of silicon-organic zones on the substrate's surface, wherein the first and the second set of regions have respectively first and second reflectivity values, such that the ratio of the second reflectivity value to the first reflectivity value is greater than about 1.1. | 04-05-2012 |
20120094402 | METHOD TO MANUFACTURE SEMICONDUCTOR DEVICE WITH OPTICAL GRATING - A method to manufacture an optical device with enhanced high frequency performance is disclosed. The method includes steps of: (a) forming semiconductor layers on a semiconductor substrate, (b) etching the semiconductor layers by using a mask to form a plurality of diffraction gratings, where the mask provides a plurality of periodic patterns each corresponding to respective gratings and having a specific pitch different from others, (c) forming an active layer on the etched semiconductor layers, (d) measuring a maximum optical gain of the active layer, (e) selecting one of diffraction gratings based on the measured optical gain, and (f) forming a current confinement structure aligned with the selected diffraction grating. | 04-19-2012 |
20120094403 | METHOD OF MANUFACTURING THIN-FILM TRANSISTOR SUBSTRATE - Provided is a method of manufacturing a TFT substrate for preventing characteristics of a native oxide layer in a boundary between a microcrystal semiconductor layer and an amorphous semiconductor layer from being degraded. The method includes forming a gate electrode, forming a gate insulating film, modifying the formed first amorphous silicon thin film into a first crystalline silicon thin film, removing a silicon oxide layer on the surface of the first crystalline silicon thin film, forming the second amorphous silicon thin film, and dry etching the first crystalline silicon thin film and the second amorphous silicon thin film, and it is determined whether or not the in-process TFT substrate after the dry etching is returned to the processes after the dry etching by measuring the emission intensity of radicals in plasma during the dry etching and detecting the presence or absence of the silicon oxide layer in the boundary. | 04-19-2012 |
20120100642 | Spectra Based Endpointing for Chemical Mechanical Polishing - A computer implemented method of monitoring a polishing process includes, for each sweep of a plurality of sweeps of an optical sensor across a substrate undergoing polishing, obtaining a plurality of current spectra, each current spectrum of the plurality of current spectra being a spectrum resulting from reflection of white light from the substrate, for each sweep of the plurality of sweeps, determining a difference between each current spectrum and each reference spectrum of a plurality of reference spectra to generate a plurality of differences, for each sweep of the plurality of sweeps, determining a smallest difference of the plurality of differences, thus generating a sequence of smallest difference, and determining a polishing endpoint based on the sequence of smallest differences. | 04-26-2012 |
20120100643 | DAMAGE EVALUATION METHOD OF COMPOUND SEMICONDUCTOR MEMBER, PRODUCTION METHOD OF COMPOUND SEMICONDUCTOR MEMBER, GALLIUM NITRIDE COMPOUND SEMICONDUCTOR MEMBER, AND GALLIUM NITRIDE COMPOUND SEMICONDUCTOR MEMBRANE - A method of evaluating damage of a compound semiconductor member, comprising: a step of performing spectroscopic ellipsometry measurement on a surface of the compound semiconductor member; and a step of evaluating damage on the surface of the compound semiconductor member, using a spectrum in a wavelength band containing a wavelength corresponding to a bandgap of the compound semiconductor member, in a spectrum of an optical constant obtained by the spectroscopic ellipsometry measurement. | 04-26-2012 |
20120107969 | METHOD AND SYSTEM FOR COMPARING LITHOGRAPHIC PROCESSING CONDITIONS AND OR DATA PREPARATION PROCESSES - A set of optical rule checker (ORC) markers are identified in a simulated lithographic pattern generated for a set of data preparation parameters and lithographic processing conditions. Each ORC marker identifies a feature in the simulated lithographic pattern that violates rules of the ORC. A centerline is defined in each ORC marker, and a minimum dimension region is generated around each centerline with a minimum width that complies with the rules of the ORC. A failure region is defined around each ORC marker by removing regions that overlap with the ORC marker from the minimum dimension region. The areas of all failure regions are added to define a figure of demerit, which characterizes the simulated lithographic pattern. The figure of demerit can be evaluated for multiple simulated lithographic patterns or iteratively decreased by modifying the set of data preparation parameters and lithographic processing conditions. | 05-03-2012 |
20120107970 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device is provided to improve the reliability of electrical coupling of the semiconductor device. The manufacturing method includes the steps of (a) laminating a main conductive film (base film) and a stopper insulating film (film to be measured) above the main conductive film, over a main surface of a semiconductor substrate, (b) forming an opening in the stopper film, (c) applying an electron beam (excitation beam) to the opening to emit characteristic X-rays, and (d) detecting the characteristic X-rays to determine the presence or absence, or thickness of the stopper insulating film at the bottom of the opening based on detection result of the characteristic X-rays. In the step (d), the presence or absence, or thickness of the stopper film is determined by a ratio of element components contained in the characteristic X-rays. | 05-03-2012 |
20120107971 | SUBSTRATE POLISHING METROLOGY USING INTERFERENCE SIGNALS - A polishing pad assembly for a chemical mechanical polishing apparatus includes a polishing pad having a polishing surface and a surface opposite the polishing surface for attachment to a platen, and a solid light-transmissive window formed in the polishing pad. The light-transmissive window is more transmissive to light than the polishing pad. The light-transmissive window has a light-diffusing bottom surface. | 05-03-2012 |
20120115258 | METHODS FOR MONITORING THE AMOUNT OF METAL CONTAMINATION IN A PROCESS - Methods are disclosed for monitoring the amount of metal contamination imparted during wafer processing operations such as polishing and cleaning. The methods include subjecting a silicon-on-insulator structure to the semiconductor process, precipitating metal contamination in the structure and delineating the metal contaminants. | 05-10-2012 |
20120122252 | METHOD FOR INSPECTING SUBSTRATE, SUBSTRATE INSPECTION APPARATUS, EXPOSURE SYSTEM, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - There is provided a method for inspecting a substrate including: irradiating an illumination light onto a first surface or a second surface opposite to the first surface, of a substrate in which a pattern having a periodicity and extending from the first surface to an inside of the substrate is formed in the first surface, the illumination light having a permeability to permeate the substrate to a predetermined depth; detecting a light reflected from or transmitted through the substrate due to irradiation of the illumination light; and inspecting the substrate by utilizing information based on the periodicity of the pattern obtained from detection of the light reflected from or transmitted through the substrate. | 05-17-2012 |
20120122253 | APPARATUS AND METHOD OF ALIGNING AND POSITIONING A COLD SUBSTRATE ON A HOT SURFACE - Embodiments of the invention contemplate a method, apparatus and system that are used to support and position a substrate on a surface that is at a different temperature than the initial, or incoming, substrate temperature. Embodiments of the invention may also include a method of controlling the transfer of heat between a substrate and substrate support positioned in a processing chamber. The apparatus and methods described herein generally may also provide an inexpensive and simple way of accurately positioning a substrate on a substrate support that is positioned in a semiconductor processing chamber. Substrate processing chambers that can benefit from the various embodiments described herein include, but are not limited to RTP, CVD, PVD, ALD, plasma etching, and/or laser annealing chambers. | 05-17-2012 |
20120129279 | IMPRINTING METHOD, IMPRINTING APPARATUS AND MEDIUM - According to one embodiment, there is provided an imprinting method for applying a first hardening resin material on a substrate to be processed and transferring a pattern of a semiconductor integrated circuit formed on a template onto the substrate to be processed on which the first hardening resin material is applied, wherein a second hardening resin material with higher separability than the first hardening resin material is applied on at least part of the outer periphery of an area in which the pattern is formed by one transferring. | 05-24-2012 |
20120135549 | Method of Processing Gallium-Nitride Semiconductor Substrates - Polishing a nitride semiconductor monocrystalline wafer leaves it with a process-transformed layer. The process-transformed layer has to be etched to be removed. The chemical inertness of nitride semiconductor materials has, however, precluded suitable etching. Although potassium hydroxide, for example, or sulfuric acid have been proposed as GaN etchants, their ability to corrosively remove material from the Ga face is weak. Dry etching utilizing a halogen plasma is carried out in order to remove the process-transformed layer. The Ga face can be etched off with the halogen plasma. Nevertheless, owing to the dry etching, a problem arises again—surface contamination due to metal particles. To address the problem, wet etching with, as the etchant, solutions such as HF+H | 05-31-2012 |
20120135550 | REFRACTION ASSISTED ILLUMINATION FOR IMAGING - Various embodiments are directed to systems and methods of imaging subsurface features of objects. An illumination source may be directed towards a surface of an object comprising subsurface features at a first angle relative to the normal of the surface. The object may have a portion between the subsurface features and the surface that has an index of refraction that is greater than the index of refraction of a surrounding medium. An imaging device may be placed with an objective lens oriented substantially normal to the surface. The first angle may be larger than an acceptance angle of the objective lens. | 05-31-2012 |
20120142124 | METHOD OF APPLYING PHOSPHOR TO SEMICONDUCTOR LIGHT-EMITTING DEVICE - A method of applying a phosphor according to a light-emission characteristic of semiconductor light-emitting devices so as to increase a yield rate of manufacture with respect to a white light-emitting device chip, the method including the operations of testing light-emission characteristics of a plurality of light-emitting devices formed on a wafer; disposing a plurality of light-emitting devices having the same light-emission characteristics on a carrier substrate; applying a same phosphor to the plurality of light-emitting devices disposed on the carrier substrate; and separating the plurality of arrayed light-emitting devices. Thus, a white light-emitting device chip manufactured by using the method may emit almost the same white light. | 06-07-2012 |
20120142125 | PHOTOLUMINESCENCE IMAGING SYSTEMS FOR SILICON PHOTOVOLTAIC CELL MANUFACTURING - A method of photoluminence (PL) imaging of a series of silicon wafers, the method including the step of: utilizing incident illumination of a wavelength greater than 808 nm. The present invention further provides a method of analysing silicon semiconductor material utilising various illumination, camera and filter combinations. In some embodiments the PL response is captured by a MOSIR camera. In another embodiment a camera is used to capture the entire PL response and a long pass filter is applied to block a portion of the signal reaching the camera/detector. | 06-07-2012 |
20120156810 | INSPECTION METHOD, INSPECTION APPARATUS, EXPOSURE CONTROL METHOD, EXPOSURE SYSTEM, AND SEMICONDUCTOR DEVICE - There is provided an inspection method for inspecting a substrate supporting portion configured to support a substrate during an exposure performed by an exposure apparatus, the method including: irradiating a surface of the exposed substrate with an illumination light beam; detecting reflected light from a pattern in the irradiated surface; determining a focusing state at the time of exposing the pattern of the substrate based on the detected reflected light; and inspecting a state of the substrate supporting portion based on the focusing state. | 06-21-2012 |
20120164763 | SURFACE INSPECTION APPARATUS, METHOD FOR INSPECTING SURFACE, EXPOSURE SYSTEM, AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - A surface inspection apparatus includes: an irradiation unit; a detection unit configured to detect a first detection signal according to a first light beam and a second detection signal according to a second light beam; a providing unit which is configured to provide a first reference data and a second reference data; and a determination unit which is configured to determine a processing condition of the pattern in the substrate as an inspection object substrate, based on consistency between the first detection signal and the first reference data, and consistency between the second detection signal and the second reference data. | 06-28-2012 |
20120184055 | Making Method of Sample for Evaluation of Laser Irradiation Position and Making Apparatus Thereof and Evaluation Method of Stability of Laser Irradiation Position and Evaluation Apparatus Thereof - A method for making a sample for evaluation of laser irradiation position and evaluating the sample, and an apparatus which is switchable between a first mode of modification of semiconductor and a second mode of making and evaluating the sample. Specifically, a sample is made by irradiating a semiconductor substrate for evaluation with a pulse laser beam while the semiconductor substrate is moved for evaluation at an evaluation speed higher than a modifying treatment speed, each relative positional information between pulse-irradiated regions in the sample is extracted, and stability of the each relative positional information between pulse-irradiated regions is evaluated. The evaluation speed is such a speed that separates the pulse-irradiated regions on the sample from each other in a moving direction. | 07-19-2012 |
20120196388 | METHOD FOR MANUFACTURING LIGHT-EMITTING DEVICE AND MANUFACTURING APPARATUS OF LIGHT-EMITTING DEVICE - An object is to provide a method for manufacturing a light-emitting device in which a defective portion is insulated. In addition, another object is to provide a manufacturing apparatus of a light-emitting device in which a defective portion is insulated. After a hemispherical lens is formed to overlap with a light-emitting element, the defective portion is detected. Then, the hemispherical lens overlapping with the light-emitting element including the detected defective portion may be irradiated with a laser beam having a low energy density, and the defective portion may be insulated by light condensed through the hemispherical lens. | 08-02-2012 |
20120202303 | CUSTOMIZED MANUFACTURING METHOD FOR AN OPTOELECTIRCAL DEVICE - The disclosure provides a customized manufacturing method for an optoelectrical device. The customized manufacturing method comprises the steps of providing a manufacturing flow including a front-end flow, a customized module subsequent to the front-end flow, and a pause step between the front-end flow and the customized module, processing a predetermined amount of semi-manufactured products queued at the pause step, tuning the customized module in accordance with a customer's request, and processing the semi-manufactured products by the tuned customized module to fulfill the customer's request. | 08-09-2012 |
20120220058 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes preparing a layout of the semiconductor device, obtaining contrast of an exposure image of the layout through a simulation under a condition of using a crosspole illumination system, separating the layout into a plurality of sub-layouts based on the contrast of the exposure image, forming a photomask having a mask pattern corresponding to the plurality of sub-layouts, and performing an exposure process using the photomask under an exposure condition of using a dipole illumination system. | 08-30-2012 |
20120225503 | DOPANT MARKER FOR PRECISE RECESS CONTROL - A method is provided including depositing a layer of material on a substrate, during deposition of the material, at a predetermined depth, laterally implanting a first dopant and a second dopant in the material, the second dopant being different from the first dopant, etching the material, during etching, detecting the positions and intensities of the first and second dopants, and calculating lateral homogeneity of the material in situ from the intensities of the first and second dopants. | 09-06-2012 |
20120231564 | MONITORING TEST ELEMENT GROUPS (TEGS) FOR ETCHING PROCESS AND METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING THE SAME - Disclosed is a monitoring TEG for an etching process in a semiconductor device. The TEG includes an etch stopping layer on a substrate and a target layer to be etched provided on the etch stopping layer. The target layer to be etched includes a first opening portion formed by etching a portion of the target layer to be etched and a second opening portion formed by etching another portion of the target layer to be etched. The second opening portion has a smaller depth than the first opening portion. A depth of a partial contact hole formed by a first partial etching process may be measured. | 09-13-2012 |
20120270342 | IN-SITU MEASUREMENT OF FEATURE DIMENSIONS - Methods and systems are provided for fabricating a semiconductor device. An exemplary method involves forming a feature of a semiconductor device in a first region of a layer of material on a semiconductor substrate and forming a test structure in a second region of the layer of material. The test structure is formed concurrently to forming the feature, and a dimension of the feature is determined using the test structure. | 10-25-2012 |
20120270343 | POLISHING METHOD AND METHOD FOR FORMING A GATE - A polishing method and a method for forming a gate are provided. The method includes forming a dummy gate on a semiconductor substrate including a sacrificial oxide layer and a polysilicon layer which covers the sacrificial oxide layer, forming spacers around the dummy gate, and successively forming a silicon nitride layer and a dielectric layer covering the silicon nitride layer. The method further includes polishing the dielectric layer until the silicon nitride layer is exposed, polishing the silicon nitride layer on a fixed abrasive pad until the polysilicon layer is exposed by using a polishing slurry with a PH value ranging from 10.5 to 11 and comprising an anionic surfactant or a zwitterionic surfactant. Additionally, the method includes forming an opening after removing the dummy gate, and forming a gate in the opening. The method eliminates potential erosion and dishing caused in the polishing of the silicon nitride layer. | 10-25-2012 |
20120276664 | METHODS OF INSPECTING AND MANUFACTURING SEMICONDUCTOR WAFERS - A method of manufacturing a plurality of semiconductor wafers comprising micro-inspecting at least one location within at least one micro-inspected pattern field and determining at least one parameter value representing a property of the wafer at the micro-inspected location, macro-inspecting a plurality of locations within the at least one micro-inspected pattern field and determining, for each macro-inspected location of the macro-inspected pattern field, at least one parameter value representing the property of the wafer at the macro-inspected location based on the light intensity recorded for the macro-inspected location and on the at least one parameter value representing the property of the wafer at the micro-inspected location of this pattern field. | 11-01-2012 |
20120288970 | HEAT TREATMENT METHOD AND HEAT TREATMENT APPARATUS FOR HEATING SUBSTRATE BY IRRADIATING SUBSTRATE WITH LIGHT - After flash irradiation on a semiconductor wafer is started and then the temperatures of front and back surfaces of the semiconductor wafer become equal to each other, the temperature of the back surface of the semiconductor wafer, which has a known emissivity, is measured with a radiation thermometer. The emissivity of the front surface of the semiconductor wafer is calculated based on the intensity of radiated light from a black body having an equal temperature to the temperature of the back surface thereof, and the intensity of radiated light actually radiated from the front surface of the semiconductor wafer. Then, the temperature of the front surface of the semiconductor wafer heated by the flash irradiation is calculated based on the calculated emissivity and the intensity of the radiated light from the front surface of the semiconductor wafer that has been measured after the flash irradiation is started. | 11-15-2012 |
20130005056 | METHOD AND APPARATUS FOR PROCESSING WAFER EDGE PORTION - Provided is a method for processing a wafer edge portion using photolithograph equipment. The method includes placing a wafer on a support plate, inspecting a bead removal state of an edge portion of the wafer placed on the support plate, and exposing the edge portion of the wafer placed on the support plate to light. The inspecting of the bead removal state is performed by capturing first images from the wafer placed on the support plate and inspecting the first images. | 01-03-2013 |
20130017629 | METHODS OF MANUFACTURING THREE-DIMENSIONAL SEMICONDUCTOR DEVICESAANM Pyo; MyungjungAACI Hwaseong-siAACO KRAAGP Pyo; Myungjung Hwaseong-si KRAANM Kim; Hyo-JungAACI SeoulAACO KRAAGP Kim; Hyo-Jung Seoul KRAANM Lim; JongHeunAACI Hwaseong-siAACO KRAAGP Lim; JongHeun Hwaseong-si KRAANM Kim; KyunghyunAACI SeoulAACO KRAAGP Kim; Kyunghyun Seoul KRAANM Yoon; ByoungmoonAACI Suwon-siAACO KRAAGP Yoon; Byoungmoon Suwon-si KRAANM Han; JaHyungAACI Suwon-siAACO KRAAGP Han; JaHyung Suwon-si KR - According to example embodiments, a methods includes forming a peripheral structure including peripheral circuits on a peripheral circuits region of a substrate, recessing a cell array region of the substrate to form a concave region having a bottom surface lower than a top surface of the peripheral structure, forming a stacked layer structure conformally covering the concave region, the stacked layer structure including a plurality of layers sequentially stacked and having a lowest top surface in the cell array region and a highest top surface in the peripheral circuits region, forming a planarization stop layer that conformally covers the stacked layer structure, and planarizing the stacked layer structure using the planarization stop layer in the cell array region as a planarization end point to expose top surfaces of the thin layers between the cell array region and the peripheral circuits region simultaneously with a top surface of the peripheral structure. | 01-17-2013 |
20130023069 | METHOD FOR CHECKING ION IMPLANTATION CONDITION AND METHOD FOR MANUFACTURING SEMICONDUCTOR WAFER - A method for checking an ion implantation condition when ions are implanted over an entirety of one surface of a semiconductor wafer having an insulator film on the one surface, the method including checking whether the ions are implanted over the entirety of the one surface of the semiconductor wafer by directly or indirectly observing light emitted when the one surface of the semiconductor wafer is irradiated with an ion beam of the implanted ions throughout the ion implantation. | 01-24-2013 |
20130045547 | PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD - In a plasma processing apparatus in which a wafer is processed while supplying radio frequency power to electrodes disposed in a sample stage in a processing chamber within a reactor via a matching box, by matching a specific value of power at transition points of data values of at least two kinds among characteristic data including light emission intensity of the plasma, magnitude of its time variation, a matching position of the matching box, and a change of a value of a voltage of the radio frequency power supplied to the electrodes detected by varying the power to a plurality of values during the processing with a value detected by using characteristic data which is detected during the processing executed on a wafer of the same kind in a different reactor, the differences of the states inside the processing chamber or plasma among a plurality of semiconductor processing apparatuses or reactors are reduced. | 02-21-2013 |
20130045548 | Apparatus and method for simultaneous deposition of a plurality of semiconductor layers in a plurality of process chambers - A method for depositing a semiconductor layer on a multiplicity of substrates. The process chamber height (H), which is defined by the spacing between a process chamber ceiling ( | 02-21-2013 |
20130078746 | RETICLE DEFECT CORRECTION BY SECOND EXPOSURE - Correction of reticle defects, such as EUV reticle defects, is accomplished with a second exposure. Embodiments include obtaining a reticle with a first pattern corresponding to a design for a wafer pattern, detecting dark defects and/or design/OPC weak spots in the first pattern, exposing a resist covered wafer using the reticle, and exposing the wafer using a second reticle with a second pattern or a second image field with openings corresponding to the dark defects, with a repair pattern on the reticle or on another reticle, or with a programmed e-beam or laser writer. | 03-28-2013 |
20130095579 | METHOD AND APPARATUS FOR THE FORMATION OF SOLAR CELLS WITH SELECTIVE EMITTERS - Methods and apparatus for forming solar cells with selective emitters are provided. A method includes positioning a substrate on a substrate receiving surface. The substrate has a surface comprising a first patterned heavily doped region having a first dopant concentration that defines the selective emitters, and a second doped emitter region having a second dopant concentration that is less than the first dopant concentration, wherein the second doped emitter region surrounds the first patterned heavily doped region. The method further comprises determining a position of the first patterned heavily doped region by using a Fourier transform to process a filtered optical image, aligning one or more distinctive elements in a screen printing mask with the first patterned heavily doped region by using information received from the determined position of the first patterned heavily doped region, and depositing a layer of material on a portion of the first patterned heavily doped region. | 04-18-2013 |
20130102094 | METHOD FOR FABRICATING ORGANIC EL DEVICE AND METHOD FOR EVALUATING ORGANIC EL DEVICE - An organic EL device (OELD) having a defective portion is irradiated with a laser beam; first luminance of light emitted from the OELD is measured after the OELD is irradiated with the laser beam, while supplying, to the OELD, a first amount of current with which the OELD in a normal state would emit light having luminance corresponding to a first grayscale level smaller than a reference level; the OELD is re-irradiated with the laser beam when the first luminance is smaller than a threshold; and second luminance of light emitted from the OELD is measured when the first luminance is greater than or equal to the threshold, while supplying, to the OELD, a second amount of current with which the OELD in the normal state would emit light having luminance corresponding to a second grayscale level greater than or equal to the reference level. | 04-25-2013 |
20130109112 | ETCH RATE DETECTION FOR PHOTOMASK ETCHING | 05-02-2013 |
20130122614 | Method and System of Improved Uniformity Testing - A method and system includes a first substrate and a second substrate, each substrate comprising a predetermined baseline transmittance value at a predetermine wavelength of light, processing regions on the first substrate by combinatorially varying at least one of materials, process conditions, unit processes, and process sequences associated with the graphene production, performing a first characterization test on the processed regions on the first substrate to generate first results, processing regions on a second substrate in a combinatorial manner by varying at least one of materials, process conditions, unit processes, and process sequences associated with the graphene production based on the first results of the first characterization test, performing a second characterization test on the processed regions on the second substrate to generate second results, and determining whether at least one of the first substrate and the second substrate meet a predetermined quality threshold based on the second results. | 05-16-2013 |
20130122615 | FABRICATION METHOD OF SEMICONDUCTOR DEVICE - A technique is provided which can exactly recognize a chip to be picked up when picking up the chip from a wafer sheet in a process of die bonding a thin chip. A camera is coupled to one end of a lens barrel, an objective lens is attached to an opposite end of the lens barrel, and an image of a main surface of a chip is photographed through the objective lens. A surface-emitting lighting unit, a diffusing plate and a half mirror are internally provided between the lens barrel and the chip. Further, another lens barrel having a coaxial drop lighting function of radiating light to the main surface of the chip along the same optical axis as that of the camera is disposed. | 05-16-2013 |
20130130412 | LIGHT EMITTING DIODE MODULE WITH THREE PART COLOR MATCHING - A light emitting diode module is produced using at least one LED and at least two selectable components that form a light mixing chamber. First and second selectable components have first and second types of wavelength converting materials with different wavelength converting characteristics. The first and second wavelength converting characteristics alter the spectral power distribution of the light produced by the LED to produce light with a color point that is a predetermined tolerance from a predetermined color point. Moreover, a set of LED modules may be produced such that each LED module has the same color point within a predetermined tolerance. The LED module may be produced by pre-measuring the wavelength converting characteristics of the different components selecting components with wavelength converting characteristics that convert the spectral power distribution of the LED to a color point that is a predetermined tolerance from a predetermined color point. | 05-23-2013 |
20130130413 | APPARATUS AND METHOD FOR IN-SITU ENDPOINT DETECTION FOR SEMICONDUCTOR PROCESSING OPERATIONS - An endpoint detection method includes processing an outer surface of a substrate, directing an incident light beam through a window in an opaque metal body onto the surface being processed, receiving at a detector a reflected light beam from the substrate and generating a signal from the detector, and generating a signal based on the reflected light beam received at the detector, and detecting a processing endpoint. The signal is a time-varying cyclic signal that varies as the thickness of the layer varies over time, and detecting the processing endpoint includes detecting that a portion of a cycle of the cyclic signal has passed, the portion being less than a full cycle of the cyclic signal. | 05-23-2013 |
20130137197 | METHODS FOR QUANTITATIVE MEASUREMENT OF A PLASMA IMMERSION PROCESS - Methods for quantitatively measuring the performance of a plasma immersion process are provided herein. In some embodiments, a method of quantitatively measuring the performance of a plasma immersion process, using a first substrate comprising an oxide layer deposited atop a silicon layer, may include subjecting the first substrate to a plasma immersion process in a first plasma immersion chamber to form a doped oxide layer atop the first substrate; and determining a thickness of the doped oxide layer by shining a beam of light upon a reflective surface of the doped oxide layer; detecting reflected beams of light off of the reflective surface of the doped oxide layer; and analyzing the reflected beams of light to determine the thickness of the doped oxide layer on the first substrate. | 05-30-2013 |
20130137198 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A method for manufacturing a silicon carbide semiconductor device includes the following steps. There is prepared a silicon carbide substrate having a first main surface and a second main surface. On the first main surface, an electrode is formed. The silicon carbide substrate has a hexagonal crystal structure. The first main surface has an off angle of ±8° or smaller relative to a {0001} plane. The first main surface has such a property that when irradiated with excitation light having energy equal to or greater than a band gap of silicon carbide, luminous regions in a wavelength range of 750 nm or greater are generated in the first main surface at a density of 1×10 | 05-30-2013 |
20130149801 | METHOD OF MANUFACTURING LIGHT-EMITTING DEVICE - A method of manufacturing a light-emitting device includes forming a wave length conversion portion on a light-emitting element. The light emitting device includes a light-emitting element which emits light of a predetermined wavelength and a wavelength conversion portion which includes a fluorescent substance which is excited by the light emitted from the light-emitting element so as to emit fluorescence of a wavelength different from the predetermined wavelength, which wavelength conversion portion is formed by including the fluorescent substance, a layered silicate mineral, and an organometallic compound. The forming the wavelength conversion portion includes forming a fluorescent substance layer on the light-emitting element using a fluorescent substance dispersion liquid including a fluorescent substance and a layered silicate mineral, applying a precursor solution including an organometallic compound on the light-emitting element, and heating the precursor solution applied on the fluorescent substance layer. | 06-13-2013 |
20130157390 | ION IMPLANTATION METHOD AND ION IMPLANTATION APPARATUS - An ion implantation method includes transporting ions to a wafer as an ion beam, causing the wafer to undergo wafer mechanical slow scanning and also causing the ion beam to undergo beam fast scanning or causing the wafer to undergo wafer mechanical fast scanning in a direction perpendicular to a wafer slow scanning direction, irradiating the wafer with the ion beam by using the wafer slow scanning in the wafer slow scanning direction and the beam fast scanning of the ion beam or the wafer fast scanning of the wafer in the direction perpendicular to the wafer slow scanning direction, measuring a two-dimensional beam shape of the ion beam before ion implantation into the wafer, and defining an implantation and irradiation region of the ion beam by using the measured two-dimensional beam shape to thereby regulate the implantation and irradiation region. | 06-20-2013 |
20130157391 | METHODS AND SYSTEMS FOR INSPECTING BONDED WAFERS - A method of inspecting a bonded wafer | 06-20-2013 |
20130177999 | METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING IN-LINE DIAGNOSTICS PERFORMED ON LOW-K DIELECTRIC LAYERS - Methods are provided for fabricating integrated circuits. In accordance with one embodiment an integrated circuit feature is formed overlying a semiconductor substrate. A layer of low dielectric constant insulator is deposited overlying the circuit feature and is subjected to a plasma environment. Properties of the low dielectric constant material are measured by scatterometry. The low dielectric constant material is heated to drive off adsorbed water and then the properties of the material are remeasured by scatterometry. The results of the measuring and the remeasuring are compared to determine whether the low dielectric constant material was damaged by the plasma environment. | 07-11-2013 |
20130183774 | Integrated Circuit Testing Method - A method for testing an integrated circuit includes determining performance data of the integrated circuit, wherein at least first and second derivatives of S parameters of the integrated circuit are taken into account when determining the expected performance data. The performance data can be determined by measuring S parameters of the integrated circuit. An equivalent non-linear model of the integrated circuit can be determined from the provided S parameters and first and second derivatives of the provided S parameters. The non-linear behavior of the integrated circuit can be quantified from the equivalent non-linear model. | 07-18-2013 |
20130183775 | PROCESS AND DEVICE FOR PRODUCING AT LEAST ONE PHOTONIC COMPONENT - A process for producing at least one photonic component ( | 07-18-2013 |
20130203189 | SUBSTRATE TREATMENT APPARATUS, SUBSTRATE TREATMENT METHOD, AND NON-TRANSITORY STORAGE MEDIUM - A substrate treatment apparatus configured such that substrates in a same lot are distributed by a delivery mechanism into a plurality of unit blocks, each unit block including a solution treatment module, an ultraviolet irradiation module, and a substrate carrying mechanism, the apparatus includes: an illuminance detection part that detects an illuminance of a light source of the ultraviolet irradiation module; and a control part that controls, when an illuminance detection value of the ultraviolet irradiation module in one unit block among the plurality of unit blocks becomes a set value or less, the delivery mechanism to stop delivery of a substrate to the one unit block and deliver subsequent substrates to another unit block, and the ultraviolet irradiation module to perform irradiation on substrates which have already been delivered to the one unit block with an irradiation time adjusted to a length according to the illuminance detection value. | 08-08-2013 |
20130236994 | Non-Uniform Alignment of Wafer Bumps with Substrate Solders - An integrated circuit structure includes a work piece selected from the group consisting of a semiconductor chip and a package substrate. The work piece includes a plurality of under bump metallurgies (UBMs) distributed on a major surface of the work piece; and a plurality of metal bumps, with each of the plurality of metal bumps directly over, and electrically connected to, one of the plurality of UBMs. The plurality of UBMs and the plurality of metal bumps are allocated with an overlay offset, with at least some of the plurality of UBMs being misaligned with the respective overlying ones of the plurality of metal bumps. | 09-12-2013 |
20130244350 | SUBSTRATE BONDING APPARATUS AND SUBSTRATE BONDING METHOD - A substrate bonding apparatus is equipped with a first table that holds one wafer of two wafers, a stage device that holds the other wafer in an orientation capable of opposing to the one wafer and that is movable at least within an XY plane, an interferometer system that measures positional information of the stage device within the XY plane, a first mark detection system that can detect subject marks including alignment marks on the other wafer held by the stage device, and a second mark detection system fixed to a part (the second table) of the stage device that can detect subject marks including alignment marks on the one wafer held by the first table. | 09-19-2013 |
20130260484 | OPTIMIZING LIGHT EXTRACTION EFFICIENCY FOR AN LED WAFER - The present disclosure involves a method of fabricating a light-emitting diode (LED) wafer. The method first determines a target surface morphology for the LED wafer. The target surface morphology yields a maximum light output for LEDs on the LED wafer. The LED wafer is etched to form a roughened wafer surface. Thereafter, using a laser scanning microscope, the method investigates an actual surface morphology of the LED wafer. Afterwards, if the actual surface morphology differs from the target surface morphology beyond an acceptable limit, the method repeats the etching step one or more times. The etching is repeated by adjusting one or more etching parameters. | 10-03-2013 |
20130273673 | METHOD FOR FORMING LIGHT-EMITTING DEVICE - A method for forming a light-emitting device of the present application comprises providing a wafer; forming a first plurality of light-emitting elements on the wafer; providing a first connection structure to connect each of the first plurality of light-emitting elements; and applying a current flow to one of the first plurality of light-emitting elements for testing at least one electrical property of the light-emitting element while no current flow is applied to the remaining of the first plurality of light-emitting elements. | 10-17-2013 |
20130280827 | METHOD OF CONTROLLING POLISHING USING IN-SITU OPTICAL MONITORING AND FOURIER TRANSFORM - A method of controlling a polishing operation includes polishing a substrate, during polishing obtaining a sequence over time of measured spectra from the substrate with an in-situ optical monitoring system, for each measured spectrum from the sequence of measured spectra applying a Fourier transform to the measured spectrum to generate a transformed spectrum thus generating a sequence of transformed spectra, for each transformed spectrum identifying a peak of interest from a plurality of peaks in the transformed spectrum, for each transformed spectrum determining a position value for the peak of interest in the transformed spectrum thus generating a sequence of position values, and determining at least one of a polishing endpoint or an adjustment of a pressure to the substrate from the sequence of position values. | 10-24-2013 |
20130280828 | MINIMUM-SPACING CIRCUIT DESIGN AND LAYOUT FOR PICA - PICA test methods are shown that includes forming semiconductor devices having proximal light emitting regions, such that the light emitting regions are grouped into distinct shapes separated by a distance governed by a target resolution size; forming logic circuits to control the semiconductor devices; activating the one or more semiconductor devices by providing an input signal; and suppressing light emissions from one or more of the activated semiconductor devices by providing one or more select signals to the logic circuits. | 10-24-2013 |
20130280829 | GRAPHENE DEPOSITION AND GRAPHENATED SUBSTRATES - Methods, devices, systems and/or articles related to techniques for forming a graphene film on a substrate, and the resulting graphene layers and graphenated substrates are generally disclosed. Some example techniques may be embodied as methods or processes for forming graphene. Some other example techniques may be embodied as devices employed to manipulate, treat, or otherwise process substrates, graphite, graphene and/or graphenated substrates as described herein. Graphene layers and graphenated substrates produced by the various techniques and devices provided herein are also disclosed. | 10-24-2013 |
20130288403 | SYSTEMS AND METHODS OF AUTOMATICALLY DETECTING FAILURE PATTERNS FOR SEMICONDUCTOR WAFER FABRICATION PROCESSES - A system and method of automatically detecting failure patterns for a semiconductor wafer process is provided. The method includes receiving a test data set collected from testing a plurality of semiconductor wafers, forming a respective wafer map for each of the wafers, determining whether each respective wafer map comprises one or more respective objects, selecting the wafer maps that are determined to comprise one or more respective objects, selecting one or more object indices for selecting a respective object in each respective selected wafer map, determining a plurality of object index values in each respective selected wafer map, selecting an object in each respective selected wafer map, determining a respective feature in each of the respective selected wafer, classifying a respective pattern for each of the respective selected wafer maps and using the respective wafer fingerprints to adjust one or more parameters of the semiconductor fabrication process. | 10-31-2013 |
20130288404 | LIGHT EMITTING ELEMENT MANUFACTURING SYSTEM AND MANUFACTURING METHOD AND LIGHT EMITTING ELEMENT PACKAGE MANUFACTURING SYSTEM AND MANUFACTURING METHOD - In manufacturing light emitting element packages by coating the top surfaces of LED elements with the resin containing the fluorescent substance, in a resin supplying operation of discharging to supply the resin onto the LED elements in a wafer state, the light emission characteristics of the light that the resin emits when excitation light from a light source part is irradiated onto a light-passing member on which the resin is test supplied for light emission characteristic measurement are measured, and the appropriate resin supply quantity is revised based on the result of the measurement and light emission characteristics prescribed beforehand, to derive an appropriate resin supply quantity of the resin which should be supplied to the LED elements for practical production. | 10-31-2013 |
20130330847 | METHOD AND SYSTEM FOR SEMICONDUCTOR DEVICE PATTERN LOADING EFFECT CHARACTERIZATION - The present disclosure provides a method and system for characterizing a pattern loading effect. A method may include performing a reflectivity measurement on a semiconductor wafer and determining an anneal process technique based on the reflectivity measurement. The determining the anneal process technique may include determining a spatial distance for a reflectivity change using a reflectivity map generated using the reflectivity measurement. This spatial distance is compared with the thermal diffusion length associated with each of the plurality of anneal process techniques. In an embodiment, a thermal profile map and/or a device performance map may be provided. | 12-12-2013 |
20130330848 | OBSERVATION DEVICE, INSPECTION DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SUBSTRATE SUPPORT MEMBER - The present invention suppresses reductions in inspection precision caused by reflected and scattered light produced by wafer holders. In a wafer holder ( | 12-12-2013 |
20130337585 | MULTIPLE OPTICAL WAVELENGTH INTERFEROMETRIC TESTING METHODS FOR THE DEVELOPMENT AND EVALUATION OF SUBWAVELENGTH SIZED FEATURES WITHIN SEMICONDUCTOR DEVICES AND MATERIALS, WAFERS, AND MONITORING ALL PHASES OF DEVELOPMENT AND MANUFACTURE - Methods and systems for resolving and determining sub-wavelength sized features and stresses by using infrared optical and thermal wavelength probing for holographic or interferometric evaluation and testing for all phases of semiconductor device development and manufacture. Specifically, systems and methods are disclosed for extending the range of optical holographic interferometric inspection for testing and evaluating microelectronic devices and determining the interplay of electromagnetic signals and dynamic stresses to the semiconductor material in which an enhanced imaging method provides continuous and varying magnification of the optical holographic interferometric images over a plurality of interleaved optical pathways of varying optical paths and imaging devices. Electronic analysis of holographic interference patterns of varying optical probing wavelengths determines and permits the display of internal and external stresses and the various effects of such stresses acting upon the operating characteristics of semiconductor devices, features, interior structures at any stage of development or manufacture. | 12-19-2013 |
20130337586 | POLISHING METHOD - A method of polishing a substrate includes: performing a first polishing process of bringing the substrate into sliding contact with a polishing pad on a first polishing table to polish a metal film; performing a second polishing process of bringing the substrate into sliding contact with a polishing pad on a second polishing table to polish the metal film until a conductive film is exposed; performing a third polishing process of bringing the substrate into sliding contact with a polishing pad on a third polishing table to polish at least the conductive film; and performing a fourth polishing process of bringing the substrate into sliding contact with a polishing pad on a fourth polishing table to polish at least a dielectric film. | 12-19-2013 |
20130344628 | ALIGNMENT BETWEEN LAYERS OF MULTILAYER ELECTRONIC SUPPORT STRUCTURES - A process for alignment a subsequent layer over a previous layer comprising metal features or vias encapsulated in dielectric material comprising the steps of: thinning and planarizing the dielectric material to create a smooth surface of dielectric material and coplanar exposed ends of the via posts; imaging the smooth surface; discerning the position of the end of at least one feature, and using the position of the end of at least one via feature as a registration mark for aligning the subsequent layer. | 12-26-2013 |
20130344629 | IMPROVED SYSTEM FOR SUBSTRATE PROCESSING - A method of processing IC units comprising the steps of: dicing said IC units from a substrate; delivering said IC units to a idle block; inspecting a face of said units as exposed during the dicing step using an inspection device whilst said units are on said idle block, then; engaging said units with a picker assembly; passing said units over a second inspection device to inspect an opposed face of said units. | 12-26-2013 |
20140017824 | POLISHING METHOD - A method of polishing a substrate having a film is provided. The method includes: performing polishing of the substrate in a polishing section; transporting the polished substrate to a wet-type film thickness measuring device prior to cleaning and drying of the substrate; measuring a thickness of the film by the wet-type film thickness measuring device; comparing the thickness with a predetermined target value; and if the thickness has not reached the predetermined target value, performing re-polishing of the substrate in the polishing section prior to cleaning and drying of the substrate. | 01-16-2014 |
20140045281 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - Provided is a substrate processing apparatus in which flexibility of disposing a device configured to determine a holding state of a substrate and the flexibility of timing of determining the holding state are enhanced. The substrate processing apparatus includes a light projector configured to radiate detection light toward a region where a substrate may exist when the substrate is held by a substrate holding member and a light receiver configured to receive the detection light radiated from the light projector. A light path of the detection light from the light projector toward the light receiver passes a substrate surrounding member installed around the substrate held by the substrate holding member. The detection light penetrates the substrate surrounding member and has a wavelength which does not penetrate the substrate. | 02-13-2014 |
20140045282 | Using Spectra to Determine Polishing Endpoints - Methods of determining a polishing endpoint are described using spectra obtained during a polishing sequence. In particular, techniques for using only desired spectra, faster searching methods and more robust rate determination methods are described. | 02-13-2014 |
20140051190 | METHOD OF LARGE-AREA CIRCUIT LAYOUT RECOGNITION - Methods for detecting the physical layout of an integrated circuit are provided. The methods of the present disclosure allow large area imaging of the circuit layout without requiring tedious sample preparation techniques. The imaging can be performed utilizing low-energy beam techniques such as scanning electron microscopy; however, more sophisticated imaging techniques can also be employed. In the methods of the present disclosure, spalling is used to remove a portion of a semiconductor layer including at least one semiconductor device formed thereon or therein from a base substrate. In some cases, a buried insulator layer that is located beneath a semiconductor layer including the at least one semiconductor device can be completely or partially removed. In some cases, the semiconductor layer including the at least one semiconductor device can be thinned. The methods improve the detection quality that the buried insulator layer and a thick semiconductor layer can reduce. | 02-20-2014 |
20140087493 | METHOD OF MANUFACTURING OPTICAL MODULATOR, AND OPTICAL MODULATOR - A method for manufacturing an optical modulator having a laser diode section and an EAM section. LD growth layers which are semiconductor layers for manufacturing the laser diode section, are formed on a semiconductor substrate. An EAM absorption layer for forming the EAM section is then formed on the semiconductor substrate. The photoluminescent wavelength of the EAM absorption layer is then measured. The LD growth layers are then etched to form a stripe structure section. The width of the stripe structure section is determined such that the difference between the lasing wavelength of the LD section and the photoluminescent wavelength of the EAM section is close to a design value. | 03-27-2014 |
20140093986 | Optically Monitoring and Controlling Nanoscale Topography - Methods and apparatus for method for characterizing a height profile of a scattering surface relative to a fiducial plane. The scattering surface, which may be an interface between distinct solid, liquid, gaseous or plasma phases, is illuminated with substantially spatially coherent light, and light scattered by the scattering surface is collected and dispersed, such as by a grating, into zeroth- and first-order beams. A spatial Fourier transform of the zeroth- and first-order beams is created, and one of the beams is low-pass filtered. The beams are interfered at a focal plane detector to generate an interferogram, which is transformed to retrieve a spatially resolved quantitative phase image and/or an amplitude image of the scattering surface. Imaging may be performed during an etching process, and may be used to adaptively control a photoetching process in a feedback loop. | 04-03-2014 |
20140093987 | Residue Detection with Spectrographic Sensor - Detecting residue of a filler material over a patterned underlying layer includes causing relative motion between a probe of an optical metrology system and a substrate, obtaining a plurality of measured spectra with the optical metrology system through the probe from a plurality of different measurement spots within an area on the substrate, comparing each of the plurality of measured spectra to a reference spectrum to generate a plurality of similarity values, the reference spectrum being a spectrum reflected from the filler material, combining the similarity values to generate a scalar value, and determining the presence of residue based on the scalar value. | 04-03-2014 |
20140113390 | Method for Producing Singulated Semiconductor Devices - A method for producing singulated semiconductor components includes providing a starting substrate. An etching process is carried out to form depressions at a side of the starting substrate. The depressions are arranged in the region of the semiconductor components to be produced. Walls present between the depressions are arranged in the region of separating regions provided for severing the starting substrate. The method furthermore comprises forming a metallic layer on the side of the starting substrate with the depressions and walls and carrying out a further etching process for severing the starting substrate in the separating regions and forming the singulated semiconductor components. | 04-24-2014 |
20140120637 | Process for Growing at Least One Nanowire Using a Transition Metal Nitride Layer Obtained in Two Steps - The process for growing at least one semiconductor nanowire ( | 05-01-2014 |
20140120638 | APPARATUS AND METHOD FOR REMOVING DEFECT - An apparatus for removing a defect according to the embodiment includes an image processing part for observing a surface of a substrate; a layer forming part for forming a layer on the surface of the substrate; and a humidity controlling part for controlling humidity in a chamber in which the substrate is placed. A method for removing a defect according to the embodiment includes detecting the defect on a surface of a substrate; forming an oxide layer by oxidizing the defect; and removing the oxide layer. A method for removing a defect according to another embodiment includes forming an oxide layer on an entire surface of a substrate; and removing the oxide layer to remove the defect. | 05-01-2014 |
20140162383 | MANUFACTURING METHOD FOR SOLAR CELL AND SOLAR CELL MANUFACTURING SYSTEM - The invention includes: a first process of forming a texture structure on both surfaces of a semiconductor substrate of a first conductivity type; a second process of measuring a reflectance distribution of the both surfaces of the semiconductor substrate on which the texture structure is formed; a third process of forming an impurity diffusion layer, in which an impurity element of a second conductivity type is diffused, on one of the both surfaces of the semiconductor substrate which is narrower in the reflectance distribution; a fourth process of forming, on the impurity diffusion layer, a light receiving surface-side electrode having a predetermined pattern and electrically connected to the impurity diffusion layer; and a fifth process of forming a back surface-side electrode on another of the both surfaces of the semiconductor substrate which is wider in the reflectance distribution. | 06-12-2014 |
20140199792 | DEFECT PATTERN EVALUATION METHOD, DEFECT PATTERN EVALUATION APPARATUS, AND RECORDING MEDIA - According to a defect pattern evaluation method of an embodiment, defects are detected by performing optical defect inspection on a pattern on a substrate. Then, the defects are classified according to a type of a pattern layout using a pattern layout corresponding to coordinates of the defects. Further, a computer calculates a defect occurrence rate by dividing the number of defects of each pattern layout by an arrangement number of the pattern layouts in an inspection region. Then, the defect occurrence rate of each pattern layout is output as an evaluation result. | 07-17-2014 |
20140206110 | Etchant and Etching Process - A system and method of etching a semiconductor device are provided. Etching solution is sampled and analyzed by a monitoring unit to determine a concentration of components within the etching solution, such as an oxidant concentration. Then, based upon such measurement, a makeup amount of the components may be added be a makeup unit to the etching solution to control the concentration of the components within the etching system. | 07-24-2014 |
20140206111 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - To improve the performance of a semiconductor device, a semiconductor device manufacturing method includes an exposing process of performing pattern exposure of a resist film formed on a substrate by using EUV light reflected from a front surface of an EUV mask as a reflective mask. In this exposing process, the resist film is subjected to pattern exposure by repeating a process of irradiating the resist film with the EUV light by changing a focal position of the EUV light with which the resist film is irradiated, along a film thickness direction of the resist film. After this exposing process, the resist film subjected to pattern exposure is developed to form a resist pattern. | 07-24-2014 |
20140206112 | METHOD FOR REDUCING CHARGE IN CRITICAL DIMENSION-SCANNING ELECTRON MICROSCOPE METROLOGY - Methods and compositions are provided for reducing or eliminating charge buildup during scanning electron microscopy (SEM) metrology of a critical dimension (CD) in a structure produced by lithography. An under layer is utilized that comprises silicon in the construction of the structure. When the lithography structure comprising the silicon-comprising under layer is scanned for CDs using SEM, the under layer reduces or eliminates charge buildup during SEM metrological observations. | 07-24-2014 |
20140234993 | STI CMP UNDER POLISH MONITORING - Methods of deducing oxide thickness using calculated and measured scattering spectra are provided. Embodiments include depositing an oxide over a semiconductor wafer, reducing the oxide from a portion of the semiconductor wafer, and deducing a thickness of oxide remaining at a location within the portion using scatterometric metrology. Embodiments further include deducing the thickness by: calculating scattering spectra for a plurality of oxide thicknesses, producing calculated scattering spectra, monitoring scattering spectra at the location within the portion of the semiconductor wafer, comparing the monitored scattering spectra at the location to the calculated scattering spectra, determining a closest matching calculated scattering spectra to the monitored scattering spectra at the location, and obtaining an oxide thickness corresponding to the closest matching calculated scattering spectra. | 08-21-2014 |
20140234994 | INSPECTION METHOD FOR SEMICONDUCTOR LIGHT-EMITTING DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR LIGHT-EMITTING DEVICE - An inspection method for a semiconductor light-emitting device includes an image capturing step for capturing an image of photoluminescence released from the active layer, an inspection region extracting step for extracting an inspection region from the captured image; a luminance average determination step for, determining the semiconductor light emitting device as defective when a luminance average is smaller than a predetermined threshold, a luminance variance determination step for determining the semiconductor light emitting device as defective when a luminance variance is larger than a predetermined threshold, a color determination step for determining the semiconductor light-emitting device as defective when a pixel in which a color component indicating a photoluminescence intensity of light released from the active layer and having a wavelength shorter than the original emitting wavelength, and a total determination step for totally determining the semiconductor light-emitting device as defective when determined in at least one of these determination results within the inspection region. | 08-21-2014 |
20140242735 | Method for Aligning a Biochip - A method of aligning a semiconductor chip includes forming a semiconductor chip with a light-activated circuit including at least one photosite, positioning the semiconductor chip relative to a device, and illuminating the positioned semiconductor chip. The method further includes generating an RF signal with an RF circuit based upon illumination of the at least one photosite, and determining the position of the photosite with respect to the device based upon the generated RF signal. | 08-28-2014 |
20140256068 | ADJUSTABLE LASER PATTERNING PROCESS TO FORM THROUGH-HOLES IN A PASSIVATION LAYER FOR SOLAR CELL FABRICATION - Embodiments of the invention contemplate formation of a high efficiency solar cell utilizing an adjustable or optimized laser patterning process to form openings with different geometry in a passivation layer disposed on a substrate based on different film properties in the passivation layer and the substrate. In one embodiment, a method of forming a solar cell includes transferring a substrate having a passivation layer formed on a back surface of a substrate into a laser patterning apparatus, performing a substrate inspection process by a detector disposed in the laser patterning apparatus, determining a laser patterning recipe configured to form openings in the passivation layer based on information obtained from the substrate inspection process, and performing a laser patterning process on the passivation layer using the determined laser patterning recipe. | 09-11-2014 |
20140273308 | METHOD OF MEASURING SURFACE PROPERTIES OF POLISHING PAD - The present invention relates to a method of measuring surface properties of a polishing pad which measures surface properties such as surface topography or surface condition of a polishing pad used for polishing a substrate such as a semiconductor wafer. The method of measuring surface properties of a polishing pad includes applying a laser beam to the polishing pad, detecting scattered light that is reflected and scattered by the polishing pad with a photodetector and performing an optical Fourier transform on the detected scattered light to produce an intensity distribution corresponding to a spatial wavelength spectrum based on surface topography of the polishing pad, and calculating a numerical value representing surface properties of the polishing pad based on the intensity distribution corresponding to two different prescribed spatial wavelength ranges. | 09-18-2014 |
20140273309 | Controlling Radical Lifetimes in a Remote Plasma Chamber - Remote-plasma treatments of surfaces, for example in semiconductor manufacture, can be improved by preferentially exposing the surface to only a selected subset of the plasma species generated by the plasma source. The probability that a selected species reaches the surface, or that an unselected species is quenched or otherwise converted or diverted before reaching the surface, can be manipulated by introducing additional gases with selected properties either at the plasma source or in the process chamber, varying chamber pressure or flow rate to increase or decrease collisions, or changing the dimensions or geometry of the injection ports, conduits and other passages traversed by the species. Some example processes treat surfaces preferentially with relatively low-energy radicals, vary the concentration of radicals at the surface in real time, or clean and passivate in the same unit process. | 09-18-2014 |
20140273310 | MONITORING PATTERN FOR DEVICES - Reticle and methods for forming a device or reticle are presented. A reticle is provided with a device pattern and a first monitoring pattern. The first monitoring pattern includes a plurality of first test cells having a first test cell area and a first test pattern. The first test cells have different first pitch ratios to an anchor pitch and the first test pattern fills the first test cell area of a first test cell. A wafer with a resist layer is exposed with a lithographic system using the reticle. The resist is developed to form a patterned resist layer on the wafer and the wafer is processed using the patterned resist layer. | 09-18-2014 |
20140273311 | Optical Absorbers - Optical absorbers and methods are disclosed. The methods comprise depositing a plurality of precursor layers comprising one or more of Cu, Ga, and In on a substrate, and heating the layers in a chalcogenizing atmosphere. The plurality of precursor layers can be one or more sets of layers comprising at least two layers, wherein each layer in each set of layers comprises one or more of Cu, Ga, and In exhibiting a single phase. The layers can be deposited using two or three targets selected from Ag and In containing less than 21% In by weight, Cu and Ga where the Cu and Ga target comprises less than 45% Ga by weight, Cu(In,Ga), wherein the Cu(In,Ga) target has an atomic ratio of Cu to (In+Ga) greater than 2 and an atomic ratio of Ga to (Ga+In) greater than 0.5, elemental In, elemental Cu, and In | 09-18-2014 |
20140273312 | PIN HOLE EVALUATION METHOD OF DIELECTRIC FILMS FOR METAL OXIDE SEMICONDUCTOR TFT - The present invention generally relates to methods measuring pinhole determination. In one aspect, a method of measuring pinholes in a stack, such as a TFT stack, is provided. The method can include forming an active layer on a deposition surface of a substrate, forming a dielectric layer over the active layer, delivering an etchant to at least the dielectric layer, to etch both the dielectric layer and any pinholes formed therein and optically measuring the pinhole density of the etched dielectric layer using the active layer. | 09-18-2014 |
20140273313 | METHOD AND APPARATUS PROVIDING INLINE PHOTOLUMINESCENCE ANALYSIS OF A PHOTOVOLTAIC DEVICE - A method and apparatus are disclosed which use a photoluminescent light intensity signature to characterize a processed photovoltaic substrate. | 09-18-2014 |
20140295583 | PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD - In a plasma processing method and apparatus for processing a film to be processed contained in a film structure preliminarily formed on an upper surface of a wafer mounted in a processing chamber, by using plasma, a residual film thickness at an arbitrary time is calculated using a result of comparing detective differential waveform pattern data with actual differential waveform pattern data. The detective differential waveform pattern data is produced by using two basic differential waveform pattern data which respectively use, as parameters, residual thicknesses of the films to be processed in film structures having underlying films with different thicknesses and the wavelengths of the interference light. The detective waveform pattern data being preliminarily prepared prior to processing of the wafer. Determination is made as to whether or not an object of the processing has been reached by using the residual film thickness. | 10-02-2014 |
20140315333 | Apparatus and Method for Monitoring a Thickness of a Silicon Wafer with a Highly Doped Layer - Apparatus for monitoring a thickness of a silicon wafer with a highly-doped layer at least at a backside of the silicon wafer is provided. The apparatus has a source configured to emit coherent light of multiple wavelengths. Moreover, the apparatus comprises a measuring head configured to be contactlessly positioned adjacent the silicon wafer and configured to illuminate at least a portion of the silicon wafer with the coherent light and to receive at least a portion of radiation reflected by the silicon wafer. Additionally, the apparatus comprises a spectrometer, a beam splitter and an evaluation device. The evaluation device is configured to determine a thickness of the silicon wafer by analyzing the radiation reflected by the silicon wafer by an optical coherence tomography process. The coherent light is emitted multiple wavelengths in a bandwidth b around a central wavelength w | 10-23-2014 |
20140329343 | METHOD AND SYSTEM FOR MONITORING CRYSTALLIZATION OF AMORPHOUS SILICON THIN FILM, AND METHOD OF MANUFACTURING THIN FILM TRANSISTOR BY USING THE METHOD AND SYSTEM - A method and system for monitoring crystallization of an amorphous silicon (a-Si) thin film, and a method of manufacturing a thin film transistor (TFT) by using the method and system are disclosed. The method of monitoring the crystallization of the a-Si thin film includes: irradiating light from a light source onto a monitoring a-Si thin film to anneal the monitoring a-Si thin film; annealing the monitoring a-Si thin film and concurrently measuring a Raman scattering spectrum of light scattered by the monitoring a-Si thin film at set time intervals; and calculating a crystallization characteristic value of the monitoring a-Si thin film based on the Raman scattering spectrum. | 11-06-2014 |
20140342477 | METHOD OF MONITORING SEMICONDUCTOR FABRICATION PROCESS USING XPS - A method of monitoring a semiconductor fabrication process including forming a barrier pattern on a substrate, forming a sacrificial pattern on the barrier pattern, removing the sacrificial pattern to expose a surface of the barrier pattern, generating photoelectrons by irradiating X-rays to a surface of the substrate, and inferring at least one material existing on the surface of the substrate by collecting and analyzing the photoelectrons may be provided. | 11-20-2014 |
20140349419 | METHOD OF MANUFACTURING LIGHT-EMITTING DEVICE - A method of manufacturing a light-emitting device includes forming a wave length conversion portion on a light-emitting element. The light emitting device includes a light-emitting element which emits light of a predetermined wavelength and a wavelength conversion portion which includes a fluorescent substance which is excited by the light emitted from the light-emitting element so as to emit fluorescence of a wavelength different from the predetermined wavelength, which wavelength conversion portion is formed by including the fluorescent substance, a layered silicate mineral, and an organometallic compound. The forming the wavelength conversion portion includes forming a fluorescent substance layer on the light-emitting element using a fluorescent substance dispersion liquid including a fluorescent substance and a layered silicate mineral, applying a precursor solution including an organometallic compound on the light-emitting element, and heating the precursor solution applied on the fluorescent substance layer. | 11-27-2014 |
20140356988 | Mechanical Debonding Method and System - A mechanical debonding method and system are provided. A mechanical debonding method, used to debond temporary bonding wafers formed by bonding a device wafer and a carrier wafer by an adhesive, includes: obtaining the height position of the adhesive through a thickness measurement apparatus; moving a cutting apparatus to a position between the device wafer and the carrier wafer based on the height position of the adhesive, then removing the adhesive at the edge of the temporary bonding wafers by the cutting apparatus; removing the carrier wafer from the temporary bonding wafers; cleaning the adhesive left on the surface of the device wafer. | 12-04-2014 |
20140370627 | MONITORING LASER PROCESSING OF SEMICONDUCTORS BY RAMAN SPECTROSCOPY - A Raman probe is used to detect crystal structure of a substrate undergoing thermal processing in a thermal processing system. The Raman probe may be coupled to a targeting system of a laser thermal processing system. The Raman probe includes a laser positioned to direct probe radiation through the targeting system to the substrate, a receiver attuned to Raman radiation emitted by the substrate, and a filter that blocks laser radiation reflected by the substrate. The Raman probe may include more than one laser, more than one receiver, and more than one filter. The Raman probe may provide more than one wavelength of incident radiation to probe the substrate at different depths. | 12-18-2014 |
20140370628 | SUBSTRATE PROCESSING APPARATUS, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, SUBSTRATE PROCESSING METHOD, AND RECORDING MEDIUM - According to the present disclosure, it is possible to prevent particles from being generated and to improve substrate processing quality. A substrate processing apparatus includes cassette mounting unit on which process substrate cassette and dummy substrate cassette are mounted, the process substrate cassette being configured to accommodate a plurality of process substrates, and the dummy substrate cassette being configured to accommodate a plurality of dummy substrates, process chamber configured to process the process substrates and the dummy substrates, substrate support unit installed within the process chamber and provided with a plurality of substrate mounting portions where the process substrates and the dummy substrates are mounted, transfer unit configured to transfer the process substrates and the dummy substrates between the cassette mounting unit and the process chamber, and control unit configured to control substrate processing and to transfer processing of the process substrates and the dummy substrates. | 12-18-2014 |
20140377890 | APPARATUS FOR MONITORING DEPOSITION RATE, APPARATUS PROVIDED WITH THE SAME FOR DEPOSITING ORGANIC LAYER, METHOD OF MONITORING DEPOSITION RATE, AND METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DISPLAY APPARATUS USING THE SAME - An apparatus for monitoring deposition rate, an apparatus including the same, for depositing an organic layer, a method of monitoring deposition rate, and a method of manufacturing an organic light emitting display apparatus using the same, are provided. The deposition rate monitoring apparatus for measuring deposition rate of a deposition material discharged from a deposition source, includes: a light source for irradiating light having a wavelength within a photoexcitation bandwidth of the deposition material; a first optical system for irradiating the light emitted from the light source toward the discharged deposition material; a second optical system for collecting the light emitted from the deposition material; and a first light sensor for detecting the amount of the light which is emitted from the deposition material and collected in the second optical system. | 12-25-2014 |
20150011027 | 3D NAND STAIRCASE CD CONTROL BY USING INTERFEROMETRIC ENDPOINT DETECTION - Embodiments of the present disclosure provide methods for forming stair-like structures with accurate profiles control in manufacturing three dimensional (3D) stacking of semiconductor chips using precise photoresist trimming process endpoint control. In one example, a method of determining a photoresist trimming endpoint for forming stair-like structures on a substrate includes performing a trimming process on a substrate to trim a patterned photoresist layer disposed on a film stack from a first width to a second width in a processing chamber, wherein the patterned photoresist layer exposes a portion of the film stack uncovered by the patterned photoresist layer during the trimming process, directing an optical signal to a surface of the patterned photoresist layer while trimming the patterned photoresist layer, collecting a return reflected optical signal reflected from the photoresist layer, and determining a trimming endpoint by analyzing the return optical signal reflected from the photoresist layer. | 01-08-2015 |
20150024521 | PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD - There is provided a plasma processing apparatus which compares a plurality of patterns detected using an interference light intensity pattern using a wavelength from at least one preset film of the plurality of film layers as a parameter and an intensity pattern using a wavelength of light from the other film as a parameter and an light intensity pattern from inside the processing chamber which is detected during processing of the film to be processed; and compares a film thickness corresponding to one of the plurality of patterns having a minimum difference obtained by the comparison and a target film thickness; and determines that the thickness of the film to be processed reaches the target film thickness. | 01-22-2015 |
20150037915 | METHOD AND SYSTEM FOR LASER FOCUS PLANE DETERMINATION IN A LASER SCRIBING PROCESS - In embodiments, a method of laser scribing a mask disposed over a semiconductor wafer includes determining a height of the semiconductor over which a mask layer is disposed prior to laser scribing the mask layer. In one embodiment the method includes: determining a height of the semiconductor wafer under the mask in a dicing street using an optical sensor and patterning the mask with a laser scribing process. The laser scribing process focuses a scribing laser beam at a plane corresponding to the determined height of the semiconductor wafer in the dicing street. Examples of determining the height of the semiconductor wafer can include directing a laser beam to the dicing street of the semiconductor wafer, which is transmitted through the mask and reflected from the wafer, and identifying an image on a surface of the wafer under the mask with a camera. | 02-05-2015 |
20150050756 | METHOD OF MANUFACTURING ORGANIC LIGHT-EMITTING DISPLAY APPARATUS - A method of manufacturing an organic light-emitting display apparatus includes providing an organic light-emitting device including a first electrode, a second electrode and an intermediate layer including an organic emission layer, on a substrate; forming a pre-thin film encapsulation layer including an inorganic layer including a low temperature viscosity (“LVT”) inorganic material, on the organic light-emitting device; and selectively irradiating a beam having certain energy to a local area of the pre-thin film encapsulation layer. | 02-19-2015 |
20150064813 | MICROPROCESSOR IMAGE CORRECTION AND METHOD FOR THE DETECTION OF POTENTIAL DEFECTS - Systems and methods are provided for developing usable chip images in order to detect and screen defects or anomalies in a manufacturing environment. More specifically, a method is provided for manufacturing at least one wafer or chip. The method includes obtaining image data of the at least one wafer or chip. The method further includes correcting the image data to remove normal variation within the image data. The method further includes comparing the corrected image data to image data for at least one other wafer or chip to determine whether the corrected image data for the at least one wafer or chip shows a defect or anomaly beyond that of the normal variation. The method further includes placing the at least one wafer or chip into a category of fabrication based on the comparison. | 03-05-2015 |
20150104889 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, SEMICONDUCTOR MANUFACTURING AND INSPECTING APPARATUS, AND INSPECTING APPARATUS - A semiconductor device having Cu wiring including a basic crystal structure which can reduce surface voids, and an inspecting technique for the semiconductor device. In the semiconductor device, surface voids can be reduced down to 1/10 or less of a current practical level by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 27 or less to all crystal grain boundaries of a Cu wiring to 60% or higher. Alternatively, a similar effect of surface void reduction can be obtained by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 3 to all crystal grain boundaries of a Cu wiring to 40% or higher. | 04-16-2015 |
20150111319 | METHOD AND SYSTEM FOR ELIMINATING YELLOW RING OCCURRING ON WHITE LIHGT EMITTING DIODE - Disclosed are a method and system for eliminating yellow ring phenomenon occurring on the white light emitting diode (LED) based on a blue light chip exciting yellow phosphor powders and having a packaging surface enclosing thereon. Lightspot images are repeatedly acquired outside the white LED, and then each analyzed to see if the yellow ring still exists on a lightspot. If yes, a further atomization process is performed on the packaging surface of white LED, until the acquired and analyzed image shows no yellow ring exists. A lightspot-by-lightspot basis is used in the yellow ring elimination task. In the image analysis, a look up table may be provided in advanced or established at the same time simultaneously with the yellow ring elimination task. The atomization performed on the lightspot may also consider a width issue. | 04-23-2015 |
20150118767 | METHOD OF MANUFACTURING EL DISPLAY DEVICE - A method of manufacturing an EL display device having a light emitting part, in which a plurality of pixels are arrayed, and a thin-film transistor array device to control light emission of the light emitting part, includes a luminance measurement step of obtaining luminance data of pixel, with the light emitting part being lit. The luminance measurement step includes a first luminance measurement step and a second luminance measurement step. In the first luminance measurement step, a first imaging apparatus obtains luminance data by measuring light emission of the each pixel. The first apparatus has a resolution corresponding to that of the pixels of the light emitting part. In the second luminance measurement step after the first step, a second imaging apparatus measures light emission of a plurality of the pixels to correct the luminance data of the each pixel obtained in the first luminance measurement step. The second imaging apparatus is lower in resolution than the first imaging apparatus. | 04-30-2015 |
20150125971 | POLISHING APPARATUS AND POLISHING METHOD - A polishing apparatus capable of monitoring an accurate progress of polishing is disclosed. The polishing apparatus includes: a polishing table for supporting a polishing pad; a table motor configured to rotate the polishing table; a top ring configured to press a substrate against the polishing pad to polish the substrate; a dresser configured to dress the polishing pad while oscillating on the polishing pad during polishing of the substrate; a filtering device configured to remove a vibration component, having a frequency corresponding to an oscillation period of the dresser, from an output current signal of the table motor; and a polishing monitoring device configured to monitor a progress of polishing of the substrate based on the output current signal from which the vibration component has been removed. | 05-07-2015 |
20150295177 | DISPLAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A display substrate and a method of manufacturing the same. The display substrate includes a substrate including an active area and an inactive area, an organic light-emitting diode (OLED) unit disposed on the active area of the substrate, and a transmittance measurement pattern unit disposed on the inactive area of the substrate. The transmittance measurement pattern unit includes a deposition assistant layer pattern disposed on the substrate. | 10-15-2015 |
20150318220 | PLASMA PROCESSING APPARATUS AND MEASUREMENT METHOD - There is provided a plasma processing apparatus, which includes: a processing chamber into which a target substrate is loaded and in which a dopant is implanted into the target substrate using a plasma of a gas which contains an element used as the dopant; a wall probe configured to measure a change in voltage corresponding to a density of charged particles in the plasma generated within the processing chamber; an OES (Optical Emission Spectrometer) configured to measure a light emission intensity of the dopant existing in the plasma; and a calculation unit configured to calculate a dose amount of the dopant implanted into the target substrate, based on a measurement result obtained at the wall probe and a measurement result obtained at the OES. | 11-05-2015 |
20150362373 | DETERMINING THERMAL PROFILES OF SEMICONDUCTOR STRUCTURES - According to embodiments of the present invention, a semiconductor substrate is formed on at least a portion of a surface of a semiconductor substrate. The emitting layer is excited for a first predetermined time period. A first luminescent intensity value of the emitting layer is determined. In response to exposing the semiconductor substrate and the emitting layer to a condition for a second predetermined time period, a second luminescent intensity value of the emitting layer is determined. A thermal profile of at least the portion of the surface of the semiconductor substrate is determined utilizing the first luminescent intensity value and the second luminescent intensity value of the emitting layer. The thermal profile at least reflects information about one or more of the condition and the semiconductor substrate subsequent to exposure to the condition. | 12-17-2015 |
20150364383 | METHOD OF CALIBRATING OR EXPOSING A LITHOGRAPHY TOOL - A method of calibrating or monitoring an exposing tool including forming a substrate pattern in a substrate, wherein forming the substrate pattern includes providing a first patterned photo resist layer having an etch coating layer disposed thereon and using the first patterned photo resist layer and the etch coating layer to pattern an underlying layer. The patterned underlying layer is then used as a masking element when etching the substrate pattern into the substrate. A second photo resist pattern is formed over the substrate pattern. An overlay measurement is executed of the second photo resist pattern to the substrate pattern. | 12-17-2015 |
20150364644 | METHOD AND APPARATUS FOR FABRICATING LIGHT EMITTING APPARATUS - A method for fabricating a light emitting apparatus in which at least a portion of a light emitting element is covered with a light transmissive resin containing phosphor which emits light when excited by light emitted by the light emitting element, the method including directly processing the phosphor by irradiating the phosphor with a laser beam which passes through the light transmissive resin, to adjust the chromaticity of light to be emitted by the light emitting apparatus. | 12-17-2015 |
20150380320 | TEST PATTERN FOR FEATURE CROSS-SECTIONING - A method includes forming a first plurality of instances of a first pattern on a substrate. The first pattern includes a plurality of features defining a first spacing between features in a first direction. The instances in the first plurality are offset from one another at least in a second direction other than the first direction. The substrate is cleaved along a cleavage line. At least a first critical dimension of a feature in the first plurality of instances intersected by the cleavage line is measured. | 12-31-2015 |
20160005661 | LIGHT EXPOSURE CONDITION ANALYSIS METHOD, NONTRANSITORY COMPUTER READABLE MEDIUM STORING A LIGHT EXPOSURE CONDITION ANALYSIS PROGRAM, AND MANUFACTURING METHOD FOR A SEMICONDUCTOR DEVICE - According to one embodiment, a pattern formed through light exposure is observed under two or more different optical conditions, and a focus shift and exposure amount in the light exposure are estimated based on a brightness value of the pattern under each of the optical conditions. | 01-07-2016 |
20160020155 | LIGHT SOURCE TESTING APPARATUS, TESTING METHOD OF LIGHTING SOURCE AND MANUFACTURING METHOD OF LIGHT-EMITTING DEVICE PACKAGE, LIGHT EMITTING MODULE, AND ILLUMINATION APPARATUS USING THE SAME - A method of fabricating a light source includes providing a semiconductor light source emitting light when power is applied thereto, supplying power to the semiconductor light source, receiving light emitted by the semiconductor light source and performing a first measurement of optical properties of the received light, receiving light emitted by the semiconductor light source after a period of time has elapsed from the first measurement and performing a second measurement of optical properties of the received light, determining whether the semiconductor light source is defective or not by comparing the results of the first measurements of optical properties and the second measurements of optical properties, and constructing the light source including the semiconductor light source by providing peripheral parts thereof, wherein the semiconductor light source is determined as being normal as a result of determining whether the semiconductor light source is defective or not. | 01-21-2016 |
20160020366 | METHOD OF MANUFACTURING LIGHT-EMITTING DEVICE PACKAGE - A method of manufacturing a light-emitting device package may include steps of preparing a light-emitting device package; holding the light-emitting device package on an inspection table; reflecting, by a reflection member, leaking blue light emitted by the light-emitting device package; capturing, by using a photographing unit, the light emitted by the light-emitting device package and the leaking blue light and generating an optical image; detecting, by a controller, the blue light from the optical image; determining a presence or absence of a defect of the light-emitting device package according to the detected blue light; and displaying the presence or absence of the defect of the light-emitting device package on a display unit. | 01-21-2016 |
20160027674 | Carousel Gas Distribution Assembly With Optical Measurements - Apparatus and methods for processing a semiconductor wafer in which an optical sensor positioned in the gas distribution assembly measures temperature and/or a film parameter during deposition. | 01-28-2016 |
20160035631 | Atomic Layer Deposition of HfAlC as a Metal Gate Workfunction Material in MOS Devices | 02-04-2016 |
20160042985 | SUBSTRATE PROCESSING APPARATUS - A substrate processing apparatus includes a mounting unit on which a substrate is mounted, a light generation and detection unit that forms an optical path parallel to a surface of the substrate at a location separated from the surface of the substrate by a predetermined distance and is capable of detecting shielding of the optical path, and a control unit that controls movement of at least one of the mounting unit and the optical path to control relative movement between the optical path and the substrate in a state where parallelism between the optical path and the surface of the substrate is maintained. | 02-11-2016 |
20160061722 | METHOD FOR DETECTING RESISTANCE OF A PHOTO RESIST LAYER - The present disclosure provides a method for detecting resistance of a photo resist layer. The method includes: providing a silicon wafer and measuring a refractive index of a surface of the silicon wafer as an initial refractive index of the surface of the silicon wafer; forming photo resist layers with different thicknesses on the surface of the silicon wafer; performing ion-implantation on the photo resist layers by predetermined amounts; peeling off the photo resist layers from the surface of the silicon wafer; and testing the refractive indexes of different areas on the surface of the silicon wafer after the ion-implantation, on which the photo resist layers with different thicknesses are located and determining the resistance of the photo resist layers with different thicknesses in contrast to the initial refractive index before the ion-implantation. | 03-03-2016 |
20160071726 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a resist pattern on a first film to be processed by using photolithography, forming a dummy pattern on the first film by using a three-dimensional modeling machine, such as a three-dimensional printer. The dummy pattern is provided on a region of the first film that is not occupied by the resist pattern. The first film is then etched using the resist pattern and the dummy pattern as a mask. A second film is then formed on the etched first film and subsequently flattened/planarized using, for example, chemical mechanical polishing. | 03-10-2016 |
20160071746 | SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD - According to one embodiment, a substrate processing apparatus ( | 03-10-2016 |
20160086792 | METHOD FOR EVALUATING SEMICONDUCTOR FILM AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for evaluating a semiconductor film of a semiconductor device which is configured to include an insulating film, the semiconductor film, and a conductive film and to have a region where the semiconductor film and the conductive film overlap with each other with the insulating film provided therebetween, includes a step of performing plasma treatment after formation of the insulating film, and a step of calculating a peak value of resistivity of a microwave in the semiconductor film by a microwave photoconductive decay method after the plasma treatment, so that the hydrogen concentration in the semiconductor film is estimated. | 03-24-2016 |
20160099147 | GAS FLOW PROFILE MODULATED CONTROL OF OVERLAY IN PLASMA CVD FILMS - Methods for modulating local stress and overlay error of one or more patterning films may include modulating a gas flow profile of gases introduced into a chamber body, flowing gases within the chamber body toward a substrate, rotating the substrate, and unifying a center-to-edge temperature profile of the substrate by controlling the substrate temperature with a dual zone heater. A chamber for depositing a film may include a chamber body comprising one or more processing regions. The chamber body may include a gas distribution assembly having a blocker plate for delivering gases into the one or more processing regions. The blocker plate may have a first region and a second region, and the first region and second region each may have a plurality of holes. The chamber body may have a dual zone heater. | 04-07-2016 |
20160099388 | METHOD OF FABRICATING LIGHT-EMITTING DEVICE PACKAGE - A method of fabricating a light-emitting device package includes preparing a carrier including a first surface and a second surface disposed opposite the first surface, forming a phosphor layer on the first surface of the carrier, emitting first light from a test light-emitting device toward the second surface of the carrier, analyzing second light passing through the phosphor layer, and determining a thickness of the phosphor layer based on the analysis. | 04-07-2016 |
20160111307 | INTEGRATED SUBSTRATE DEFECT DETECTION USING PRECISION COATING - Apparatuses and methods for improved substrate defect detection is provided. Substrate defects may be detected, possibly with defect detection equipment such as laser metrology equipment. Defects smaller than the detection limit of the detection equipment may be decorated with a layer of material to increase the effective sizes of the defects. The thickness and composition of the material deposited may be tuned depending on the composition of the substrate and the defects. The composition of the detected defects may be identified with defect identification equipment. The defect identification equipment may be an electron generating apparatus and the composition of the defects may be identified from the interaction of the electrons with the defect. The deposited material may be removed either before or during the defect identification phase to aid in the identification of the defect composition. | 04-21-2016 |
20160116412 | METHOD AND SYSTEM FOR INSPECTING INDIRECT BANDGAP SEMICONDUCTOR STRUCTURE | 04-28-2016 |
20160131838 | HYBRID PHOTONIC AND ELECTRONIC INTEGRATED CIRCUITS - A sequence of processing steps presented herein is used to embed an optical signal path within an array of nanowires, using only one lithography step. Using the techniques disclosed, it is not necessary to mask electrical features while forming optical features, and vice versa. Instead, optical and electrical signal paths can be created substantially simultaneously in the same masking cycle. This is made possible by a disparity in the widths of the respective features, the optical signal paths being significantly wider than the electrical ones. Using a damascene process, the structures of disparate widths are plated with metal that over-fills narrow trenches and under-fills a wide trench. An optical cladding material can then be deposited into the trench so as to surround an optical core for light transmission. | 05-12-2016 |
20160141213 | AUTOMATED OPTICAL INSPECTION OF UNIT SPECIFIC PATTERNING - A method of automated optical inspection (AOI) for a plurality of unique semiconductor packages can comprise providing a plurality of semiconductor die formed as a reconstituted wafer. A plurality of unit specific patterns can be formed by forming a unit specific pattern over each of the plurality of semiconductor die, wherein each of the unit specific patterns is customized to fit its respective semiconductor die. A plurality of images can be acquired by acquiring an image for each of the plurality of unit specific patterns. A plurality of unique reference standards can be created by creating a unique reference standard for each of the plurality of unit specific patterns. Defects can be detected in the plurality of unit specific patterns by comparing one of the plurality of unique reference standards to a corresponding one of the plurality of images for each of the plurality of unit specific patterns. | 05-19-2016 |
20160148817 | GALLIUM NITRIDE SUBSTRATE AND OPTICAL DEVICE USING THE SAME - A method of processing a gallium nitride substrate, includes providing a gallium nitride substrate, polishing a surface of the gallium nitride substrate, and cleaning the polished surface of the gallium nitride substrate. The polished surface includes a GaLα/CKα peak intensity ratio in energy dispersive X-ray microanalysis (EDX) spectrum which is not less than 2, the EDX spectrum being obtained in an EDX of the surface of the gallium nitride substrate using a scanning electron microscope (SEM) at an accelerating voltage of 3 kV. | 05-26-2016 |
20160181165 | METHOD AND APPARATUS FOR REAL-TIME MONITORING OF PLASMA ETCH UNIFORMITY | 06-23-2016 |
20160190020 | SEMICONDUCTOR INSPECTION METHOD, SEMICONDUCTOR INSPECTION DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR ELEMENT - In a semiconductor inspection method using a semiconductor inspection device, by selecting an incident energy and a negative potential and scanning an inspection surface of a wafer with primary electrons to detect secondary electrons, a first inspection image is acquired, and a macro defect, stacking faults, a basal plane dislocation and a threading dislocation contained in the first inspection image are discriminated by image processing based on a threshold value of a signal amount of the secondary electrons determined in advance. Moreover, by selecting the incident energy and a positive potential and scanning the inspection surface of the wafer with primary electrons to detect the secondary electrons, a second inspection image is acquired, and a threading screw dislocation of a dot-shaped figure contained in the second inspection image is discriminated by image processing based on a threshold value of a signal amount of the secondary electrons determined in advance. | 06-30-2016 |
20160204042 | METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE | 07-14-2016 |
20160204043 | Methods for Monitoring Semiconductor Fabrication Processes Using Polarized Light | 07-14-2016 |
20160379860 | SiC EPITAXIAL WAFER AND METHOD FOR PRODUCING SAME, AND DEVICE FOR PRODUCING SiC EPITAXIAL WAFER - A SiC epitaxial wafer manufacturing method of the present invention includes: manufacturing a SiC epitaxial wafer including a SiC epitaxial layer on a surface of a SiC single crystal wafer while supplying a raw material gas into a chamber using a SiC epitaxial wafer manufacturing apparatus; and manufacturing a subsequent SiC epitaxial wafer after measuring a surface density of triangular defects originating from a material piece of an internal member of the chamber on the SiC epitaxial layer of the previously manufactured SiC epitaxial wafer. | 12-29-2016 |
20190148333 | METHOD FOR BONDING WAFERS AND BONDING TOOL | 05-16-2019 |