Entries |
Document | Title | Date |
20080206907 | Method for fabricating semiconductor device to which test is performed at wafer level and apparatus for testing semiconductor device - A method for fabricating a semiconductor device includes placing a semiconductor wafer on a stage, the semiconductor wafer having a plurality of ball-shaped external connecting terminals projected from a surface, bringing a probe card close to the semiconductor wafer placed on the stage to bring a plurality of probe terminals included in the probe card into contact with the external connecting terminals respectively, and applying a voltage to the semiconductor wafer through the probe terminal to perform a test of the semiconductor wafer. The probe terminals contact all the external connecting terminals. | 08-28-2008 |
20080241976 | Semiconductor device production process - A semiconductor device production process includes forming, on a prepared SOI wafer, semiconductor functional devices and substrate contacts. The substrate contacts connect to a support substrate of the SOI wafer. The semiconductor device production process also includes forming a pattern that connects the substrate contacts to external connection pads formed on the semiconductor functional devices such that the external connection pads are not connected to each other. The semiconductor device production process also includes measuring conductivity between the external connection pads. | 10-02-2008 |
20080248601 | Method of fusing trimming for semiconductor device - Deviation occurring in a particular region in a plane of a resistor group which constitutes a semiconductor integrated circuit is improved and a quick increase in yield is accomplished. Provided is a fuse trimming method for a semiconductor device in which circuit elements such as transistors and resistors are formed on a semiconductor wafer and which has fuse elements capable of adjusting a resistance value of the resistors by laser trimming, including a resistor correction step of correcting in the particular region of the semiconductor wafer the resistance value of the resistors based on an amount of deviation from a target value of the resistance value of the resistors. | 10-09-2008 |
20080280383 | Method of real-time monitoring implantation - A method of real-time monitoring implantation includes plotting a calibration curve for monitoring implantation first. Next, a testing substrate covered a photoresist is provided and then implanted. Since photoresist surface roughness will be changed after implantation, surface roughness change could be quantitatively determined by monitoring scattering light. Finally, the detected scattering light intensity is used to calculate the corresponding implantation condition by the use of the calibration curve. | 11-13-2008 |
20090011526 | INCREASING AN ELECTRICAL RESISTANCE OF A RESISTOR BY NITRIDIZATION - A method for increasing an electrical resistance of a resistor. A semiconductor structure that includes the resistor is placed in a chamber that includes a gas including nitrogen-containing molecules at an nitrogen concentration. A fraction F of an exterior surface of a surface layer of the resistor is exposed to the nitrogen-comprising molecules. A portion of the surface layer is heated at a heating temperature. A combination of the nitrogen concentration and the heating temperature is sufficient to nitridize the portion of the surface layer by reacting the portion with the nitrogen-containing molecules. Heating the portion of the surface layer includes directing a beam of radiation or particles into the portion of the surface layer heat the portion of the surface layer. The portion of the surface layer is nitridized by being reacted with the nitrogen-containing molecules such that an electrical resistance of the resistor is increased. | 01-08-2009 |
20090017565 | MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A probe is contacted to a test pad, without destroying the circuit formed in the chip at the time of a probe test. Therefore, a load jig, a pressing tool, an elastomer, an adhesion ring, and a plunger are made into one by fixation with a nut and a bolt. The elastic force of the spring installed between the spring retaining jig and the load jig acts so that the member used as these one may be depressed toward pad PD. The thrust transmitted from the spring in a plunger to a thin films sheet is used only for the extension of a thin films sheet. | 01-15-2009 |
20090035883 | Auto Routing for Optimal Uniformity Control - A method for improving within-wafer uniformity is provided. The method includes forming an electrical component by a first process step and a second process step, wherein the electrical component has a target electrical parameter. The method includes providing a first plurality of production tools for performing the first process step; providing a second plurality of production tools for performing the second process step; providing a wafer; performing the first process step on the wafer using one of the first plurality of production tools; and selecting a first route including a first production tool from the second plurality of production tools. A within-wafer uniformity of the target electrical parameter on the wafer manufactured by the first route is greater than a second route including a second production tool in the second plurality of production tools. | 02-05-2009 |
20090042322 | METHOD FOR INSPECTING SEMICONDUCTOR DEVICE - According to the present invention, a method for inspecting a semiconductor device includes the steps of carrying out a first test for inspecting characteristic of semiconductor devices under a shielded (dark) condition to discriminate non-defective devices; and carrying out a second test to semiconductor devices, which have been passed the first test as non-defective devices, for inspecting characteristic of the semiconductor devices. The second test is carried out while a predetermined color of light is applied to semiconductor devices. | 02-12-2009 |
20090042323 | PROBE CARD, SEMICONDUCTOR INSPECTING APPARATUS, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A frame bonded and fixed to a back face of a probe sheet so as to surround a group of pyramid-shaped or truncated pyramid-shaped contact terminals collectively formed at a central region portion of the probe sheet on a probing side thereof is protruded from a multi-layered wiring board, and pressing force is imparted to the frame and a pressing piece at a central portion by a plurality of guide pins having spring property so as to tilt finely. | 02-12-2009 |
20090042324 | SUBSTRATE SUPPORTING APPARATUS - A substrate supporting apparatus includes first and second shafts spaced by a distance that corresponds to or exceeds a width of a substrate, and at least one wire to support the substrate. The wire has ends coupled to respective ones of the first and second shafts. The wire is raised and lowered to place a substrate onto a lower electrode in a substrate processing chamber and to remove the substrate when processing is completed. | 02-12-2009 |
20090047748 | ENHANCED SENSITIVITY NON-CONTACT ELECTRICAL MONITORING OF COPPER CONTAMINATION ON SILICON SURFACE - Methods of measuring copper impurities on a silicon surface are disclosed. In certain embodiments, copper is electrically activated by ultra-violet illumination of the surface at room temperature. Activation can enhance the copper contribution to surface recombination and to surface voltage which are measured in a non-contact manner using a ac-surface photovoltage and a vibrating Kelvin-probe, respectively. Differential measurements before and after activation enable the separations of the copper impurities from other surface contaminants. | 02-19-2009 |
20090061546 | METHOD FOR SETTING PREDEFINABLE PARAMETERS - A method for setting predefinable parameters is described, in which for an electronic component, for example a voltage regulator having at least one integrated circuit, the latter has an external connection, via which it is connectable to a programming device. For the latter, a so-called zero programming is provided in the manufacture of the integrated circuit, and predefinable parameters or settings are programmed in following the completion of the manufacturing process, in particular following the assembly of the component or the voltage regulator with the associated generator. | 03-05-2009 |
20090061547 | Landing Pad for Use As a Contact to a Conductive Spacer - A landing pad for use as a contact to a conductive spacer adjacent a structure in a semiconductor device comprises two islands, each of which is substantially rectangularly shaped and is spaced apart from one another and from the structure. Conductive spacers are adjacent to each island and overlapping each other and overlapping with the conductive spacer adjacent to the structure. The contact to the landing pad is on the conductive spacers adjacent to the islands and spaced apart from the structure. | 03-05-2009 |
20090068771 | Electro Chemical Deposition Systems and Methods of Manufacturing Using the Same - An electro chemical deposition system is described for forming a feature on a semiconductor wafer. The electro chemical deposition is performed by powering electrodes that includes a cathode, an anode and a plurality of electrically independent auxiliary electrodes. | 03-12-2009 |
20090081819 | METHOD AND APPARATUS FOR MANAGING MANUFACTURING EQUIPMENT, METHOD FOR MANUFACTURING DEVICE THEREBY - Provided is a method for managing manufacturing apparatuses used in a managed production line including a plurality of manufacturing processes for manufacturing an electronic device, each of the apparatuses being used in each of the processes, the method including: acquiring a property of a reference device manufactured in a predetermined reference production line including the manufacturing processes to be performed; performing at least one of the manufacturing processes in the managed production line, performing the other manufacturing processes in the reference production line, and manufacturing a comparison device; measuring a property of the comparison device; comparing the measured properties between the reference and the comparison devices; and judging whether the manufacturing apparatus used in the at least one manufacturing process is defective or not, based on a property difference between the reference and the comparison devices. | 03-26-2009 |
20090087930 | Inspection System, Inspection Method, and Method for Manufacturing Semiconductor Device - The present invention provides an inspection system of ID chips that can supply a signal or power supply voltage to an ID chip without contact, and can increase throughput of an inspection process and an inspection method using the inspection system. The inspection system according to the present invention includes a plurality of inspection electrodes, a plurality of inspection antennas, a position control unit, a unit for applying voltage to each of the inspection antennas, and a unit for measuring potentials of the inspection electrodes. One feature of the inspection system is that a plurality of ID chips and the plurality of inspection electrodes are overlapped with a certain space therebetween, and the plurality of ID chips and the plurality of inspection antennas are overlapped with a certain space therebetween, and the plurality of ID chips are interposed between the plurality of inspection electrodes and the plurality of inspection antennas by the position control unit. | 04-02-2009 |
20090098670 | SEMICONDUCTOR DEVICE FOR MONITORING CURRENT CHARACTERISTIC AND MONITORING METHOD FOR CURRENT CHARACTERISTIC OF SEMICONDUCTOR DEVICE - A method for monitoring current characteristics of a semiconductor device includes forming an isolation layer and a well area over a substrate, and then forming a P+ area and an N+ area spaced apart by the isolation layer to define active areas, and then forming a gate oxide layer over the substrate including the P+ area and the N+ area, and then forming a polysilicon layer over one of the N+ area and the P+ area, and then connecting a electronic measuring probe to one of the N+ area and the P+ area and connecting a power terminal to the polysilicon layer, and then measuring the current characteristics of the semiconductor device using the polysilicon layer as a power pad and one of the N+ area and the P+ area as a pad. | 04-16-2009 |
20090130785 | MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - As the thickness of the card holder for preventing warping of a multilayered wiring substrate | 05-21-2009 |
20090137070 | Manufacturing Method for Partially-Good Memory Modules with Defect Table in EEPROM - A manufacturing method makes memory modules from partially-good DRAM chips soldered to its substrate. The partially-good DRAM chips have a number of defective memory cells that is below a test threshold, such as 10%. Packaged DRAM chips are optionally pre-screened and considered to pass when the number of defects found is less than the test threshold. A defect table is created during testing and written to a serial-presence-detect electrically-erasable read-only memory (SPD-EEPROM) on the memory module. The memory module is finally tested on a target-system tester that reads the defect table during booting, and redirects memory access to defective memory locations identified by the defect table. The memory modules may be burned in or tested at various temperatures and voltages to increase reliability. | 05-28-2009 |
20090148967 | METHODS OF MAKING AND USING INTEGRATED AND TESTABLE SENSOR ARRAY - A method for making a testable sensor assembly is provided. The method includes forming a first sensor array on a first substrate having a first side and a second side, wherein the first sensor array is formed on the first side of the first substrate, coupling a first semiconductor wafer having a first side and a second side to the first sensor array, wherein the first side of the first semiconductor wafer is coupled to the first sensor array, thinning one of the second side of the first substrate or the second side of the first semiconductor wafer, and testing the first sensor array to identify operational and non-operational units in the testable sensor assembly before integration of the sensor assembly with interface electronics. | 06-11-2009 |
20090155936 | MODULAR FLOW CELL AND ADJUSTMENT SYSTEM - A combinatorial processing system having modular dispense heads is provided. The modular dispense heads are disposed on a rail system enabling an adjustable pitch of the modular dispense heads for the combinatorial processing. The modular dispense heads are configured so that sections of the modular dispense heads are detachable in order to accommodate various processes through a first section without having to completely disconnect and re-connect facilities to a second section. | 06-18-2009 |
20090186430 | Test Patterns for Detecting Misalignment of Through-Wafer Vias - A semiconductor chip including a test pattern is provided. The semiconductor chip includes a semiconductor substrate; a through-wafer via in the semiconductor substrate; and a plurality of conductive patterns over the semiconductor substrate and adjacent to each other. The bottom surfaces of the plurality of conductive patterns and a top surface of the through-wafer via are substantially coplanar. The through-wafer via is at least adjacent to the plurality of conductive patterns. The semiconductor chip further includes a plurality of bonding pads on a surface of the semiconductor chip, each being connected to one of the plurality of conductive patterns. | 07-23-2009 |
20090209053 | CONNECTION DEVICE AND TEST SYSTEM - To achieve high speed exchange of electrical signals between a connection device and a tester, a support member is provided for supporting the connection device, a plurality of pointed contact terminals are arrayed in an area on the probing side, a multilayer film is provided having a plurality of lead out wires electrically connected to the contact terminals and a ground layer enclosing an insulation layer, and a frame is clamped on the rear side of the multilayer film. A clamping member is provided on the frame to make the multilayer film project out to eliminate slack in the multilayer film. A contact pressure means is provided for making the tips of the contact terminals contact each of the electrodes with predetermined contact pressure from the support member to the clamping member. A compliance mechanism is provided so that the contact terminal group of the tip surface is arrayed in parallel with the electrode group terminal surface, so that the tips of the contact terminals contact the surface of the electrodes with an equal pressure. | 08-20-2009 |
20090215206 | System and method for controlling a semiconductor manufacturing process - A semiconductor manufacture and testing device is provided, comprising: a process device configured to perform a semiconductor processing operation on a semiconductor wafer; a testing device configured to perform a testing operation on the semiconductor wafer and generate real-time testing metrics relating to the testing operation; a data storage element configured to store the real-time testing metrics as stored testing metrics; a control and dispatch element configured to receive the stored testing metrics and generate dispatch control signals based on the stored testing metrics and a set of evaluation rules; and a test routing element located between the process element and the testing element, and configured to route the semiconductor wafer either from the process element to the testing element or from the process element around the testing element, based the dispatch control signals. | 08-27-2009 |
20090215207 | Alignment method of two substrates by microcoils - Substrates to be aligned comprise microcoils arranged at the level of their facing surfaces. In an alignment phase, power is supplied to at least the microcoils of the first substrate, whereas the inductance of the microcoils of the second substrate is measured. The microcoils are preferably flat microcoils in the form of a spiral or a serpentine. | 08-27-2009 |
20090239316 | METHOD AND SYSTEM TO DYNAMICALLY COMPENSATE FOR PROBE TIP MISALIGNEMENT WHEN TESTING INTEGRATED CIRCUITS - Method for dynamically compensating probe tip misalignment with a semiconductor wafer. The wafer is located on a handler and the wafer is adjusted to a first temperature. Probe tips of an inspection system are moved to a first position centered above pads of a test module on the wafer. The first position is recorded in a memory of the inspection system at the first temperature. The wafer and the probe tips are adjusted to a second temperature while the wafer remains in the inspection system. A second position of the probe tips is recorded in the memory while the probe tips and the wafer are equilibrated at the second temperature. A difference between the first and second position is calculated. Relative positions of the probe tips or the wafer is compensated based on the calculated difference, such that the probe tips are re-centered above the pads at the second temperature. | 09-24-2009 |
20090269865 | Method for PMOS Device Processing Using a Polysilicon Footing Characteristic to Achieve Low Leakage - A method for manufacturing a MOS device. The method includes providing a semiconductor substrate. The method forms a gate dielectric layer overlying the semiconductor substrate and a polysilicon gate overlying the gate dielectric layer. The polysilicon gate is characterized by a thickness, a width and a polysilicon footing profile. In a specific embodiment, the method performs a TCAD simulation and determines a response of device performance due to the polysilicon footing profile from the model. The method uses the model to provide a process control window for fabricating the polysilicon gate. | 10-29-2009 |
20090280583 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device according to one embodiment includes: forming a plurality of Si-based pattern portions above a semiconductor substrate, the plurality of Si-based pattern portions being adjacent in a direction substantially parallel to a surface of the semiconductor substrate via insulating films; forming a metal film above the plurality of Si-based pattern portions and the insulating films so as to contact with the plurality of Si-based pattern portions; processing whole areas or upper portions of the plurality of Si-based pattern portions into a plurality of silicide layers by a silicidation reaction between the plurality of Si-based pattern portions and the metal film by heat treatment; and removing the plurality of silicide layers formed above the insulating films by applying planarizing treatment to the plurality of silicide layers. | 11-12-2009 |
20090291514 | Process management method and process management data for semiconductor device - A process management method for managing manufacturing variability of an interconnection included in a semiconductor device is provided. The process management method includes: calculating interconnect resistance and interconnect capacitance regarding an interconnection included in the semiconductor device, under a condition that manufacturing variability of a width and a thickness of the interconnection is expressed by points on a predetermined circle of equal probability of a joint probability density function; and defining, based on the calculated interconnect resistance and interconnect capacitance, a variation range of interconnect resistance and interconnect capacitance caused by manufacturing variability. The variation range is defined two-dimensionally in a coordinate system where a first axis represents interconnect resistance and a second axis represents interconnect capacitance. | 11-26-2009 |
20090291515 | Semiconductor device and a semiconductor device manufacturing method - A semiconductor device for fingerprint sensors reduces a mounting area of the semiconductor device and improves a processing capacity of assembling and testing process. The semiconductor device has a functional surface that provides a predetermined function. A semiconductor element has a circuit formation surface on which a plurality of electrodes are formed and a back surface opposite to the circuit formation surface. A part of the circuit formation surface functions as the functional surface. Wiring is formed on the back surface of the semiconductor element. A plurality of connection parts extends between the circuit formation surface and the back surface of the semiconductor element so as to electrically connect the electrodes to the wiring. A plurality of external connection terminals are exposed outside the semiconductor device on a side of the back surface of the semiconductor element. | 11-26-2009 |
20090325327 | METHOD FOR CLEANING A SOLAR CELL SURFACE OPENING MADE WITH A SOLAR ETCH PASTE - A thin silicon solar cell having a back dielectric passivation and rear contact with local back surface field is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness from 50 to 500 micrometers. A barrier layer and a dielectric layer are applied at least to the back surface of the silicon wafer to protect the silicon wafer from deformation when the rear contact is formed. At least one opening is made to the dielectric layer. An aluminum contact that provides a back surface field is formed in the opening and on the dielectric layer. The aluminum contact may be applied by screen printing an aluminum paste having from one to 12 atomic percent silicon and then applying a heat treatment at 750 degrees Celsius. | 12-31-2009 |
20090325328 | Plasma processing apparatus and plasma processing method - A plasma processing method is provided. The method includes providing photon detection sensors for measuring an ultraviolet-light-induced current around circumferential portions of a wafer stage within a plasma chamber. The method also includes providing a semiconductor wafer on the wafer stage and performing plasma processing so as to form an insulating layer the semiconductor wafer or etch an insulating layer formed on the semiconductor wafer. | 12-31-2009 |
20100009473 | Method for manufacturing semiconductor device - A method for manufacturing a semiconductor device includes preparing two substrates having a first and a second surface and having first and second pads and a second testing-dedicated pad, the first pads in the first surface, the second pads in the second surface and arranged with an inter-pad distance that is larger than that for the first pad, and the second testing-dedicated pad being in the second surface; coupling a wafer with a apparatus, and inspecting the wafer with a probe card, the wafer having a LSI, which is an object of an inspection, the apparatus applicable signal to the LSI formed in the wafer, and measurable electrical characteristics of the LSI formed in the wafer, and the probe card having one of the two substrates; dicing the wafer into semiconductor elements containing the LSI; and packaging the semiconductor element over the other of the two substrates. | 01-14-2010 |
20100022038 | Method for evaluating semiconductor wafer - The present invention provides a method for evaluating a semiconductor wafer, including at least: forming an oxide film on a front surface of a semiconductor wafer; partially removing the oxide film to form windows at two positions; diffusing a dopant having a conductivity type different from a conductivity type of a semiconductor as an evaluation target through the windows at the two positions and forming diffused portions in the semiconductor as the evaluation target to form PN junctions; and performing leakage current measurement and/or DLTS measurement in a part between the two diffused portions to evaluate the semiconductor wafer. As a result, there is provided the method for evaluating a semiconductor wafer that can perform junction leakage current measurement or DLTS measurement to easily evaluate a quality of the inside of the semiconductor wafer. In particular, there can be provided the method that can evaluate not only a PW or an EPW but also the inside of an SOI layer of an SOI wafer. | 01-28-2010 |
20100055809 | PROCESS OF FABRICATING A WORKPIECE USING A TEST MASK - A product workpiece can be processed to form product dice. A test mask can allow intentional changes to be made to a feature on the product workpiece to examine how the altered feature performs. Use of the test mask may be used or not used based on the needs or desires of skilled artisans. By using the test mask, a separate dedicated test structure is not required to be formed in a scribe lane or within an area that could otherwise be used for a product die. Thus, the sampling level by using the test mask can be varied. Also, separate test workpieces, which may not be processed using a significantly different process flow or at significantly different times as compared to product workpieces, are not required. The product workpiece with the altered feature can be electrically tested without the need to form test or bond pads. | 03-04-2010 |
20100062550 | METHOD FOR REDUCING OCCURRENCE OF SHORT-CIRCUIT FAILURE IN AN ORGANIC FUNCTIONAL DEVICE - A method, for reducing occurrence of short-circuit failure in an organic functional device ( | 03-11-2010 |
20100068835 | THIN FILM SCRIBE PROCESS - A method and apparatus for improving a thin film scribing procedure is presented. Embodiments of the invention include a method and apparatus for determining a scribe setting for removal of an absorber layer of a photovoltaic device that improves contact resistance between a back contact layer and a front contact layer of the device. | 03-18-2010 |
20100068836 | METHOD OF MEASURING RESISTIVITY OF SIDEWALL OF CONTACT HOLE - A method of measuring a resistivity of a sidewall of a contact hole formed in a semiconductor device, wherein said semiconductor device includes a first electrode formed on a substrate; a second electrode formed on the first electrode with an insulating film in between; a resist pattern formed on the first electrode and the second electrode; a contact hole formed in the first electrode and the second electrode; and an organic film deposited on the sidewall of the contact hole, includes the steps of: placing a probe needle on the first electrode and the second electrode so that the probe needle contacts with the first electrode and the second electrode several times; establishing electrical conductivity of the probe needle relative to the first electrode and the second electrode; and measuring the resistivity of the organic film between the first electrode and the second electrode. | 03-18-2010 |
20100068837 | Structures and Methods for Wafer Packages, and Probes - This document describes the fabrication and use of multilayer ceramic substrates, having one or more levels of internal thick film metal conductor patterns, wherein any or all of the metal vias intersecting one or both of the major surface planes of the substrates, extend out of the surface to be used for making flexible, temporary or permanent interconnections, to terminals of an electronic component. Such structures are useful for wafer probing, and for packaging, of semiconductor devices. In some embodiments, such structures are shown to be useful for simultaneously testing multiple devices on a semiconductor wafer, or for assembling multiple substrates on to a wafer, to accomplish both testing and packaging of the dies on the wafer. In yet another embodiment of the invention, single or multilevel ceramic interconnect structures with thick film metal conductors, are fabricated right on the product wafer to facilitate economical testing and packaging of the dies on the wafer. | 03-18-2010 |
20100075444 | METHOD OF MANUFACTURING SEMICONDUCTOR CHIP AND SEMICONDUCTOR MODULE - An FOM (figure of merit) enabling evaluation from a cost aspect, as well as evaluation of electrical performance, is newly proposed to provide a method of manufacturing based on the FOM a semiconductor chip intended for a lower cost production in addition to satisfying electrical performance. An FOM | 03-25-2010 |
20100081219 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - In the method of manufacturing a semiconductor device, first, values of diffusion parameters of a semiconductor device are acquired in a middle of manufacturing the semiconductor device. Next, a target value of another diffusion parameter to be determined by a processing implemented in a subsequent process of the semiconductor device manufacturing process is calculated. The another diffusion parameter is calculated by substituting the acquired values of diffusion parameters and a desired value of an electrical characteristic of the semiconductor device into a predetermined prediction expression. The prediction expression is an expression showing a corresponding relationship between the electrical characteristic and a plurality of types of diffusion parameters of the semiconductor device. Subsequently, processing conditions for the processing implemented in the subsequent process to realize the target value is determined. Then, the processing to the semiconductor device in the subsequent process is implemented under the determined processing conditions. | 04-01-2010 |
20100124792 | EDDY CURRENT SENSOR WITH ENHANCED EDGE RESOLUTION - An apparatus for monitoring the thickness of a conductive layer on a substrate includes a support to hold a substrate having a conductive layer, an eddy current monitoring system including a first plurality of core portions, and a motor to cause relative motion between the support and the eddy current monitoring system such that the substrate moves across the first plurality of core portions in a direction that defines a first axis. At least one core portion is positioned further from a second axis than at least two other core portions. The second axis is orthogonal to the first axis. | 05-20-2010 |
20100124793 | HIGH VOLTAGE SENSOR DEVICE AND METHOD THEREFOR - In one embodiment, a high voltage element is formed overlying a doped semiconductor region that can be depleted during the operation of the high voltage element includes a conductor overlying a space in a resistor. | 05-20-2010 |
20100144069 | Methods and Apparatus For Thinning, Testing And Singulating A Semiconductor Wafer - A wafer translator is provided with a patterned layer of wafer bonding thermoset plastic and is removably attached with a wafer so as to form a wafer/wafer translator pair. The wafer translator acts as a mechanical support during a thinning process as well as during a wafer dicing operation. The singulated integrated circuits are then removed from the wafer translator. In some embodiments, wafer level testing of the integrated circuits on the wafer is performed subsequent to the wafer thinning process but before the wafer and wafer translator are separated. In other embodiments, wafer level testing of the integrated circuits on the wafer is performed subsequent to the wafer dicing operation but before the diced wafer and wafer translator are separated. | 06-10-2010 |
20100151599 | Apparatus and method for manufacturing semiconductor device - A method of manufacturing a semiconductor device includes depositing material on a wafer in a process chamber to form a thin film on the wafer, a by-product layer being simultaneously formed on an inner part of the process chamber, monitoring a change in thickness or mass of the by-product layer on the inner part of the process chamber during a process in the process chamber by using a QCM installed in the process chamber, and determining an end point of the process in the process chamber based on the monitored change in thickness or mass of the by-product layer in the process chamber. | 06-17-2010 |
20100173432 | GAP MAINTENANCE FOR OPENING TO PROCESS CHAMBER - A semiconductor processing apparatus includes a reaction chamber, a movable susceptor, a movement element, and a control system. The reaction chamber includes a baseplate. The baseplate includes an opening. The movable susceptor is configured to hold a workpiece. The movable element is configured to move a workpiece held on the susceptor towards the opening of the baseplate. The control system is configured to space the susceptor from the baseplate by an unsealed gap during processing of a workpiece in the reaction chamber. Purge gases may flow through the gap into the reaction chamber. Methods of maintaining the gap during processing include calibrating the height of pads and capacitance measurements when the susceptor is spaced from the baseplate. | 07-08-2010 |
20100190277 | Power Network Stacked Via Removal For Congestion Reduction - A method of automatically reducing stacked vias while minimizing voltage drop in a power network of an integrated circuit (IC) is provided. In this method, any feasible (i.e. other than connectivity-necessary and uncongested stacked vias) stacked vias of the power network can be virtually removed. If a target voltage drop of the power network is exceeded, then a measurement of the severity of at least a maximum voltage drop on the IC can be updated. After this updating, a set of voltage drop improvement stacked vias can be virtually returned to the power network. The steps of determining whether the target voltage drop is exceeded, updating the severity of the voltage drop at one or more hot spots, and virtually returning the set of additional stacked vias can be repeated until the target voltage drop is not exceeded. | 07-29-2010 |
20100190278 | TESTING FOR CORRECT UNDERCUTTING OF AN ELECTRODE DURING AN ETCHING STEP - A probe electrode structure on a substrate is described, comprising a first probe electrode and a neighboring second probe electrode on a layer sequence that generally includes, in a direction from the substrate to the probe electrodes, an electrically conductive bottom layer, an electrically insulating center layer and a electrically conductive top layer. The probe-electrode structure of the invention provides a means to detect an undercutting of the first probe electrode in an etching step that aims at removing the top layer from regions outside the first probe electrode. An undercutting that exceeds an admissible distance from the first edge of the first electrode will remove the first top-layer probe section in the first probe opening, which causes a detectable change of the electrical resistance between the first and second probe electrodes. | 07-29-2010 |
20100197052 | ION IMPLANTATION PROCESS CHARACTERIZATION METHOD - A method of characterizing an ion implantation process, the method including a first step of producing a PN junction degraded by the ion implantation of species, the species implantation being obtained by the ion implantation process to be characterized; a second step of measuring a parameter representative of an electrical conduction of the degraded PN junction and a dispersion of the parameter on a surface on which the degraded PN junction is produced, the parameter and the dispersion forming a reference parameter and a reference dispersion, the first and second steps being repeated in time so as to follow the evolution of the parameter representative of electrical conduction with relation to the reference parameter and the dispersion of the representative parameter with relation to the reference dispersion. | 08-05-2010 |
20100203655 | GAP CAPACITORS FOR MONITORING STRESS IN SOLDER BALLS IN FLIP CHIP TECHNOLOGY - A semiconductor structure formation method and operation method. The structure includes (i) a dielectric layer, (ii) a bottom capacitor plate and an electrically conductive line on the dielectric layer, (iii) a top capacitor plate on top of the bottom capacitor plate, (iv) a gap region, and (v) a solder ball on the dielectric layer. The dielectric layer includes a top surface that defines a reference direction perpendicular to the top surface. The top capacitor plate overlaps the bottom capacitor plate in the reference direction. The gap region is sandwiched between the bottom capacitor plate and the top capacitor plate. The gap region does not include any liquid or solid material. The solder ball is electrically connected to the electrically conductive line. The top capacitor plate is disposed between the dielectric layer and the solder ball. | 08-12-2010 |
20100210043 | IN-LINE DEPTH MEASUREMENT OF THRU SILICON VIA - A system, method and device for measuring a depth of a Through-Silicon-Via (TSV) in a semiconductor device region on a wafer during in-line semiconductor fabrication, includes a resistance measurement trench structure having length and width dimensions in a substrate, ohmic contacts on a surface of the substrate disposed on opposite sides of the resistance measurement trench structure, and an unfilled TSV structure in semiconductor device region having an unknown depth. A testing circuit makes contact with the ohmic contacts and measures a resistance therebetween, and a processor connected to the testing circuit calculates a depth of the trench structure and the unfilled TSV structure based on the resistance measurement. The resistance measurement trench structure and the unfilled TSV are created simultaneously during fabrication. | 08-19-2010 |
20100210044 | CHARGE TRANSFER DEVICE - A charge transfer device | 08-19-2010 |
20100221850 | CARBON-CONTAINING SEMICONDUCTING DEVICES AND METHODS OF MAKING THEREOF - Embodiments of the present invention relate to semiconducting carbon-containing devices and methods of making thereof. The semi-conducting carbon containing devices comprise an n-type semiconducting layer and a p-type semiconducting layer, both of which are positioned over a substrate. The n-type semiconducting layer can be formed by pyrolyzing a carbon- and nitrogen-containing polymer, and the p-type semiconducting layer can be formed by pyrolyzing an aromatic- and aliphatic-group-containing polymer. In some embodiments, the devices are solar cell devices. | 09-02-2010 |
20100240156 | METHOD FOR PROVIDING A NON-VOLATILE MEMORY - Testing a non volatile memory by exposing the non volatile memory to particle radiation (e.g. xenon ions) to emulate memory cell damage due to data state changing events of a non volatile memory cell. After the exposing, the memory cells are subjected to tests and the results of the tests are used to develop reliability indications of the non volatile memory. Integrated circuits with non volatile memories of the same design are provided. Reliability representations of the integrated circuits can be made with respect to a number of data state charging events based on the exposure and subsequent tests. | 09-23-2010 |
20100248401 | Kind of Method of Constituting Light Source using Multiple Light-emitting units - A method for forming a light source by plurality of light-emitting units, includes: step (A), determining the number of the light-emitting units based on following factors: the factors include a maximum supply voltage of a power supply circuit and a working voltage of each of the light-emitting units; step (B), determining a set power of each of the light-emitting units based on a set power of the light source and the number of the light-emitting units determined in the step (A); step (C), fabricating or selecting each of the light-emitting units based on the working voltage of each of the light emitting units and the set power of each of the light-emitting units determined in the step (B); step D), forming the light source by connecting each of the light-emitting units obtained in the step (C) in series according to the number of the light-emitting units determined in the step (A). For the light source formed as the above method, the high efficient power supply with the maximum output voltage, to the light source load, can be realized and the same power supply circuit can supply power to the light source with different set power with maximum supply efficiency. | 09-30-2010 |
20100267175 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - In a process for a semiconductor typically represented by a vertical power MOSFET, etc. of repeating various fabrications in a state of a thin film wafer with the thickness of the wafer being 200 μm or less, it is a standard procedure of conducting processing in a stage of bonding a reinforcing glass sheet to a device surface of the wafer (main surface on the side of surface) in the step after film thickness-reduction. However according to the study of the present inventors, it has been found that about 70% for the manufacturing cost is concerned with the reinforcing glass sheet. In the present invention, a stress relief insulation film pattern is formed to the peripheral end of the rear face of a wafer in which processing to the device surface (surface side face) of the wafer has been completed substantially and back grinding has been applied. | 10-21-2010 |
20100273279 | PRODUCTION LINE FOR THE PRODUCTION OF MULTIPLE SIZED PHOTOVOLTAIC DEVICES - Embodiments of the present invention generally relate to a system used to form solar cell devices using processing modules adapted to perform one or more processes in the formation of the solar cell devices. In one embodiment, the system is adapted to form thin film solar cell devices by accepting a large unprocessed substrate and performing multiple deposition, material removal, cleaning, bonding, testing, and sectioning processes to form multiple complete, functional, and tested solar cell devices that can then be shipped to an end user for installation in a desired location to generate electricity. The system is adapted to receive a single large substrate and form multiple silicon thin film solar cell devices from the single large substrate. | 10-28-2010 |
20100279442 | SEMICONDUCTOR PROCESS EVALUATION METHODS INCLUDING VARIABLE ION IMPLANTING CONDITIONS - Semiconductor process evaluation methods perform multiple scans of a test semiconductor substrate (e.g., test wafer) using ion beams under different ion implanting conditions. Parameters of the test semiconductor substrate that was scanned using the ion beams under different ion implanting conditions are then measured to conduct the semiconductor process evaluation. | 11-04-2010 |
20100285616 | TRANSITIONING DIGITAL INTEGRATED CIRCUIT FROM STANDBY MODE TO ACTIVE MODE VIA BACKGATE CHARGE TRANSFER - Circuits and methods are provided for facilitating transitioning of a digital circuit from backgate biased standby mode to active mode. The digital circuit includes a semiconductor substrate, multiple n-channel transistors disposed at least partially in one or more p-type wells in the semiconductor substrate, multiple p-channel transistors disposed at least partially in one or more n-type wells in the semiconductor substrate, and a backgate control circuit. The backgate control circuit is electrically coupled to the p-type well(s) and to the n-type well(s) to facilitate transitioning of the multiple n-channel transistors and the multiple p-channel transistors from backgate biased standby mode to active mode by automatically shunting charge from the n-type well(s) to the p-type well(s) until a well voltage threshold is reached indicative of a completed transition of the transistors from backgate biased standby mode to active mode. | 11-11-2010 |
20100297791 | METHOD FOR INSPECTING PHOTORESIST PATTERN - A method for inspecting a photoresist pattern is disclosed. First, a substrate with a first doping region is provided. Then, a photoresist is formed to cover the substrate. Later, the photoresist is patterned to form a photoresist pattern. Afterwards, the substrate is doped by using the photoresist pattern, and a PN junction exists in the first doping region. Thereafter, a current passing through the PN junction is tested to inspect the photoresist pattern. | 11-25-2010 |
20100297792 | SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR CHIP, AND METHOD FOR THE PRODUCTION THEREOF - A semiconductor device having a semiconductor chip having an active surface with flip-chip contacts and a passive surface is disclosed. In one embodiment, the flip-chip contacts are surrounded by an electrically insulating layer as underfill material, the layer having a UV B-stageable material. The UV B-stageable material is applied on the active surface of the semiconductor wafer. | 11-25-2010 |
20100304509 | CONTACTLESS TECHNIQUE FOR EVALUATING A FABRICATION OF A WAFER - The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed. | 12-02-2010 |
20100304510 | FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle. | 12-02-2010 |
20100304511 | METHOD OF SENSING A HIGH VOLTAGE - In one embodiment, a high voltage element is formed overlying a doped semiconductor region that can be depleted during the operation of the high voltage element includes a conductor overlying a space in a resistor. | 12-02-2010 |
20100311192 | PACKAGING AND TESTING OF MULTIPLE MEMS DEVICES ON A WAFER - A wafer containing a plurality of electro-optical devices, each device being enclosed in chamber that has a translucent cover. An X-Y matrix of pairs of interconnections on the wafer are connected to the circuitry of the electro-optical devices for addressing the electro-optical devices. The pairs of interconnections extend outside of the chambers enclosing the devices to testing areas on the periphery of the wafer. Testing is done by signals applied through the interconnections while simultaneously exposing the devices to light through the translucent covers. | 12-09-2010 |
20100323462 | PROCESS ENVIRONMENT VARIATION EVALUATION - Structures and methods are disclosed for evaluating the effect of a process environment variation. A structure and related method are disclosed including a plurality of electrical structures arranged in a non-collinear fashion for determining a magnitude and direction of a process environment variation in the vicinity of the plurality of electrical structures. The plurality of structures may include a first polarity FET coupled to a second polarity FET, each of the first polarity FET and the second polarity FET are coupled to a first pad and a second pad such that the structure allows independent measurement of the first polarity FET and the second polarity FET using only the first and second pads. Alternatively, the electrical structures may include resistors, diodes or ring oscillators. Appropriate measurements of each electrical structure allow a gradient field including a magnitude and direction of the effect of a process environment variation to be determined. | 12-23-2010 |
20110003404 | DRY HIGH POTENTIAL TESTER AND SOLAR SIMULATOR TOOL - A method and apparatus for testing a photovoltaic substrate disposes the substrate on a support gantry with connection points such as vacuum cups. The gantry is actuated into a test position. A probe nest coupled to the gantry connects to a junction box on the substrate. A power supply applies voltage to the junction box, and an actuated frame contacts an edge region of the substrate to detect any breakthrough current. The actuated frame comprises a liner for maximizing contact with the edge of the substrate. The liner may be conductive, or may have a conductive surface. Current sensors coupled to the conductive liner of the frame detect any breakthrough current. A solar spectrum simulator provides solar spectrum radiation for testing the photovoltaic properties of the substrate. | 01-06-2011 |
20110014727 | THIN FILM PROBE SHEET AND SEMICONDUCTOR CHIP INSPECTION SYSTEM - In the highly accurate thin film probe sheet which is used for the contact to electrode pads disposed in high density with narrow pitches resulting from the increase in integration degree of semiconductor chips and for the inspection of semiconductor chips, a large spatial region in which a metal film selectively removable relative to terminal metal is formed in advance is formed in the peripheral region around minute contact terminals having sharp tips and disposed in high density with narrow pitches equivalent to those of the electrode pads. Thus, occurrence of damage in an inspection process is significantly reduced, and an inspection device simultaneously achieving the miniaturization and the durability can be provided. | 01-20-2011 |
20110020963 | METHOD AND APPARATUS FOR MANUFACTURING SOLAR CELL - A method for manufacturing a solar cell, includes: forming a photoelectric converter which includes a plurality of compartment elements, and in which the compartment elements adjacent to each other are electrically connected; specifying a compartment element having a structural defect in the photoelectric converter; restricting a portion in which the structural defect exists in the compartment element by specifying a defect portion based on a resistance distribution that is obtained by measuring resistances of portions between the compartment elements adjacent to each other; and removing the structural defect by supplying a bias voltage to the portion in which the structural defect exists. | 01-27-2011 |
20110045616 | METHOD OF FABRICATING AN ULTRA-SMALL CONDENSER MICROPHONE - In the present invention, a semiconductor substrate wherein a plurality of MEMS microphones is formed is disposed opposed to a discharge electrode in a state of being stuck on a sheet. Electretization of a dielectric film provided in the MEMS microphone is performed by irradiating the dielectric film between a fixed electrode and a vibration film provided in the MEMS microphone with ions resulting from a corona discharge of the discharge electrode in a state that a predetermined potential difference is applied to the fixed electrode and the vibration film and fixing charges based on the ions to the dielectric film. The electretization is successively performed to each MEMS microphone on the semiconductor substrate by relatively moving the semiconductor substrate and the discharge electrode. Therefore, electretization of the dielectric film in the MEMS microphone chip is realized using a low-cost and simple fabricating equipment and productivity can be enhanced. | 02-24-2011 |
20110065217 | PRESSURE-SENSITIVE ADHESIVE SHEET AND PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE HAVING SAME - A pressure-sensitive adhesive sheet according to the present invention is a pressure-sensitive adhesive sheet in which a pressure-sensitive adhesive layer is provided on a base film, in which the base film contains conductive fibers, and in which an electrically conductive path is formed between the pressure-sensitive adhesive layer and the base film. With this structure, an electrical continuity test can be performed even in a condition where a semiconductor wafer or a semiconductor chip formed by dicing the semiconductor wafer is applied, and deformation (warping) and damage of the semiconductor wafer and generation of flaws and scratches on the backside can be prevented in the test. | 03-17-2011 |
20110070670 | PROCESS CONDITION EVALUATION METHOD FOR LIQUID CRYSTAL DISPLAY MODULE - A process condition evaluation method for a liquid crystal display module (LCM) includes: a first step of obtaining a threshold power measuring pattern, an analysis sample for a cell bonding status in an LCD fabrication process, and obtaining a lower substrate sample by separating an upper substrate from the threshold power measuring pattern; a second step of supplying voltages on a gate pad on the lower substrate sample with sequentially increasing a voltage level by a predetermined unit by using an electrical device, and obtaining a threshold current and a threshold voltage by measuring currents at a drain pad whenever voltage increased by a predetermined unit is applied to the gate pad; and a third step of obtaining threshold power based on the threshold current and the threshold voltage, and thereby evaluating process conditions of the LCM. | 03-24-2011 |
20110076790 | METHOD FOR CONTROLLING THRESHOLD VOLTAGE OF SEMICONDUCTOR ELEMENT - A method for controlling the threshold voltage of a semiconductor element having at least a semiconductor as a component is characterized in including a process to measure one of a threshold voltage and a characteristic value serving as an index for the threshold voltage; a process to determine one of the irradiation intensity, irradiation time, and wavelength of the light for irradiating the semiconductor based on one of the measured threshold voltage and the measured characteristic value serving as the index for the threshold voltage; and a process to irradiate light whose one of the irradiation intensity, irradiation time, and wavelength has been determined onto the semiconductor; wherein the light irradiating the semiconductor is a light having a longer wavelength than the wavelength of the absorption edge of the semiconductor, and the threshold voltage is changed by the irradiation of the light. | 03-31-2011 |
20110086445 | METHODS RELATING TO CAPACITIVE MONITORING OF LAYER CHARACTERISTICS DURING BACK END-OF-THE-LINE PROCESSING - Methods are provided that relate to the capacitive monitoring of characteristic pertaining to layer formed during the back end-of-the-line (BEOL) processing of a semiconductor device. In one embodiment, a method includes the steps of forming a first capacitor array including first and second overlying contacts each formed in a different one of the plurality of BEOL layers, measuring the interlayer capacitance between the first and second overlying contacts, and converting the measured interlayer capacitance to a distance between the first and second overlying contacts. | 04-14-2011 |
20110104831 | Deletable nanotube circuit - Carbon nanotube template arrays may be edited to form connections between proximate nanotubes and/or to delete undesired nanotubes or nanotube junctions. | 05-05-2011 |
20110111535 | METHOD FOR EVALUATING OXIDE SEMICONDUCTOR AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - Many of the principles of an oxide semiconductor are still unclear and therefore there is no established method for evaluating an oxide semiconductor. Thus, an object is to provide a novel method for evaluating an oxide semiconductor. Carrier density is evaluated, and hydrogen concentration is also evaluated. Specifically, a MOS capacitor (a diode or a triode) is manufactured, and the C-V characteristics of the MOS capacitor are obtained. Then, the carrier density is estimated from the C-V characteristics obtained. | 05-12-2011 |
20110136272 | FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle. | 06-09-2011 |
20110151596 | Cascaded-Based De-embedding Methodology - An embodiment is a method for de-embedding. The method comprises forming a primary structure in a semiconductor chip and forming an auxiliary structure in the semiconductor chip. The auxiliary structure replicates a first portion of the primary structure. The method further comprises determining a transmission matrix for each of the primary structure and the auxiliary structure based on measurements and extracting a transmission matrix of a first component of the primary structure by determining a product of the transmission matrix of the primary structure and an inverse of the transmission matrix of the auxiliary structure. | 06-23-2011 |
20110151597 | Analysis method for semiconductor device - An analysis method for a semiconductor device is described. The semiconductor device having an abnormal region is provided. Thereafter, a focused ion beam microscope analysis process is performed to the abnormal region, wherein the result of the focused ion beam microscope analysis process shows that the abnormal region has a defect therein. After the focused ion beam microscope analysis process, an electrical property measurement step is performed to the abnormal region, so as to determine whether the defect in the abnormal region is a device failure root cause or not. | 06-23-2011 |
20110177629 | Chip Packaging with Metal Frame Pin Grid Array - A packaging technology for silicon chips is similar to ball grid array packaging technology of the prior art without, however, the use of printed board substrate of the prior art Instead pins are used that are part of a planar frame, the pins folded to a position 90 degrees from the plane of the frame, after which the frame is disposed in contact with the chip, pads on the frame and the chip are connected, and then entire assembly is then encapsulated. The edges of the frame are then cut off, leaving the encapsulation to maintain the configuration of the package in place. | 07-21-2011 |
20110189798 | CHIP ID APPLYING METHOD SUITABLE FOR USE IN SEMICONDUCTOR INTEGRATED CIRCUIT - A chip forming position specifying method for applying chip IDs indicative of positions on a wafer where semiconductor chips are formed, and thereby specifying their positions. In the chip forming position specifying method, different marks are formed for every chip in a transfer mask (hereinafter called “mark forming mask”) used to form a wiring layer, in addition to normal functional wirings. The positions of the chips on the wafer are respectively specified according to combinations of the marks of a plurality of the mark forming masks, which have been transferred onto the wafer. | 08-04-2011 |
20110201139 | METHOD OF MANAGING SUBSTRATE - The electrostatic chuck is made up of: a chuck main body having electrodes; a chuck plate of a dielectric material and having a rib portion with which a peripheral edge portion of the substrate is capable of coming into surface contact, and a plurality of supporting portions which are vertically disposed at a predetermined distance from one another in an inner space enclosed by the rib portion; and a gas introduction means for introducing a predetermined gas into the inner space. When the substrate is held by the electrostatic chuck which is arranged to attract the substrate by the chuck plate and to form a gas atmosphere by supplying a predetermined gas into the inner space, a current value is monitored by causing an AC current to flow in a capacitance of the chuck plate through an AC power supply, a gas flow amount is monitored by causing the gas to flow through the gas introduction means, and a substrate state is managed based on a variation in at least one of the current value and the gas flow amount to prevent damages to the substrate. | 08-18-2011 |
20110212551 | CONTACTOR, TEST DEVICE FOR SEMICONDUCTOR APPARATUS, AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS - A contactor includes a contactor base material including a first material and a conductor film including a second material. The conductor film is formed only on a contact surface with an electrode of a semiconductor apparatus at a tip of the contactor film. | 09-01-2011 |
20110212552 | DEVICE MANUFACTURING METHOD - There is provided a wafer on which a plurality of electronic devices and circuits under test are to be formed, where each circuit under test includes a plurality of transistors under measurement provided in electrically parallel, a selecting section which sequentially selects the respective transistors under measurement, and an output section which sequentially outputs the source voltages of the transistors under measurement sequentially selected by the selecting section. | 09-01-2011 |
20110229990 | FORMING AND TRAINING PROCESSES FOR RESISTANCE-CHANGE MEMORY CELL - During the manufacture of a set of non-volatile resistance-switching memory elements, a forming process is performed in which a voltage is applied over forming period until a conductive filament is formed in a resistance-switching layer. A heat source at a temperature of 50° C. to 150° C. is applied to expedite the forming process while reducing the required magnitude of the applied voltage. Manufacturing time and reliability are improved. After the forming process, an expedited training process can be performed in which a fixed number of cycles of voltage pulses are applied without verifying the memory elements. Subsequently, the memory elements are verified by determining their read current in an evaluation. Another fixed number of cycles of voltage pulses is applied without verifying the memory elements, if the memory elements do not pass the evaluation. | 09-22-2011 |
20110244604 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor wafer having IGBT elements and transistors formed on a surface thereof is prepared. Electron beams are emitted all over the surface of the semiconductor wafer. Recombination centers are formed in the IGBT elements and the transistors. ON voltages of the transistors are measured by a measurement device, and lifetimes defined in the IGBT elements and the transistors are recovered by a prescribed annealing treatment. When the lifetimes are recovered, a control device controls an annealing treatment amount in the annealing treatment based on the measured ON voltages of the transistors such that ON voltages of the IGBT elements are each equal to a desired ON voltage. Variations in the ON voltages of a plurality of IGBT elements obtained from the semiconductor wafer are reduced. | 10-06-2011 |
20110250709 | METHOD AND APPARATUS FOR MANUFACTURING THIN FILM PHOTOELECTRIC CONVERSION MODULE - A method for manufacturing a thin film photoelectric conversion module comprising the steps of: (A) forming a plurality of divided strings by dividing a string, in which thin film photoelectric conversion elements provided by sequentially laminating a first electrode layer, a photoelectric conversion layer and a second electrode layer on the surface of an insulating substrate are electrically connected in series, into a plurality of strings by dividing grooves, electrically insulating and separating the first electrode layer and the second electrode layer one from the other and extending in a serial connection direction; and (B) performing reverse biasing by applying a reverse bias voltage to each of thin film photoelectric conversion elements of the divided string. | 10-13-2011 |
20110250710 | ELECTRICAL ALIGNMENT MARK SET AND METHOD FOR ALIGNING WAFER STACK - An electrical alignment mark set and the method for using the same is disclosed. The electrical alignment mark set includes at least a top mark and a bottom mark. The top mark includes multiple pads disposed on a top wafer and having first pads and second pads, and a monitoring via electrically connected to the first pads. The bottom mark includes a first bottom pad corresponding to the monitoring via and a second bottom pad corresponding to the second pads. Further the first bottom pad and the second bottom pad are electrically connected to each other so that the monitoring via maybe electrically connected to the second pads by means of the first bottom pad when the top mark and the bottom mark are aligned with each other. | 10-13-2011 |
20110281380 | PROBE CARD AND METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - Provided is a probe card for LSI inspection that can achieve electrical conduction to electrodes on an LSI with a low load without damaging the electrodes and a structural body therebelow, even if the electrodes are arranged at a narrow pitch and in a complex manner. A contact terminal is formed in a truncated square pyramidal recess provided on a film-shaped probe. A dent is often formed on a surface of the film-shaped probe just above the contact terminal. A resin coating film is formed so as to eliminate the dent and flatten the surface of the film-shaped probe. At this time, it is preferred that an amount of cure shrinkage of a resin paste for forming the resin coating film is 0.1% or less. | 11-17-2011 |
20110287561 | THIN FILM TRANSISTOR ARRAY SUBSTRATE WITH IMPROVED TEST TERMINALS - A thin film transistor array substrate comprises thin film transistors and pixel electrodes formed at respective pixels that are defined by gate lines and data lines that orthogonally intersect each other. The thin film transistor array substrate further comprises a plurality of gate pad units that group a plurality of gate pads extended from the gate lines, and a plurality of data pad units that groups a plurality of data pads extended from the data lines. The thin film transistor array substrate further includes a plurality of gate test terminals connected to the gate pad units and beside at least one side of the respective gate pad units, and a plurality of data test terminals connected to the data pad units and located beside at least one side of the respective data pad units. | 11-24-2011 |
20110318851 | MANUFACTURING METHOD AND TEST METHOD OF SEMICONDUCTOR DEVICE - Provided is a test method by which a transistor whose reliability is low can be detected with low stress and high accuracy in a shorter period of time than a BT test. Provided is to detect a transistor whose reliability is high in a shorter period of time than a BT test and manufacture an electronic device with high reliability efficiently. Hysteresis characteristics revealed in the result of the Vg-Id measurement with light irradiation to the transistor correlate with the result of a BT test; whether the reliability of the transistor is Good or Not-Good can be judged. Accordingly, the test method by which a transistor whose reliability is low can be detected with low stress and high accuracy in a shorter period of time than a BT test can be provided. | 12-29-2011 |
20120009695 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The semiconductor device is formed by forming a first metal film over a first main surface of a semiconductor wafer having a first thickness, performing back grinding to a second main surface of the semiconductor wafer thereby making a second thickness thinner than the first thickness and forming an insulation film pattern having a first insulation film and containing an annular insulation film pattern along the periphery of a second main surface of the semiconductor wafer over the second main surface along the periphery thereof. The second main surface of the semiconductor wafer is bonded to a pressure sensitive adhesive sheet thereby holding the device semiconductor wafer by way of the pressure sensitive adhesive sheet to a dicing frame in a state where the insulation film pattern is present. | 01-12-2012 |
20120028381 | SOLAR BATTERY PANEL INSPECTION APPARATUS, METHOD OF INSPECTING SOLAR BATTERY PANEL, AND METHOD OF MANUFACTURING SOLAR BATTERY PANEL - A solar battery panel inspection apparatus is an apparatus for inspecting a solar battery panel including a transparent insulating substrate having a main surface, and a transparent electrode layer, a semiconductor photoelectric conversion layer and a back electrode layer which are sequentially stacked and having an outer circumferential insulating region in which the main surface is exposed, to check the insulation performance of the outer circumferential insulating region. The solar battery panel inspection apparatus includes the first terminal to be brought into contact with the back electrode layer; the second terminal to be brought into contact with a region of or in proximity to an outer circumferential edge of the outer circumferential insulating region; one or more third terminals to be brought into contact with the outer circumferential insulating region between the first terminal and the second terminal; a voltage application unit for applying a voltage each between two terminals selected from these terminals; and a current detection unit detecting a current flowing between the two terminals to which a voltage is applied. | 02-02-2012 |
20120028382 | SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR CHIP, AND METHOD FOR THE PRODUCTION THEREOF - A semiconductor device having a semiconductor chip having an active surface with flip-chip contacts and a passive surface is disclosed. In one embodiment, the flip-chip contacts are surrounded by an electrically insulating layer as underfill material, the layer having a UV B-stageable material. The UV B-stageable material is applied on the active surface of the semiconductor wafer. | 02-02-2012 |
20120064644 | Fluid Ejection Device and Method - A fluid ejection device includes one or more digital data storage arrays having plural EPROM cells. A method for affirming performance adequacy of EPROM cells in the one or more arrays includes the steps of identifying a reference cell in each array, measuring a selected performance criterion for the reference cells, obtaining a reference criterion value, and evaluating the actual performance of at least one cell in each array with respect to the reference criterion value. | 03-15-2012 |
20120064645 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device according to the present invention comprises: forming a semiconductor circuit including a first transistor with a first threshold voltage and a first drain-source current; applying a stress voltage to the first transistor to make at least one of a change from the first threshold voltage a second threshold voltage and a change from the first drain-source current to a second drain-source current; and shipping the semiconductor circuit while the first transistor is presenting one of the second threshold voltage and the second drain-source current. | 03-15-2012 |
20120070918 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device may include, but is not limited to the following processes. First and second grooves are formed in a semiconductor substrate having a first surface. The first and second grooves have substantially the same vertical dimension. The first surface has first and second regions surrounded by the first and second grooves, respectively. An actual resistance value of the semiconductor substrate between a first point on the first region and a second point on the second region is measured. The vertical dimension of the first and second grooves is calculated with reference to the actual resistance value. | 03-22-2012 |
20120083055 | STRUCTURE AND METHOD FOR DETERMINING A DEFECT IN INTEGRATED CIRCUIT MANUFACTURING PROCESS - The present invention discloses a structure and method for determining a defect in integrated circuit manufacturing process, wherein the structure comprises a plurality of normal active areas formed in a plurality of first arrays and a plurality of defective active areas formed in a plurality of second arrays. The first arrays and second arrays are interlaced, and the defect is determined by monitoring a voltage contrast from a charged particle microscope image of the active areas. | 04-05-2012 |
20120156811 | METHODS OF ADDING PADS AND ONE OR MORE INTERCONNECT LAYERS TO THE PASSIVATED TOPSIDE OF A WAFER INCLUDING CONNECTIONS TO AT LEAST A PORTION OF THE INTEGRATED CIRCUIT PADS THEREON - A pattern of conductive ink is disposed on the topside of the unsingulated integrated circuits of a wafer, and, typically after wafer probing, the pattern of conductive ink is removed. The conductive ink pattern provides an electrical pathway between bond pads on an integrated circuit and large contact pads disposed on the topside of the integrated circuit. Each of the large contact pads is much greater in area than the corresponding bond pads, and are spaced apart so that the pitch of the large contact pads is much greater than that of the bond pads. In one aspect of the present invention, the conductive ink includes a mixture of conductive particles and wafer bonding thermoset plastic. In another aspect of the present invention, the conductive ink is heated and disposed on a wafer by an ink jet printing system. | 06-21-2012 |
20120178189 | METHOD FOR FORMING AN OVER PAD METALIZATION (OPM) ON A BOND PAD - A method of making a semiconductor structure includes forming a bond pad, depositing by laser defined deposition a conductive pad, and attaching an electrical connector to the conductive pad. The bond pad is a portion of an integrated circuit. The bond pad includes an exposed portion. The bond pad functions as a contact to the integrated circuit. The conductive pad is deposited on the exposed portion and is confined within a bond pad region around the exposed portion of the bond pad | 07-12-2012 |
20120196389 | DEFECT INSPECTION METHOD AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - According to one embodiment, electrolytic solution is selectively jetted onto an imprint pattern, the electrolytic solution is jetted onto each shot or part of an area in a shot, an electrode is separated for each shot, and the electrode is switched according to a shot to be an inspection target. | 08-02-2012 |
20120225504 | METHODS OF FABRICATING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes providing a wafer, forming a memory device which includes phase change material layer on the wafer, completing a wafer level process of manufacturing the semiconductor device, and performing a thermal treatment process on the wafer to densify the phase change material. To this end, the process temperature of the thermal treatment is higher than the crystallization temperature of the phase change material and lower than the melting point of the phase change material. | 09-06-2012 |
20120238044 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND REINFORCING PLATE - According to one embodiment, in a method for manufacturing a semiconductor device, a semiconductor substrate having a plurality of first pads is covered with a bonding material. The semiconductor substrate is attached to a reinforcing plate having a plurality of first through-holes corresponding respectively to the first pads. The semiconductor substrate is removed until becoming a predetermined thickness. An electrode film is formed on the semiconductor substrate. A remover of the bonding material is injected into the first through-holes so as to expose the first pads. A probe is in contact with the exposed first pads through the first through-holes so as to measure a current flowing between the probe and the electrode film. The remover is injected into the first through-holes so as to separate the semiconductor substrate from the reinforcing plate. The semiconductor substrate is diced into a plurality of chips. | 09-20-2012 |
20120244649 | POLISHING METHOD, POLISHING APPARATUS AND POLISHING TOOL - A polishing method and a polishing apparatus particularly suitable for finishing a surface of a substrate of a compound semiconductor containing an element such as Ga or the like to a desired level of flatness, so that a surface of a substrate of a compound semiconductor containing an element of Ga can be flattened with high surface accuracy within a practical processing time. In the presence of water ( | 09-27-2012 |
20120276665 | APPARATUS AND METHOD FOR ELECTRICAL CHARACTERIZATION BY SELECTING AND ADJUSTING THE LIGHT FOR A TARGET DEPTH OF A SEMICONDUCTOR - The present disclosure provides methods and apparatus that enable characterization of an electrical property of a semiconductor specimen, e.g., dopant concentration of a near-surface region of the specimen. In exemplary method, a target depth for measurement is selected. This thickness may, for example, correspond to a nominal production thickness of a thin active device region of the specimen. A light is adjusted to an intensity selected to characterize a target region of the specimen having a thickness no greater than the target depth and a surface of the specimen is illuminated with the light. An AC voltage signal induced in the specimen by the light is measured and this AC voltage may be used to quantify an aspect of the electrical property, e.g., to determine dopant concentration, of the target region. | 11-01-2012 |
20120301979 | System and Method for Preconditioning Photovoltaic Modules for Performance Testing - A system and method for preconditioning a photovoltaic device is described. One embodiment includes a method for preconditioning a photovoltaic device, the method comprising applying a forward-bias to the photovoltaic device, wherein a forward-bias current is equal to or greater than I | 11-29-2012 |
20120301980 | METHODOLOGY FOR EVALUATION OF ELECTRICAL CHARACTERISTICS OF CARBON NANOTUBES - The present disclosure relates to a structure comprising
| 11-29-2012 |
20120322175 | Methods and Systems For Controlling SiIicon Rod Temperature - Systems and methods are provided for controlling silicon rod temperature. In one example, a method of controlling a surface temperature of at least one silicon rod in a chemical vapor deposition (CVD) reactor during a CVD process is presented. The method includes determining an electrical resistance of the at least one silicon rod, comparing the resistance to a set point to determine a difference, and controlling a power supply to control a power output coupled to the at least one silicon rod to minimize an absolute value of the difference. | 12-20-2012 |
20120329180 | MEMS DEVICE AND FABRICATION METHOD - A method and structure for uncovering captive devices in a bonded wafer assembly comprising a top wafer and a bottom wafer. One embodiment method includes forming a plurality of cuts in the top wafer and removing a segment of the top wafer defined by the plurality of cuts. The bottom wafer remains unsingulated after the removal of the segment. | 12-27-2012 |
20130023070 | PRODUCTION METHOD FOR OXIDIZED CARBON THIN FILM, AND ELEMENT HAVING OXIDIZED CARBON THIN FILM AND PRODUCTION METHOD THEREFOR - The production method for the oxidized carbon thin film of the present disclosure includes: a first step of preparing a carbon thin film and iron oxide that is in contact with the carbon thin film and contains Fe | 01-24-2013 |
20130059403 | METHOD AND APPARATUS FOR WAFER TEMPERATURE MEASUREMENT USING AN INDEPENDENT LIGHT SOURCE - An apparatus is provided for measuring a substrate temperature during an etching process, comprising: one or more windows formed in a substrate supporting surface; a first signal generator configured to pulse a first signal; and a first sensor positioned to receive energy transmitted from the first signal generator through the one or more windows. A method is provided for measuring a substrate temperature during an etching process comprising: heating a substrate using radiant energy; pulsing a first light; determining a metric indicative of total transmittance through the substrate when the first light is pulsed on; determining a metric indicative of background transmittance through the substrate when the first light is pulsed off; and determining a process temperature. | 03-07-2013 |
20130071957 | System and Methods for Semiconductor Device Performance Prediction During Processing - Methods and systems for predicting semiconductor device performance criteria during processing. A method is described that includes receiving a semiconductor wafer; performing semiconductor processing on the semiconductor wafer forming active devices that, when completed, will exhibit a device performance criteria; during the semiconductor processing, measuring in line at least one device performance criteria related physical parameter; projecting an estimated value for the device performance criteria of the active devices using the at least one in line measurement and using estimated measurements for device performance criteria related physical parameters corresponding to later semiconductor processing steps; comparing the estimated value for the device performance criteria to an acceptable range; and determining, based on the comparing, whether the active devices on the semiconductor wafer will have a device performance criteria within the acceptable range. A system for processing semiconductor wafers that includes a programmable processor for performing the methods is described. | 03-21-2013 |
20130071958 | MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In wafer probe inspection for a flip-chip semiconductor device having a solder bump, electric test may be performed at a high temperature by causing a probe needle to directly contact a solder bump over a wafer. The inventors have examined such high temperature probe tests in various ways and revealed the following problems. When a high temperature probe test is performed at 90° C. or higher using a palladium alloy probe needle, tin diffusion due to a solder bump occurs at the needle point to raise resistance, resulting in causing open failure. According to the invention of the present application, at least the tip of a palladium-based probe needle has mainly a granular grain structure in a high temperature probe test performed with the palladium-based probe needle contacting a solder bump electrode over a semiconductor wafer. | 03-21-2013 |
20130078747 | SUBSTRATE ETCHING METHOD AND SUBSTRATE ETCHING APPARATUS - A method for selectively etching a substrate includes providing a template having opening portions formed on an upper surface in a predetermined pattern and flow channels penetrating through the template from the opening portions to a lower surface of the template, filling an etching solution into the flow channels, coupling the upper surface of the template to a substrate such that the opening portions correspond to the predetermined pattern of through holes to be formed through the substrate, and supplying the etching solution onto the substrate through the opening portions of the template such that the through holes are etched through the substrate. | 03-28-2013 |
20130095580 | SEMICONDUCTOR DEVICE AND STRUCTURE - A method for formation of a semiconductor device including a first mono-crystalline layer comprising first transistors and first alignment marks, the method comprising forming a doped layer within a wafer, forming a second mono-crystalline layer on top of the first mono-crystalline layer by transferring at least a portion of the doped layer using layer transfer step, and processing second transistors on the second mono-crystalline layer comprising a step of forming a gate dielectric, wherein the second transistors are horizontally oriented. | 04-18-2013 |
20130115723 | Method of manufacturing semiconductor device and semiconductor manufacturing system - In a method of manufacturing a semiconductor device using an electron beam lithography apparatus configured to emit an electron beam to perform lithography of a pattern, processing including pattern formation with the electron beam lithography apparatus is performed on a wafer, and an electric characteristic of the thus manufactured semiconductor devices is measured by a semiconductor testing apparatus. Then, electron beam lithography data to be used by the electron beam lithography apparatus is adjusted based on a result of measurement of the electric characteristic so as to reduce a variation in the electric characteristic of the semiconductor device within a surface of the wafer. | 05-09-2013 |
20130122616 | THIN FILM SOLAR CELL PROCESSING AND TESTING METHOD AND EQUIPMENT - A method of providing a plurality of classified photovoltaic articles, including the steps of providing a first photo-voltaic element that includes a plurality of photovoltaic articles on a continuous flexible substrate, forming a electrically insulating material on the first photovoltaic element at one or more predetermined locations, separating adjacent photovoltaic articles from each other, determining an efficiency of each photovoltaic article by measuring its current-voltage characteristics, and classifying each photovoltaic article according to its efficiency. | 05-16-2013 |
20130130414 | HIGH PRODUCTIVITY COMBINATORIAL WORKFLOW FOR PHOTORESIST STRIP APPLICATIONS - Electrical testing of metal oxide semiconductor (MOS) high-k capacitor structures is used to evaluate photoresist strip or cleaning chemicals using a combinatorial workflow. The electrical testing can be able to identify the damages on the high-k dielectrics, permitting a selection of photoresist strip chemicals to optimize the process conditions in the fabrication of semiconductor devices. The high productivity combinatorial technique can provide a compatibility evaluation of photoresist strip chemicals with high-k devices. | 05-23-2013 |
20130137199 | SYSTEMS AND METHODS FOR MONITORING HETEROJUNCTION BIPOLAR TRANSISTOR PROCESSES - Disclosed are systems and methods related to monitoring of heterojunction bipolar transistor (HBT) processes. In some embodiments, a capacitance element can be fabricated during an HBT process by forming an emitter layer having material such as indium gallium phosphide (InGaP) over a gallium arsenide (GaAs) base layer, forming a barrier layer such as a tantalum nitride (TaN) layer over the emitter layer, and forming a metal layer over the barrier layer. Aside from the metallization of the emitter, the resulting capacitance element has a capacitance value representative of the thickness of the emitter layer. Accordingly, monitoring of such a capacitance value during various HBT processes allows monitoring of the integrity of the emitter layer. | 05-30-2013 |
20130203190 | METHOD FOR MAKING A REDISTRIBUTED WAFER USING TRANSFERRABLE REDISTRIBUTION LAYERS - A method of making redistributed electronic devices that includes providing a wafer having a plurality of electronic devices, each electronic device having a pattern of contact areas forming die pads. The method also includes forming redistribution layers on a temporary substrate having a pattern of contact areas forming wafer bonding pads matching the die pads and a pattern of contact areas forming redistributed pads different than the wafer bonding pads, the wafer bonding pads are coupled to the redistributed pads through a plurality of stacked conductive and insulating layers. The die pads are coupled to the wafer bonding pads, and the temporary substrate is removed. The wafer and redistribution layers are then divided into a plurality of redistributed electronic devices. | 08-08-2013 |
20130203191 | DEVICE AND METHOD FOR FORMING ON A NANOWIRE MADE OF A SEMICONDUCTOR AN ALLOY OF THIS SEMICONDUCTOR WITH A METAL OR A METALLOID - Device for forming, on a nanowire made of a semiconductor, an alloy of this semiconductor with a metal or metalloid by bringing this nanowire into contact with electrically conductive metal or metalloid probes and Joule heating the nanowire at the points of contact with the probes so as to form an alloy such as a silicide. Application to the production of controlled-channel-length metal-silicide transistors. | 08-08-2013 |
20130244351 | METHOD OF INSPECTING SEMICONDUCTOR DEVICE, METHOD OF FABRICATING SEMICONDUCTOR DEVICE, AND INSPECTION TOOL - An aspect of one embodiment, there is provided a method of inspecting a semiconductor device, attaching an inspection tool on a back surface of a semiconductor substrate, the inspection tool including a sheet and a holding frame, the sheet being larger than the semiconductor substrate and being provided an opening in a center portion of the sheet, the opening being smaller than the semiconductor substrate, the holding frame holding an outer periphery of the sheet, a supporting substrate being attached on a front surface of the semiconductor substrate, removing the supporting substrate attached on the front surface of the semiconductor substrate, and inspecting electrical characteristics of the semiconductor substrate. | 09-19-2013 |
20130252355 | Methods for Achieving Width Control in Etching Processes - A method includes performing a patterning step on a layer using a process gas. When the patterning step is performed, a signal strength is monitored, wherein the signal strength is from an emission spectrum of a compound generated from the patterning step. The compound includes an element in the patterned layer. At a time the signal strength is reduced to a pre-determined threshold value, the patterning step is stopped. | 09-26-2013 |
20130260485 | EDGE TRIGGERED CALIBRATION - Circuitry for measuring a propagation delay in a circuit path. The circuitry includes a one-shot edge triggered element that can be connected in a loop with the circuit path. An edge signal propagating through the circuit path triggers the one-shot element to output a pulse. The pulse propagates around the loop, again triggering the one-shot element to produce a pulse, creating a repeating series of pulses. The period between these pulses is influenced by propagation time of an edge through the loop such that a difference in the period with the circuit path connected and not connected in the loop indicates propagation delay in the circuit path. Such circuitry can be configured to independently measure, and therefore calibrate for, propagation delays associated with rising and falling edges. Calibration to separately equalize propagation delays for rising and falling edges can increase the timing accuracy of an automatic test system. | 10-03-2013 |
20130273674 | Apparatus and Method for Endpoint Detection During Electronic Sample Preparation - An apparatus for endpoint detection during removal of material from an electronic component includes a mounting plate operable to provide physical and electrical attachment for a device-under-test (DUT), a spindle operable to hold a tip for removing material from the DUT, a signal generator operable to provide an input signal to a first electrode, and a microprocessor connected to use an output signal from a second electrode to terminate the removal of material when an endpoint is reached, the first electrode being one of the tip and the DUT and the second electrode being the opposite one of the tip and the DUT. | 10-17-2013 |
20130295699 | METHOD FOR TESTING THROUGH-SILICON-VIA (TSV) STRUCTURES - A method for testing TSV structures includes providing a wafer having a front side and a back side, the wafer further comprising a plurality of TSV structures formed therein; thinning the wafer from the back side of the wafer; forming a first under bump metallization layer on the back side of the wafer blanketly; providing a probing card to the front side of the wafer to test the TSV structures; and patterning the first UBM layer. | 11-07-2013 |
20130295700 | METHOD FOR INTEGRATED CIRCUIT DIAGNOSIS - A method provides a mechanism to examine physical properties and/or diagnose problems at a selected location of an integrated circuit. Such a method can include creating a layer of a reactive material a selected distance above and in proximity with a surface of the integrated circuit so that the reactive material can be evaluated to form chemical radicals above and in proximity to the surface of the integrated circuit. A portion of the reactive material can be excited. A portion of the surface of the integrated circuit can be removed to a selected level to evaluate an exposed electrical structure of the integrated circuit. The exposed electrical structure can be evaluated to determine a potential problem in the integrated circuit. | 11-07-2013 |
20130309786 | METHOD FOR MANUFACTURING IMAGE SENSOR MODULE - An image sensor module includes a semiconductor chip, a transparent substrate, and metal lines. The semiconductor chip includes image sensors disposed in an image sensor region, pads electrically connected to the image sensors and disposed in a peripheral region defined along a periphery of the image sensor region, and through-electrodes electrically connected to the pads. The transparent substrate has a groove defined by a surface covering the image sensors and the pads of the semiconductor chip. The metal lines are disposed on a lower surface of the semiconductor chip and are electrically connected to the through-electrodes. | 11-21-2013 |
20130316472 | HIGH PRODUCTIVITY COMBINATORIAL OXIDE TERRACING AND PVD/ALD METAL DEPOSITION COMBINED WITH LITHOGRAPHY FOR GATE WORK FUNCTION EXTRACTION - Metal gate high-k capacitor structures with lithography patterning are used to extract gate work function using a combinatorial workflow. Oxide terracing, together with high productivity combinatorial process flow for metal deposition can provide optimum high-k gate dielectric and metal gate solutions for high performance logic transistors. The high productivity combinatorial technique can provide an evaluation of effective work function for given high-k dielectric metal gate stacks for PMOS and NMOS transistors, which is critical in identifying and selecting the right materials. | 11-28-2013 |
20130323863 | Method for Generating Graphene Structures - A method for depositing graphene is provided. The method includes depositing a layer of non-conducting amorphous carbon over a surface of a substrate and depositing a transition metal in a pattern over the amorphous carbon. The substrate is annealed at a temperature below 500° C., where the annealing converts the non-conducting amorphous carbon disposed under the transition metal to conducting amorphous carbon. A portion of the pattern of the transition metal is removed from the surface of the substrate to expose the conducting amorphous carbon. | 12-05-2013 |
20130323864 | SEMICONDUCTOR TEST EQUIPMENT AND METHOD OF TESTING AND MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME - A method of manufacturing a semiconductor device including a substrate is disclosed. The method includes: providing the substrate on a wafer chuck; positioning a probe card having probe needles above the substrate; positioning a tester head above the probe card; using a sensor included in the tester head, measuring a deformation of the probe card; using a variable load device included in the tester head, adjusting the deformation of the probe card based on the measured deformation; and testing the substrate using the adjusted probe card. | 12-05-2013 |
20140004628 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND POLISHING APPARATUS | 01-02-2014 |
20140017825 | ION IMPLANTATION METHOD AND ION IMPLANTATION APPARATUS - The ion implantation method includes setting an ion beam scanning speed and a mechanical scanning speed of an object during ion implantation using hybrid scan in advance and implanting ions based on the set ion beam scanning speed and the set mechanical scanning speed of the object. In the setting in advance, each of the ion beam scanning speeds is set based on each of ion beam scanning amplitudes changing severally according to a surface outline of an object which is irradiated with the ions so that an ion beam scanning frequency is maintained constant for any of ion beam scanning amplitudes, and the mechanical scanning speed of the object corresponding to the ion beam scanning speed is set so that an ion implantation dose per unit area to be implanted into the surface of the object is maintained constant. | 01-16-2014 |
20140024145 | METHOD AND STRUCTURE FOR MULTI-CORE CHIP PRODUCT TEST AND SELECTIVE VOLTAGE BINNING DISPOSITION - Operating speeds of integrated circuit devices are tested to establish maximum and minimum frequency at maximum and minimum voltage. The devices are sorted into relatively-slow and relatively-fast devices to classify the devices into different voltage bins. A bin-specific voltage limit is established for each of the voltage bins needed for core performance at system use conditions. The bin-specific voltage limit is compared to core minimum chip-level functionality voltage at system maximum and minimum frequency specifications. The method correlates system design evaluation of design maximum and minimum frequency at design maximum and minimum voltage conditions with evaluation of tested maximum and minimum frequency at tested maximum and minimum voltage conditions. A chip-specific functionality voltage limit is established for the device. Initial system voltage for all devices from a voltage bin is set at a greater of the bin-specific voltage limit and the chip-specific functionality voltage limit consistent with the evaluation conditions. | 01-23-2014 |
20140024146 | SEMICONDUCTOR STRUCTURE - A semiconductor structure is provided and includes a substrate having an edge surface and a device surface with a central area, a crack stop structure disposed on the device surface and a circuit structure including components disposed on the device surface in the central area and interconnects electrically coupled to the components. The interconnects are configured to extend from the central area to the edge surface while bridging over the crack stop structure. | 01-23-2014 |
20140038319 | METHOD FOR FORMING AN ELECTRICAL CONNECTION BETWEEN METAL LAYERS - A method includes forming a connection between a first metal layer and a second metal layer. The second metal layer is over the first metal layer. A via location for a first via between the first metal layer and the second metal layer is identified. Additional locations for first additional vias are determined. The first additional vias are determined to be necessary for stress migration issues. Additional locations necessary for second additional vias are determined. The second additional vias are determined to be necessary for electromigration issues. The first via and the one of the group consisting of (i) the first additional vias and second additional vias (ii) the first additional vias plus a number of vias sufficient for electromigration issues taking into account that the first additional vias, after taking into account the stress migration issues, still have an effective via number greater than zero. | 02-06-2014 |
20140051191 | EXTREMELY NON-DEGENERATE TWO PHOTON ABSORPTION OPTICAL SENSING METHOD, APPARATUS AND APPLICATIONS - An extremely non-degenerate two photon absorption (END-2PA) method and apparatus provide for irradiating a semiconductor material substrate simultaneously with two photons each of different energy less than a bandgap energy of the semiconductor material substrate but in an aggregate greater than the bandgap energy of the semiconductor material substrate. A ratio of a higher energy photon energy to a lower energy photon energy is at least about 3.0. Alternatively, or as an adjunct, the higher energy photon has an energy at least about 75% of the bandgap energy and the lower energy photon has an energy no greater than about 25% of the bandgap energy. | 02-20-2014 |
20140065737 | ION IMPLANTATION METHOD AND ION IMPLANTATION APPARATUS - Provided is an ion implantation method of transporting ions generated by an ion source to a wafer and implanting the ions into the wafer by irradiating an ion beam on the wafer, including, during the ion implantation into the wafer, using a plurality of detection units which can detect an event having a possibility of discharge and determining a state of the ion beam based on existence of detected event having a possibility of discharge and a degree of influence of the event on the ion beam. | 03-06-2014 |
20140073070 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE, SUPPORTING SUBSTRATE, AND SEMICONDUCTOR MANUFACTURING APPARATUS - A method for fabricating a semiconductor device comprising: a first process for attaching a first supporting substrate having a plurality of through holes to a semiconductor substrate having a first surface and a second surface, so that each of the through holes is opposed to a semiconductor device formed in the semiconductor substrate; a second process for contacting probes of an electric characteristic inspection apparatus with a first electrode formed on the first surface, and a second electrode formed on the second surface via the through hole; and a third process for measuring electric characteristic of the semiconductor device. | 03-13-2014 |
20140080233 | COMBINATORIAL OPTIMIZATION OF INTERLAYER PARAMETERS - The embodiments describe methods and apparatuses for combinatorial optimization of interlayer parameters for capacitor stacks. The capacitor stacks may include a substrate, an insulating layer disposed on the substrate, a ruthenium disposed electrode on the insulating layer, and an interlayer disposed on the ruthenium electrode, where the interlayer is configured to prevent etching of the electrode when growing a high-k dielectric using an ozone-based precursor. The parameters for forming the interlayer may include interlayer thickness, precursor chemistry, oxidant strength, precursor purge times, oxidant purge times, and other suitable parameters. Each of these parameters may be evaluated through deposition of the capacitor stacks through a combinatorial optimization process. Thus, a plurality of different parameters may be evaluated with a single substrate to ascertain associated properties of Ruthenium electrode etching in a combinatorial manner. | 03-20-2014 |
20140106481 | METHOD FOR WAFER LEVEL RELIABILITY - A method for ensuring wafer level reliability is provided. The method involves: forming a gate oxide layer having a thickness of less than 50 Å on a semiconductor substrate; forming a PMOS element having a channel length of less than 0.13 μm on the semiconductor substrate; and assessing hot carrier injection (HCI) for the PMOS element. | 04-17-2014 |
20140127838 | METHOD OF TESTING A SEMICONDUCTOR PACKAGE - A method of testing a semiconductor package is provided, including: disposing at least an interposer on a top surface of an adhesive layer, the interposer having a first surface and a second surface opposite to the first surface, a plurality of conductive elements disposed between the second surface of the interposer and the adhesive layer; disposing at least a semiconductor chip on the first surface of the interposer, and performing an electrical test on the semiconductor chip via the conductive elements, wherein if there are a plurality of semiconductor chips that are disposed on the first surface of the interposer, the step of disposing the semiconductor chip and performing the electrical test on the semiconductor chip is iterated; and removing the adhesive layer. By using the method, the fabrication cost and equipment cost of the semiconductor package are reduced, and product yield is increased. | 05-08-2014 |
20140147943 | Method for Determining Carrier Concentrations in Semiconductor Fins - A method includes probing at least one semiconductor fin using a four-point probe head, with four probe pins of the four-point probe head contacting the at least one semiconductor fin. A resistance of the at least one semiconductor fin is calculated. A carrier concentration of the semiconductor fin is calculated from the resistance. | 05-29-2014 |
20140147944 | RESISTANCE COMPONENT EXTRACTION FOR BACK CONTACT BACK JUNCTION SOLAR CELLS - Methods and structures for extracting at least one electric parametric value from a back contact solar cell having dual level metallization are provided. | 05-29-2014 |
20140147945 | METHOD FOR MANUFACTURING A PHOTODETECTOR HAVING A BANDWIDTH TUNED HONEYCOMB CELL PHOTODIODE STRUCTURE - A photodetector with a bandwidth-tuned cell structure is provided. The photodetector is fabricated from a semiconductor substrate that is heavily doped with a first dopant. A plurality of adjoining cavities is formed in the semiconductor substrate having shared cell walls. A semiconductor well is formed in each cavity, moderately doped with a second dopant opposite in polarity to the first dopant. A layer of oxide is grown overlying the semiconductor wells and an annealing process is performed. Then, metal pillars are formed that extend into each semiconductor well having a central axis aligned with an optical path. A first electrode is connected to the metal pillar of each cell, and a second electrode connected to the semiconductor substrate. The capacitance between the first and second electrodes decreases in response to forming an increased number of semiconductor wells with a reduced diameter, and forming metal pillars with a reduced diameter. | 05-29-2014 |
20140154819 | POWER SWITCHING SYSTEM FOR ESC WITH ARRAY OF THERMAL CONTROL ELEMENTS - A semiconductor substrate support for supporting a semiconductor substrate in a plasma processing chamber includes a heater array comprising thermal control elements operable to tune a spatial temperature profile on the semiconductor substrate, the thermal control elements defining heater zones each of which is powered by two or more power supply lines and two or more power return lines wherein each power supply line is connected to at least two of the heater zones and each power return line is connected to at least two of the heater zones. A power distribution circuit is mated to a baseplate of the substrate support, the power distribution circuit being connected to each power supply line and power return line of the heater array. A switching device is connected to the power distribution circuit to independently provide time-averaged power to each of the heater zones by time divisional multiplexing of a plurality of switches. | 06-05-2014 |
20140162384 | PVD-ALD-CVD hybrid HPC for work function material screening - A substrate is provided wherein the substrate includes a number of site-isolated regions (SIRs). At least one material is deposited using PVD on a sub-set of the SIRs. At least one of the material or the process conditions are varied in a combinatorial manner across the sub-set of SIRs. Next, at least one material is deposited using ALD on a sub-set of the SIRs. At least one of the material or the process conditions are varied in a combinatorial manner across the sub-set of SIRs. Next, a material is deposited across the entire substrate using CVD. Each device within each of the SIRs is evaluated for at least one of an electric property or a material property. | 06-12-2014 |
20140179033 | Methods for Forming Templated Materials - Methods of forming layers can comprise defining a plurality of discrete site-isolated regions (SIRs) on a substrate, forming a first layer on one of the discrete SIRs, forming a second layer on the first layer, measuring a lattice parameter or an electrical property of the second layer, The process parameters for the formation of the first layer are varied in a combinatorial manner between different discrete SIRs to explore the possible layers that can result in suitable lattice matching for second layer of a desired crystalline structure. | 06-26-2014 |
20140193928 | CURRENT APPLICATION DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR ELEMENT - Provided is a current application device capable of applying a test current of a magnitude necessary for testing of a semiconductor element without any trouble. A current application device | 07-10-2014 |
20140206113 | Semiconductor Test Structures - A method performed using a resistive device, where the resistive device includes a substrate with an active region separated from a gate electrode by a dielectric and electrical contacts along a longest dimension of the gate electrode, the method comprising, performing one or more processes to form the resistive device, measuring a resistance between the electrical contacts, and correlating the measured resistance with a variation in one or more of the processes. | 07-24-2014 |
20140273314 | High Productivity Combinatorial Workflow to Screen and Design Chalcogenide Materials as Non Volatile Memory Current Selector - Combinatorial workflow is provided for evaluating materials and processes for current selector devices in a cross point memory array. Blanket layers, metal-insulator-metal devices, and compete memory structures are combinatorially fabricated on multiple regions of a substrate, with each region having a different material and process condition for the current selector devices. The current selector devices are then characterized, and the data are compared to obtain the optimum materials and processes. | 09-18-2014 |
20140329344 | TESTING AN ELECTRICAL CONNECTION OF A DEVICE CAP - A method of testing a device includes setting a potential of a cap terminal of the device to a first voltage, setting a potential of a self test plate of the device to a testing voltage, and detecting a first displacement of a proof mass of the device when the cap terminal is set to the first voltage and the self test plate is set to the testing voltage. The method includes setting a potential of the cap terminal of the device to a second voltage, detecting a second displacement of the proof mass of the device when the cap terminal is set to the second voltage and the self test plate is set to the testing voltage, and comparing the first displacement and the second displacement to evaluate an electrical connection between the cap terminal and a cap of the device. | 11-06-2014 |
20140356989 | METHOD OF MANUFACTURING MEMS DEVICES WITH RELIABLE HERMETIC SEAL - Manufactured capped MEMS device wafers are tested for hermeticity on a vacuum prober at differing pressures or on a wafer prober at differing temperatures. Resonant frequency testing is conducted. Leaking MEMS devices are distinguished from the remaining MEMS devices on the basis of quality factor (“Q”) measurements obtained from the resonant frequency testing. | 12-04-2014 |
20140363905 | Optical Wafer and Die Probe Testing - An optical die probe wafer testing circuit arrangement and associated testing methodology are described for mounting a production test die ( | 12-11-2014 |
20140363906 | METHOD OF TESTING SEMICONDUCTOR DEVICE - A method of testing a semiconductor device having a substrate in and on which a cell structure and a termination structure are formed, the cell structure having a main current flowing therethrough, the termination structure surrounding the cell structure, the method includes a first test step of testing dielectric strength of the semiconductor device, a charge removal step of, after the first test step, removing charge from a top surface layer of the termination structure, the top surface layer being located on the substrate and formed of an insulating film or a semi-insulating film, and a second test step of, after the charge removal step, testing dielectric strength of the semiconductor device. | 12-11-2014 |
20140377891 | CHARGED PARTICLE BEAM IRRADIATION APPARATUS AND METHODS RELATED THERETO - A charged particle beam irradiation apparatus, which irradiates a substrate with a charged particle beam, includes a capacitance sensor and an optical sensor configured to measure a surface position of the substrate, a storage unit configured to store respective measurement values of the surface position of the substrate measured by the optical sensor and the capacitance sensor, and a calculation unit configured to obtain surface position data of the substrate, in which the calculation unit obtains a correction amount by using respective measurement values of the surface position measured by the capacitance sensor and the optical sensor in a region within a scribe line formed on the substrate, which are stored in the stored unit, and applies the correction amount to the measurement value of the surface position measured by the capacitance sensor, to obtain the surface position data of the substrate. | 12-25-2014 |
20140377892 | METHOD OF FORMING AN INTEGRATED INDUCTOR BY DRY ETCHING AND METAL FILLING - The present invention discloses an inductive element formed by through silicon via interconnections. The inductive element formed by means of the special through silicon via interconnection by using through silicon via technology features advantages such as high inductance and density. Moreover, the through silicon via interconnection integrated process forming the inductive element is compatible with the ordinary through silicon interconnection integrated process without any other steps, thus making the process simple and steady. The inductive element using the present invention is applicable to the through silicon via package manufacturing of various chips, especially the package manufacturing of power control chips and radio-frequency chips. | 12-25-2014 |
20150011028 | STACK TYPE SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING AND TESTING THE SAME - There are proposed a stack type semiconductor device and a method of fabricating and testing the same. A stack type semiconductor device according to an embodiment of the present invention includes a plurality of contact pads externally exposed, a via array electrically connected to the contact pads, a semiconductor substrate configured to have vias, forming the via array, electrically conductive with each other or insulated from each other, and a bias pad configured to supply a bias to the semiconductor substrate, wherein the semiconductor substrate may be subject to back-grinding. | 01-08-2015 |
20150031149 | MULTI-CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME - A multi-chip package may include a first semiconductor chip, a second semiconductor chip, a first stud bump, a first nail head bonding bump, a second stud bump, and a first conductive wire. The first semiconductor chip may have a first bonding pad. The second semiconductor chip may be stacked on the first semiconductor chip so the first bonding pad remains exposed. The second semiconductor chip may have a second bonding pad. The first stud bump may be formed on the first bonding pad. The first nail head bonding bump may be formed on the first stud bump, with one end of a first conductive wire formed between the two. The second stud bump may be formed on the second bonding pad, with another end of the first conductive wire formed between the two. An electrical connection test may be performed on each of the wire bonding processes. | 01-29-2015 |
20150044788 | TEST APPARATUS AND TEST METHOD - A test apparatus includes a foreign matter removal unit having a first slope provided with an abrasive coating or an adhesive sheet and a second slope provided with an abrasive coating or an adhesive sheet, the second slope facing the first slope in such a manner that an upper end of the second slope is spaced from an upper end of the first slope a greater distance than a lower end of the second slope is spaced from a lower end of the first slope, a test unit for testing electrical characteristics of a semiconductor chip, and a transfer unit for holding and releasing the semiconductor chip at a position above the first and second slopes and transferring the semiconductor chip to the test unit. | 02-12-2015 |
20150050757 | METHOD FOR TESTING SUSCEPTOR OF CHEMICAL VAPOR DEPOSITION APPARATUS AND METHOD FOR MANUFACTURING ORGANIC LIGHT EMITTING DISPLAY APPARATUS BY USING THE SAME - A method for testing a susceptor of a chemical vapor deposition (CVD) apparatus includes preparing a substrate including a transparent conductive layer, disposing the substrate with the transparent conductive layer on the susceptor of the CVD apparatus, and determining whether or not the susceptor of the CVD apparatus is normal by measuring a surface resistance across the transparent conductive layer. | 02-19-2015 |
20150056727 | METHOD OF INSPECTING SEMICONDUCTOR DEVICE, METHOD OF FABRICATING SEMICONDUCTOR DEVICE, AND INSPECTION TOOL - A method of inspecting a semiconductor device includes attaching an inspection tool on a back surface of a semiconductor substrate including the semiconductor device, the inspection tool including a sheet and a holding frame, the sheet being larger than the semiconductor substrate and being provided with an opening in a center portion of the sheet, the opening being smaller than the semiconductor substrate, the holding frame holding an outer periphery of the sheet, and a supporting substrate being attached on a front surface of the semiconductor substrate, removing the supporting substrate attached on the front surface of the semiconductor substrate, and measuring electrical characteristics of the semiconductor device. | 02-26-2015 |
20150064814 | MECHANISMS FOR MONITORING ION BEAM IN ION IMPLANTER SYSTEM - In accordance with some embodiments, an assembly of an ion implanter system is provided. The assembly includes a control unit, a wafer holder and a detecting device. The wafer holder and the detecting device are respectively positioned at two sides of the control unit. The control unit is configured to drive the wafer holder and the detecting device to rotate about at least one rotation axis. | 03-05-2015 |
20150064815 | Method of Making Molded LED Package - Methods of packaging a light emitting diode (LED) include providing a first lead having a first recess in a bottom surface and a second lead having a second recess in a bottom surface, placing a LED die over a top surface of at least one of the first and the second leads, electrically connecting the LED die to the first lead and to the second lead, forming a package around the LED die that includes an opening in its upper surface exposing at least the LED die, and separating the package containing the LED die, the first lead and the second lead from a lead frame such that the package contains a first castellation and a second castellation in a side surface of the package, such that the castellations expose the leads and/or a first platable metal which is electrically connected to the leads. | 03-05-2015 |
20150072447 | DETECTION OF DISASSEMBLY OF MULTI-DIE CHIP ASSEMBLIES - A multi-die chip assembly is described, the multi-die chip assembly including at least one detection apparatus which detects manipulations of the multi-die chip assembly, the detection apparatus including a distributed circuit including a circuit whose elements are distributed among those dies which include the elements of a local reference circuit, the distributed circuit including a free running clock, at least one local reference circuit disposed in at least one die of the multi-die chip assembly, each of the local reference circuits including a free running clock, and at least one non-volatile memory, in which is stored during manufacture of the multi-die chip assembly, an allowed range of a result of a function having at least two arguments for each reference circuit a value of the frequency of the local reference circuit as manufactured, and a value of the frequency of the distributed circuit as manufactured, at least one element of the plurality of memories being disposed in each die including the elements of the local reference circuit. Related methods, apparatus, and systems are also described. | 03-12-2015 |
20150072448 | METHOD FOR MANUFACTURING SiC SEMICONDUCTOR DEVICE - A method for manufacturing an SiC semiconductor device according to the present invention includes the steps of (a) implanting an impurity into a surface layer of an SiC substrate at a concentration of 1×10 | 03-12-2015 |
20150079705 | METHOD OF MANUFACTURING CONTAMINATION LEVEL OF ION IMPLANTING APPARATUS - A method of measuring a contamination level of an ion implanting apparatus is disclosed. The method may include the steps of providing a wafer, forming a first layer on the wafer, injecting impurities into the first layer, preparing an analysis sample by removing the first layer and concurrently collecting the impurities captured in the first layer from the wafer, and analyzing the analysis sample. | 03-19-2015 |
20150079706 | ON-CHIP PLASMA CHARGING SENSOR - A device for monitoring charging effects includes a semiconductor substrate having a surface region. The device also includes first, second, and third doped regions spaced apart in the semiconductor substrate and a dielectric layer overlying the surface region. The device also includes a first gate overlying a first portion of the dielectric layer disposed between the first and the second doped regions, and a second gate overlying a second portion of the dielectric layer disposed between the second and the third doped regions, the second gate being characterized by a first surface area. Moreover, the device has a conductive layer electrically coupled to the second gate for collecting plasma charges. The conductive layer is characterized by a second surface area. The first gate is connected to a conductor that is coupled to a bias voltage, and the second gate is a floating gate that is not connected to any voltage. | 03-19-2015 |
20150087090 | MONITOR TEST KEY OF EPI PROFILE - A method and apparatus for estimating a height of an epitaxially grown semiconductor material in other semiconductor devices. The method includes epitaxially growing first, second, and third portions of semiconductor material on a first semiconductor device, measuring a height of the third portion of semiconductor material and a height of the first or second portion of semiconductor material, measuring a first saturation current through the first and second portions of semiconductor material, measuring a second saturation current through the first and third portions of semiconductor material, and preparing a model of the first saturation current relative to the height of the first or second portion of semiconductor material and the second saturation current relative to an average of the height of the first and third portions of semiconductor material. The model is used to estimate the height of an epitaxially grown semiconductor material in the other semiconductor devices. | 03-26-2015 |
20150087091 | MANUFACTURING METHOD AND TEST METHOD OF SEMICONDUCTOR DEVICE - Provided is a test method by which a transistor whose reliability is low can be detected with low stress and high accuracy in a shorter period of time than a BT test. Provided is to detect a transistor whose reliability is high in a shorter period of time than a BT test and manufacture an electronic device with high reliability efficiently. Hysteresis characteristics revealed in the result of the Vg-Id measurement with light irradiation to the transistor correlate with the result of a BT test; whether the reliability of the transistor is Good or Not-Good can be judged. Accordingly, the test method by which a transistor whose reliability is low can be detected with low stress and high accuracy in a shorter period of time than a BT test can be provided. | 03-26-2015 |
20150099315 | MECHANISMS FOR MONITORING IMPURITY IN HIGH-K DIELECTRIC FILM - Embodiments of mechanisms of monitoring metal impurity in a high-k dielectric film are provided. The method includes forming an interfacial layer over a substrate. The method also includes forming a high-k dielectric film on the interfacial layer, and the interfacial layer and the high-k dielectric film form a stacked structure over the substrate. The method further includes conducting the first thickness measurement on the stacked structure. In addition, the method includes performing a treatment to the stacked structure after the first thickness measurement, and the treatment includes an annealing process. The method also includes conducting the second thickness measurement on the stacked structure after the treatment. | 04-09-2015 |
20150132868 | Method of Electrically Isolating Leads of a Lead Frame Strip - A lead frame strip includes a plurality of connected unit lead frames, each unit lead frame having a die paddle and a plurality of leads connected to a periphery of the unit lead frame. The lead frame strip is processed by attaching a semiconductor die to each of the die paddles and covering the unit lead frames with a molding compound after the semiconductor dies are attached to the die paddles. Spaced apart cuts are formed in the periphery of each unit lead frame that sever the leads from the periphery of each unit lead frame and extend at least partially into the molding compound in regions of the periphery where the leads are located so that the molding compound remains intact between the cuts. The lead frame strip is processed after the cuts are formed, and the unit lead frames are later separated into individual packages. | 05-14-2015 |
20150132869 | METHODS OF FABRICATING SEMICONDUCTOR DIE ASSEMBLIES - Methods of fabricating multi-die assemblies including a base semiconductor die bearing a peripherally encapsulated stack of semiconductor dice of lesser lateral dimensions, the dice vertically connected by conductive elements between the dice, resulting assemblies, and semiconductor devices comprising such assemblies. | 05-14-2015 |
20150140696 | Combinatorial Method for Solid Source Doping Process Development - One or more small spot showerhead apparatus are used to provide dopant exposure and/or to deposit materials using CVD, PECVD, ALD, or PEALD on small spots in a site isolated, combinatorial manner. The small spot showerheads may be configured within a larger combinatorial showerhead to allow multi-layer film stacks to be deposited in a combinatorial manner. Anneal processes where the area of the process can be controlled such as laser annealing or site-isolated rapid thermal processing (RTP) can be used to vary the annealing conditions in a combinatorial manner. | 05-21-2015 |
20150147830 | DETECTION OF SUBSTRATE DEFECTS BY TRACKING PROCESSING PARAMETERS - A method comprising processing a substrate exposed to a plasma in a processing chamber, obtaining a metric indicative of a parameter of the plasma during the processing of the substrate, and determining a defect in the substrate by comparing the metric to a predefined criteria. | 05-28-2015 |
20150293171 | METHODS AND APPARATUS FOR THINNING, TESTING AND SINGULATING A SEMICONDUCTOR WAFER - A wafer translator is provided with a patterned layer of wafer bonding thermoset plastic and is removably attached with a wafer so as to form a wafer/wafer translator pair. The wafer translator acts as a mechanical support during a thinning process as well as during a wafer dicing operation. The singulated integrated circuits are then removed from the wafer translator. In some embodiments, wafer level testing of the integrated circuits on the wafer is performed subsequent to the wafer thinning process but before the wafer and wafer translator are separated. In other embodiments, wafer level testing of the integrated circuits on the wafer is performed subsequent to the wafer dicing operation but before the diced wafer and wafer translator are separated. | 10-15-2015 |
20150332979 | MANUFACTURING METHOD OF ARRAY SUBSTRATE - An embodiment of the present invention provides a manufacturing method of an array substrate comprising forming a gate detecting pattern on the array substrate with gate lines and common electrode lines formed thereon, the gate detecting pattern being arranged on one side of a pixel region of the array substrate and used to connect all the common electrode lines for pixel units; and performing a short circuit or a open circuit detection, wherein if the difference between a signal received by a receiving terminal for a gate line and a signal transmitted from a transmitting terminal for the gate line is larger than a predetermined detection threshold value, it is determined that short circuit between the gate line and a common electrode line or open circuit in the gate line occurs. | 11-19-2015 |
20160005609 | MANUFACTURING METHOD OF GRAPHENE MODULATED HIGH-K OXIDE AND METAL GATE MOS DEVICE - A manufacturing method of a graphene modulated high-k oxide and metal gate Ge-based MOS device, which comprises the following steps: 1) introducing a graphene thin film on a Ge-based substrate; 2) conducting fluorination treatment to the graphene thin film to form fluorinated graphene; 3) activating the surface of the fluorinated graphene by adopting ozone plasmas, and then forming a high-k gate dielectric on the surface of the fluorinated graphene through an atomic layer deposition technology; and 4) forming a metal electrode on the surface of the high-k gate dielectric. Since the present invention utilizes the graphene as a passivation layer to inhibit the formation of unstable oxide GeO | 01-07-2016 |
20160005664 | METHOD FOR MEASURING RECOMBINATION LIFETIME OF SILICON SUBSTRATE - Provided is a method of measuring a recombination lifetime of a silicon substrate, which is capable of evaluating metal contamination and crystal defects in a silicon substrate manufacturing process and a device manufacturing process with high accuracy. The method includes: measuring a recombination lifetime of a silicon substrate after subjecting a surface of the silicon substrate to chemical passivation processing; and performing ultraviolet protection processing of protecting at least the silicon substrate from ultraviolet rays during a period from the chemical passivation processing to a time when the measurement of the recombination lifetime is completed. | 01-07-2016 |
20160035633 | LOW ENERGY COLLIMATED ION MILLING OF SEMICONDUCTOR STRUCTURES - A method of delayering a surface of a semiconductor structure may include applying a voltage in the range of about 50 eV to less than 300 eV to an inductively coupled Argon ion source operating at a radio frequency. A collimated ion beam incident on the surface of the semiconductor structure may be generated, from the Argon ion source, for the planar removal of layers of the surface. A structural material underlying the surface of the semiconductor structure is exposed using an end-point detector based on the planar removal of the layers. | 02-04-2016 |
20160056085 | SEMICONDUCTOR DEVICE TESTING APPARATUS, SEMICONDUCTOR DEVICE TESTING METHOD, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device testing apparatus according to an embodiment includes: a first terminal and a second terminal that apply voltage to a semiconductor device; and a light source that irradiates the semiconductor device with ultraviolet light. | 02-25-2016 |
20160064292 | METHOD OF MEASURING BREAKDOWN VOLTAGE OF SEMICONDUCTOR ELEMENT AND METHOD OF MANUFACTURING SEMICONDUCTOR ELEMENT - A method of measuring a breakdown voltage of a semiconductor element includes the steps below. A wafer provided with a plurality of semiconductor elements each having an electrode is prepared. The wafer is divided into a plurality of chips provided with at least one semiconductor element. After the step of division into the plurality of chips, a breakdown voltage of the semiconductor element is measured while a probe is in contact with the electrode of the semiconductor element in an insulating liquid. | 03-03-2016 |
20160079130 | METHOD FOR EVALUATING A SEMICONDUCTOR WAFER - A method for evaluating a semiconductor wafer including preparing a reference wafer in which contamination element and amount of contamination are known, forming a plurality of cells including p-n junctions on the reference wafer, measuring junction leakage currents in the plurality of cells on the reference wafer to acquire a distribution of the junction leakage currents of the reference wafer, associating the distribution of the junction leakage currents of the reference wafer with a contamination element, forming a plurality of cells including p-n junctions on a wafer to be measured, measuring junction leakage currents in the plurality of cells on the wafer to be measured to acquire a distribution of the junction leakage currents of the wafer to be measured, and identifying a contamination element of the wafer to be measured based on the association. | 03-17-2016 |
20160086863 | SEMICONDUCTOR DEVICE FOR TESTING LARGE NUMBER OF DEVICES AND COMPOSING METHOD AND TEST METHOD THEREOF - Provided is a method for testing a plurality of transistors of a semiconductor device. The method includes forming a plurality of elements or a plurality of logic using a Front End Of Line (FEOL) process, forming a selection logic using at least one of the plurality of elements or the plurality of logic cells, connecting the selection logic and the plurality of transistors, forming a pad for connecting an input terminal of the selection logic and drain or source terminals of the plurality of transistors, and sequentially selecting the plurality of transistors using the selection logic and measuring an electrical characteristic of selected transistors among the plurality of transistors. | 03-24-2016 |
20160093753 | SOLAR CELL MANUFACTURING METHOD - There is provided a solar cell manufacturing method comprising: a step of preparing a photoelectric conversion cell having a first main surface and a second main surface; a step of forming a first collector electrode on the first main surface and forming a second collector electrode on the second main surface; a step of measuring characteristic values of the photoelectric conversion cell having the first collector electrode and the second collector electrode thereon; and a step of forming a third collector electrode on at least one of the first main surface and the second main surface based on the characteristic values. | 03-31-2016 |
20160111342 | METHOD AND APPARATUS FOR CHARACTERIZING METAL OXIDE REDUCTION - Method and apparatus for characterizing metal oxide reduction using metal oxide films formed by exposure to an oxygen plasma are disclosed. A substrate including a metal seed layer is exposed to the oxygen plasma to form a metal oxide of the metal seed layer, where the exposure can take place at a low temperature and low pressure. Oxidized substrates formed in this manner provide metal oxides that are repeatable, uniform, and stable. The oxidized substrates can be stored for later use or exposed to a reducing treatment to the metal oxide to metal. In some implementations, exposure to the reducing treatment includes exposure to plasma of a reducing gas species, where the plasma of the reducing gas species and the oxygen plasma can both be produced in a remote plasma source. | 04-21-2016 |
20160126149 | METHOD FOR PROCESSING A SUBSTRATE AND A METHOD OF PROCESS SCREENING FOR INTEGRATED CIRCUITS - According to various embodiments, a method for processing a substrate may include: forming a dielectric layer over the substrate, the dielectric layer may include a plurality of test regions; forming an electrically conductive layer over the dielectric layer to contact the dielectric layer in the plurality of test regions; simultaneously electrically examining the dielectric layer in the plurality of test regions, wherein portions of the electrically conductive layer contacting the dielectric layer in the plurality of test regions are electrically conductively connected with each other by an electrically conductive material; and separating the electrically conductive layer into portions of the electrically conductive layer contacting the dielectric layer in the plurality of test regions from each other. | 05-05-2016 |
20160141216 | PROBE PAD WITH INDENTATION - An integrated electronic circuit has probe indentations filled by a hard covering substance. The integrated circuit device results from a process of manufacturing including forming a substrate comprising a plurality of functional components of the electronic circuit, creating a plurality of conductive layers on such substrate to form an electric contact region with high hardness equal to or greater than a first hardness value of about 300 HV, contacting the electric contact region with a probe thereby causing an indentation. The process further comprises, after the test run, creating a covering conductive layer on at least one part of the electric contact region contacted by the probe to fill the indentation. | 05-19-2016 |
20160190022 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - Degradation of reliability of a semiconductor device is prevented. An electrode pad included mainly of aluminum is formed over a main surface of a semiconductor wafer. Subsequently, a first insulating member and a second insulating member are formed over the main surface of the semiconductor wafer so as to cover the electrode pad, and thereafter an opening portion that exposes a surface of the electrode pad is formed in the first insulating member and the second insulating member by a dry etching method using an etching gas including a halogen-based gas. Thereafter, an oxide film with a thickness of 2 nm to 6 nm is formed over the exposed surface of the electrode pad by performing a heat treatment at 200° C. to 300° C. in an air atmosphere, and then the semiconductor wafer is stored. | 06-30-2016 |