Top Inventors for class "Data processing: design and analysis of circuit or semiconductor mask" |
Rank | Inventor's name | Country | City/State | Last publication | # of patent apps in this class |
1 | Yi-Kan Cheng | TW | Taipei | Aug 04, 2022 / 20220246509 - PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME | 50 |
2 | Chandramouli Visweswariah | US | Croton-On-Hudson, NY | Jul 13, 2017 / 20170199956 - ACCURATE STATISTICAL TIMING FOR BOUNDARY GATES OF HIERARCHICAL TIMING MODELS | 49 |
3 | Jason R. Baumgartner | US | Austin, TX | Jun 12, 2014 / 20140165015 - VECTORIZATION OF BIT-LEVEL NETLISTS | 36 |
4 | Vladimir Zolotov | US | Putnam Valley, NY | Jul 13, 2017 / 20170199953 - SENSITIVITY CALCULATION FILTERING FOR STATISTICAL STATIC TIMING ANALYSIS OF AN INTEGRATED CIRCUIT | 35 |
5 | Jun Ye | US | Palo Alto, CA | Feb 04, 2016 / 20160033872 - METHOD OF PERFORMING MODEL-BASED SCANNER TUNING | 35 |
6 | Eric A. Foreman | US | Fairfax, VT | Jul 13, 2017 / 20170199953 - SENSITIVITY CALCULATION FILTERING FOR STATISTICAL STATIC TIMING ANALYSIS OF AN INTEGRATED CIRCUIT | 34 |
7 | Hari Mony | US | Austin, TX | Mar 12, 2015 / 20150074628 - Enhanced Case-Splitting Based Property Checking | 34 |
8 | Peter A. Habitz | US | Hinesburg, VT | Mar 19, 2015 / 20150082260 - MODELING MULTI-PATTERNING VARIABILITY WITH STATISTICAL TIMING | 34 |
9 | Chung-Hsing Wang | TW | Baoshan Township | Sep 08, 2022 / 20220285263 - SEMICONDUCTOR ARRANGEMENT AND METHOD OF MAKING | 32 |
10 | David J. Hathaway | US | Underhill, VT | Dec 29, 2016 / 20160380839 - EFFICIENT PARALLEL PROCESSING OF A NETWORK WITH CONFLICT CONSTRAINTS BETWEEN NODES | 31 |
11 | Victor Moroz | US | Saratoga, CA | Mar 19, 2020 / 20200089841 - Mapping Intermediate Material Properties to Target Properties to Screen Materials | 31 |
12 | Akira Fujimura | US | Saratoga, CA | Oct 07, 2021 / 20210313143 - METHOD AND SYSTEM FOR DETERMINING A CHARGED PARTICLE BEAM EXPOSURE FOR A LOCAL PATTERN DENSITY | 30 |
13 | Chin Ngai Sze | US | Austin, TX | Jun 07, 2018 / 20180154176 - TRANSLATING DIFFERENT CLINICAL PROTOCOLS FOR PARTICLE THERAPY INTO A SET OF CONSTRAINTS | 29 |
14 | Shou-Kuo Hsu | TW | Tu-Cheng | May 21, 2015 / 20150138744 - PRINTED CIRCUIT BOARD | 28 |
15 | Mahesh A. Iyer | US | Fremont, CA | Jul 07, 2022 / 20220215147 - Temperature Control Systems And Methods For Integrated Circuits | 27 |
16 | Lee-Chung Lu | TW | Taipei | Oct 07, 2021 / 20210313985 - FLIP-FLOP DEVICE AND METHOD OF OPERATING FLIP-FLOP DEVICE | 27 |
17 | Viresh Paruthi | US | Austin, TX | Mar 31, 2022 / 20220100474 - DETECTION OF UNINTENDED DEPENDENCIES IN HARDWARE DESIGNS WITH PSEUDO-RANDOM NUMBER GENERATORS | 26 |
18 | Zhuo Li | US | Cedar Park, TX | May 12, 2016 / 20160132769 - FAULT-TOLERANT POWER-DRIVEN SYNTHESIS | 24 |
19 | Huang-Yu Chen | TW | Zhudong Township | May 07, 2015 / 20150128101 - PROMOTING EFFICIENT CELL USAGE TO BOOST QOR IN AUTOMATED DESIGN | 24 |
20 | Wen-Chun Huang | TW | Tainan City | Sep 14, 2017 / 20170262571 - ENVIRONMENTAL-SURROUNDING-AWARE OPC | 24 |
21 | Steven Teig | US | Menlo Park, CA | Mar 24, 2016 / 20160087635 - Operational Time Extension | 23 |
22 | Natesan Venkateswaran | US | Hopewell Junction, NY | Jul 13, 2017 / 20170199953 - SENSITIVITY CALCULATION FILTERING FOR STATISTICAL STATIC TIMING ANALYSIS OF AN INTEGRATED CIRCUIT | 23 |
23 | Amir H. Mottaez | US | Los Altos, CA | Feb 05, 2015 / 20150040107 - SOLVING AN OPTIMIZATION PROBLEM USING A CONSTRAINTS SOLVER | 22 |
24 | Ru-Gun Liu | TW | Zhubei City | Sep 08, 2022 / 20220285168 - METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES | 21 |
25 | Robert L. Kanzelman | US | Rochester, MN | Nov 14, 2013 / 20130305197 - METHOD AND SYSTEM FOR OPTIMAL DIAMETER BOUNDING OF DESIGNS WITH COMPLEX FEED-FORWARD COMPONENTS | 21 |
26 | Kenneth S. Mcelvain | US | Los Altos, CA | Jun 30, 2016 / 20160188774 - Circuit Design and Optimization | 21 |
27 | Kenneth S. Mcelvain | US | Menlo Park, CA | Jul 31, 2014 / 20140215427 - Optimizing Designs of Integrated Circuits | 21 |
28 | Ru-Gun Liu | TW | Hsinchu City | Sep 04, 2014 / 20140248555 - EXTREME ULTRAVIOLET LIGHT (EUV) PHOTOMASKS, AND FABRICATION METHODS THEREOF | 21 |
29 | Yu Cao | US | Saratoga, CA | Sep 01, 2022 / 20220276564 - METHOD AND APPARATUS FOR PHOTOLITHOGRAPHIC IMAGING | 21 |
30 | Michael C. Smayling | US | San Jose, CA | Apr 22, 2010 / 20100096671 - Cell of Semiconductor Device Having Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and At Least Eight Transistors | 20 |
31 | Scott T. Becker | US | San Jose, CA | Apr 22, 2010 / 20100096671 - Cell of Semiconductor Device Having Gate Electrode Conductive Structures Formed from Rectangular Shaped Gate Electrode Layout Features and At Least Eight Transistors | 20 |
32 | Dipankar Pramanik | US | Saratoga, CA | May 26, 2016 / 20160149129 - Using Metal Silicides as Electrodes for MSM Stack in Selector for Non-Volatile Memory Application | 20 |
33 | Alan E. Rosenbluth | US | Yorktown Heights, NY | Apr 21, 2016 / 20160109795 - SOURCE, TARGET AND MASK OPTIMIZATION BY INCORPORATING CONTOUR BASED ASSESSMENTS AND INTEGRATION OVER PROCESS VARIATIONS | 19 |
34 | John P. Dubuque | US | Jericho, VT | Dec 29, 2016 / 20160378903 - DYNAMIC AND ADAPTIVE TIMING SENSITIVITY DURING STATIC TIMING ANALYSIS USING LOOK-UP TABLE | 19 |
35 | Ken-Hsien Hsieh | TW | Taipei City | Sep 08, 2022 / 20220285168 - METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES | 19 |
36 | Michael L. Case | US | Pflugerville, TX | Mar 06, 2014 / 20140067897 - FORMAL VERIFICATION OF BOOTH MULTIPLIERS | 18 |
37 | International Business Machines Corporation | US | Armonk, NY | Sep 18, 2014 / 20140282563 - DEPLOYING PARALLEL DATA INTEGRATION APPLICATIONS TO DISTRIBUTED COMPUTING ENVIRONMENTS | 18 |
38 | Wen-Ju Yang | TW | Hsinchu City | Apr 16, 2020 / 20200117848 - METHOD OF DETERMINING COLORABILITY OF A SEMICONDUCTOR DEVICE AND SYSTEM FOR IMPLEMENTING THE SAME | 18 |
39 | Jeanne P. Bickford | US | Essex Junction, VT | Dec 29, 2016 / 20160377674 - INTEGRATED CIRCUIT CHIP RELIABILITY QUALIFICATION USING A SAMPLE-SPECIFIC EXPECTED FAIL RATE | 18 |
40 | Yuan-Te Hou | TW | Hsinchu City | Dec 16, 2021 / 20210390240 - INTEGRATED CIRCUIT WITH THICKER METAL LINES ON LOWER METALLIZATION LAYER | 18 |
41 | Chin-Chang Hsu | TW | Banqiao City | Apr 16, 2020 / 20200117848 - METHOD OF DETERMINING COLORABILITY OF A SEMICONDUCTOR DEVICE AND SYSTEM FOR IMPLEMENTING THE SAME | 18 |
42 | Charles J. Alpert | US | Austin, TX | May 12, 2016 / 20160132769 - FAULT-TOLERANT POWER-DRIVEN SYNTHESIS | 18 |
43 | Jeffrey G. Hemmett | US | St. George, VT | Jul 13, 2017 / 20170199953 - SENSITIVITY CALCULATION FILTERING FOR STATISTICAL STATIC TIMING ANALYSIS OF AN INTEGRATED CIRCUIT | 18 |
44 | Kerim Kalafala | US | Rhinebeck, NY | Jan 14, 2021 / 20210011980 - FEEDBACK-AWARE SLACK STEALING ACROSS TRANSPARENT LATCHES EMPOWERING PERFORMANCE OPTIMIZATION OF DIGITAL INTEGRATED CIRCUITS | 18 |
45 | Sani R. Nassif | US | Austin, TX | Jun 07, 2018 / 20180154176 - TRANSLATING DIFFERENT CLINICAL PROTOCOLS FOR PARTICLE THERAPY INTO A SET OF CONSTRAINTS | 17 |
46 | Gi-Joon Nam | US | Austin, TX | May 12, 2016 / 20160132769 - FAULT-TOLERANT POWER-DRIVEN SYNTHESIS | 17 |
47 | Hsiao-Shu Chao | TW | Baoshan Township | Feb 19, 2015 / 20150052493 - METHOD OF GENERATING A SIMULATION MODEL OF A PREDEFINED FABRICATION PROCESS | 17 |
48 | Jui-Feng Kuan | TW | Zhubei City | May 18, 2017 / 20170141003 - ELECTRMIGRATION SIGN-OFF METHODOLOGY | 17 |
49 | Natarajan Viswanathan | US | Austin, TX | Jul 16, 2015 / 20150199465 - BOUNDARY LATCH AND LOGIC PLACEMENT TO SATISFY TIMING CONSTRAINTS | 17 |
50 | Xi-Wei Lin | US | Fremont, CA | Dec 10, 2015 / 20150356232 - Method and System for Generating a Circuit Design, Method for Calibration of an Inspection Apparatus and Method for Process Control and Yield Management | 17 |
51 | Jason D. Hibbeler | US | Williston, VT | Aug 20, 2015 / 20150234422 - Tunable Sector Buffer for Wide Bandwidth Resonant Global Clock Distribution | 16 |
52 | Ke-Ying Su | TW | Taipei City | May 26, 2016 / 20160147928 - METHOD, DEVICE AND COMPUTER PROGRAM PRODUCT FOR INTEGRATED CIRCUIT LAYOUT GENERATION | 16 |
53 | Kanak B. Agarwal | US | Austin, TX | Jan 03, 2019 / 20190004579 - CONTINUOUSLY AVAILABLE POWER CONTROL SYSTEM | 16 |
54 | Andrew Caldwell | US | Santa Clara, CA | Mar 24, 2016 / 20160087635 - Operational Time Extension | 16 |
55 | Yuri Granik | US | Palo Alto, CA | May 19, 2016 / 20160140278 - Modeling Photoresist Shrinkage Effects In Lithography | 16 |
56 | Fedor G. Pikus | US | Beaverton, OR | Apr 28, 2016 / 20160117437 - Electrostatic Damage Protection Circuitry Verification | 16 |
57 | Timothy D. Helvey | US | Rochester, MN | Jun 15, 2017 / 20170169155 - METHOD TO ADJUST ALLEY GAP BETWEEN LARGE BLOCKS FOR FLOORPLAN OPTIMIZATION | 15 |
58 | Lars W. Liebmann | US | Poughquag, NY | Dec 27, 2018 / 20180374932 - GATE TIE-DOWN ENABLEMENT WITH INNER SPACER | 15 |
59 | Ruchir Puri | US | Baldwin Place, NY | Oct 13, 2016 / 20160299975 - Concept Analysis Operations Utilizing Accelerators | 15 |
60 | Toshiya Kotani | JP | Machida-Shi | Sep 17, 2015 / 20150263026 - SEMICONDUCTOR DEVICE AND DESIGN APPARATUS FOR SEMICONDUCTOR DEVICE | 15 |
61 | Chia-Nan Pai | TW | Tu-Cheng | May 21, 2015 / 20150138744 - PRINTED CIRCUIT BOARD | 15 |
62 | Hanying Feng | US | Fremont, CA | Jun 22, 2017 / 20170176864 - OPTIMIZATION FLOWS OF SOURCE, MASK AND PROJECTION OPTICS | 14 |
63 | James A. Culp | US | Newburgh, NY | Dec 17, 2015 / 20150363536 - CORRECTING FOR STRESS INDUCED PATTERN SHIFTS IN SEMICONDUCTOR MANUFACTURING | 14 |
64 | Paul G. Villarrubia | US | Austin, TX | Jul 16, 2015 / 20150199465 - BOUNDARY LATCH AND LOGIC PLACEMENT TO SATISFY TIMING CONSTRAINTS | 14 |
65 | Li-Chun Tien | TW | Tainan City | Sep 15, 2022 / 20220293638 - SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME | 14 |
66 | Samuel I. Ward | US | Austin, TX | Jan 07, 2016 / 20160006977 - RECORDING EVENTS IN A VIRTUAL WORLD | 14 |
67 | Tsong-Hua Ou | TW | Taipei City | Jun 30, 2016 / 20160190070 - Multiple Edge Enabled Patterning | 14 |
68 | Charles J. Alpert | US | Cedar Park, TX | Sep 02, 2010 / 20100223586 - TECHNIQUES FOR PARALLEL BUFFER INSERTION | 14 |
69 | Juan Andres Torres Robles | US | Wilsonville, OR | Aug 13, 2015 / 20150227676 - Generating Guiding Patterns For Directed Self-Assembly | 13 |
70 | Wen-Hao Chen | TW | Hsin-Chu City | Nov 25, 2021 / 20210366844 - VIA RAIL SOLUTION FOR HIGH POWER ELECTROMIGRATION | 13 |
71 | Cheng Kun Tsai | TW | Hsinchu City | Jun 09, 2016 / 20160162627 - Method for Integrated Circuit Manufacturing | 13 |
72 | Jinjun Xiong | US | White Plains, NY | Feb 16, 2017 / 20170046307 - RUNTIME OF CUBLAS MATRIX MULTIPLICATION ON GPU | 13 |
73 | Dureseti Chidambarrao | US | Weston, CT | Dec 29, 2016 / 20160378888 - MODELING TRANSISTOR PERFORMANCE CONSIDERING NON-UNIFORM LOCAL LAYOUT EFFECTS | 13 |
74 | Chung-Min Fu | TW | Chungli | Apr 30, 2015 / 20150121329 - METHOD AND SYSTEM FOR DESIGNING FIN-FET SEMICONDUCTOR DEVICE | 13 |
75 | Fook-Luen Heng | US | Yorktown Heights, NY | Sep 15, 2022 / 20220294700 - NETWORK MANAGEMENT USING HIERARCHICAL AND MULTI-SCENARIO GRAPHS | 12 |
76 | Vaughn Betz | CA | Toronto | Jun 04, 2015 / 20150154338 - Method and Apparatus for Performing Parallel Routing Using a Multi-Threaded Routing Procedure | 12 |
77 | Charles Jay Alpert | US | Austin, TX | Jun 26, 2014 / 20140181772 - DETERMINING HIGH QUALITY INITIAL CANDIDATE SINK LOCATIONS FOR ROBUST CLOCK NETWORK DESIGN | 12 |
78 | Luoqi Chen | US | Saratoga, CA | Jun 22, 2017 / 20170176864 - OPTIMIZATION FLOWS OF SOURCE, MASK AND PROJECTION OPTICS | 12 |
79 | Chin-Hsiung Hsu | TW | Guanyin Township | Apr 02, 2015 / 20150095857 - METHOD AND SYSTEM FOR MULTI-PATTERNING LAYOUT DECOMPOSITION | 12 |
80 | Mu-Jen Huang | TW | Taipei City | Jul 01, 2021 / 20210197721 - WARNING SYSTEM IMPLEMENTED IN A VEHICLE AND METHOD THEREOF | 12 |
81 | Toshiya Kotani | JP | Tokyo | Apr 23, 2015 / 20150113485 - PATTERN DATA GENERATION METHOD, PATTERN VERIFICATION METHOD, AND OPTICAL IMAGE CALCULATION METHOD | 12 |
82 | Takahiko Orita | JP | Kawasaki | Jul 09, 2015 / 20150195213 - REQUEST DISTRIBUTION METHOD AND INFORMATION PROCESSING APPARATUS | 12 |
83 | Zhuo Li | US | Austin, TX | Mar 27, 2014 / 20140088791 - SOLVING TRAFFIC CONGESTION USING VEHICLE GROUPING | 11 |
84 | David White | US | San Jose, CA | Aug 21, 2014 / 20140237440 - METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR IMPLEMENTING ELECTRONIC CIRCUIT DESIGNS WITH SIMULATION AWARENESS | 11 |
85 | Scott T. Becker | US | Scotts Valley, CA | Sep 17, 2020 / 20200295044 - Semiconductor Chip Including Integrated Circuit Having Cross-Coupled Transistor Configuration and Method for Manufacturing the Same | 11 |
86 | Louise H. Trevillyan | US | Katonah, NY | Jul 18, 2013 / 20130185691 - TASK-BASED MULTI-PROCESS DESIGN SYNTHESIS | 11 |
87 | Kazuyuki Hagiwara | JP | Tokyo | Apr 19, 2018 / 20180108513 - METHOD AND SYSTEM FOR DIMENSIONAL UNIFORMITY USING CHARGED PARTICLE BEAM LITHOGRAPHY | 11 |
88 | Ryosuke Oishi | JP | Kawasaki | Dec 31, 2015 / 20150379177 - COMPUTER PRODUCT FOR SUPPORTING DESIGN AND VERIFICATION OF INTEGRATED CIRCUIT | 11 |
89 | Juergen Koehl | DE | Weil Im Schoenbuch | May 31, 2012 / 20120137262 - METHOD FOR COMPUTING THE SENSITIVITY OF A VLSI DESIGN TO BOTH RANDOM AND SYSTEMATIC DEFECTS USING A CRITICAL AREA ANALYSIS TOOL | 11 |
90 | Nazmul Habib | US | South Burlington, VT | Jan 26, 2017 / 20170023924 - APPLICATION OF STRESS CONDITIONS FOR HOMOGENIZATION OF STRESS SAMPLES IN SEMICONDUCTOR PRODUCT ACCELERATION STUDIES | 11 |
91 | Ying Liu | US | Austin, TX | Jun 22, 2017 / 20170177767 - CONFIGURATION OF LARGE SCALE ADVECTION DIFFUSION MODELS WITH PREDETERMINED RULES | 11 |
92 | James C. Parker | US | Zionsville, PA | Feb 27, 2014 / 20140059505 - METHOD FOR DESIGNING INTEGRATED CIRCUITS EMPLOYING CORRECT-BY-CONSTRUCTION PROGRESSIVE MODELING AND AN APPARATUS EMPLOYING THE METHOD | 11 |
93 | Yu Cao | US | Cupertino, CA | Jan 05, 2012 / 20120005637 - SMART SELECTION AND/OR WEIGHTING OF PARAMETERS FOR LITHOGRAPHIC PROCESS SIMULATION | 11 |
94 | Michael S. Gray | US | Fairfax, VT | Mar 21, 2013 / 20130074025 - POST TIMING LAYOUT MODIFICATION FOR PERFORMANCE | 11 |
95 | Tong Gao | US | Cupertino, CA | Mar 27, 2014 / 20140089868 - AUTOMATED REPAIR METHOD AND SYSTEM FOR DOUBLE PATTERNING CONFLICTS | 11 |
96 | Haoxing Ren | US | Austin, TX | Sep 15, 2022 / 20220292335 - Reinforcement driven standard cell placement | 11 |
97 | Mark A. Lavin | US | Katonah, NY | Sep 15, 2022 / 20220294700 - NETWORK MANAGEMENT USING HIERARCHICAL AND MULTI-SCENARIO GRAPHS | 10 |
98 | Stephen G. Shuma | US | Underhill, VT | Jul 13, 2017 / 20170199953 - SENSITIVITY CALCULATION FILTERING FOR STATISTICAL STATIC TIMING ANALYSIS OF AN INTEGRATED CIRCUIT | 10 |
99 | James Walter Blatchford | US | Richardson, TX | Jun 22, 2017 / 20170178966 - ELONGATED CONTACTS USING LITHO-FREEZE-LITHO-ETCH PROCESS | 10 |
100 | Ming Su | CA | Nepean | Sep 11, 2014 / 20140258953 - HIGH PERFORMANCE DESIGN RULE CHECKING TECHNIQUE | 10 |