Patent application number | Description | Published |
20080209376 | SYSTEM AND METHOD FOR SIGN-OFF TIMING CLOSURE OF A VLSI CHIP - A method for performing timing optimization of a detail routed netlist, incorporating statistical variability information, common path pessimism reduction, and capacitative coupling information, in a tightly coupled, incremental manner with minimal perturbations to the placement, routing, and asserted parasitic information. The method corrects violations in a placed and routed design of a VLSI circuit chip, where the design is represented by a netlist describing logical and physical characteristics of the design and by a corresponding timing graph, the method including the steps of: identifying violations in the design; iteratively eliminating the violations by incrementally transforming the logical and the physical characteristics of the design, incorporating in the design only legal placements and routes; and applying incremental timing to evaluate the transformations, and updating the existing timing graphs to reflect changes consisting of the legal placements and routes. | 08-28-2008 |
20080282213 | METHOD TO REDUCE THE WIRELENGTH OF ANALYTICAL PLACEMENT TECHNIQUES BY MODULATION OF SPREADING FORCES VECTORS - A method of force directed placement programming is presented. The method includes: assigning a plurality of objects from a cell netlist to bins; shifting the objects based on the bins; computing a magnitude of a spreading force for each object of the plurality of objects based on the shifting; sorting the objects based on the magnitude of the spreading force of the objects; selecting a subset of the sorted objects based on a threshold value indicating at least one of a top percentage, a threshold force, and a threshold value that is based on a placement congestion; adjusting the spreading force of the selected objects to be equal to a predetermined value indicating a minimum spreading force; and determining a placement of the objects based on adjusted spreading force of the selected objects. | 11-13-2008 |
20100042955 | Method of Minimizing Early-mode Violations Causing Minimum Impact to a Chip Design - A system and a method for correcting early-mode timing violations that operate across the process space of a circuit design. Optimizations are performed to replace padding that increase path delays on fast paths. At the stage in the design process where early-mode violations are addressed, placement, late-mode timing closure, routing, and detailed electrical and timing analysis are assumed to have been completed. The optimizations are designed to be effective in delaying fast paths while minimizing the impact on already-completed work on the chip, in contrast to relying only on adding pads that can have a negative impact on all of these quantities. The optimizations are classified according to their invasiveness and are followed by their deployment. The deployment is designed to minimize using delay pads, reduce design disruptions, and minimize effects on other aspects of the design. | 02-18-2010 |
20100192155 | SCHEDULING FOR PARALLEL PROCESSING OF REGIONALLY-CONSTRAINED PLACEMENT PROBLEM - Scheduling of parallel processing for regionally-constrained object placement selects between different balancing schemes. For a small number of movebounds, computations are assigned by balancing the placeable objects. For a small number of objects per movebound, computations are assigned by balancing the movebounds. If there are large numbers of movebounds and objects per movebound, both objects and movebounds are balanced amongst the processors. For object balancing, movebounds are assigned to a processor until an amortized number of objects for the processor exceeds a first limit above an ideal number, or the next movebound would raise the amortized number of objects above a second, greater limit. For object and movebound balancing, movebounds are sorted into descending order, then assigned in the descending order to host processors in successive rounds while reversing the processor order after each round. The invention provides a schedule in polynomial-time while retaining high quality of results. | 07-29-2010 |
20110302544 | POST-PLACEMENT CELL SHIFTING - A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells. | 12-08-2011 |
20110302545 | DETAILED ROUTABILITY BY CELL PLACEMENT - A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing. | 12-08-2011 |
20110320992 | BUFFER-AWARE ROUTING IN INTEGRATED CIRCUIT DESIGN - A method, system, and computer usable program product for buffer-aware routing in integrated circuit design are provided in the illustrative embodiments. The design has cells, and the circuit includes buffers and wires. A route is received from a set of routes. The route couples a first point in the circuit to a second point in the circuit and including at least one buffer between the first point and the second point. A determination is made whether the route violates a set of hard constraints for a part of the circuit, where the set of hard constraints includes a reach length constraint. In response to the route not violating any hard constraint in the set of hard constraints, the route is selected as a buffer-aware routing solution between the first and the second points in the circuit. | 12-29-2011 |
20120131530 | PARTITIONING FOR HARDWARE-ACCELERATED FUNCTIONAL VERIFICATION - A circuit design is partitioned for hardware-accelerated functional verification using a directed hypergraph with edge weights that are a function of slack. Slack may be computed as the difference between the early and late ranks for the source of an edge. The weight may further be computed as the difference between the edge's slack and a maximum slack value. In a preferred implementation each vertex also has multiple weights associated with resource requirements of different node types, and the partitioning is constrained to prevent vertex movement that would result in vertex weights for a given partition exceeding a partition resource capacity based on the accelerator architecture. Edge and vertex weights can be recomputed for the next level of partitioning. The partitioning process can be repeatedly iteratively until a termination criterion is met, the termination criterion being based in part on the number of directed cuts in each of the partitions. | 05-24-2012 |
20120284733 | Scheduling for Parallel Processing of Regionally-Constrained Placement Problem - Scheduling of parallel processing for regionally-constrained object placement selects between different balancing schemes. For a small number of movebounds, computations are assigned by balancing the placeable objects. For a small number of objects per movebound, computations are assigned by balancing the movebounds. If there are large numbers of movebounds and objects per movebound, both objects and movebounds are balanced amongst the processors. For object balancing, movebounds are assigned to a processor until an amortized number of objects for the processor exceeds a first limit above an ideal number, or the next movebound would raise the amortized number of objects above a second, greater limit. For object and movebound balancing, movebounds are sorted into descending order, then assigned in the descending order to host processors in successive rounds while reversing the processor order after each round. The invention provides a schedule in polynomial-time while retaining high quality of results. | 11-08-2012 |
20120297355 | WHITESPACE CREATION AND PRESERVATION IN CIRCUIT DESIGN - A method, system, and computer program product for whitespace creation and preservation in the design of an integrated circuit (IC) are provided in the illustrative embodiments. A first estimate is formed by estimating an amount of whitespace that is needed to reduce a congestion value of a congested area of the design to a threshold value. A set of virtual filler cells is added to the congested area, wherein adding the set of virtual filler cells does not add actual whitespace cells to the congested area but reduces the congested area by at least the first estimate. A virtual filler cell in the set of virtual filler cells is replaced with a corresponding real filler cell. A determination is made whether the design has improved. A final placement solution is created when the design has not improved. | 11-22-2012 |
20120317527 | PARTITIONING FOR HARDWARE-ACCELERATED FUNCTIONAL VERIFICATION - A circuit design is partitioned for hardware-accelerated functional verification using a directed hypergraph with edge weights that are a function of slack. Slack may be computed as the difference between the early and late ranks for the source of an edge. The weight may further be computed as the difference between the edge's slack and a maximum slack value. In a preferred implementation each vertex also has multiple weights associated with resource requirements of different node types, and the partitioning is constrained to prevent vertex movement that would result in vertex weights for a given partition exceeding a partition resource capacity based on the accelerator architecture. Edge and vertex weights can be recomputed for the next level of partitioning. The partitioning process can be repeatedly iteratively until a termination criterion is met, the termination criterion being based in part on the number of directed cuts in each of the partitions. | 12-13-2012 |
20130326455 | ELEMENT PLACEMENT IN CIRCUIT DESIGN BASED ON PREFERRED LOCATION - An improved circuit design system may include a computer processor to perform a placement for a circuit by physical synthesis. The system may also include a controller to compute a preferred location of at least one selected element of the circuit, and to calculate placement constraints for each selected element. The system may further include an updated design for the circuit generated by performing another round of physical synthesis with the placement constraints. | 12-05-2013 |
20130346938 | POST-PLACEMENT CELL SHIFTING - A computer implemented method for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells. | 12-26-2013 |
20140033154 | Scheduling for Parallel Processing of Regionally-Constrained Placement Problem - Scheduling of parallel processing for regionally-constrained object placement selects between different balancing schemes. For a small number of movebounds, computations are assigned by balancing the placeable objects. For a small number of objects per movebound, computations are assigned by balancing the movebounds. If there are large numbers of movebounds and objects per movebound, both objects and movebounds are balanced amongst the processors. For object balancing, movebounds are assigned to a processor until an amortized number of objects for the processor exceeds a first limit above an ideal number, or the next movebound would raise the amortized number of objects above a second, greater limit. For object and movebound balancing, movebounds are sorted into descending order, then assigned in the descending order to host processors in successive rounds while reversing the processor order after each round. The invention provides a schedule in polynomial-time while retaining high quality of results. | 01-30-2014 |
20140149957 | STRUCTURED PLACEMENT OF LATCHES/FLIP-FLOPS TO MINIMIZE CLOCK POWER IN HIGH-PERFORMANCE DESIGNS - A latch placement tool determines a shape for a cluster of latches from a preliminary layout (or based on a netlist), including an aspect ratio of the shape, and generates a template for placement of the latches in conformity with the shape. Latches are placed around a local clock buffer (LCB) based on latch size, from largest latch first to smallest latch last, and based on their ideal locations given the target aspect ratio. The ideal locations may be further based on the clock driver pin configuration of the LCB. The final template preferably has an aspect ratio that is approximately equal to the aspect ratio of the shape of the cluster, but the latch placement may be constrained by clock routing topology. Latch placement within a cluster can be further optimized by swapping one of the latches with another to minimize total wirelength of the design. | 05-29-2014 |
20140359546 | STRUCTURED PLACEMENT OF HIERARCHICAL SOFT BLOCKS DURING PHYSICAL SYNTHESIS OF AN INTEGRATED CIRCUIT - Integrated circuit design uses a library of structured soft blocks (SSBs) composed of pre-defined sets of cells with their logic implementation and placement templates with their relative placement information. A compiler receives a circuit description which includes an instance of an SSB and unfolds the instance according to the placement template to generate a modified circuit description which includes the relative placement information. The placement of circuit objects is optimized while maintaining relative locations for cells of the SSB instance according to the relative placement information. The SSB may be hierarchical. Gate resizing of cells in the SSB instance may result in a change in its bounds. A timing optimization procedure for the modified circuit description may be carried out while hiding internal details of the SSB instance. For example, buffers may be inserted in nets external to the SSB instance while preventing insertion of buffers in any internal nets. | 12-04-2014 |