Patent application number | Description | Published |
20080301601 | TECHNIQUES FOR USE WITH AUTOMATED CIRCUIT DESIGN AND SIMULATIONS - Various techniques for use in connection with automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving initial condition signals from circuitry in a chip, and correlating values of at least some of the initial condition signals with objects in a hardware description language (HDL) used in simulation, wherein the HDL was used in describing at least some of the circuitry in the chip. Still other embodiments involve memory substitutions. Replicated circuitry may be in the same chip(s) are the design circuitry or a different chip(s). Still other embodiments are described. | 12-04-2008 |
20080301608 | Methods and apparatuses for designing multiplexers - Methods and apparatuses for designing multiplexers in one or more integrated circuits are described. One exemplary method includes receiving a representation of a first multiplexer and converting the representation to a partition neutral representation of the first multiplexer and partitioning the partition neutral representation to create a plurality of second multiplexers. Another exemplary method includes decomposing a representation of a first multiplexer into a representation of a plurality of second multiplexers, which are coupled together at a common output without any intervening multiplexers between the second multiplexers and the common output, and partitioning the second multiplexers between portions of at least one integrated circuit. | 12-04-2008 |
20080313578 | Techniques For Use With Automated Circuit Design and Simulations - Various techniques involving snapshots of the contents of registers are described and claimed. In some embodiments, a method includes receiving descriptions of design circuitry including design registers to receive register input signals. The method also includes generating additional descriptions through at least one computer program including descriptions of additional registers (snapshot registers) to receive snapshots of the register input signals, wherein the additional registers provide register initial condition signals for use in a simulation of at least a portion of the design circuitry. Other embodiments are described. | 12-18-2008 |
20080313579 | Techniques For Use With Automated Circuit Design and Simulations - Various techniques related to clocking for use with automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving descriptions of design circuitry including logic to receive input signals. The method further includes generating additional descriptions through at least one computer program including descriptions of a multiplexer to multiplex the input signals and delayed input signals, and provide them to the logic, and a demultiplexer to demultiplex output signals and delayed output signals from the logic. Other embodiments are described. | 12-18-2008 |
20080313589 | Techniques For Use With Automated Circuit Design and Simulations - Various techniques related to clocking signals used for automated circuit design and simulations are disclosed. In some embodiments, a method includes receiving first and second asynchronous clock signals having a first phase relationship at a first time and sampling the second clock signal at transitions of the first clock. The method further includes storing the samples; and analyzing the samples to ascertain the first phase relationship of the second clock signal with respect to the first clock signal and provide a representation of the first phase relationship. Other embodiments are described. | 12-18-2008 |
20090031277 | ARCHITECTURAL PHYSICAL SYNTHESIS - The present invention discloses methods and apparatuses to design an integrated circuit. According to one aspect, the present invention circuit design discloses an iterative process of synthesis and placement where each iteration provides incremental changes on the design of the integrated circuit. The synthesis transform is then made with accurate timing information from the placement, and the process is incrementally iterative toward the final timing enclosure of the design. The incrementally iterative approach of the present invention provides a continuous advancement from synthesis to placement and vice versa, with the incremental improvements on synthesis made with knowledge of current instance placement, and the incremental improvements on placement made with knowledge of current circuit logic. | 01-29-2009 |
20090031278 | ARCHITECTURAL PHYSICAL SYNTHESIS - The present invention discloses methods and apparatuses to design an integrated circuit. According to one aspect, the present invention circuit design discloses an iterative process of synthesis and placement where each iteration provides incremental changes on the design of the integrated circuit. The incrementally iterative approach of the present invention provides a continuous advancement from synthesis to placement and vice versa, with the incremental improvements on synthesis made with knowledge of current instance placement, and the incremental improvements on placement made with knowledge of current circuit logic. According to another aspect, the present invention circuit design discloses incremental force directed placement transforms utilizing resource layers to address the heterogeneous resource distribution problem, where the force on an instance can be a weighted average of the forces from its resource layers based on the local congestion of those resources. In addition, incremental area removal method can be utilized to address resource utilization problem through a quality metric based on force directed placement transforms, such as a resource demand topological mapping. | 01-29-2009 |
20100058261 | TEMPORALLY-ASSISTED RESOURCE SHARING IN ELECTRONIC SYSTEMS - Methods and apparatuses to optimize integrated circuits by identifying functional modules in the circuit having similar functionality that can share circuit resources and producing a modified description of the circuit where the similar functional modules are folded onto common circuit resources and time-multiplexed using an original system clock or a fast clock. | 03-04-2010 |
20100058298 | APPROXIMATE FUNCTIONAL MATCHING IN ELECTRONIC SYSTEMS - Methods and apparatuses for approximate functional matching are described including identifying functionally similar subsets of an integrated circuit design or software program, distinguishing control inputs of the subsets from data inputs, and assigning combinations of logic values to the input control signals to capture co-factors for functional matching. | 03-04-2010 |
20100153899 | METHODS AND APPARATUSES FOR DESIGNING LOGIC USING ARITHMETIC FLEXIBILITY - Methods and apparatuses for designing logic are described. In one embodiment, a method includes determining a directive which specifies a format for data in a data processing operation and creating a representation of logic to perform the data processing operation, wherein the creating uses the directive as a minimum format, rather than an exact or required format, for at least a portion of the representation of logic. Other methods are disclosed, and systems and machine readable media are also disclosed. | 06-17-2010 |
20100199234 | METHODS AND APPARATUSES FOR CIRCUIT DESIGN AND OPTIMIZATION - In one aspect of an embodiment, a method implemented on a data processing system for circuit design, includes: identifying one or more first portions (e.g., islands) of a design of a circuit, where each of the one or more first portions contains a set of elements interconnected via timing critical nets; and reporting inter-dependency between portions of the circuit in view of the one or more first portions. In one aspect of an embodiment, a method implemented on a data processing system for circuit design, includes: identifying a first portion (e.g., island) of a design of a circuit, the first portion containing a set of elements interconnected via timing critical nets; and performing a synthesis transformation of the first portion to isolate timing dependency of the first portion on a non-critical net connected to an element of the first portion. | 08-05-2010 |
20100218157 | TIMING-OPTIMAL PLACEMENT, PIN ASSIGNMENT, AND ROUTING FOR INTEGRATED CIRCUITS - Techniques for timing-optimal placement, pin assignment, and routing for integrated circuits are described herein. According to one embodiment, a list of paths providing implementation possibilities is constructed. A means is provided for removing paths from the list as well as a means for committing paths to the implementation if such paths are required for making the circuit implementation valid. Paths with worst case attributes are iteratively removed from the list until all paths in the list are committed to the implementation. Other methods and apparatuses are also described. | 08-26-2010 |
20100229132 | STATISTICAL FORMAL ACTIVITY ANALYSIS WITH CONSIDERATION OF TEMPORAL AND SPATIAL CORRELATIONS - Techniques for statistical formal activity analysis with consideration of temporal and/or spatial correlations are described herein. According to one embodiment, a sequential circuit having a feedback loop is unrolled into multiple unrolled circuits, where the sequential circuit is represented by a finite state machine (FSM). A temporal correlation is introduced to each of the unrolled circuits via a correlation network for an activity analysis of the sequential circuit. The temporal correlation represents a dependency relationship between a current logic state of a signal and a previous logic state of the signal. Other methods and apparatuses are also described. | 09-09-2010 |
20110013650 | PSEUDO-SYNCHRONOUS TIME DIVISION MULTIPLEXING - Methods and apparatuses to multiplex logic data pseudo synchronously are described. A representation of a multiplexer logic is generated to transmit data items asynchronously relative to a design clock. The data items may be transmitted under control of a transmission clock from a first integrated circuit to a second integrated circuit. A representation of a counter logic may be generated to couple with the multiplexer logic for transmitting the data asynchronously. Additionally, a representation of reset logic may be generated for a configuration to repeatedly reset the counter logic. Synchronization signals may be generated for a design clock cycle of a design clock driving the data items. The synchronization signals may be transmitted via the transmission clock asynchronous with the design clock. The data items may be transmitted via a number of transmission slots determined based on the clock cycles of the transmission clock and the design clock The total time for the transmission slots for transmitting the logic data may be less than the clock cycle of the design clock. One or more transmission slots within the clock cycle of the design clock may be used to transmit the synchronization data to indicate a new cycle to transmit the data items according to the design clock. | 01-20-2011 |
20110113399 | Methods and Systems for Optimizing Designs of Integrated Circuits - Methods and systems for optimizing and/or designing integrated circuits. One exemplary method includes routing, as part of a process of designing an integrated circuit (IC), connections on a representation of the IC using a first set of wiring resources and marking wiring resources as used once the wiring resources within the first set have been used for routing and routing, using a second set of wiring resources in the representation, connections on the IC without checking whether wiring resources within the second set have been previously used to route connections, wherein wiring resources in the second set differ, on average, in physical size, from wiring resources in the first set. Other methods and systems for optimizing and/or designing ICs are also described, and machine-readable media containing executable program instructions which cause systems to perform one or more of these methods are also described. | 05-12-2011 |
20120174053 | TEMPORALLY-ASSISTED RESOURCE SHARING IN ELECTRONIC SYSTEMS - Methods and apparatuses to optimize integrated circuits by identifying functional modules in the circuit having similar functionality that can share circuit resources and producing a modified description of the circuit where the similar functional modules are folded onto common circuit resources and time-multiplexed using an original system clock or a fast clock. | 07-05-2012 |
20130061195 | Methods and Apparatuses for Circuit Design and Optimization - In one aspect of an embodiment, a method implemented on a data processing system for circuit design, includes identifying one or more first portions of a design of a circuit, each of the one or more first portions containing a set of elements interconnected via timing nets and generating weights for the timing critical nets, the weights being generated after identifying the one or more first portions and executing a placer algorithm which uses the weights for the timing critical nets to place the set of elements on a representation of the design. In this method, in one embodiment, the weights for the timing critical nets can be generated to have values that differ from weights for non-critical nets. The placer algorithm can be any one of a variety of conventional placer algorithms such as a weighted wire length driven placer algorithm or a force directed timing driven placer algorithm or a min-cut placer algorithm. | 03-07-2013 |
20130162346 | INTERCONNECTION DEVICE IN A MULTI-LAYER SHIELDING MESH - An integrated circuit (IC) comprising a shielding mesh in at least one layer of the IC, the shielding mesh having a first plurality of lines which are designed to provide a first reference voltage and having a second plurality of lines which are designed to provide a second reference voltage and wherein the shielding mesh comprises a window in which signal lines are routed with less shielding than signal lines which are routed in the shielding mesh. The IC further comprising power supply lines in at least a first layer of the IC, the first layer being different than the at least one layer which contains the shielding mesh, the power supply lines being coupled to the shielding mesh and being larger in width than the first plurality of lines and the second plurality of lines. | 06-27-2013 |
20130254430 | APPROXIMATE FUNCTIONAL MATCHING IN ELECTRONIC SYSTEMS - Methods and apparatuses for approximate functional matching are described including identifying functionally similar subsets of an integrated circuit design or software program, distinguishing control inputs of the subsets from data inputs, and assigning combinations of logic values to the input control signals to capture co-factors for functional matching. | 09-26-2013 |
20130290920 | DESIGN AND ANALYSIS OF DIGITAL CIRCUITS WITH TIME DIVISION MULTIPLEXING - Methods and apparatuses to design and analyze digital circuits with time division multiplexing. In one embodiment, the method for designing a digital circuit comprises determining signal timing for a portion of the digital circuit, and automatically replacing nets for a plurality of connections in the digital circuit with a Time Division Multiplexing (TDM) channel in response to a determining of routing congestion. | 10-31-2013 |
20140053120 | ARCHITECTURAL PHYSICAL SYNTHESIS - The present invention discloses methods and apparatuses to design an integrated circuit. According to one aspect, a method of designing an integrated circuit comprises determining a state of a design of the integrated circuit at a high level design representation of the integrated circuit, wherein the state of the design of the integrated circuit comprises a netlist with at least one of timing data, resource information, placement information, routing information, and power data. The method further comprises determining a first transform for the state, changing the state of the design at the high level design representation of the integrated circuit using the first transform, and determining a second transform based on the changed state. | 02-20-2014 |
20140053124 | THERMAL ANALYSIS BASED CIRCUIT DESIGN - Methods and apparatuses for circuit design to reduce power usage, such as reducing temperature dependent power usage, and/or to improve timing, such as reducing temperature dependent delay or transition time. At least one embodiment of the method implemented on a data processing system for circuit design, the method comprises determining for a first design of a circuit a first temperature solution and a first power dissipation solution, the first power dissipation solution and the first temperature solution being interdependent, and transforming the first design of the circuit into a second design of the circuit using the first temperature solution to reduce leakage power of the circuit under one or more design constraints. | 02-20-2014 |
20140082579 | ARCHITECTURAL PHYSICAL SYNTHESIS - Methods and apparatuses to design an integrated circuit are discussed. In one embodiment, the method of designing an integrated circuit comprises partitioning a chip resource into a plurality of sections, and calculating the rank of the sections based on a quality metric. The method further comprises removing the sections with the lowest ranks from consideration by a placement transform. | 03-20-2014 |
20140165024 | STATISTICAL FORMAL ACTIVITY ANALYSIS WITH CONSIDERATION OF TEMPORAL AND SPATIAL CORRELATIONS - Techniques for statistical formal activity analysis with consideration of temporal and/or spatial correlations are described herein. According to one embodiment, a machine-implemented method for circuit analysis comprises unrolling a sequential circuit having a feedback loop into a plurality of unrolled circuits and introducing a spatial correlation via an encoding circuit coupled to the plurality of unrolled circuits for an activity analysis of the sequential circuit, the spatial correlation representing a dependency relationship between logic states of an input and logic states of other signals. | 06-12-2014 |
20140215427 | Optimizing Designs of Integrated Circuits - Methods and systems for optimizing and/or designing integrated circuits. One exemplary method includes determining fanout of a driving component in a representation of an integrated circuit (IC) being designed, determining for the driving component, the loads in the representation of the IC driven by the driving component, and determining use of existing wiring resources used to connect the loads to the driving component. The method further includes optimizing, based on the use of existing wiring resources, the fanout of the driving component, and the loads being driven by the driving component, a design of the IC. | 07-31-2014 |