| Entries |
| Document | Title | Date |
|---|
| 20080219063 | SYSTEM AND METHOD OF SELECTIVE ROW ENERGIZATION BASED ON WRITE DATA - A system and method of selective row energization based on write data, with a selective row energization system including a storage array | 09-11-2008 |
| 20080291751 | SCR MATRIX STORAGE DEVICE - One of the simplest forms of data storage devices is the diode array storage device. However, a problem with diode array storage devices is that as the size of the array increases, the number of non-addressed diodes connected between a given selected row or column of the array and the non-addressed columns or rows of the array, respectively, also becomes very large. While the leakage current through any one non-addressed diode on the selected row or column will have little impact on the operation of the device, the cumulative leakage through multiple thousands of non-addressed diodes can become significant. This aggregate leakage current can become great enough that the output voltage can be shifted such that the threshold for distinguishing between a one state and a zero state of the addressed diode location can become obscured and can result in a misreading of the addressed diode location. The present invention is a means to manage the leakage currents in a diode array storage device. This is accomplished by actively changing the forward voltage of the diodes in the storage array such that a diode connected to the selected row line but that is not connected to the selected column line is in its high impedance state and a diode connected to the selected column line but that is not connected to the selected row line is in its high impedance state; only a diode that is connected to both the selected row line and the selected column line will switch to its low impedance state. The present invention is an enhancement to all types of arrays of diodes or arrays of other nonlinear conducting elements including: storage devices, programmable logic devices, display arrays, sensor arrays, and many others. | 11-27-2008 |
| 20080304338 | SEMICONDUCTOR MEMORY DEVICE - To provide a semiconductor memory device capable of increasing its drive capability at operating time while reducing a leak current at standby time without the s need to make a significant change to the design of an existing semiconductor memory device a semiconductor memory device having a memory cell comprises: a latch section that includes a transistor having a back gate to which a back gate voltage is supplied; a memory cell that includes a transfer gate constituting the memory cell the transfer gate being subjected to switching control by a word line signal and having a lo back gate to which a back gate voltage is supplied; and a back gate voltage control circuit that controls the back gate voltage based on an address signal. | 12-11-2008 |
| 20090021991 | MEMORY DEVICE, CONTROL METHOD FOR THE SAME, CONTROL PROGRAM FOR THE SAME, MEMORY CARD, CIRCUIT BOARD AND ELECTRONIC EQUIPMENT - A memory device having a single or a plurality of memory chips includes a memory part (control register, SPD memory unit) inside each memory chip, which memory part stores control data concerning the memory chip. The memory device enables writing-in or readout of the control data stored on the memory part to be able to set any desired control data for each memory chip, and, when the memory device has the plurality of memory chips, enables separate use of each of the memory chips. | 01-22-2009 |
| 20090040839 | READING MULTI-CELL MEMORY DEVICES UTILIZING COMPLEMENTARY BIT INFORMATION - Providing differentiation between overlapping memory cell bits in multi-cell memory devices is described herein. By way of example, select groups of memory cells of the multi-cell memory devices can be iteratively disabled to render state distributions of remaining, non-disabled memory cells, non-overlapped. System components can measure distributions rendered non-overlapped to uniquely identify states of such distributions. Identified state distributions can subsequently be disabled to render other state distributions non-overlapped, and therefore identifiable. In such a manner, read errors associated with overlapped bit states of multi-cell memory devices can be mitigated. | 02-12-2009 |
| 20090073783 | MULTI-LEVEL MEMORY CELL UTILIZING MEASUREMENT TIME DELAY AS THE CHARACTERISTIC PARAMETER FOR LEVEL DEFINITION - A memory array and computer program product for operating a memory cell and memory array. An embodiment of the invention entails receiving a request to read a binary value stored in the memory cell. A pre-charging operation pre-charges a bit-line capacitor in an electronic circuit formed by the memory cell to a pre-charge voltage. A word-line in the electronic circuit is then activated. A discharging operation discharges the bit-line capacitor through the said memory cell in the electronic circuit to the word-line. Additionally, an electron discharge time measurement is started when the word-line is activated. The electron discharge time measurement is stopped when the voltage level in the bit-line falls below a pre-defined reference voltage. A determining operation determines the binary value from the measured electron discharge time. | 03-19-2009 |
| 20090073784 | MULTI-LEVEL MEMORY CELL UTILIZING MEASUREMENT TIME DELAY AS THE CHARACTERISTIC PARAMETER FOR LEVEL DEFINITION - A memory array and computer program product for operating a memory cell and memory array. An embodiment of the invention entails receiving a binary value to be stored by a memory cell. A determining operation determines a target discharge time corresponding to the binary value. The target discharge time being the time needed to discharge a pre-charged circuit through the said memory cell to a predetermined level. A storing operation stores a characteristic parameter in the memory cell such that an electron discharge time through an electronic circuit formed, at least partially, by the memory cell, is substantially equal to the target discharge time. | 03-19-2009 |
| 20090073785 | MULTI-LEVEL MEMORY CELL UTILIZING MEASUREMENT TIME DELAY AS THE CHARACTERISTIC PARAMETER FOR LEVEL DEFINITION - A method for operating a memory cell. Memory cells represent binary values by storing a characteristic parameter. The method of memory cell operation entails receiving a binary value to be stored by a memory cell. A determining operation determines a target discharge time corresponding to the binary value. The target discharge time being the time needed to discharge a pre-charged circuit through the said memory cell to a predetermined level. A storing operation stores a characteristic parameter in the memory cell such that an electron discharge time through an electronic circuit formed, at least partially, by the memory cell, is substantially equal to the target discharge time. | 03-19-2009 |
| 20090091990 | Apparatus and method of multi-bit programming - Disclosed are a multi-bit programming apparatus and a multi-bit programming method. The multi-bit programming apparatus may include a first control unit that may generates 2 | 04-09-2009 |
| 20090109765 | Single via structured IC device - A configurable logic array may include a multiplicity of logic components, which may contain customizable look-up tables, and layers of fixed metal segments all of which may be customizable using a single custom via layer. The integrated circuit containing the configurable logic array may also include a multiplicity of customizable register files, customizable RAM blocks; a ROM block with customizable contents; or test logic With customizable test options and configurations to separately test logic and the PLLs. | 04-30-2009 |
| 20090141565 | SEMICONDUCTOR STORAGE DEVICE - A bit line potential monitor circuit is provided in a bit line, and a step-down circuit of the bit line is controlled base on information from the monitor circuit. As a result, the bit line is easily stepped down to an optimal potential level in accordance with a potential and a load capacity thereof without being affected by variability in devices or operation conditions. | 06-04-2009 |
| 20090213668 | ADJUSTABLE PIPELINE IN A MEMORY CIRCUIT - A technique for operating a memory circuit that improves performance of the memory circuit and/or power consumption for at least some operating points of the memory circuit includes adjusting a number of operational pipeline stages at least partially based on an operating point of the memory. In at least one embodiment of the invention, a method for operating a memory circuit includes selecting a mode of operating the memory circuit at least partially based on a feedback signal generated by the memory circuit. The technique includes operating the memory circuit using a number of pipeline stages based on the selected mode of operation of the memory circuit. In at least one embodiment of the invention, the technique includes sensing a timing margin associated with an individual pipeline stage and generating the feedback signal based thereon. | 08-27-2009 |
| 20090238012 | CONTROLLING SLEW RATE PERFORMANCE ACROSS DIFFERENT OUTPUT DRIVER IMPEDANCES - Embodiments are provided including one directed to an output driver system, having an adjustable pre-driver configured to maintain a generally constant slew rate of an output driver across a plurality of output driver impedances. Other embodiments provide a method of operating a memory device, including determining an output driver strength of an output driver and configuring the pre-driver based on the determined output driver strength. | 09-24-2009 |
| 20090262589 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device and a method for operating the same can improve a refresh characteristic of the semiconductor memory device by physically writing only logic low data in memory cells, irrespective of logic level of input data, either high or low. The semiconductor memory device includes a positive word line configured to control a first memory cell connected to a positive bit line, a negative word line configured to control a second memory cell connected to a negative bit line, and a word line control circuit configured to enable one of the positive word line and the negative word line according to a logic level of data in a write operation. | 10-22-2009 |
| 20090296498 | Memory access method and semiconductor memory device - A semiconductor memory device includes a memory cell array provided with blocks each having a plurality of memory cells arranged in columns and rows, a column selection circuit selecting a column via bit lines based on a column section signal, a word line driver circuit selecting a row via a word line based on a row selection signal and the column selection signal, and a write/read circuit writing data to and reading data from a selected memory cell via the bit lines based on a write and read switching signal. The selected memory cell is arranged at a position determined by the column selected by the column selection circuit and the row selected by the word line driver circuit within one block. Rows corresponding to the blocks are provided in common with the same number of word lines as the columns, and the memory cells arranged in one row within one block are coupled to mutually different word lines. | 12-03-2009 |
| 20090303805 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device has a nonvolatile memory cell to which data writing operation is limited to a predetermined logic value. In the case of rewriting data “10101010” written in a first memory core to data “01010101”, since the data writing operation includes writing of a logic value “1” opposite to the predetermined logic value, an erasing operation is needed and the data writing is regulated. By rewriting a pointer value stored in a pointer memory in place of performing the erasing operation, an operation of switching a memory core to be selected to a second memory core (data “11111111”) is performed. Data is newly written into the second memory core selected by the rewritten pointer value. | 12-10-2009 |
| 20090316499 | Semiconductor memory device operational processing device and storage system - A thin film magnetic memory includes a size-variable Read Only Memory (ROM) region and a size-variable Random Access Memory (RAM) coupled to different ports for parallel access to the ports, respectively. A memory system allowing fast and efficient data transfer can be achieved. | 12-24-2009 |
| 20090323439 | MEMORY FOR STORING A BINARY STATE - A memory cell for storing a binary state, the memory cell being adapted for storing a binary state based on a write indication and a binary write masking value and for storing a complementary binary state based on the write indication and a complementary binary write masking value. | 12-31-2009 |
| 20100008163 | MEMORY ARCHITECTURE AND CELL DESIGN EMPLOYING TWO ACCESS TRANSISTORS - An improved memory array architecture and cell design is disclosed in which the cell employs two access transistors. In one embodiment, the two access transistors in each cell are coupled at one of their channel terminals to a memory element, which in turn is connected to a bit line. The other of the channel terminals are effectively tied together via reference lines. The word lines (i.e., gates) of the two access transistors are also tied together. The result in a preferred embodiment is a cell having two access transistors wired and accessed in parallel. With such a configuration, the widths of the access transistors can be made one-half the width of more-traditional one-access-transistor designs, saving layout space in that (first) dimension. Moreover, because the word lines of adjacent cells will be deselected, the improved design does not require cell-to-cell isolation (e.g., trench isolation) in the other (second) dimension. The result, when applied to a phase change memory, comprises about a 37% reduction in layout area from previous cell designs. | 01-14-2010 |
| 20100008164 | MEMORY - A memory capable of suppressing reduction of data determination accuracy is provided. This memory includes a memory cell connected to a bit line for holding data and a bipolar transistor whose base is connected to the bit line. In data reading, the memory reads the data by amplifying a current, corresponding to the data of the memory cell, appearing on the bit line with the bipolar transistor. | 01-14-2010 |
| 20100027355 | PLANAR DOUBLE GATE TRANSISTOR STORAGE CELL - A semiconductor device suitable for use as a storage cell includes a semiconductor body having a top surface and a bottom surface, a top gate dielectric overlying the semiconductor body top surface, an electrically conductive top gate electrode overlying the top gate dielectric, a bottom gate dielectric underlying the semiconductor body bottom surface, an electrically conductive bottom gate electrode underlying the bottom gate dielectric, and a charge trapping layer. The charge trapping layer includes a plurality of shallow charge traps, adjacent the top or bottom surface of the semiconductor body. The charge trapping layer may be of aluminum oxide, silicon nitride, or silicon nanoclusters. The charge trapping layer may located positioned between the bottom gate dielectric and the bottom surface of the semiconductor body. | 02-04-2010 |
| 20100054053 | Integrated Circuit Memory Devices Including Mode Registers Set Using A Data Input/Output Bus - An integrated circuit memory device may include a memory cell array and a plurality of data input/output pins. The plurality of data input/output pins may be configured to receive data from a memory controller to be written to the memory cell array during a data write operation, and the data input/output pins may be further configured to provide data to the memory controller from the memory cell array during a data read operation. A mode register may be configured to store information defining an operational characteristic of the memory device, and the mode register may be configured to be set using the data input/output bus. Related methods, systems, and additional devices are also discussed. | 03-04-2010 |
| 20100067313 | MEMORY DEVICE - A memory device that can include a power-supply voltage detector that detects power-supply voltage values and that outputs a detection result indicating which power-supply voltage value is detected; a data-rate setter that sets data rates corresponding to the detection result of the power-supply voltage detector, in synchronization with a rising edge or falling edge of a clock signal; and a memory cell array that performs reading/writing at the data rates set by the data-rate setter. | 03-18-2010 |
| 20100091585 | STATIC RANDOM ACCESS MEMORIES AND ACCESS METHODS THEREOF - A static random access memory device capable of preventing stability issues during a write operation is provided, in which a memory cell is coupled to a read word line, a write word line, a read bit line, a write bit line and a complementary write bit line, and a multiplexing unit is coupled to the read bit line, the write bit line and the complementary write bit line. The multiplexing unit applies first and second logic voltages representing a logic state stored in the memory cell to the write bit line and the complementary write bit line, respectively, when the memory cell is not selected to be written by an input signal from a data driver and the read word line is activated, in which the first and second logic voltages are opposite to each other. | 04-15-2010 |
| 20100091586 | TECHNIQUES FOR SIMULTANEOUSLY DRIVING A PLURALITY OF SOURCE LINES - Techniques for simultaneously driving a plurality of source lines are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus for simultaneously driving a plurality of source lines. The apparatus may include a plurality of source lines coupled to a single source line driver. The apparatus may also include a plurality of dynamic random access memory cells arranged in an array of rows and columns, each dynamic random access memory cell including one or more memory transistors. Each of the one or more memory transistors may include a first region coupled to a first source line of the plurality of source lines, a second region coupled to a bit line, a body region disposed between the first region and the second region, wherein the body region may be electrically floating, and a gate coupled to a word line and spaced apart from, and capacitively coupled to, the body region. | 04-15-2010 |
| 20100128541 | INTEGRATED CIRCUIT HAVING MEMORY WITH CONFIGURABLE READ/WRITE OPERATIONS AND METHOD THEREFOR - An integrated circuit having a memory and a method for operating the memory are provided. The method for operating the memory comprises: accessing a first portion of the memory, the first portion having a first access margin; detecting an error in the first portion of the memory; changing the first access margin to a second access margin, the second access margin being different than the first access margin; determining that the error is corrected with the first portion having the second access margin; and storing an access assist bit in a first storage element, the access assist bit corresponding to the first portion, wherein the assist bit, when set, indicates that subsequent accesses to the first portion are accomplished at the second access margin. | 05-27-2010 |
| 20100142290 | OUTPUT CIRCUIT FOR A SEMICONDUCTOR MEMORY DEVICE AND DATA OUTPUT METHOD - An outputting transistor circuit of a push-pull structure has an outputting PMOS transistor and an outputting NMOS transistor connected in series between a first power supply and a grounded power supply. In a standby state, a voltage level of a gate terminal of the outputting PMOS transistor is set to a voltage level of a second power supply higher than a voltage level of the first power supply. In an active state, a voltage level of the gate terminal of the outputting PMOS transistor is changed to a voltage level of the first power supply in response to an active command or a read command, or in response to the state of a semiconductor memory device changing to the active state or a read state, and either the outputting PMOS transistor or the outputting NMOS transistor is turned ON in response to a data read signal from a memory cell. | 06-10-2010 |
| 20100157696 | SEMICONDUCTOR MEMORY APPARATUS AND A METHOD FOR READING DATA STORED THEREIN - A semiconductor memory apparatus includes a data bus inversion (DBI) section configured to receive a plurality of input data and decide whether to invert or output, without an inversion, the plurality of input data depending upon logic levels of the plurality of data, and further configured to generate a plurality of inversion data based on the decision; and a data output section configured to receive the plurality of inversion data, invert or output, without an inversion the plurality of inversion data in response to a mode signal, and generate a plurality of output data. | 06-24-2010 |
| 20100172194 | Dual-threshold-voltage two-port sub-threshold SRAM cell apparatus - The invention relates to a dual-threshold-voltage two-port sub-threshold SRAM cell apparatus. The above-mentioned apparatus comprises a first inverter, a second inverter, an access transistor and a read buffer. The first inverter and the second inverter include a plurality of first operating elements and a plurality of second operating elements for storing data. The access transistor is coupled to the first inverter and the second inverter, wherein the first operating elements and the second operating elements are high threshold voltage operating elements and the access transistor is low threshold voltage operating transistor. The read buffer is used for performing a read operation. | 07-08-2010 |
| 20100182853 | Semiconductor Memory Device Having a Floating Storage Bulk Region Capable of Holding/Emitting Excessive Majority Carriers - A semiconductor memory device includes: a semiconductor layer formed on an insulating layer; a plurality of transistors formed on the semiconductor layer and arranged in a matrix form, each of the transistors having a gate electrode, a source region and a drain region, the electrodes in one direction constituting word lines; source contact plugs connected to the source regions of the transistors; drain contact plugs connected to the drain regions of the transistors; source wirings each of which commonly connects the source contact plugs, the source wirings being parallel to the word lines; and bit lines formed so as to cross the word lines and connected to the drain regions of the transistors via the drain contact plugs. Each of the transistors has a first data state having a first threshold voltage and a second data state having a second threshold voltage. | 07-22-2010 |
| 20100188908 | Setting Memory Device VREF in a Memory Controller and Memory Device Interface in a Communication Bus - A memory device is connected through an interface to a memory controller. The memory device's reference voltage is set based on a driver's impedance of the memory device and the controller driver drive strength during driver training. The voltage is applied to a reference resistor pair at the memory device and changed until the voltage level switches. The voltage is then set at the reference resistor pair of the memory device. | 07-29-2010 |
| 20100208530 | Two Bits Per Cell Non-Volatile Memory Architecture - A memory circuit for holding a single binary value. A first bit cell holds one of a logical high value and a logical low value, and a second bit cell also holds one of a logical high value and a logical low value. Circuitry is provided for placing a logical high value in the first bit cell when the binary value in the memory circuit is to be a logical high value, and circuitry is provided for placing a logical high value in the second bit cell when the binary value in the memory circuit is to be a logical low value. In this manner, a logical high value exists within the memory circuit, whether the single binary value within the memory circuit is a logical high value or a logical low value. The difference between the two values of the binary value is which of the two bit cells holds the logical high value. Thus, this memory circuit can be sensed without the use of a sense amplifier. | 08-19-2010 |
| 20100226186 | PARTIAL WRITE-BACK IN READ AND WRITE-BACK OF A MEMORY - An integrated circuit having a functional memory and methods of operating and reducing an operating power of the integrated circuit are provided. The functional memory includes an array of memory cells connected to row and column periphery units and organized in corresponding rows and columns. The memory also includes a word line that provides row access to a memory cell. The memory further includes at least one bit line that provides column access to the memory cell. The memory still further includes a partial write-back module, connected to the at least one bit line, that establishes a bit line bias to maintain a current state of the memory cell when in a half-selected condition based on a read of the current state and during a write cycle to a selected memory cell in the array. | 09-09-2010 |
| 20100238743 | FAST EMBEDDED BiCMOS-THYRISTOR LATCH-UP NONVOLATILE MEMORY - This disclosure describes a new semiconductor non-volatile memory that can be potentially faster than DRAM and FLASH, and the manufacturing cost can be lower than SRAM, which is volatile. It is possible to fabricate an ULSI microprocessor and this type of new memory array in the same chip—realizing the “embedded” process. There are a CMOS transistor and latched-up Bipolar transistors (A thyristor) in the device. The fast read, write and erase operations are done by charging the MOS gate capacitor interface and sensing the latch-up voltage of the thyristor. The latch-up voltage of the thyristor is reduced for the additional MOSFET current during the write process, causing early avalanche breakdown and the latch-up of the bipolar transistors. The semiconductor memory can be fabricated as a planar device or a vertical device. | 09-23-2010 |
| 20100246285 | METHODS, DEVICES, AND SYSTEMS RELATING TO A MEMORY CELL HAVING A FLOATING BODY - Methods, devices, and systems are disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer and including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and the drain, a second region positioned remote from each of the source and drain, and a passage and extending through the insulation layer and coupling the first region to the second region. Additionally, the memory cell includes a bias gate at least partially surrounding the second region and configured for operably coupling to a bias voltage. Furthermore, the memory cell may include a plurality of dielectric layers, wherein each outer vertical surface of the second region has a dielectric layer of the plurality adjacent thereto. | 09-30-2010 |
| 20100254201 | MEMORY DEVICE, HOST CIRCUIT, CIRCUIT BOARD, LIQUID RECEPTACLE, METHOD OF TRANSMITTING DATA STORED IN A NONVOLATILE DATA MEMORY SECTION TO A HOST CIRCUIT, AND SYSTEM INCLUDING A HOST CIRCUIT AND A MEMORY DEVICE DETACHABLY ATTACHABLE TO THE HOST CIRCUIT - A memory device is electrically connectable to a host circuit. The memory device includes a nonvolatile data memory section, a read/write control section, and a data transmission section. The read/write control section reads a first data from the nonvolatile data memory section where the first data has a prescribed data amount. The data transmission section transmits to the host circuit the first data together with second data, wherein the second data is different from the first data and has prescribed correlation with content of the first data. The second data having an identical data amount to the data amount of the first data. | 10-07-2010 |
| 20100277989 | INCREASED CAPACITY HETEROGENEOUS STORAGE ELEMENTS - Providing increased capacity in heterogeneous storage elements including a method for storing data including a write process writing to a memory and a read process reading from the memory. Physical characteristics of memory cells in the memory support different sets of data levels. The write process takes into account the different sets of data levels when writing to the memory. The read process first obtains data in the memory and subsequently determines how to interpret the data. | 11-04-2010 |
| 20100277990 | INTEGRATED CIRCUIT HAVING MEMORY REPAIR INFORMATION STORAGE AND METHOD THEREFOR - A storage unit on an integrated circuit stores information that identifies a circuit on the integrated circuit, a selected operating condition, and a required operating configuration for the circuit for the selected operating condition. The manner of operating the circuit is changed to the required operating configuration in response to an operating condition of the circuit changing to the selected operating condition. This allows for efficiently identifying the few circuits that do not meet specified requirements based on a reduction in, for example, operating voltage, and altering their operation in order to meet the specified requirements relative to the reduced operating voltage without having to do so for the vast majority of the circuits that are able to meet the requirements at the lowered operating voltage. | 11-04-2010 |
| 20100277991 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a memory cell having a circuit configuration in which a potential supplied to sources of load transistors | 11-04-2010 |
| 20100309736 | SRAM WITH READ AND WRITE ASSIST - A memory includes an SRAM bitcell including a pair of cross-coupled inverters, wherein a first inverter of the pair includes a first device having a body and a second inverter of the pair includes a second device having a body. A first selection circuit has a first input coupled to a first supply voltage terminal, a second input coupled to a second supply voltage terminal, and an output coupled to a first current electrode of the first device and to a first current electrode of the second device. A second selection circuit has a first input coupled to the first supply voltage terminal, a second input coupled to the second supply voltage terminal, and an output coupled to the body of each of the first and second devices. A word line coupled to the SRAM bitcell is driven by a word line driver coupled to the first supply voltage terminal. | 12-09-2010 |
| 20100315889 | SRAM MEMORY CELL WITH DOUBLE GATE TRANSISTORS PROVIDED WITH MEANS TO IMPROVE THE WRITE MARGIN - A random access memory cell including: two double-gate access transistors respectively arranged between a first bit line and a first storage node and between a second bit line and a second storage node, a word line, a first double-gate load transistor and a second double-gate load transistor, a first double-gate driver transistor and a second double-gate driver transistor, a mechanism to apply a given potential to at least one electrode of each of the load or driver transistors, and a mechanism to cause the given potential to vary. | 12-16-2010 |
| 20100329043 | Two-Transistor Floating-Body Dynamic Memory Cell - Embodiments relate to a two-transistor (2T) floating-body cell (FBC) for embedded-DRAM applications. Further embodiments pertain to a floating-body/gate cell (FBGC), which yields reduction in power dissipation, in addition to better signal margin, longer data retention, and higher memory density. | 12-30-2010 |
| 20110002178 | VERTICAL NON-VOLATILE MEMORY DEVICE, METHOD OF FABRICATING THE SAME DEVICE, AND ELECTRIC-ELECTRONIC SYSTEM HAVING THE SAME DEVICE - Provided is a vertical non-volatile memory device having a metal source line. The vertical non-volatile memory device includes cell string units that are formed on first portions of a semiconductor substrate and are vertically arranged with respect to a surface of the semiconductor substrate, impurity regions formed on second portions of the semiconductor substrate between the cell string units, conductive lines formed on the impurity regions, and spacers that are formed on the sidewalls of the cell string units and insulate the conductive lines from the cells string units. | 01-06-2011 |
| 20110019488 | DOUBLE-GATE FLOATING-BODY MEMORY DEVICE - A memory device is provided comprising a transistor having a floating body positioned between source and drain regions, the floating body being sandwiched between first and second insulated gates each comprising a gate electrode. A control circuit is arranged to program the state of said floating body to have an accumulation or depletion of majority carriers by applying one of first and second voltage levels between the first gate and at least one of the source and drain regions, and to retain the programmed state of said floating body by applying a third voltage level to the second gate. The voltages are switched over a time duration shorter than 100 ns. | 01-27-2011 |
| 20110063926 | Write Through Speed Up for Memory Circuit - A method of performing a write-through operation with a memory circuit having a write enable line, a write address line, a data in line, a read address line, a data out line, a bit array, a comparator, and a mux. A write address is received on the write address line, a read address is received on the read address line, data is received on the data in line. The comparator determines as a first condition whether the write address is identical to the read address, and determines as a second condition whether the write enable line is enabled. When both the first condition and the second condition are met, the comparator signals the mux to directly output the data receiving on the data in line on the data out line without writing the data to the bit array. In this manner, the memory circuit checks to determine whether a write-through operation is called for. If it is, then the mux sends the data on the data in line directly to the data out line, instead of retrieving data from the bit array of the memory, such as through the read decoder, which would take much longer. | 03-17-2011 |
| 20110069564 | SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME - A semiconductor device may include, but is not limited to: a first insulating film; first and second impurity layers on the first insulating film; a semiconductor layer on the first insulating film; a second insulating film covering the semiconductor layer; a first electrode on the second insulating film over the semiconductor layer; and a second electrode on the second insulating film over the semiconductor layer. The first and second impurity layers have a first conductive type. The first impurity layer is separated from the second impurity layer. The semiconductor layer is positioned between the first and second impurity layers. The semiconductor layer has a second conductive type which is different from the first conductive type. The first electrode is electrically insulated from the second electrode. The second electrode at least partially overlaps the first electrode in plan view. | 03-24-2011 |
| 20110103159 | Degradation Equalization for a Memory - In an embodiment, an integrated circuit includes a memory and a control circuit configured to cause an inversion of at least a portion of the data stored in the memory to more evenly balance the amount of time that a given memory cell in the memory stores a binary one or a binary zero. In some implementations, the inversion may be controlled for the memory as a whole via a global indication. In other implementations, data may be inverted on a row-by-row or column-by-column basis. In other embodiments, the global indication may be changed at each boot of a device including the integrated circuit. | 05-05-2011 |
| 20110194363 | SEMICONDUCTOR MEMORY CELL AND ARRAY USING PUNCH-THROUGH TO PROGRAM AND READ SAME - An integrated circuit device (for example, logic or discrete memory device) comprising a memory cell including a punch-through mode transistor, wherein the transistor includes a source region, a drain region, a gate, a gate insulator, and a body region having a storage node which is located, at least in part, immediately beneath the gate insulator. The memory cell includes at least two data states which are representative of an amount of charge in the storage node in the body region. First circuitry is coupled to the punch-through mode transistor of the memory cell to: (1) generate first and second sets of write control signals, and (2a) apply the first set of write control signals to the transistor to write a first data state in the memory cell and (2b) apply the second set of write control signals to the transistor to write a second data state in the memory cell. In response to the first set of write control signals, the punch-through mode transistor provides at least the first charge in the body region via impact ionization. The transistor may be disposed on a bulk-type substrate or SOI-type substrate. | 08-11-2011 |
| 20110205816 | Vertical type semiconductor device, method of manufacturing a vertical type semiconductor device and method of operating a vertical semiconductor device - A vertical pillar semiconductor device includes a substrate, a single crystalline semiconductor pattern, a gate insulation layer structure and a gate electrode. The substrate may include a first impurity region. The single crystalline semiconductor pattern may be on the first impurity region. The single crystalline semiconductor pattern has a pillar shape substantially perpendicular to the substrate. A second impurity region may be formed in an upper portion of the single crystalline semiconductor pattern. The gate insulation layer structure may include a charge storage pattern, the gate insulation layer structure on a sidewall of the single crystalline semiconductor pattern. The gate electrode may be formed on the gate insulation layer structure and opposite the sidewall of the single crystalline semiconductor pattern. The gate electrode has an upper face substantially lower than that of the single crystalline semiconductor pattern. | 08-25-2011 |
| 20110211399 | METHOD OF MANUFACTURING A VERTICAL-TYPE SEMICONDUCTOR DEVICE AND METHOD OF OPERATING A VERTICAL-TYPE SEMICONDUCTOR DEVICE - In a vertical-type semiconductor device, a method of manufacturing the same and a method of operating the same, the vertical-type semiconductor device includes a single-crystalline semiconductor pattern having a pillar shape provided on a substrate, a gate surrounding sidewalls of the single-crystalline semiconductor pattern and having an upper surface lower than an upper surface of the single-crystalline semiconductor pattern, a mask pattern formed on the upper surface of the gate, the mask pattern having an upper surface coplanar with the upper surface of the single-crystalline semiconductor pattern, a first impurity region in the substrate under the single-crystalline semiconductor pattern, and a second impurity region under the upper surface of the single-crystalline semiconductor pattern. The vertical-type pillar transistor formed in the single-crystalline semiconductor pattern may provide excellent electrical properties. The mask pattern is not provided on the upper surface of the single-crystalline semiconductor pattern in the second impurity region, to thereby reduce failures of processes. | 09-01-2011 |
| 20110222356 | TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE - Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region. | 09-15-2011 |
| 20110235443 | VOLTAGE STABILIZATION CIRCUIT AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME - A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in response to the detection signal. | 09-29-2011 |
| 20110267903 | SEMICONDUCTOR MEMORY DEVICE HAVING DRAM CELL MODE AND NON-VOLATILE MEMORY CELL MODE AND OPERATION METHOD THEREOF - A semiconductor memory device may have a DRAM cell mode and a non-volatile memory cell mode without a capacitor, including multiple transistors arranged in an array and having floating bodies, word lines connected to gate electrodes of the transistors, bit lines at a first side of the gate electrodes connected to drains of the transistors, source lines at a second side of the gate electrodes, different from the first side, and connected to sources of the transistors on the semiconductor substrate, and charge storage regions between the gate electrodes and the floating bodies. | 11-03-2011 |
| 20110273941 | TECHNIQUES FOR REFRESHING A SEMICONDUCTOR MEMORY DEVICE - Techniques for refreshing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region coupled to a source line and a second region coupled to a carrier injection line. Each memory cell may also include a body region capacitively coupled to at least one word line and disposed between the first region and the second region and a decoupling resistor coupled to at least a portion of the body region. | 11-10-2011 |
| 20110280089 | DATA BUS POWER-REDUCED SEMICONDUCTOR STORAGE APPARATUS - In one or more of the disclosed embodiments, the number of times toggle operations of a data bus are performed at the time of a data transmission in a semiconductor storage apparatus is reduced, thereby reducing the power consumption. For example, a semiconductor storage apparatus according to one embodiment of the present invention comprises a DRF bus, a DR11F bus, a GDRF bus and a GDR11F bus. The DRF bus and DR11F bus, and the GDRF bus and GDR11F bus, are placed in parallel for the purpose of reducing the number of times toggle operations of a data bus are performed at the time of a data transmission. The DR11F bus is added to make the DRF11F bus perform a toggle operation only when the DRF buses on both sides are made to perform a toggle operation if the data transmission were performed in a conventional system. | 11-17-2011 |
| 20110286290 | DRIVING METHOD OF SEMICONDUCTOR DEVICE - A period (inverted period) in which a high negative potential is applied to a gate of the transistor is provided between a writing period and a retention period. In the inverted period, supply of positive electric charge from the drain of the transistor to the oxide semiconductor layer is promoted. Thus, accumulation of positive electric charge in the oxide semiconductor layer or at the interface between the oxide semiconductor layer and a gate insulating film can converge in a short time. Therefore, it is possible to suppress a decrease in the positive electric charge in the node electrically connected to the drain of the transistor in the retention period after the inverted period. That is, the temporal change of data stored in the semiconductor device can be suppressed. | 11-24-2011 |
| 20110299345 | Early Read After Write Operation Memory Device, System And Method - A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write data, and a read address. A memory core is coupled to the interface and includes a first memory section having a first data path and a first address path and a second memory section having a second data path and a second address path. In an embodiment of the present invention, the first data and first address path is independent of the second data and second address path. The first write data is provided on the first data path responsive to the first write address being provided on the first address path while a read data is provided on the second data path responsive to the read address being provided on the second address path. | 12-08-2011 |
| 20110310680 | Interleave Memory Array Arrangement - A memory array includes a plurality of memory cells, wherein each cell of the plurality of memory cells is defined by a row and a column, wherein each row includes a unique identifying address, and wherein each column is associated with one of two sets, the columns arranged such that a column associated with a first set is adjacent to a column of a second set. | 12-22-2011 |
| 20110317500 | SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME - Disclosed is a semiconductor device having a memory cell which comprises a transistor having a control gate and a storage gate. The storage gate comprises an oxide semiconductor and is able to be a conductor and an insulator depending on the potential of the storage gate and the potential of the control gate. Data is written by setting the potential of the control gate to allow the storage gate to be a conductor, supplying a potential of data to be stored to the storage gate, and setting the potential of the control gate to allow the storage gate to be an insulator. Data is read by supplying a potential for reading to a read signal line connected to one of a source and a drain of the transistor and detecting the change in potential of a bit line connected to the other of the source and the drain. | 12-29-2011 |
| 20120002490 | SEMICONDUCTOR STORAGE DEVICE - According to the embodiments, a semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, and a row selector that multiply-selects the word lines, wherein the semiconductor storage device satisfies N | 01-05-2012 |
| 20120008429 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a data coding logic for generating converted data groups and a inverted flag data from original data groups received by the semiconductor memory device. The number of zeros in the converted data groups is less than or equal to the number of zeros in the original data groups. The semiconductor memory device also includes data decoding logic for generating the original data groups from the converted data groups and the inverted flag data. A peripheral circuit may be enabled to program the converted data groups and the inverted flag data into the memory cells and read the converted data groups and the inverted flag data from the memory cells. A control logic may be enabled to generate control signals for the data coding logic, the data decoding logic, and the peripheral circuit. | 01-12-2012 |
| 20120026808 | Integrated Circuit With Low Power SRAM - An integrated circuit containing a SRAM memory with SRAM bits optimized to have a lower minimum read voltage than the minimum write voltage. A method for reading a SRAM memory bit using a read voltage that is lower than the write voltage. | 02-02-2012 |
| 20120044775 | Semiconductor integrated circuit device - The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines. | 02-23-2012 |
| 20120081976 | SEMICONDUCTOR MEMORY DEVICE HAVING AN ELECTRICALLY FLOATING BODY TRANSISTOR - A method for performing a holding operation to a semiconductor memory array having rows and columns of memory cells, includes: applying an electrical signal to buried regions of the memory cells, wherein each of the memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and wherein the buried region of each memory cell is located within the memory cell and located adjacent to the floating body region, the buried region having a second conductivity type. | 04-05-2012 |
| 20120081977 | SEMICONDUCTOR MEMORY DEVICE HAVING AN ELECTRICALLY FLOATING BODY TRANSISTOR - A method for performing a holding operation to a semiconductor memory array having rows and columns of memory cells, includes: applying an electrical signal to buried regions of the memory cells, wherein each of the memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and wherein the buried region of each memory cell is located within the memory cell and located adjacent to the floating body region, the buried region having a second conductivity type. | 04-05-2012 |
| 20120113730 | RAM MEMORY ELEMENT WITH ONE TRANSISTOR - A memory element includes a MOS transistor having a drain, a source and a body region covered by an insulated gate, wherein the thickness of the body region is divided into two distinct regions separated by a portion of an insulating layer extending parallel to the plane of the gate. | 05-10-2012 |
| 20120147680 | SEMICONDUCTOR MEMORY DEVICE - A power supply control circuit which can cut off a power supply independently is provided for each column in a memory cell array. The power supply control circuit is controlled by a circuit which is provided for each column and determines whether or not it is necessary to hold information, whereby a power supply for a memory cell which does not need to hold information is cut off. | 06-14-2012 |
| 20120147681 | METHODS, DEVICES, AND SYSTEMS RELATING TO A MEMORY CELL HAVING A FLOATING BODY - Methods, devices, and systems are disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the transistor including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and the drain, a second region positioned remote from each of the source and drain, and a passage extending through the insulation layer and coupling the first region to the second region. Additionally, the memory cell may include a bias gate at least partially surrounding the second region and configured for operably coupling to a bias voltage. Furthermore, the memory cell may include a plurality of dielectric layers, wherein each outer vertical surface of the second region has a dielectric layer of the plurality adjacent thereto. | 06-14-2012 |
| 20120213013 | MEMORY BUILDING BLOCKS AND MEMORY DESIGN USING AUTOMATIC DESIGN TOOLS - The memory building blocks can be used in conjunction with ASIC automatic design tools to generate a memory macro (e.g., a memory array) using a known ASIC design flow including, for example, register transfer level (RTL), synthesis, automatic place and route (APR) and timing analysis. | 08-23-2012 |
| 20120218836 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a semiconductor memory device comprises a first silicon pillar including a first pair of columnar portions and a first connection portion, a second silicon pillar including a second pair of columnar portions and a second connection portion in the shunt region, the second silicon pillar being adjacent to the first silicon pillar, a first interconnection connected to one of the first pair of columnar portions of the first silicon pillar, a second interconnection connected to one of the second pair of columnar portions of the second silicon pillar. The first interconnection is connected to a dummy bit line. The first interconnection and the second interconnection are connected on the same level. | 08-30-2012 |
| 20120218837 | VOLTAGE REGULATOR - A voltage regulator may include an input terminal for receiving an input voltage and an output terminal for providing a respective output voltage, a regulation transistor having a first conduction terminal coupled to the input terminal for receiving the input voltage, a second conduction terminal coupled to the output terminal, and a control terminal coupled to the output of a first operational amplifier. The first operational amplifier may have a non-inverting input terminal for receiving a first reference voltage, and an inverting input terminal coupled to a first terminal of a divider circuit for receiving a second reference voltage. | 08-30-2012 |
| 20120224438 | SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a fin formed on a semiconductor substrate, a gate electrode provided on both sides of the fin via a gate dielectric film, a depletion layer that forms a potential barrier, which confines a hole in a body region between channel regions of the fin, in the fin, and a source/drain layer formed in the fin to sandwich the gate electrode are included. | 09-06-2012 |
| 20120230128 | Integrated Circuitry, Switches, and Methods of Selecting Memory Cells of a Memory Device - Some embodiments include switches that have a graphene structure connected to a pair of spaced-apart electrodes. The switches may further include first and second electrically conductive structures on opposing sides of the graphene structure from one another. The first structure may extend from one of the electrodes, and the second structure may extend from the other of the electrodes. Some embodiments include the above-described switches utilized as select devices in memory devices. Some embodiments include methods of selecting memory cells. | 09-13-2012 |
| 20120230129 | Method of altering distribution of a chosen characteristic of a plurality of memory cells forming a memory device - A method is provided for altering distribution of a chosen characteristic of a plurality of memory cells forming a memory device. The method comprises identifying a subset of the memory cells whose value of the chosen characteristic is within a predetermined end region of the distribution, and then performing a burn-in process during which one or more operating parameters of the memory device are set to induce aging of the memory cells. During the burn-in process, for each memory cell in the subset, the value stored in that memory cell is fixed to a selected value which exposes that memory cell to a stress condition. In contrast, for each memory cell not in the subset, the value stored in that memory cell is alternated during the burn-in process in order to alleviate exposure of that memory cell to the stress condition. Such an approach allows a tightening of the distribution of the chosen characteristic, thus improving the worst case memory cells. | 09-13-2012 |
| 20120230130 | Memory Cell System and Method - A memory cell system/method incorporating reduced transistor counts and/or improved design-for-manufacturability (DFM) is disclosed. The system/method incorporates cross-coupled feedthru ( | 09-13-2012 |
| 20120243345 | OUTPUT DRIVER CIRCUIT, OUTPUT DRIVER SYSTEM AND SEMICONDUCTOR MEMORY DEVICE - The output driver circuit includes a plurality of pull-up sub-drivers that pull up a voltage at the output terminal according to a pull-up signal based on the output data. The output driver circuit includes a plurality of pull-down sub-drivers that pull down the voltage at the output terminal according to a pull-down signal based on the output data. Selection from among the pull-up sub-drivers is made by an assigned pull-up calibration signal and selection from among the pull-down sub-drivers by an assigned pull-down calibration signal so as to make a pull-up current drivability and a pull-down current drivability for the voltage at the output terminal equal. A timing of turning on of the pull-up sub-drivers is calibrated by the pull-down calibration signal. A timing of turning on of the pull-down sub-drivers is calibrated by the pull-up calibration signal. | 09-27-2012 |
| 20120243346 | Control Method for Memory Cell - A control method for at least one memory cell. The memory cell includes a transistor and a resistor. The resistor is connected to the transistor in series between a first node and a second node. In a programming mode, the memory cell is programmed. When it is determined that the memory cell has been successfully programmed, impedance of the memory cell is in a first state. When it is determined that the memory cell has not been successfully programmed, a specific action is executed to reset the memory cell. The impedance of the memory cell is in a second state after the step resetting the memory cell. The impedance of the memory cell in the second state is higher than that of the memory cell in the first state. | 09-27-2012 |
| 20120250428 | MEMORY DEVICE, RECORDING METHOD, AND RECORDING AND REPRODUCING METHOD - A memory device, includes a recording medium; a probe to write a plurality of the signals; a first driving portion to vibratory drive the recording medium; a detecting unit which, when the first driving portion changes a frequency to vibratory drive the recording medium, detects a change in an amplitude of the resonance drive, detects the frequency at which the amplitude becomes maximum as a resonance frequency; and a calculating unit which calculates a timing when the probe writes a plurality of the signals using the resonance frequency; wherein, the first driving portion vibratory drives the recording medium and the probe writes a plurality of the signals. | 10-04-2012 |
| 20120250429 | SECURITY-PROTECTION OF A WAFER OF ELECTRONIC CIRCUITS - A process is provided for fabricating a wafer including a plurality of chips separated by scribe lines. The method includes locking at least one chip on the wafer using a secret key, and writing the secret key into at least one memory present on the wafer. | 10-04-2012 |
| 20120294097 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - A semiconductor memory device includes a plurality of wordlines and a driver configured to, when an wordline of the plurality of wordlines is activated by an active command, drive at least one non-activated wordline neighboring the activated wordline and remaining non-activated wordlines with different wordline driving voltage levels during a period of time that the activated wordline is driven to a high voltage level. | 11-22-2012 |
| 20120327725 | CIRCUIT DEVICES AND METHODS HAVING ADJUSTABLE TRANSISTOR BODY BIAS - Circuits, integrated circuits devices, and methods are disclosed that may include biasable transistors with screening regions positioned below a gate and separated from the gate by a semiconductor layer. Bias voltages can be applied to such screening regions to optimize multiple performance features, such as speed and current leakage. Particular embodiments can include biased sections coupled between a high power supply voltage and a low power supply voltage, each having biasable transistors. One or more generation circuits can generate multiple bias voltages. A bias control section can couple one of the different bias voltages to screening regions of biasable transistors to provide a minimum speed and lowest current leakage for such a minimum speed. | 12-27-2012 |
| 20130003469 | CIRCUITS AND METHODS FOR MEMORY - Embodiments for data dependent boosted (DDB) bit cells that may allow for smaller minimum cell supplies (Vmin) without necessarily having to increase device dimensions are presented. | 01-03-2013 |
| 20130003470 | INDEPENDENT LINK AND BANK SELECTION - Provided is a memory system that has a plurality of memory banks and a plurality of link controllers. For each memory bank, there is first switching logic for receiving output for each link controller, and for passing on the output of only one of the link controllers to the memory bank. For each link controller, there is second switching logic for receiving an output of each memory bank, and for passing on the output of only one of the memory banks to the link controller. According to an embodiment of the invention, there is switch controller logic for controlling operation of both the first switching logic and the second switching logic to prevent simultaneous or overlapping access by multiple link controllers to the same memory bank, and for preventing simultaneous or overlapping access to multiple banks by the same link controller. | 01-03-2013 |
| 20130010548 | METHOD OF OPERATING SEMICONDUCTOR DEVICE - A semiconductor device is operated by, inter alia: programming selected memory cells by applying a first program voltage which is increased by a first step voltage to a selected word line and by applying a first pass voltage having a constant level to unselected word lines, and when a voltage difference between the first program voltage and the first pass voltage reaches a predetermined voltage difference, programming the selected memory cells by applying a second program voltage which is increased by a second step voltage lower than the first step voltage to the selected word line and by applying a second pass voltage which is increased in proportion to the second program voltage to first unselected word lines adjacent to the selected word line among the unselected word lines. | 01-10-2013 |
| 20130010549 | METHODS OF OPERATING SEMICONDUCTOR DEVICE - A method of operating a semiconductor device according to an embodiment of the present invention includes programming selected memory cells by applying a first program voltage, which gradually rises, to a selected word line and applying a first pass voltage, which is constant, to remaining unselected word lines; and programming the selected memory cells while applying a second program voltage, which is constant, to the selected word line and applying a second pass voltage, which gradually rises, to first unselected word lines adjacent to the selected word line, when a difference between the first program voltage and the first pass voltage reaches a critical voltage difference. | 01-10-2013 |
| 20130028030 | PROGRAMMABLE KEEPER FOR SEMICONDUCTOR MEMORIES - A method includes receiving a memory code identifying a number of logic zeroes and logic ones to be stored in a semiconductor memory, determining a number of bit cells of a first type that are to be coupled to a first bit line of the semiconductor memory from the memory code, and selecting a first keeper circuit from a plurality of keeper circuits based on the number of bit cells of the first type that are to be coupled to the first bit line. An electronic representation of a layout of the semiconductor memory is stored in a non-volatile machine readable storage medium. | 01-31-2013 |
| 20130051162 | CODED DIFFERENTIAL INTERSYMBOL INTERFERENCE REDUCTION - Encoder and decoder circuits that encode and decode a series of data words to/from a series of code words. The data words include L symbols. The code words include M symbols, where M is larger than L. A set of tightly coupled M links to convey respective symbols in each of the series of code words. The code words are selected such that between every two consecutive code words in a series of code words, an equal number of transitions from low to high and high to low occur on a subset of the M-links. | 02-28-2013 |
| 20130058173 | SEMICONDUCTOR APPARATUS - A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a mode information storage unit that stores first and second mode information, the first and second mode information being able to be set through the first bus-interface circuit, a first memory core that operates based on the first mode information, the first memory core being connected to the first bus-interface circuit and supplied with a first clock signal, a second memory core, the second memory core being supplied with a second clock signal and a select circuit that selectively connects the second memory core to the first or second bus-interface circuit based on predetermined switching information, in which the second memory core operates based on the second mode information when the second memory core is connected to the second bus-interface circuit. | 03-07-2013 |
| 20130064022 | Method and Apparatus for Memory Access - An interleaver or deinterleaver comprises a memory having M logical memory units arranged in groups of N memory units such that accesses to memory units within a group are faster after a first access to a memory in that group using first access. An address generator is arranged to write consecutive data items a number of memory units apart that is less than the size of groups N of memory units so that two or more data items are written within groups. The arrangement provides fast interleaving without increasing memory size. | 03-14-2013 |
| 20130083610 | ENERGY EFFICIENT MEMORY WITH RECONFIGURABLE DECODING - A sacrificial memory bank is added to a block of regular banks in a memory to reduce dynamic power consumption of the memory. The sacrificial bank is accessed by a set of bit lines that is substantially shorter than corresponding bit lines extending through all of the regular memory banks. Memory read and write operations, which are addressed to one of the regular banks, are deliberately redirected to the sacrificial bank having the short bit lines. Tracking circuitry identifies the regular bank that was addressed for each location in the sacrificial bank. Data is moved from the sacrificial bank to a regular bank only when a new write operation does not match the bank of the previous write operation. Dynamic power is reduced because locality of reference causes access to the sacrificial bank without having to access a regular bank for most memory read and write operations. | 04-04-2013 |
| 20130100747 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a memory cell array having memory cells coupled to a plurality of word lines and a peripheral circuit group configured to supply a pass voltage to unselected word lines among the plurality of word lines, wherein the peripheral circuit group stepwise raises the pass voltage supplied to the unselected word lines to a target level. | 04-25-2013 |
| 20130100748 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - In a conventional DRAM, data read errors are more likely to occur along with miniaturization of DRAM. A small change in the potential of a first bit line is inverted by a first inverter constituted by an n-channel transistor and a p-channel transistor, and is output to a second bit line through a first selection transistor, which is a first switch. Since the potential of the second bit line is the inverse of the potential of the first bit line, the potential difference between the first bit line and the second bit line is increased. The increased potential difference is amplified by a known sense amplifier, a flip-flop circuit composed of the first inverter and a second inverter (constituted by an n-channel transistor and a p-channel transistor), or the like. | 04-25-2013 |
| 20130100749 | NANO-SENSE AMPLIFIER - A sense amplifier for a series of cells of a memory, including a writing stage comprising a CMOS inverter, the input of which is directly or indirectly connected to an input terminal of the sense amplifier, and the output of which is connected to an output terminal of the sense amplifier intended to be connected to a local bitline addressing the cells of the series, and a reading stage that includes a sense transistor, the gate of which is connected to the output of the inverter and the drain of which is connected to the input of the inverter. | 04-25-2013 |
| 20130100750 | SEMICONDUCTOR DEVICE - Disclosed is a semiconductor device which is intended to reduce the total number of storage element blocks that constitute a desired logic circuit. The semiconductor device includes N address lines (N is an integer equal to two or more), N data lines, and a plurality of storage sections. Each of the storage sections includes an address decoder for decoding an address supplied via the N address lines to output a word select signal to word lines; and a plurality of storage elements which are connected to the word lines and the data lines, each store data that constitute a truth table, and input or output the data via the data lines in accordance with the word select signal supplied via the word lines. The semiconductor device is adapted such that the N address lines for the storage sections are connected to the respective data lines of other N ones of the storage sections, while the N data lines for the storage sections are connected to the respective address lines of other N ones of the storage sections. | 04-25-2013 |
| 20130114354 | NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF OPERATION - A memory device comprises a nonvolatile memory device and a controller. The nonvolatile memory comprises a first memory area comprising single-bit memory cells and a second memory area comprising multi-bit memory cells. The controller is configured to receive a first unit of write data, determine a type of the first unit of write data, and based on the type, temporarily store the first unit of write data in the first memory area and subsequently migrate the temporarily stored first unit of write data to the second memory area or to directly store the first unit of write data in the second memory area, and is further configured to migrate a second unit of write data temporarily stored in the first memory area to the second memory area where the first unit of write data is directly stored in the second memory area. | 05-09-2013 |
| 20130128677 | DYNAMIC RANDOM ACCESS MEMORY DEVICE WITH IMPROVED CONTROL CIRCUITRY FOR THE WORD LINES - A dynamic random access memory device may include DRAM memory cells including several lines of memory cells, and line selection circuitry associated with each line. The line selection circuitry may include a first voltage-elevator stage configured to receive two initial control logic signals each having an initial voltage level corresponding to a first logic state, and to deliver two intermediate control logic signals each having an intermediate voltage level above the initial level and corresponding to the first logic state. The line selection circuitry may also include a control circuit to be supplied by PMOS transistors with a supply voltage having a second voltage level greater than the intermediate voltage level, and configured to, in the presence of the two intermediate control logic signals have their first logic state deliver to the gates of the memory cell transistors, a selection logic signal having the second voltage level. | 05-23-2013 |
| 20130148440 | METHOD FOR OPERATING MEMORY SYSTEM IN RING TOPOLOGY - A method for operating a memory system includes providing a memory system including a memory controller, and first and second memory devices constituting a ring topology. The memory controller is connected to the first memory device through first and second links. The second memory device is disposed on the first link. The first memory device starts a first operation. The first link is used as a communication path between the first memory device and the memory controller. The second memory device starts a second operation before the first memory device completes the first operation. The communication path between the first memory device and the memory controller is changed into the second link. The first link is used as a communication path between the second memory device and the memory controller. | 06-13-2013 |
| 20130148441 | RAM MEMORY CELL COMPRISING A TRANSISTOR - The invention relates to a memory cell consisting of an isolated MOS transistor having a drain ( | 06-13-2013 |
| 20130148442 | MEMORY CONTROL CIRCUIT AND MEMORY CIRCUIT - A memory circuit includes a plurality of divided memory cell blocks, a write circuit and a read circuit which connect via a pair of bit lines to each of the divided memory cell blocks. The output of write data to one of the bit line of the write circuit is made to be performed by one system. It is possible to achieve an increase of speed by bit lien division while reducing increase in the memory circuit area accompanying the bit line division. | 06-13-2013 |
| 20130155788 | DDR 2D VREF TRAINING - A method is provided for performing memory operations in response to instructions to perform a double data rate (DDR) memory reference voltage training in the voltage domain by a processing device and determining a DDR memory reference voltage and a DDR memory delay time based upon the memory operation. Computer readable storage media are also provided. A circuit is provided that includes a communication interface portion coupled to a memory and to a processing device. The circuit also includes a circuit portion, coupled to the communication interface portion that has a hardware state machine or an algorithm. The state machine or algorithm provides instructions to the processing device to perform a double data rate (DDR) reference voltage training in the voltage domain. | 06-20-2013 |
| 20130155790 | STORAGE DEVICE - Noise attributed to signals of a word line, in first and second bit lines which are overlapped with the same word line in memory cells stacked in a three-dimensional manner is reduced in a storage device with a folded bit-line architecture. The storage device includes a driver circuit including a sense amplifier, and first and second memory cell arrays which are stacked each other. The first memory cell array includes a first memory cell electrically connected to the first bit line and a first word line, and the second memory cell array includes a second memory cell electrically connected to the second bit line and a second word line. The first and second bit lines are electrically connected to the sense amplifier in the folded bit-line architecture. The first word line, first bit line, second bit line, and second word line are disposed in this manner over the driver circuit. | 06-20-2013 |
| 20130163349 | PROGRAMMING PULSE GENERATION CIRCUIT AND NON-VOLATILE MEMORY APPARATUS HAVING THE SAME - A program pulse generation circuit includes: a set pulse generator configured to apply a set pulse to an output node in response to a driving signal, a set pulse control signal, and a first switching signal, and a current controller configured to control step reductions forming the set pulse in response to the driving signal and a second switching signal. | 06-27-2013 |
| 20130176796 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF WRITING INTO SEMICONDUCTOR MEMORY DEVICE - The semiconductor memory device includes a memory cell, a pair of bit lines and a cell power line connected to the memory cell, a first switch connected to the bit lines and a power voltage line, a second switch connected to the cell power line and a write assist cell power line, and a write control circuit configured to control the bit lines, the first switch and the second switch, wherein the write control circuit applies a first voltage of a high level to one bit line and a second voltage of a low level to the other bit line, connects one bit line to the power voltage line and disconnects the other bit line from the power voltage line by the first switch, and then connects the cell power line to the write assist cell power line lower which is than the first voltage by the second switch. | 07-11-2013 |
| 20130201769 | NONVOLATILE MEMORY APPARATUS, PROGRAM METHOD THEREOF, AND DATA PROCESSING SYSTEM USING THE SAME - A nonvolatile memory apparatus includes: a memory cell area including a plurality of memory cells connected to a word line and a bit line; a program time controller configured to determine a program voltage application time for a selected word line, as the selected word line is selected in response to a program command and an address signal; and a controller configured to apply a program voltage to the selected word line according to the program voltage application time determined by the program time controller. | 08-08-2013 |
| 20130201770 | MEMORY WITH DEFERRED FRACTIONAL ROW ACTIVATION - Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated. | 08-08-2013 |
| 20130201771 | Volatile Memory with a Decreased Consumption - A volatile memory including volatile memory cells adapted to the performing of data write and read operations. The memory cells are arranged in rows and in columns and, further, are distributed in separate groups of memory cells for each row. The memory includes a first memory cell selection circuit configured to perform write operations and a second memory cell selection circuit, different from the first circuit, configured to perform read operations. The first circuit is capable of selecting, for each row, memory cells from one of the group of memory cells for a write operation. The second circuit is capable of selecting, for each row, memory cells from one of the groups of memory cells for a read operation. | 08-08-2013 |
| 20130201772 | LOW VOLTAGE EFUSE PROGRAMMING CIRCUIT AND METHOD - A circuit for programming a fuse is disclosed. The circuit includes a voltage supply terminal (Vf) and a semiconductor controlled rectifier ( | 08-08-2013 |
| 20130208551 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR ACCESSING THE SAME - A semiconductor memory device and a method for accessing the same are disclosed. The semiconductor memory device includes an oxide heterojunction transistor which includes: an oxide substrate; an oxide film on the oxide substrate, wherein an interfacial layer between the oxide substrate and the oxide film behaves like two-dimensional electron gas; a source electrode and a drain electrode being located on the oxide film and electrically connected with the interfacial layer; a front gate on the oxide film; and a back gate on a lower surface of the oxide substrate, wherein the source electrode and the drain electrode of the oxide heterojunction transistor are respectively connected with a first word line and a first bit line for reading operation, and wherein the front gate and the back gate are respectively connected with a second word line and a second bit line for writing operation. | 08-15-2013 |
| 20130223163 | SYSTEMS, AND DEVICES, AND METHODS FOR PROGRAMMING A RESISTIVE MEMORY CELL - Embodiments disclosed herein may relate to programming a memory cell with a programming pulse that comprises a quenching period having different portions. | 08-29-2013 |
| 20130223164 | SENSE AMPLIFIER CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE - To improve reading accuracy of a sense amplifier circuit and a semiconductor memory device. A sense amplifier circuit includes an N type FET which is a sensing transistor connected between a power supply and a ground via a data line that extends to a memory cell, a resistance element that is connected between a gate of the sensing transistor and the power supply, and a capacitance element that is connected between the gate of the sensing transistor and the ground. | 08-29-2013 |
| 20130235679 | Boosting Memory Reads - A memory device comprises memory elements that are arranged in an array. The array includes rows associated with wordlines and columns associated with bitlines. The memory elements in a row share a wordline and memory elements in a column share a bitline. For each wordline, a wordline driver circuit is associated with the wordline. The memory device comprises a boost circuit that has an output coupled to the wordline driver circuits. The boost circuit is configured to provide a negative voltage to the wordlines during a read operation of the memory device such that unselected wordlines are held at a negative voltage below a ground potential while a selected wordline is held at a supply voltage during the read operation. | 09-12-2013 |
| 20130242676 | FAST-SWITCHING WORD LINE DRIVER - A word line driver of a semiconductor memory includes logic circuitry for coupling a word line to a first node set at a first voltage level when the word line driver is in a first state or to a second node set at a second voltage level when the word line driver is in a second state. A capacitor is configured to be charged to a third voltage level that is greater than the first and second voltage levels. First and second transistors are configured to selectively couple the word line to the capacitor and to a third node set at a fourth voltage level when the word line driver is in a third state. The fourth voltage level is greater than the first voltage level and less than the second voltage level. | 09-19-2013 |
| 20130279275 | SEMICONDUCTOR DEVICE - A semiconductor memory device includes a bit line connected to a memory cell; an input/output line configured to input a data signal to the memory cell during a writing operation and to output a data signal stored in the memory cell during a reading operation; and a column select transistor including a first source/drain connected to the bit line and a second source/drain connected to the input/output line, wherein a resistance of the first source/drain is smaller than a resistance of the second source/drain. | 10-24-2013 |
| 20130279276 | SEPARATE MICROCHANNEL VOLTAGE DOMAINS IN STACKED MEMORY ARCHITECTURE - Separate microchannel voltage domains in a stacked memory architecture An embodiment of a memory device includes a memory stack including one or more coupled memory dies, wherein a first memory die of the memory stack includes multiple microchannels, and a logic chip coupled with the memory stack, the logic chip including a memory controller. Each of the microchannels includes a separate voltage domain, and a voltage level is controlled for each of the plurality of microchannels. | 10-24-2013 |
| 20130294179 | CIRCUITS AND METHODS FOR CALIBRATING OFFSET IN AN AMPLIFIER - In one embodiment, the present disclosure includes a circuit comprising an amplifier having an input and an output, an offset detection circuit to detect an offset of the amplifier at the output of the amplifier, and an offset generation circuit having an input coupled to the offset detection circuit and an output coupled to the input of the amplifier to generate an offset at the input of the amplifier during an operational phase of the amplifier based on the detected offset. The generated offset cancels a least a portion of the offset of the amplifier. In one implementation, the amplifier is a sense amplifier in a memory. | 11-07-2013 |
| 20130294180 | CHARGE STORAGE ORGANIC MEMORY SYSTEM - A memory system is disclosed. The system comprises a memory layer between a first layer and a second layer, wherein the first layer and the second layer are configured to apply an electrical bias to the memory layer. In some embodiments the memory layer comprises nanodots made of a material selected from the group consisting of peptides and amino acids. | 11-07-2013 |
| 20130301366 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device of the present invention includes a memory cell array with cell strings having word lines stacked on a substrate and a vertical channel layer formed through the word lines, a peripheral circuit configured to select one of the word lines and perform a program operation on the selected word line, and a control circuit configured to control the peripheral circuit to perform the program operation by applying a program voltage to a word line selected for the program operation, applying a ground voltage to a word line of which a program operation has been completed and applying a pass voltage to the other word lines. | 11-14-2013 |
| 20130315011 | SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF - A semiconductor device in which a nonvolatile memory can normally operate and power saving can be performed with a P-state function, and a driving method of the semiconductor device are provided. The semiconductor device includes: a first circuit configured to control a state including a driving voltage and a clock frequency of a processor core; a first memory circuit and a second memory circuit which store state data; a second circuit generating a power supply voltage and a third circuit generating a clock which are electrically connected to the first circuit; and the processor core electrically connected to the second circuit and the third circuit through a switch. The processor cores includes: a volatile memory; and a nonvolatile memory transmitting and receiving data to/from the first memory. | 11-28-2013 |
| 20130315012 | SEMICONDUCTOR MEMORY DEVICE, AND METHOD OF CONTROLLING THE SAME - A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device. | 11-28-2013 |
| 20130322187 | SEMICONDUCTOR DEVICE AND PROCESSING UNIT - A semiconductor device in which the power consumption of a register is low is provided. Further, a processing unit whose operation speed is high and whose power consumption is low is provided. In the semiconductor device, a register operating at high speed and a nonvolatile FILO (first-in-last-out) register capable of reading and writing data from/to the register are provided. | 12-05-2013 |
| 20130322188 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device that detects an operation error of an SRAM caused by a device variation fluctuating with time is provided. In the SRAM, a memory cell has a transfer MOS transistor whose gate is connected to a word line. At the time of a write test of the memory cell, a control circuit including a test/normal operation selection circuit and a word line driver circuit applies a third voltage to the word line in a preparation period before writing test data, thereafter a first voltage to the word line, and a second voltage to the word line at the end of writing. Due to this, the threshold voltage of the transfer MOS transistor, which fluctuates with time, can be controlled. Therefore, it is possible to enhance detection efficiency for a malfunctioning cell of the SRAM due to a temporal variation. | 12-05-2013 |
| 20140003166 | ELECTRONIC EQUIPMENT | 01-02-2014 |
| 20140029360 | TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE - Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region. | 01-30-2014 |
| 20140050036 | GRAPHENE-BASED NON-VOLATILE MEMORY - Embodiments relate to a method for representing data in a graphene-based memory device. The method includes applying a first voltage to a back gate of a graphene-based memory device and a second voltage to a first graphene layer of the graphene-based memory device. The graphene-based memory device includes the first graphene layer and a second graphene layer and a first insulation layer located between the first and second graphene layers. The first insulation layer has an opening between the first and second graphene layers. The back gate is located on an opposite side of the second graphene layer from the first insulation layer. The first graphene layer is configured to bend into the opening of the first insulation layer to contact the second graphene layer based on a first electrostatic force generated by the applying the first voltage to the back gate. | 02-20-2014 |
| 20140063983 | Error Detection And Correction In A Memory System - A method including providing a plurality of random access memories having at least a first region, a second region and a third region; storing protected data on the first region on at least two of the random access memories, where the protected data is stored distributed among the at least two random access memories of the first region; storing parity information for the protected data on the second region on at least a third one of the random access memories; and storing unprotected data on the third region. | 03-06-2014 |
| 20140063984 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device is provided. The semiconductor memory device includes memory cells having first to fourth middle states corresponding to different threshold voltage distributions. The semiconductor memory device also includes a peripheral circuit configured to perform a first program operation to program memory cells having the third and the fourth middle states to have four upper states and perform a second program operation to program memory cells having the first and the second middle states to have another four upper states. | 03-06-2014 |
| 20140063985 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device is provided. The semiconductor memory device includes a memory cell array including cell strings coupled between bit lines and a common source line, each of the cell strings comprising a plurality of memory cells stacked above a substrate. The semiconductor memory device also includes a peripheral circuit configured to supply a negative voltage to one or more word lines coupled to the cell strings and supply a positive voltage to the common source line, wherein the peripheral circuit supplies the positive voltage and the negative voltage before a program operation is performed. | 03-06-2014 |
| 20140071773 | OUTPUT DRIVER TO DRIVE SEMICONDUCTOR DEVICE AND MEMORY SYSTEM - According to one embodiment, an output driver which outputs an output signal to a transmission line, the output driver includes a pre-driver and a main driver. The pre-driver changes the duty ratio of a first drive signal and the duty ratio of a second drive signal to a plurality of patterns in accordance with a control signal. The main driver connects in series a first driver driven by the first drive signal and a second driver driven by the second drive signal. The main driver outputs the output signal to the transmission line from a connection node of the first and second drivers. | 03-13-2014 |
| 20140071774 | LOW VOLTAGE EFUSE PROGRAMMING CIRCUIT AND METHOD - A circuit for programming a fuse is disclosed. The circuit includes a voltage supply terminal (Vf) and a semiconductor controlled rectifier ( | 03-13-2014 |
| 20140092694 | MULTI-BIT RESISTANCE MEASUREMENT - An example embodiment is a circuit for determining a binary value of a memory cell. The circuit includes shunt capacitors having different capacitances to selectively couple with the memory cell, and a controller configured to iteratively charge the shunt capacitors to a first voltage until a selected shunt capacitor causes the first voltage to decay through the memory cell to a first reference voltage within a predetermined time range, determine a binary value of the most significant bits of the memory cell based on the selected shunt capacitor, charge the selected shunt capacitor to a second voltage after determining the binary value of the most significant bits of the memory cell, and determine a binary value of the least significant bits of the memory cell based on a decay of the second voltage at the selected shunt capacitor through the memory cell. | 04-03-2014 |
| 20140098619 | NON-VOLATILE MEMORY WITH OVERWRITE CAPABILITY AND LOW WRITE AMPLIFICATION - Providing for a non-volatile memory architecture having write and overwrite capabilities providing low write amplification to a storage system is described herein. By way of example, a memory array is disclosed comprising blocks and sub-blocks of two-terminal memory cells. The two-terminal memory cells can be directly overwritten in some embodiments, facilitating a write amplification value as low as one. Furthermore, the memory array can have an input-output multiplexer configuration, reducing sneak path currents of the memory architecture during memory operations. | 04-10-2014 |
| 20140104965 | Non-volatile Memory Array And Method Of Using Same For Fractional Word Programming - A non-volatile memory device that includes N planes of non-volatile memory cells (where N is an integer greater than 1). Each plane of non-volatile memory cells includes a plurality of memory cells configured in rows and columns. Each of the N planes includes gate lines that extend across the rows of the memory cells therein but do not extend to others of the N planes of non-volatile memory cells. A controller is configured to divide each of a plurality of words of data into N fractional-words, and program each of the N fractional-words of each word of data into a different one of the N planes of non-volatile memory cells. The controller uses a programming current and a program time period for the programming, and can be configured to vary the programming current by a factor and inversely vary the program time period by the factor. | 04-17-2014 |
| 20140112081 | DATA-DEPENDENT PULLUP TRANSISTOR SUPPLY AND BODY BIAS VOLTAGE APPLICATION FOR A STATIC RANDOM ACCESS MEMORY (SRAM) CELL - A memory cell includes a true data node, a true pullup transistor, a complement data node and a complement pullup transistor. A true switching circuit selectively supplies a first or second supply voltage to a source of the true pullup transistor. A true bias switching circuit selectively supplies a third or fourth supply voltage to a body of the true pullup transistor. When writing a logic high data value to the true data storage node, a control circuit causes the true switching circuit to supply the second supply voltage and the true bias switching circuit to supply the third supply voltage. The second supply voltage is higher than the first supply voltage, and the fourth supply voltage is higher than the third supply voltage. A similar operation is performed with respect to the complement pullup transistor when writing a logic high data value to the complement data storage node. | 04-24-2014 |
| 20140112082 | DATA STORAGE DEVICE, CONTROLLER, AND OPERATING METHOD OF DATA STORAGE DEVICE - A nonvolatile memory is provided which includes a memory cell array including a plurality of nonvolatile memory cells; a decoder connected with the memory cell array through a plurality of word lines; a data input/output circuit connected with the memory cell array through a plurality of bit lines; a voltage detector configured to detect a variation in a power supply voltage to output a voltage variation signal; and control logic configured to control the decoder and the data input/output circuit such that data stored at the memory cell array is invalidated in response to the voltage variation signal. | 04-24-2014 |
| 20140126307 | TECHNIQUES FOR REFRESHING A SEMICONDUCTOR MEMORY DEVICE - Techniques for refreshing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region coupled to a source line and a second region coupled to a carrier injection line. Each memory cell may also include a body region capacitively coupled to at least one word line and disposed between the first region and the second region and a decoupling resistor coupled to at least a portion of the body region. | 05-08-2014 |
| 20140146621 | NONVOLATILE MEMORY AND METHOD OF OPERATING NONVOLATILE MEMORY - A nonvolatile memory includes multiple banks, control logic and multiple read and write (RW) circuits. Each bank includes multiple memory cells. The control logic includes multiple storage units corresponding to the banks, respectively, and configured to output write enable signals and read enable signals to respective banks based on mode information stored in respective storage units. The RW circuits are connected to the banks, respectively, and are configured to independently enable or disable write and read operations of the respective banks in response to the write enable signals and the read enable signals of the respective banks. In an initial state after the mode information is stored in the respective storage units, the control logic activates the write enable signals and the read enable signals of the respective banks regardless of the mode information stored in the respective storage units. | 05-29-2014 |
| 20140160865 | INTER-WORD-LINE PROGRAMMING IN ARRAYS OF ANALOG MEMORY CELLS - A method includes selecting a word line for programming in an array of analog memory cells that are arranged in rows associated with respective word lines and columns associated with respective bit lines. Word-line voltages, which program the memory cells in the selected word line, are applied to the respective word lines. Bit-line voltages, which cause one or more additional memory cells outside the selected word line to be programmed as a result of programming the selected word line, are applied to the respective bit lines. Using the applied word-line and bit-line voltages, data is stored in the memory cells in the selected word line and the additional memory cells are simultaneously programmed. | 06-12-2014 |
| 20140160866 | APPLICATIONS FOR INTER-WORD-LINE PROGRAMMING - A method includes, in an array of analog memory cells that are arranged in rows associated with respective word lines, reading a first group of the memory cells in a selected word line, including one or more memory cells that store a status of at least one word line in the array other than the selected word line. A readout configuration for a second group of the memory cells is set responsively to the read status. The second group of the memory cells is read using the readout configuration. | 06-12-2014 |
| 20140160867 | APPARATUSES AND METHODS FOR UNIT IDENTIFICATION IN A MASTER/SLAVE MEMORY STACK - Apparatuses and methods including a plurality of memory units are disclosed. An example apparatus includes a plurality of memory units. Each of the plurality of memory units include a master/slave identification (ID) node coupled to a first voltage source node via a resistive element. Each of the plurality of memory units further include a master/slave ID circuit configured to determine whether a memory unit is a master memory unit or a slave memory unit based on a voltage level detected at the master/slave ID node. The master/slave ID node of each of the plurality of memory units other than a first memory unit is further coupled to a respective second voltage source node via a through-substrate via (TSV) of a respective adjacent memory unit of the plurality of memory units. | 06-12-2014 |
| 20140160868 | Method of Maintaining the State of Semiconductor Memory Having Electrically Floating Body Transistor - Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell, and accessing the cell. | 06-12-2014 |
| 20140160869 | BUILT-IN SELF TRIM FOR NON-VOLATILE MEMORY REFERENCE CURRENT - A non-volatile memory built-in self-trim mechanism is provided by which product reliability can be improved by minimizing drift of reference current used for accessing the non-volatile memory and for performing initial trimming of the reference current. Embodiments perform these tasks by using an analog-to-digital converter to provide a digital representation of the reference current (Iref) and then comparing that digital representation to a stored target range value for Iref and then adjusting a source of Iref accordingly. For a reference current generated by a NVM reference bitcell, program or erase pulses are applied to the reference cell as part of the trimming procedure. For a reference current generated by a bandgap-based circuit, the comparison results can be used to adjust the reference current circuit. In addition, environmental factors, such as temperature, can be used to adjust the measured value for the reference current or the target range value. | 06-12-2014 |
| 20140160870 | METHOD AND APPARATUS OF CHANGING DEVICE IDENTIFICATION CODES OF A MEMORY INTEGRATED CIRCUIT DEVICE - In the disclosed technology, the device identification code of a memory integrated circuit is changeable. In some cases, multiple device identification codes are stored on the memory integrated circuit, and multiple device identification code selection data are stored on the memory integrated circuit. A device identification code register can store a selected device identification code. | 06-12-2014 |
| 20140177352 | SHARED TRACKING CIRCUIT - A system comprises a plurality of first memory macros and a first tracking circuit to be shared by the plurality of first memory macros. The first tracking circuit includes at least one of a first tracking circuit associated with a row of memory cells of a first memory macro of the plurality of first memory macros, a first tracking circuit associated with a column of memory cells of the first memory macro of the plurality of first memory macros, a first decoder tracking circuit associated with decoding circuitries of the first memory macro of the plurality of first memory macros, and a first input-output tracking circuit associated with input-output circuitries of the first memory macro of the plurality of first memory macros. | 06-26-2014 |
| 20140185392 | MEMORY SENSE AMPLIFIER VOLTAGE MODULATION - Memory sense amplifier voltage modulation. An embodiment of a an apparatus includes a memory including a sense amplifier; a first node for an high voltage rail for the sense amplifier and a second node for a low voltage rail for the sense amplifier; one or more elements to provide a first voltage to the first node and a second voltage to the second node; and a voltage control engine to control the one or more elements, where the voltage control engine is to independently set a value of the first voltage and a value of the second voltage over time. | 07-03-2014 |
| 20140185393 | DESIGN FOR TEST (DFT) READ SPEED THROUGH TRANSITION DETECTOR IN BUILT-IN SELF-TEST (BIST) SORT - A memory is disclosed that can operate in a normal mode of operation or a testing mode of operation. In the testing mode of operation, the memory can measure various benchmarks of performance, such as read speed. The memory can perform an asynchronous read operation to read a word of electronic data that corresponds to an address or a page read operation in which multiple asynchronous read operations are performed to read multiple words of electronic data, also referred to as a page of electronic data, that correspond to multiple addresses. The memory can measure a time required, referred to as read speed, to read the word of electronic data or the multiple words of electronic data from the memory. In the normal mode of operation, the memory can perform the asynchronous read operation, the page read operation, an asynchronous write operation in which a word of electronic data is stored into the memory that correspond to the address, or a page write operation in which a page electronic data is stored into the memory that correspond to the multiple addresses. | 07-03-2014 |
| 20140198588 | N-WELL SWITCHING CIRCUIT - A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit biases the switched n-well to prevent voltage damage to the dual-mode PMOS transistor despite its relatively small size and thin gate-oxide thickness. | 07-17-2014 |
| 20140204688 | REFERENCE CURRENT DISTRIBUTION - Example reference current distribution circuitry described herein include current mirrors having resistive elements of varying sizes between gate nodes of sense amplifier transistors along a voltage, distribution line. Examples of counter coupling capacitances which may be coupled to the gate nodes of sense amplifier transistors are also described. | 07-24-2014 |
| 20140233329 | COMPENSATION SCHEME FOR NON-VOLATILE MEMORY - Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell. | 08-21-2014 |
| 20140241077 | TRACKING CIRCUIT - A current flowing through a voltage line and/or a data line in a column of a tracking circuit is determined. A threshold tracking time delay of the tracking circuit is determined. Based on the determined current handled by the voltage line and/or the data line and the determined threshold tracking time delay, a plurality of columns in the tracking circuit, a number of first cells in each column of the plurality of columns, and a number of second cells in the each column of the plurality of columns are determined. | 08-28-2014 |
| 20140247674 | VERTICAL ACCESS DEVICE AND APPARATUSES HAVING A BODY CONNECTION LINE, AND RELATED METHOD OF OPERATING THE SAME - Methods, apparatuses, and systems for providing a body connection to a vertical access device. The vertical access device may include a digit line extending along a substrate to a digit line contact pillar, a body connection line extending along the substrate to a body connection line contact pillar, a body region disposed on the body connection line, an electrode disposed on the body region, and a word line extending to form a gate to the body region. A method for operation includes applying a first voltage to the body connection line, and applying a second voltage to the word line to cause a conductive channel to form through the body region. A memory cell array may include a plurality of vertical access devices. | 09-04-2014 |
| 20140254289 | DATA CIRCUIT - A circuit includes a first plurality of memory cells coupled with a first data line and a first data transfer circuit coupled with the first data line and a second data line. In a first operation mode of the circuit, the first data line is left floating and is caused to have a first logical value by a current in at least one memory cell of the first plurality of memory cells. In a second operation mode of the circuit, the first data line is configured to reflect data stored in a memory cell of the plurality of memory cells, and the second data line is configured to reflect the data on the first data line through the first data transfer circuit. | 09-11-2014 |
| 20140269111 | NON-VOLATILE MEMORY (NVM) WITH BLOCK-SIZE-AWARE PROGRAM/ERASE - A memory includes a plurality of blocks in which each block includes a plurality of memory cells. The memory includes a set of charge pumps which apply voltages to the plurality of blocks. A method includes selecting a block of the plurality of memory blocks; determining an array size of the selected block; determining a set of program/erase voltages based on the array size and temperature from a temperature sensor; and programming/erasing the selected block, wherein the set of program/erase voltages are applied by the set of charge pumps during the programming/erasing of the selected block. | 09-18-2014 |
| 20140321221 | SEMICONDUCTOR INTEGRATED CIRCUIT WITH THICK GATE OXIDE WORD LINE DRIVING CIRCUIT - A semiconductor integrated circuit according to one aspect of the present invention may includes a plurality of driving circuits to drive a respective plurality of word lines with either a first voltage supplied from a first power supply or a second voltage supplied from a second power supply in accordance with a control signal, and a plurality of gate transistors in each of which a gate is connected to one of the plurality of word lines, and a connection state between a storage node and a bit line is changed based on the voltage provided to the word line connected to the gate. In the semiconductor integrated circuit, a gate oxide film of each of the plurality of gate transistors is thinner than a gate oxide film of each of transistors constituting the plurality of driving circuits. | 10-30-2014 |
| 20140328131 | INTER-WORD-LINE PROGRAMMING IN ARRAYS OF ANALOG MEMORY CELLS - A method includes selecting a word line for programming in an array of analog memory cells that are arranged in rows associated with respective word lines and columns associated with respective bit lines. Word-line voltages, which program the memory cells in the selected word line, are applied to the respective word lines. Bit-line voltages, which cause one or more additional memory cells outside the selected word line to be programmed as a result of programming the selected word line, are applied to the respective bit lines. Using the applied word-line and bit-line voltages, data is stored in the memory cells in the selected word line and the additional memory cells are simultaneously programmed. | 11-06-2014 |
| 20140334237 | APPARATUSES, DEVICES AND METHODS FOR SENSING A SNAPBACK EVENT IN A CIRCUIT - Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be initiated and subsequently changed in response to a determination that a snapback event has occurred in a circuit. For example, a circuit may comprise a memory cell that may experience a snapback event as a result of an applied electric potential. In certain example implementations, a sense circuit may be provided which is responsive to a snapback event occurring in a memory cell to generate a feed back signal to initiate a change in an electric potential applied to the memory cell. | 11-13-2014 |
| 20140340972 | Method of Maintaining the State of Semiconductor Memory Having Electrically Floating Body Transistor - Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell. | 11-20-2014 |
| 20140355361 | CIRCUIT IN DYNAMIC RANDOM ACCESS MEMORY DEVICES - A circuit in dynamic random access memory devices includes a command extension circuit. The command extension circuit is configured to generate at least one multiple-cycle command signal by lengthening a single-cycle clock command signal from a command decoding circuit. Control logic extends and reduces the multiple-cycle command signal to provide additional functions such as burst length and burst chop. Additional control logic is configured to determine whether a clock signal is enabled in output control logic circuitry according to the multiple-cycle command and logic level generated in the output logic circuitry. | 12-04-2014 |
| 20140362650 | APPARATUSES AND METHODS FOR EFFICIENT WRITE IN A CROSS-POINT ARRAY - A memory circuit, including a memory array (such as a cross-point array), may include circuit elements that may function both as selection elements/drivers and de-selection elements/drivers. A selection/de-selection driver may be used to provide both a selection function as well as an operation function. The operation function may include providing sufficient currents and voltages for WRITE and/or READ operations in the memory array. When the de-selection path is used for providing the operation function, highly efficient cross-point implementations can be achieved. The operation function may be accomplished by circuit manipulation of a de-selection supply and/or de-selection elements. | 12-11-2014 |
| 20140369141 | Screening for Reference Cells in a Memory - Selecting an array from among a plurality of arrays in a memory as a reference array. An exemplary method includes evaluating memory cells within the reference array to select a first reference cell associated with a first operation of the memory, and repeating the evaluating and the selecting to select a second reference cell from within the reference array, the second reference cell being associated with a second operation of the memory. | 12-18-2014 |
| 20150009767 | PROGRAMMABLE LSI - A low-power programmable LSI that can perform configuration (dynamic configuration) at high speed and can quickly start is provided. The programmable LSI includes a plurality of logic elements and a memory element for storing configuration data to be input to the plurality of logic elements. The plurality of logic elements each include a configuration memory. Each of the plurality of logic elements performs different arithmetic processing and changes an electrical connection between the logic elements in accordance with the configuration data stored in the configuration memory. The memory element is formed using a storage element including a transistor whose channel is formed in an oxide semiconductor layer and a node set in a floating state when the transistor is turned off. | 01-08-2015 |
| 20150023114 | SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME - One of a source and a drain of a first oxide semiconductor (OS) transistor is connected to a gate of a second OS transistor and one electrode of a first capacitor. One of a source and a drain of the second OS transistor is connected to one electrode of a second capacitor and one of a source and a drain of a Si transistor. The gate of the second OS transistor serves as a charge retention node. Charge injection and retention at this node is controlled by the first OS transistor. The other of the source and the drain of the second OS transistor is connected to a wiring applying a high potential, and a potential of the second capacitor that corresponds to the write data is maintained. A signal corresponding to the write data is read by the Si transistor. | 01-22-2015 |
| 20150023115 | COMPENSATION SCHEME FOR NON-VOLATILE MEMORY - Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell. | 01-22-2015 |
| 20150049561 | NONVOLATILE MEMORY APPARATUS, AND SEMICONDUCTOR SYSTEM AND COMPUTER DEVICE USING THE SAME - A nonvolatile memory apparatus includes a memory cell array including a plurality of sub arrays. A plurality of analog-to-digital converters (ADCs) configured to sense sensing voltages outputted from memory cells of the plurality of sub arrays and a path selection unit configured to electrically couple the plurality of sub arrays with the plurality of ADCs in one-to-one correspondence in a first operation mode, and electrically couple the plurality of ADCs with a terminal of a power supply voltage in a second operation mode. | 02-19-2015 |
| 20150078106 | NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF OPERATION - A memory device comprises a nonvolatile memory device and a controller. The nonvolatile memory comprises a first memory area comprising single-bit memory cells and a second memory area comprising multi-bit memory cells. The controller is configured to receive a first unit of write data, determine a type of the first unit of write data, and based on the type, temporarily store the first unit of write data in the first memory area and subsequently migrate the temporarily stored first unit of write data to the second memory area or to directly store the first unit of write data in the second memory area, and is further configured to migrate a second unit of write data temporarily stored in the first memory area to the second memory area where the first unit of write data is directly stored in the second memory area. | 03-19-2015 |
| 20150078107 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device is provided. The semiconductor memory device includes a memory cell array including cell strings coupled between bit lines and a common source line, each of the cell strings comprising a plurality of memory cells stacked above a substrate. The semiconductor memory device also includes a peripheral circuit configured to supply a negative voltage to one or more word lines coupled to the cell strings and supply a positive voltage to the common source line, wherein the peripheral circuit supplies the positive voltage and the negative voltage before a program operation is performed. | 03-19-2015 |
| 20150085588 | METHOD AND APPARATUS FOR ADJUSTING DRAIN BIAS OF A MEMORY CELL WITH ADDRESSED AND NEIGHBOR BITS - The storage layer such as a nitride layer of a nonvolatile memory cell has two storage parts storing separately addressable data, typically respectively proximate to the source terminal and the drain terminal. The applied drain voltage while sensing the data of one of the storage parts depends on the data stored at the other storage part. If the data stored at the other storage part is represented by a threshold voltage exceeding a minimum threshold voltage, then the applied drain voltage is raised. This technology is useful in read operations and program verify operations to widen the threshold voltage window. | 03-26-2015 |
| 20150117123 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a memory cell array having memory cells coupled to a plurality of word lines and a peripheral circuit group configured to supply a pass voltage to unselected word lines among the plurality of word lines, wherein the peripheral circuit group stepwise raises the pass voltage supplied to the unselected word lines to a target level. | 04-30-2015 |
| 20150138899 | DATA STORAGE DEVICE AND OPERATING METHOD THEREOF - An operating method of a data storage device may include performing a first write operation on a first memory region, and performing a second write operation on a second memory region to store position information on the first write operation. | 05-21-2015 |
| 20150138900 | DATA STORAGE DEVICE AND OPERATING METHOD THEREOF - An operating method of a data storage device includes performing a read operation on a nonvolatile memory device based on a read request and a logical address from a host device, determining whether one or more physical addresses, which correspond to one or more logical addresses continuous to the logical address, are continuous to a physical address corresponding to the logical address, and prefetching data stored in a region of the nonvolatile memory device, corresponding to the one or more physical addresses, when the one or more physical addresses are determined to be continuous. | 05-21-2015 |
| 20150294696 | STABILIZING CIRCUIT - A stabilizing circuit is provided that is connected to a biased voltage. The stabilizing circuit is configured to inhibit a change in voltage of the biased voltage caused by a first change in voltage of one or more nodes that are connected to the biased voltage through a first parasitic capacitance. In some embodiments, the stabilizing circuit induces a voltage on the biased voltage through a second parasitic capacitance that changes from a first voltage level to a second voltage level during the first change in voltage such that a total change in parasitic voltage that is induced at the biased voltage during the first change in voltage is close to 0 V. | 10-15-2015 |
| 20150302902 | WRITE/READ PRIORITY BLOCKING SCHEME USING PARALLEL STATIC ADDRESS DECODE PATH - A write block read apparatus for a memory device includes a dynamic read address decoder that receives static read address bits as inputs thereto and having an output used to implement a read operation of a memory location corresponding to the read address bits; a dynamic write address decoder that receives static write address bits as inputs thereto and having an output used to implement a write operation of a memory location corresponding to the write address bits; and a static write address decoder, configured in parallel with the dynamic write address decoder, the static write address decoder configured to receive a portion of the static write address bits as inputs thereto, and wherein the static write address decoder is coupled to the dynamic read address decoder so as to block the read operation upon an address conflict with the write operation. | 10-22-2015 |
| 20150302908 | WRITE/READ PRIORITY BLOCKING SCHEME USING PARALLEL STATIC ADDRESS DECODE PATH - A method of implementing a write block read function for a memory device includes configuring a dynamic read address decoder to receive static read address bits as inputs thereto and to generate an output used to implement a read operation of a memory location corresponding to the read address bits; configuring a dynamic write address decoder to receive static write address bits as inputs thereto and to generate an output used to implement a write operation of a memory location corresponding to the write address bits; and configuring a static write address decoder, in parallel with the dynamic write address decoder, to receive a portion of the static write address bits as inputs thereto, and coupling the static write address decoder to the dynamic read address decoder so as to block the read operation upon an address conflict with the write operation. | 10-22-2015 |
| 20150303199 | MEMORY STRUCTRUE AND OPERATION METHOD THEREOF - This invention provides a memory structure and an operation method thereof. The memory structure includes a triode for alternating current (TRIAC) and a memory cell. The memory cell is electrically connected to the TRIAC. | 10-22-2015 |
| 20150332737 | MEMORY SENSING METHOD USING ONE-TIME SENSING TABLE AND ASSOCIATED MEMORY DEVICE - A memory sensing method is provided. The memory sensing method comprises the following steps: sensing a first memory unit to obtain a first sensing result; sensing a second memory unit to obtain a second sensing result; and looking up a one-time sensing table according to the first and second sensing results to obtain an output data. | 11-19-2015 |
| 20150332753 | MULTI-DIE MEMORY DEVICE - A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays. | 11-19-2015 |
| 20150357023 | PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY - The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells, sensing circuitry coupled to the array of memory cells via a sense line, and a controller coupled to the array of memory cells and the sensing circuitry. The sensing circuitry includes a sense amplifier and does not include an accumulator. The controller is configured to perform logical operations using the array of memory cells as an accumulator without transferring data out of the memory array and sensing circuitry. | 12-10-2015 |
| 20150371686 | Read Assist Techniques in a Memory Device - A memory device is provided which comprises an array of bitcells and a plurality of wordlines. Each bitcell of the array of bitcells is selectively coupled to a wordline of the plurality of wordlines and access to a selected bitcell of the array of bitcells requires an asserted voltage on a selected wordline with which the selected bitcell is associated. Read assist circuitry is provided, which is configured, when read access to the selected bitcell is carried out, to implement a reduction in the asserted voltage on the selected wordline, and wherein the read assist circuitry is configured to implement the reduction in the asserted voltage by selective connection of the selected wordline to a further wordline of the plurality of wordlines. | 12-24-2015 |
| 20150380074 | SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME - The semiconductor memory device includes a power control signal generator and a sense amplifier circuit. The power control signal generator generates a first power control signal that is enabled in response to a temperature latch signal generated in response to latching a temperature signal in a predetermined mode. The sense amplifier circuit generates a first power signal having a first drive voltage in response to the first power control signal. In addition, the sense amplifier circuit senses and amplifies a voltage level of a bit line using the first power signal as a power supply voltage. | 12-31-2015 |
| 20160005444 | DATA STORAGE DEVICE - A data storage device includes a first memory device suitable for performing an internal operation in response to a first internal operation command; and a state checking block suitable for performing a state read operation by transmitting a state read command one or more times to the first memory device during one of an initial mode and a repeat mode which is set based on a type of the internal operation. | 01-07-2016 |
| 20160005447 | INDEPENDENTLY ADDRESSABLE MEMORY ARRAY ADDRESS SPACES - Examples of the present disclosure provide devices and methods for accessing a memory array address space. An example memory array comprising a first address space comprising memory cells coupled to a first number of select lines and to a number of sense lines and a second address space comprising memory cells coupled to a second number of select lines and to the number of sense lines. The first address space is independently addressable relative to the second address space. | 01-07-2016 |
| 20160043715 | SEMICONDUCTOR DEVICE - To generate an analog current without restriction by a power supply voltage. A semiconductor device includes a first node, a second node, a first- to an n-th-stage power storage element (n is an integer greater than or equal to 2), and a first- to an n-th-stage switch. The capacities of the first- to the n-th-stage power storage element are different from one another. The first- to the n-th-stage power storage element are electrically connected in parallel between the first node and the second node. A first terminal of a k-th stage power storage element (k is an integer greater than or equal to 1 and less than or equal to n) is electrically connected to the first input node via a k-th stage switch. The on/off states of the first- to the n-th-stage switch are controlled by a first to an n-th signal. | 02-11-2016 |
| 20160064045 | APPARATUSES AND METHODS FOR STORING A DATA VALUE IN MULTIPLE COLUMNS - An example apparatus comprises an array of memory cells coupled to sensing circuitry. The apparatus can include a control component configured to cause computing of a data value equal to a logical OR between the digit of a mask and a data value stored in a memory cell located in a row at a column of the array corresponding to a digit of a vector stored in the array. The control component can cause storing of the data value equal to the logical OR in the memory cell located in the row at the column of the array corresponding to the digit of the vector. | 03-03-2016 |
| 20160071553 | BUS CIRCUITS FOR MEMORY DEVICES - Embodiments of bus circuits and related techniques are disclosed herein. In some embodiments, a bus circuit may include: a source follower arrangement, including a first transistor and a second transistor, coupled between a supply voltage and an access line of a memory cell, wherein the first transistor and the second transistor each have a gate terminal and wherein the access line is a bit line or a word line; a capacitor having a first terminal coupled to the gate terminal of the first transistor and having a second terminal coupled to a reference voltage; and a switch coupled between the first terminal of the capacitor and a voltage regulator. Other embodiments may be disclosed and/or claimed. | 03-10-2016 |
| 20160086639 | APPARATUS POWER CONTROL - The present disclosure includes apparatuses and methods for apparatus power control. A number of embodiments include determining a power profile for each of a number of commands in a command queue that are ready for execution and selecting a portion of the number of commands in the command queue for execution based on the power profiles of the number of commands to control power consumption in the apparatus. | 03-24-2016 |
| 20160093342 | PORTABLE STORAGE DEVICE THAT CAN CHECK MEMORY FREE SPACE - A portable storage device is provided with a memory part, a free space detecting part, a vibration detecting part, a reporting part, and a controller. The memory part stores data. The free space detecting part detects a free space of the memory part. The vibration detecting part detects vibration. The reporting part reports the free space. The controller performs writing and reading of data for the memory part. If vibration is detected by the vibration detecting part, the controller causes the reporting part to report corresponding to the detection result of the free space of the memory part by the free space detecting part. | 03-31-2016 |
| 20160093348 | DEVICES, METHODS, AND SYSTEMS SUPPORTING ON UNIT TERMINATION - The present disclosure includes devices, methods, and systems supporting on unit termination. A number of embodiments include a number of memory units, wherein a memory unit includes termination circuitry, and a memory unit does not include termination circuitry. | 03-31-2016 |
| 20160155482 | APPARATUSES AND METHODS FOR CONVERTING A MASK TO AN INDEX | 06-02-2016 |
| 20160169750 | SEMICONDUCTOR DEVICE HAVING TEMPERATURE SENSOR CIRCUITS | 06-16-2016 |
| 20160204746 | Sense Amplifier | 07-14-2016 |
