| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 365206000 | Noise suppression | 16 |
| 20080239850 | APPARATUS OF PROCESSING A SIGNAL IN A MEMORY DEVICE AND A CIRCUIT OF REMOVING NOISE IN THE SAME - A circuit for removing noise from an input signal includes a falling edge signal delaying circuit configured to output a first delay output signal generated by delaying a falling edge of a first output signal for a preset time; a falling edge sensing circuit configured to sense the falling edge of the first output signal, and generate a pulse signal in accordance with the sense; a flip-flop configured to output the first delay output signal in accordance with an input clock signal; and a first logic operation circuit configured to perform a logic operation on an output signal of the flip-flop and the first output signal delayed for the preset time, thereby generating a second output signal. | 10-02-2008 |
| 20090046529 | Biasing and shielding circuit for source side sensing memory - A shielding circuit for preventing a sense current of a target cell from the influence of a source current of first adjacent cell includes a pre-discharge device, first and second biasing units, first and second voltage pull-down units, and a connection units. The pre-discharge device is for setting the voltage of the sense node to a negative voltage. The first and second biasing units are for biasing the source voltage of the target and the first adjacent cell equal to a biasing voltage, respectively. The first and second voltage pull-down units are for pulling down the source voltage of the target and the first adjacent cell closing to a ground level, respectively. The connection unit is for receiving and outputting the sense current passing through the first biasing unit to the sense node. | 02-19-2009 |
| 20090080275 | REDUCING BIT LINE LEAKAGE CURRENT IN NON-VOLATILE MEMORIES - In example embodiments, methods are provided for reducing bit line leakage current. In an example embodiment, an unselected program word line is biased to a bias voltage. The unselected program word line is connected to a memory cell and the memory cell includes a plurality of transistors. In another example embodiment, an unselected memory cell is biased to a negative bias voltage during read operations. | 03-26-2009 |
| 20090116325 | ON-CHIP CHARACTERIZATION OF NOISE-MARGINS FOR MEMORY ARRAYS - A circuit, method, and computer readable medium for on-chip measuring of noise margins in a memory device memory device are disclosed. The on-chip method includes electrically coupling at least a first circuit to a memory cell. A voltage divider is electrically coupled to at least a first voltage and a second voltage. A multiplexer circuit is electrically coupled to the voltage divider. The multiplexer selects one of the first voltage and second voltage for producing a test voltage. A selecting line is electrically coupled to a force\measure network. A comparator is coupled to the force\measure network. The force-measure network supplies the test voltage to the comparator and a measured voltage to the comparator for determining when the measured voltage exceeds the test voltage. | 05-07-2009 |
| 20090161462 | CONTROLLING AC DISTURBANCE WHILE PROGRAMMING - A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation. | 06-25-2009 |
| 20090161463 | CIRCUIT PROVIDING COMPENSATED POWER FOR SENSE AMPLIFIER AND DRIVING METHOD THEREOF - The present invention discloses a circuit providing a power for a sense amplifier that stabilizes a power voltage supplied to the sense amplifier by compensating a noise generated in the power voltage when the sense amplifier operates with an selectively generated decoupling noise. The circuit providing a power for a sense amplifier includes a sense amplifying circuit sensing and amplifying data loaded on a bit line with a first power. A power supplying unit provides the first power to the sense amplifying circuit. A decoupling unit generates a decoupling noise with a second power and provides the decoupling noise to the first power voltage. The decoupling noise is maintained for a period including a time point of an operation of the sense amplifying circuit and a predetermined time thereafter. | 06-25-2009 |
| 20090168575 | DEVICE AND METHOD TO REDUCE SIMULTANEOUS SWITCHING NOISE - By reducing a cumulative number of drivers changing values during a transition, the cumulative current change may be reduced, along with the simultaneous switching noise effects. Also, a reduced cumulative current change can also reduce voltage fluctuations in ground and/or power planes of a chip, thereby minimizing potential improper logic functions due to voltage dips or spikes. In one implementation, the method includes reading values of a first state of a first set of bits of a first word and obtaining a projected value of a second state of each of the first set of bits. If the first switching noise cumulative effect can be reduced by changing the projected values of the second state of the first set of bits, an alternate set of values having at least one value differing from the projected values of the second state is determined to reduce the first switching noise cumulative effect. | 07-02-2009 |
| 20090296507 | Memory power delivery noise suppression - An operation voltage is provided to a memory system. The operation voltage provided to the memory system is adjusted during transient events of the memory system. | 12-03-2009 |
| 20100103757 | SEMICONDUCTOR DEVICE - A semiconductor device may include, but is not limited to, a first signal line, a second signal line, and a first shield line. The first signal line is supplied with a first signal. The first signal is smaller in amplitude than a potential difference between a power potential and a reference potential. The second signal line is disposed in a first side of the first signal line. The second signal line is supplied with a second signal. The second signal is smaller in amplitude than the potential difference. The first shield line is disposed in a second side of the first signal line. The second side is opposite to the first side. The first shield line reduces a coupling noise that is applied to the first shield line from the second side. | 04-29-2010 |
| 20100118632 | CIRCUITS, SYSTEMS, AND METHODS FOR REDUCING SIMULTANEOUS SWITCHING OUTPUT NOISE, POWER NOISE, OR COMBINATIONS THEREOF - Memory devices and methods are provided for reducing simultaneous switching output noise and power supply noise during burst data write and refresh operations. An embodiment of a memory device according to the present invention includes a first power domain coupled to some of the components of the memory device and a second power domain coupled to different components of the memory device. One or more distributed power domain coupling circuits may be coupled to the first and second power domains. The power domain coupling circuit includes a controller configured to generate an enable signal responsive to control signals, data signals, or any combination thereof. The power domain coupling circuit also includes coupling circuitry coupled to the first and second power domains and coupled to the controller. The coupling circuitry is configured to couple the first and second power domains together responsive to the enable signal. | 05-13-2010 |
| 20100214860 | SENSE AMPLIFIER SCHEME FOR LOW VOLTAGE SRAM AND REGISTER FILES - A sense amplifier scheme for SRAM is disclosed. In accordance with one of the embodiments of the present application, a sense amplifier circuit includes a bit line, a sense amplifier output, a power supply node having a power supply voltage, a keeper circuit including an NMOS transistor, and a noise threshold control circuit. The keeper circuit is sized to supply sufficient current to compensate a leakage current of the bit line and maintains a voltage level of the bit line and the noise threshold control circuit lowers a trip point of the sense amplifier output. | 08-26-2010 |
| 20100290301 | MEMORY ARRAY INCORPORATING NOISE DETECTION LINE - A memory array includes a sensing circuit for sensing bit line current while keeping the voltage of the selected bit line substantially unchanged. The word lines and bit lines are biased so that essentially no bias voltage is impressed across half-selected memory cells, which substantially eliminates leakage current through half-selected memory cells. The bit line current which is sensed arises largely from only the current through the selected memory cell. A noise detection line in the memory array reduces the effect of coupling from unselected word lines to the selected bit line. In a preferred embodiment, a three-dimensional memory array having a plurality of rail-stacks forming bit lines on more than one layer, includes at least one noise detection line associated with each layer of bit lines. A sensing circuit is connected to a selected bit line and to its associated noise detection line. | 11-18-2010 |
| 20110158022 | SEMICONDUCTOR MEMORY DEVICE HAVING A REDUCED NOISE INTERFERENCE - A semiconductor memory device having a reduced noise interference is presented. The semiconductor memory device includes a first switch and a second switch. The first switch is disposed in a sub hole region or an edge region and is configured to be turned on in response to a first pre-control signal, which is enabled before a time point at which a sense amplifier array begins to operate, and to apply an external voltage to a first voltage line through which a bias voltage is supplied to the sense amplifier array. The second switch is configured to be turned on in response to a first control signal, which is enabled in a sense amplifier overdriving period, and to apply the external voltage to the first voltage line. | 06-30-2011 |
| 20130128680 | READ ASSIST CIRCUIT FOR AN SRAM - A memory circuit includes a bit cell that receives a word line, complementary bit lines and an array supply voltage; a word line driver coupled to the word line, the word line driver receiving one of the array supply voltage and a periphery supply voltage; and a word line suppression circuit coupled to the word line. The word line suppression circuit includes a diode and a switch coupled in series. The switch is responsive to the array supply voltage. The word line suppression circuit limits a word line voltage to a value lower than the array supply voltage such that the static noise margin (SNM) of the bit cell is increased. | 05-23-2013 |
| 20130194885 | SPURIOUS INDUCED CHARGE CLEANUP FOR ONE TIME PROGRAMMABLE (OTP) MEMORY - A high density, low voltage, and low-power one time programmable (OTP) memory is based on core cells with a one transistor design. A CLEAN pulse is directed to a single shunt device at the output of the column decoder so spurious charges that may have been stored in the floating nodes can be cleaned up. Such arrangement also allows for the simultaneous initialization of bit lines, data lines, and sensing lines to zero. Core area layout size is substantially reduced, and operational power requirements are exceeding low making these particularly suitable in HF and UHF RFID applications. | 08-01-2013 |
| 20140241089 | READ ASSIST CIRCUIT FOR AN SRAM TECHNICAL FIELD - A memory circuit includes a bit cell that receives a word line, complementary bit lines and an array supply voltage; a word line driver coupled to the word line, the word line driver receiving one of the array supply voltage and a periphery supply voltage; and a word line suppression circuit coupled to the word line. The word line suppression circuit includes a diode and a switch coupled in series. The switch is responsive to the array supply voltage. The word line suppression circuit limits a word line voltage to a value lower than the array supply voltage such that the static noise margin (SNM) of the bit cell is increased. | 08-28-2014 |
