Entries |
Document | Title | Date |
20080198672 | Power Supply Control Circuit and Controlling Method Thereof - The present invention provides a power supply control circuit and a control method thereof, capable of securing an accurate operation of a GIO in a burst data transmission having a high compression rate. The power supply control circuit of a semiconductor memory device includes: a counter which is reset in response to a read command signal or a write command signal to count an input clock and then, to output a counting completion signal; and a power supply enable signal generator enabled in response to the read command signal or the write command signal and disabled in response to the counting completion signal, for generating a power supply enable signal. | 08-21-2008 |
20080205167 | Voltage generator for nonvolatile memory and writing and erasing method of nonvolatile memory - A voltage generator for nonvolatile memory that generates an applied voltage to be applied to a nonvolatile memory includes a first voltage generator to generate a first voltage corresponding to the applied voltage, a reference voltage generator to generate a reference voltage, a comparator to compare the first voltage with the reference voltage and output a boost operation control signal according to a comparison result, and a booster to generate the applied voltage in a pulse-like voltage waveform by starting or stopping boost operation based on the boost operation control signal. The applied voltage corresponding to the first voltage upon inversion of the boost operation control signal is varied within one pulse-like voltage waveform by varying one of the first voltage and the reference voltage. | 08-28-2008 |
20080212381 | Voltage generating circuits for semiconductor memory devices and methods for the same - In a voltage generating circuit for a semiconductor memory device, each of a plurality of reset signal generators individually generates a reset signal in response to one of a plurality of external source voltages. The plurality of external source voltages have different voltage levels. An output voltage generator generates a plurality of output voltages by independently driving each of the plurality of external source voltages in response to a corresponding one of the plurality of reset signals. The output voltage generator outputs the plurality of output voltages through a common output terminal. | 09-04-2008 |
20080219061 | APPARATUS AND METHOD FOR DETECTING LEAKAGE CURRENT OF SEMICONDUCTOR MEMORY DEVICE, AND INTERNAL VOLTAGE GENERATING CIRCUIT USING THE SAME - A semiconductor memory device is capable of generating a back bias voltage based on a target level changed according to a leakage current of the semiconductor memory devices, thereby minimizing the amount of the leakage current. The semiconductor memory device includes a leakage current detector and a back bias voltage generator. The leakage current detector is configured to detect a leakage current of a cell array. The back bias voltage generator is configured to generate a back bias voltage having a target level changed according to the leakage current. | 09-11-2008 |
20080219062 | SEMICONDUCTOR MEMORY DEVICE - In one embodiment, a semiconductor memory device includes a plurality of pairs of bit lines, each of the pairs including a first bit line, a second bit line, a memory cell coupled to the first bit line, a sense amplifier determining the logical value stored in the memory cell according to a potential difference between the first and the second bit line, a reference voltage generation circuit, and a reference voltage supply switch coupling an output of the reference voltage generation circuit to the second bit line. | 09-11-2008 |
20080225609 | VOLTAGE GENERATING CIRCUIT AND REFERENCE VOLTAGE GENERATING CIRCUIT FOR SEMICONDUCTOR MEMORY APPARATUS, AND SEMICONDUCTOR SYSTEM USING THE SAME - A voltage generating circuit for a semiconductor memory apparatus according includes a data logic voltage generating unit that, when a data output unit outside a semiconductor memory apparatus outputs low-level data, generates an internal data logic voltage at the same potential level as the low-level data in response to an on-die termination signal. In addition, a reference voltage generating circuit for a semiconductor memory apparatus that uses the voltage generating circuit includes a reference voltage generating unit that can be configured to generate a reference voltage at an average potential level between a maximum potential and a minimum potential of input data. | 09-18-2008 |
20080232174 | Interleaving Charge Pumps for Programmable Memories - Systems and methods, including computer software for performing operations enable interleaving of charging operations in a charging pump. A first charge pump is charged to a predetermined level, and a first operation is performed using a charge stored in the first charge pump after it reaches the predetermined level. A second charge pump is charged during a time that overlaps with performing the first operation. A second operation is performed using a charge stored in the second charge pump as a result of charging the second charge pump. | 09-25-2008 |
20080239836 | Method for Managing Electrical Load of an Electronic Device - Methods and apparatus for managing electrical loads of electronic devices are disclosed. According to one embodiment, a current load imposed by an electronic device, such as a memory device (or memory system), can be measured. Then, using the measured current load, the memory device can determine whether (and to what extent) operational performance should be limited. By limiting operational performance, the memory device is able to limit its current load so as to satisfy a specification criterion or other requirement. The electrical load management is well suited for use in portable memory products (e.g., memory cards) to manage current loads being drawn. | 10-02-2008 |
20080239837 | SEMICONDUCTOR DEVICE - A semiconductor memory device includes a boosting circuit which boosts in a second voltage higher than an external power supply by using a first voltage as a reference voltage, and a bandgap reference circuit which operates by using the second voltage generated by the boosting circuit as a power supply voltage. | 10-02-2008 |
20080239838 | Semiconductor memory device for reducing power consumption - A semiconductor memory device which includes: a voltage supplying unit for outputting a power source voltage as a driving source signal during a predetermined time, and then outputting a high voltage as the driving source signal in response to a driving control signal activated in response to an address signal; and a word line control unit for activating a word line at a voltage level of the driving source signal in response to the driving control signal. | 10-02-2008 |
20080253202 | Communicating Information Using an Existing Light Source of an Electronic Device - An electronic device | 10-16-2008 |
20080279019 | SEMICONDUCTOR DEVICE - A semiconductor includes a first sensor amplifier, a second sensor amplifier, a first switch and a second switch. The first sensor amplifier is coupled between a local data line and a memory unit to amplify signals of the memory unit. The second sensor amplifier is coupled to a middle data line to amplify signals of the middle data line. The first switch is coupled between the middle data line and the local data line to equalize voltage levels between the middle data line and the local data line by turning on the first switch according to a data control signal. The second switch is coupled between the local data line and a reference voltage to equalize the local data line to the voltage level of the reference voltage by turning on the second switch according to a local data control signal. | 11-13-2008 |
20080285357 | 1-TRANSISTOR TYPE DRAM CELL, DRAM DEVICE AND DRAM COMPRISING THEREOF AND DRIVING METHOD THEREOF AND MANUFACTURING METHOD THEREOF - The present invention relates to a semiconductor device, and more precisely to an 1-transistor type DRAM cell implemented using bulk silicon, a DRAM device and a DRAM comprising thereof and a driving method thereof and a manufacturing method thereof. The driving method of an 1-transistor type DRAM comprises: a data hold process biasing a word line at a negative voltage level and biasing a sensing line and a bit line at a first constant voltage level; a data purging process resetting data by biasing the word line at a second constant voltage level and biasing the sensing line and the bit line at the first constant voltage level; and a data write process allowing a write current to be flowed from the bit line to a floating body by raising the bit line to the second constant voltage level and raising the sensing line to the half second constant voltage level, while maintaining the bias of the word line at the second constant voltage level. | 11-20-2008 |
20080285358 | Method and circuit for stressing upper level interconnects in semiconductor devices - A device or method for effectively stressing an interconnect in a current path of a semiconductor device. A bidirectional current is established across the current path, which stresses the interconnect therein. | 11-20-2008 |
20080291750 | Semiconductor device that uses a plurality of source voltages - A semiconductor device includes a first memory; and a voltage adjusting portion configured to receive a first voltage, a second voltage higher than the first voltage, and a third voltage higher than the second voltage. The first memory includes: a memory cell configured to be connected to a word line and a bit line, a word-line driving circuit configured to drive the word line, and a sense amplifier configured to sense information stored in the memory cell. The voltage adjusting portion includes: a voltage modifying circuit configured to step down or boost up the third voltage at a predetermined mode to generate a fourth voltage higher than the second voltage, and supply the fourth voltage to the sense amplifier or the word-line driving circuit. | 11-27-2008 |
20080298139 | Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and /or controlling same - A method of generating a voltage as well as an integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each memory cell array including (i) a plurality of memory cells, arranged in a matrix of rows and columns, and (ii) a plurality of bit lines, wherein each bit line includes a plurality of memory cells. The integrated circuit further includes voltage generation circuitry, coupled to a plurality of the bit lines, to (i) apply a first voltage to a first group of associated bit lines, and (ii) apply a second voltage to a second group of associated bit lines, and (iii) generate a third voltage by connecting the first group of associated bit lines and the second group of associated bit lines, and (iv) output the third voltage. Also, disclosed is a method of operation and/or control of such an integrated circuit device as well as such voltage generation circuitry. | 12-04-2008 |
20090003088 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is capable of measuring internal voltages via a shared pad to reduce a chip size. The semiconductor memory device includes a selector and a monitoring pad. The selector is configured to select one of a plurality of internal signals in response to a test signal and output the selected internal signal. The monitoring pad is configured to output an output signal of the selector to an outside of the semiconductor memory device. | 01-01-2009 |
20090003089 | Semiconductor memory device having input device - A semiconductor memory device includes a pad for receiving an external signal through a first external pin, a reference voltage pad for receiving an external reference voltage through a second external pin, an internal reference voltage generator configured to generate an internal reference voltage using an external voltage in response to a reference voltage select signal, a reference voltage supply unit for generating the reference voltage select signal in response to a plurality of select signals, and selecting one reference voltage between the external reference voltage and the internal reference voltage to output the selected one as a reference voltage, a buffer for converting an output signal of the pad into an internal voltage level on the basis of the reference voltage, and a signal selector for controlling an internal signal to be inputted/outputted through the reference voltage pad in response to the plurality of select signals. | 01-01-2009 |
20090010078 | Semiconductor memory device - A semiconductor memory device includes: an input pad set configured to receive an external input signal and a reference voltage; an input buffer set configured to detect and transmit the input signal to an internal circuit of the semiconductor memory device by comparing the input signal with the reference voltage; and a reference voltage generation circuit configured to generate the reference voltage to supply the reference voltage to the input pad set and the input buffer set during a test operation, the reference voltage generation circuit being deactivated after the semiconductor memory device is packaged. | 01-08-2009 |
20090010079 | One-transistor type dram - A one-transistor type DRAM includes a floating body storage element connected between a bit line and a source line and controlled by a word line. The DRAM comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a plurality of reference bit lines arranged in a column direction, a cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a reference cell array including the floating body storage element, formed in a region where the source line, the word line and the bit line are crossed and configured to output a reference current having a plurality of levels, a plurality of reference voltage generating units connected to the reference bit lines and configured to generate a plurality of reference voltages corresponding to the reference current having a plurality of levels, and a sense amplifier and a write driving unit connected to the bit line and configured to receive the plurality of reference voltages. | 01-08-2009 |
20090010080 | SEMICONDUCTOR MEMORY DEVICE, AND METHOD OF CONTROLLING THE SAME - An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells. | 01-08-2009 |
20090016121 | SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREOF - When a predetermined code is set to a mode register, a switching signal generating circuit is activated, and a switching signal TCLKE becomes at a high level. When the switching signal TCLKE becomes at a high level, input data supplied from a data input and output terminal DQ is used as an internal clock ICLK. Accordingly, during a test in a wafer state, a clock signal can be received from the data input and output terminal DQ, even when a clock terminal, an address terminal, and a command terminal are connected in common to plural semiconductor memory devices. Therefore, a code for artificially performing a fine adjustment of a reference voltage can be individually supplied for each chip. | 01-15-2009 |
20090021989 | PROGRAMMABLE BIAS FOR A MEMORY ARRAY - A method determines a body bias for a memory cell. A supply voltage is applied to the memory cell and a bit line is precharged to a voltage lower than the supply voltage. A programmable bias voltage circuit provides a bias voltage to the memory cell in response to values on its input. Initial test values for the input are used. The memory cell is tested to determine a pass or a fail condition of the memory cell. The initial values are retained as the input values if the memory cell passes. If the memory cell fails, the memory cell is tested at changed values for the input. If the changed input values result in the memory cell being in a pass condition, the programmable bias voltage circuit is configured, in non-volatile fashion, to have the changed input values. | 01-22-2009 |
20090027975 | METHOD FOR DRIVING PHASE CHANGE MEMORY DEVICE - A method is disclosed for driving a phase change memory device including a phase change resistor. The method includes applying a trigger voltage to the phase change resistor for a first write time to preheat the phase change resistor, applying a first write voltage to the phase change resistor for a second write time to control a first state of the phase change resistor, and applying a second voltage to the phase change resistor for a third write time to control a second state of the phase change resistor. | 01-29-2009 |
20090046519 | METHOD, DEVICE AND SYSTEM FOR CONFIGURING A STATIC RANDOM ACCESS MEMORY CELL FOR IMPROVED PERFORMANCE - A computer-implemented method of configuring a static random access memory (SRAM) bit cell for operation, an adaptive biasing device and semiconductor wafer testing system. In one embodiment, the method includes: (1) determining a performance characteristic of the SRAM bit cell on a wafer, (2) comparing the performance characteristic to a target and (3) configuring biasing circuitry associated with the SRAM bit cell based on the comparing. | 02-19-2009 |
20090059685 | SRAM BIAS FOR READ AND WRITE - An integrated circuit includes a SRAM array including a plurality of SRAM cells arranged in a plurality of rows and columns and having a plurality of word lines and bit lines for accessing rows and columns of cells. A power supply controller has an input operable for receiving an operation signal indicative of whether the array is in a read or write operation. The power supply controller is operable to provide a variable low voltage for the array (VSSM) coupled to a low voltage supply terminal of the array. A level of the VSSM is based on the operation signal, wherein VSSM is at a lower level when in the read operation than when in the write operation. A high voltage supply for said array (VDDM) coupled to a high voltage supply terminal for the array is biased above a word line voltage (VWL) level in the read operation. | 03-05-2009 |
20090067263 | CORE VOLTAGE DISCHARGE DRIVER - A core voltage discharge driver prevents a core voltage discharging operation from interrupting the core voltage generating operation. The core voltage discharge driver includes a comparing unit configured to compare a core voltage generating control signal for controlling generation of a core voltage with a core voltage discharging control signal for controlling discharge of the core voltage, and an adjusting unit configured to adjust the core voltage discharging control signal based on a comparison result of the comparing unit. | 03-12-2009 |
20090073781 | Sense Amplifier - A single ended sense amplifier circuit is disclosed that is operable to measure a state of a memory cell. The amplifier can track and compensate for variations in cell current via feedback to maintain precision. The amplifier can be used with low supply voltages while still providing high-speed operation. | 03-19-2009 |
20090073782 | SYSTEM, APPARATUS, AND METHOD TO INCREASE READ AND WRITE STABILITY OF SCALED SRAM MEMORY CELLS - Circuits, systems, and methods are disclosed for SRAM memories. An SRAM includes memory cells wherein read stability and write stability can be modified by adjusting a well bias signal operably coupled to an N-well of the memory cell. The well bias signal is generated at VDD or at a bias offset from VDD for both the read and the write operations. The memory cells may be adjusted for operation by designing the memory device to be stable relative to local parameter variations with a well bias substantially equal to VDD. The memory cells are then tested for stable read operations and stable write operations. If the write operations are unstable or the read operations are unstable, the well bias is modified and the memory cells are tested again. | 03-19-2009 |
20090080266 | DOUBLE DATA RATE (DDR) LOW POWER IDLE MODE THROUGH REFERENCE OFFSET - Embodiments of the invention are generally directed to systems, methods, and apparatuses for a double data rate (DDR) low power idle mode through reference offset. In some embodiments, a host offsets a reference voltage from a termination voltage of a command/address interconnect when the interconnect is tri-stated. Other embodiments are described and claimed. | 03-26-2009 |
20090080267 | Generating reference currents compensated for process variation in non-volatile memories - In a current reference generator device, a voltage reference generator stage generates a reference voltage (V | 03-26-2009 |
20090086554 | System and Method for Operating a Semiconductor Memory - A method for operating a semiconductor memory cell is disclosed. A first voltage is applied to the memory cell. The first voltage is dependent on temperature and semiconductor process variation in a manner that keeps the memory cell in a stable region of operation. | 04-02-2009 |
20090086555 | VOLTAGE SUPPLY CIRCUIT AND SEMICONDUCTOR MEMORY - Each of first and second differential amplifiers has a function of increasing a bias current in response to the activation of a drivability control signal. A first driving circuit connects an output node to a high power supply line in response to the activation of an output signal of the first differential amplifier, and connects the output node to a low power supply line in response to the activation of an output signal of the second differential amplifier. Only during the activation period of the drivability control signal, a second driving circuit connects the output node to the high power supply line in response to the activation of the output signal of the first differential amplifier, and connects the output node to the low power supply line in response to the activation of the output signal of the second differential amplifier. | 04-02-2009 |
20090091988 | Writing bit alterable memories - A bit alterable memory may include current generators in a periphery outside the main memory core. Current may be generated in the periphery and driven into the core. As a result, the capacitance of the memory cells has a lowered effect. The current may be generated using the chip supply voltage and then mirrored using a pump voltage. In some embodiments, the mirroring may be ratioed at the partition level and multiplied at the plane level. A delay may be provided before applying the currents to the cell to accommodate for transients. | 04-09-2009 |
20090091989 | SEMICONDUCTOR MEMORY DEVICE AND BIASING METHOD THEREOF - The present invention relates to a semiconductor memory device, and more precisely to a semiconductor memory device which controls the voltage supplied to a dummy bit line and a biasing method thereof. The semiconductor memory device includes: a dummy bit line disposed in a cell array; and a switching unit which switches the supply of a bias voltage to the dummy bit line by a control signal related to an operation of the cell array. | 04-09-2009 |
20090097333 | Semiconductor memory device with internal voltage generating circuit and method for operating the same - Semiconductor memory device with internal voltage generating circuit and method for operating the same includes a high voltage detecting circuit configured to detect a voltage level of a high voltage and activate a pumping determining signal when the voltage level of the high voltage is below a predetermined level; a pumping circuit configured to perform a pumping operation in response to the pumping determining signal and an active signal; and an auxiliary pumping circuit configured to perform the pumping operation in response to the pumping determining signal and a bank active pulse signal. | 04-16-2009 |
20090103377 | ACCESS UNIT FOR A STATIC RANDOM ACCESS MEMORY - An access unit for a static random access memory (SRAM) is provided. The access unit comprises two inverters. Two different variable voltages are supplied to the two inverters via bitlines to cause an imbalance in the current strengths between the two inverters so that data can be written on the SRAM. | 04-23-2009 |
20090109764 | INTEGRATED CIRCUIT HAVING SUPPLY VOLTAGE CONTROLLER - An integrated circuit includes a supply voltage controller operable to receive a plurality of control signals and at least one circuit supply voltage and to output at least one variable supply voltage to at least one supply terminal of the integrated circuit The controller is operable to switch the variable supply voltage to a first voltage level when the control signals define a first operation and to a second voltage level different from the first voltage level when the control signals define a second operation. The controller is also operable to float the variable supply voltage to a third voltage level different from the first voltage level when the control signals define a third operation. | 04-30-2009 |
20090116304 | Wordline driving circuit of semiconductor memory device - Wordline driving circuit of semiconductor memory device includes a bias generator configured to generate a threshold bias voltage for accessing data, an over-driver configured to increase the threshold bias voltage at an initial stage of a data accessing operation and a wordline driver configured to activate a wordline in response to the threshold bias voltage and a signal output from the over-driver. | 05-07-2009 |
20090116305 | WORD LINE DRIVER AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SAME - A word line driver for use in a semiconductor memory device includes a boosted voltage generator, a sub word line driver and a main word line driver. The boosted voltage generator generates a boosted voltage by receiving an internal power supply voltage and pumping electric charge. The sub word line driver receives the internal power supply voltage and activates a boosted voltage control signal after supplying the internal power supply voltage to a boost node in a command operating mode. The main word line driver enables a word line by supplying the boosted voltage to the boost node in response to the boosted voltage control signal in a normal operating mode, and enables the word line with the boosted voltage after boosting the word line to the internal power supply voltage by changing the boost node from the internal power supply voltage to the boosted voltage in the command operating mode. | 05-07-2009 |
20090116306 | DELAY LOCKED LOOP CIRCUIT OF SEMICONDUCTOR DEVICE - A semiconductor memory device includes a delay locked loop circuit that can control input/output timing of data according to a system clock of a high frequency. The semiconductor memory device includes a phase comparator configured to detect a phase difference between an internal clock and a reference clock to output a state signal having a pulse width corresponding to the detected phase difference, a phase adjuster configured to generate a digital code for determining a delay time corresponding to the state signal for locking a phase of the internal clock, a digital-to-analog converter configured to convert the digital code to an analog voltage, and a multiphase delay signal generator configured to delay the internal clock according to a bias voltage corresponding to the analog voltage to feed back the delayed internal clock as the internal clock and generate multiphase delay signals. | 05-07-2009 |
20090129175 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device precharging a bit line pair to a ground potential includes a sense amplifier connected between the bit line pair, a storage cell connected to one of the bit line pair and storing data, a first transistor controlling a conduction state between the other of the bit line pair and a reference cell node, a second transistor connected between a reference voltage source generating a reference voltage and the reference cell node, the second transistor exclusively controlled from the first transistor, and a capacitor setting a potential of the reference cell node. | 05-21-2009 |
20090135661 | Controlling power supply to memory cells - A semiconductor memory storage cell and a memory comprising an array of these storage cells is disclosed. The storage cell comprising: a feedback loop comprising two devices for storing opposite binary values; data input and output for inputting data to and outputting data from said two devices; and each of said two devices comprising a power source input, such that each device can be powered independently of the other. | 05-28-2009 |
20090135662 | MEMORY DEVICE - A memory device includes a power supply line, a memory cell, a memory cell power supply node provided between the memory cell and the power supply line, a first voltage generating circuit coupled to the memory cell power supply node for supplying the memory cell power supply node with a first potential lower than a potential of the power supply line for a first period corresponding to at least a part of a writing operation period, and a second voltage generating circuit that is coupled to the memory cell power supply node for supplying the memory cell power supply node with a second potential lower than the potential of the power supply line for a second period corresponding to at least a part of the writing operation period. | 05-28-2009 |
20090147594 | VOLTAGE REGULATOR FOR SEMICONDUCTOR MEMORY - A voltage regulator in a semiconductor memory has: a comparing unit including first and second bias current sources, for comparing an output voltage with first and second reference voltages under control of a first signal, the second bias current source being ON under control of a second signal; and a driver active element, coupled to the comparing unit, for outputting the output voltage. Before sensing operations, the output voltage is reset to the second reference voltage. During the sensing operations, the output voltage is maintained at the first reference voltage and the second signal is asserted for turning ON the second bias current source for raising speed of the comparing unit. After the sensing operations, the output voltage is reset to the second reference voltage. | 06-11-2009 |
20090147595 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes: a memory cell array composed of electrically rewritable memory cells; an internal voltage generating circuit having a boosting circuit for generating a voltage boosted from a supply voltage, and a voltage detecting circuit for detecting an output voltage of the boosting circuit as a monitor voltage and controlling on/off of the boosting circuit for holding the output voltage of the boosting circuit at a specified level, the internal voltage generating circuit outputting the output voltage of the boosting circuit as an internal voltage; a control circuit for controlling the internal voltage generating circuit; and a writing circuit for applying the internal voltage to the memory cell as a writing voltage when writing data into the memory cell, wherein the control circuit controls the internal voltage to a first voltage necessary for writing data into the memory cell when writing data into the memory cell, and to a second voltage lower than the first voltage in a write verify operation following the data write operation. | 06-11-2009 |
20090154258 | FLOATING BODY CONTROL IN SOI DRAM - A system including a DRAM memory device on an integrated circuit (IC) using a control logic device to initiate a body refresh operation to provide a means for maintaining a low voltage at a floating body and discourage data loss, and a design structure including the DRAM memory device embodied in a machine readable medium is provided. A plurality of DRAM cells are connected to a first word line circuit and a first bit line circuit. The control logic device is coupled to the DRAM memory device and the IC for initiating the body refresh cycle. The control logic communicates with a first bit line and word line circuits and communicates with a reference word line and bit line circuits. A sense amplifier circuit and signal is provided for amplifying the voltage at the first bit line and the reference bit line. The body refresh cycle includes deactivating the first word line voltage while the first bit line and reference bit line voltages continue. | 06-18-2009 |
20090154259 | Swapped-Body RAM Architecture - A method for operating an SRAM cell comprises, during a read operation, forward biasing an N-well of a first and second pull-up transistor, and forward biasing a P-well of a first and second pull-down transistor and a first and second access transistor. The method further comprises, during a write operation, zero or reverse biasing an N-well of a first and second pull-up transistor, and forward biasing a P-well of a first and second pull-down transistor and a first and second access transistor. The method further comprises, during an idle state, zero biasing an N-well of a first and second pull-up transistor and zero biasing a P-well of a first and second pull-down transistor and a first and second access transistor. In addition, one or more rows or columns of memory cells may receive a bias voltage. | 06-18-2009 |
20090168554 | LOW COUPLE EFFECT BIT-LINE VOLTAGE GENERATOR - A bit-line voltage generator is provided. The bit-line voltage generator includes a discharge enhanced bias source and a switch unit. The switch unit includes a clamp transistor having a source, a gate connected to the discharge enhanced bias source, and a drain receiving a voltage; a switch transistor having a gate receiving a control signal, a drain connected to the source of the clamp transistor, and a source connected to a memory array, wherein a parasitic capacitor exists between the gate and the source of the clamp transistor; a resistor having a first terminal connected to the drain of the switch transistor, and a second terminal connected to ground; and a capacitor having a first terminal connected to the drain of the switch transistor, and a second terminal connected to ground, wherein a charge in the parasitic capacitor, when the switch transistor is turned on, is almost identical to that when the switch transistor is turned off, so that a couple effect between the switch unit and the discharge enhanced bias source is reduced, thereby stabilizing a bias applied to the memory array. | 07-02-2009 |
20090168555 | Delay circuit and semiconductor memory device having the same - A delay circuit is capable of securing a constant delay time in spite of a process variation as well as voltage and temperature variations. Using the delay circuit that secures a sensing margin time in spite of process, voltage and temperature variations, a semiconductor memory device is capable of amplifying desired data within a preset RAS to CAS delay (tRCD). The delay circuit includes a delay unit including a current source controlled by a bias voltage, a delay time of the delay unit being changed depending on current amount of the current source, and a bias voltage generating unit configured to divide a power supply voltage using a first resistor to generate the bias voltage, wherein the delay unit includes a second resistor inserted into a current path of the current source. | 07-02-2009 |
20090168556 | SEMICONDUCTOR MEMORY DEVICE FOR GENERATING BACK-BIAS VOLTAGE WITH VARIABLE DRIVING FORCE - A semiconductor memory device is capable of maintaining a predetermined back-bias voltage level regardless of operation modes of the semiconductor memory device, by generating a back-bias voltage with driving force changed according to the operation modes. The semiconductor memory device includes an active pumping control signal generating unit for generating an active pumping control signal in response to a plurality of active signals, a voltage detecting unit for detecting a voltage level of a back-bias voltage terminal to output a detection signal, an oscillator for generating an oscillation signal oscillating at a predetermined frequency in response to the detection signal, and a charge pumping unit for performing a charge pumping operation in response to the oscillation signal by controlling a force of driving the back-bias voltage terminal in response to the active pumping control signal. | 07-02-2009 |
20090175095 | VOLTAGE SENSING CIRCUIT AND METHOD FOR OPERATING THE SAME - A voltage sensing circuit is capable of controlling a pumping voltage to be stably generated in a low voltage environment. The voltage sensing circuit includes a current mirror having first and second terminals, a first switching element configured to control current on the first terminal of the current mirror by a reference voltage, a second switching element configured to control current from the second terminal of the current mirror in response to a pumping voltage, and a third switching element configured to control current sources of the first and second switching elements to receive a negative voltage. | 07-09-2009 |
20090190413 | SELF-REPAIR INTEGRATED CIRCUIT AND REPAIR METHOD - A method for repairing degraded field effect transistors includes forward biasing PN junctions of one of a source and a drain of a field effect transistor (FET), and a body of the FET. Charge is injected from a substrate to a gate region to neutralize charge in the gate region. The method is applicable to CMOS devices. Repair circuits are disclosed for implementing the repairs. | 07-30-2009 |
20090190414 | SEMICONDUCTOR DEVICE - A semiconductor device includes a mode register and a plurality of voltage generators in connection with a plurality of banks. Based on an operation mode set to the mode register, the voltage generators are selectively driven in response to an access to each bank and a CAS latency number defining a delay time between the input timing of an external command and the input/output timing of data of each bank. The number of voltage generators being driven is controlled based on the CAS latency number so that an adequate internal voltage is supplied to the peripheral circuitry, thus adjusting the current consumption without increasing the power consumption. | 07-30-2009 |
20090207674 | DEVICE AND METHOD GENERATING INTERNAL VOLTAGE IN SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device and a method of generating an internal voltage in the semiconductor memory device are provided. The semiconductor memory device includes a controller configured to activate a sensing enable signal when an active command is applied from outside, inactivate the sensing enable signal when a precharge command is applied, and output the sensing enable signal, and an array internal voltage generator configured to output an active array power supply voltage as an array power supply voltage when the sensing enable signal is activated, output an external array power supply voltage and a standby array power supply voltage as the array power supply voltage when the sensing enable signal is inactivated, and output the standby array power supply voltage alone as the array power supply voltage when the sensing enable signal is inactivated for at least a specific period. | 08-20-2009 |
20090213666 | LOW VOLTAGE OPERATION BIAS CURRENT GENERATION CIRCUIT - Devices and systems for generating a bias current with a low minimum voltage, for example, are disclosed. One such device includes a first transistor having a source coupled to a voltage supply, a drain coupled to a first node, and a gate coupled to a second node, a second transistor having a source coupled to a reference, and a drain and a gate coupled to the first node, a third transistor having a source coupled to the reference, a drain coupled to a third node, and a gate coupled to the first node, a first resistive element coupled between the voltage supply and the third node, a second resistive element coupled between the voltage supply and the second node, and a fourth transistor having a source coupled to the reference, a drain coupled to the second node, and a gate coupled to the third node. | 08-27-2009 |
20090213667 | SEMICONDUCTOR MEMORY DEVICE ENHANCING RELIABILITY IN DATA READING - An internal voltage generating circuit generates and supplies a boosted voltage higher than an internal power supply voltage, as an operating power supply voltage, to a sense amplifier in a read circuit for reading data of a memory cell. A bit line precharge current supplied via an internal data line is produced from the internal power supply voltage. It is possible to provide a nonvolatile semiconductor memory device, which can perform a precise sense operation and an accurate reading of data even under a low power supply voltage condition. | 08-27-2009 |
20090219766 | APPARATUS, SYSTEM, AND METHOD FOR ADJUSTING MEMORY HOLD TIME - An apparatus, system, and method are disclosed for adjusting memory hold time. A detection module detects a hold time violation for a memory. An adjustment module increases a first voltage of a voltage controller in response to the hold time violation. The voltage controller supplies electrical current at the first voltage to a memory controller and at a reference voltage to the memory. The first and reference voltages are set independently. | 09-03-2009 |
20090219767 | PRE-CHARGE VOLTAGE GENERATION AND POWER SAVING MODES - A system includes a voltage generator to produce a pre-charge voltage signal for pre-charging one or more signals in a memory circuit. The one or more signals can be data bus lines used to access memory. The voltage generator can include an input indicating whether the memory circuit is set to a power-saving mode. According to one embodiment, the input adjusts a magnitude of the pre-charge voltage signal produced by the voltage generator. Such an embodiment is useful over conventional methods because adjusting the pre-charge voltage can result in power savings. As an example, when in the power-saving mode, the voltage generator circuit can adjust the pre-charge voltage to a value that reduces an amount of leakage current associated with a pre-charge voltage. Reducing the leakage with respect to the pre-charge voltage means that the saved power can be used for other useful purposes. | 09-03-2009 |
20090238011 | VCC CONTROL INSIDE DATA REGISTER OF MEMORY DEVICE - A memory device including current-limiting circuitry coupled to a first inverter inside a data register is provided. The current-limiting circuitry controls a voltage supplied to the first inverter and a reference voltage may be adjusted so that the voltage supplied to the first inverter is prevented from dropping below a voltage supplied to a second inverter inside the data register. The memory device may include a switch to allow coupling to the current-limiting circuitry for programming of the memory device. | 09-24-2009 |
20090257287 | PROGRAMMABLE BIAS CIRCUIT ARCHITECTURE FOR A DIGITAL DATA/CLOCK RECEIVER - Receiver architectures and related bias circuits for a data processor are provided. One embodiment of a receiver architecture for a computer processor includes a first linear receiver stage configured to receive a first input, a second input, and a first bias voltage. The first linear receiver stage is configured to generate a first differential output signal in response to a comparison between the first input and the second input. The first differential output signal has a specified programmable voltage swing that is influenced by the first bias voltage. The receiver architecture also includes a first programmable bias circuit coupled to the first linear receiver stage. The first programmable bias circuit is configured to generate the first bias voltage. | 10-15-2009 |
20090257288 | APPARATUS AND METHOD FOR INCREASING DATA LINE NOISE TOLERANCE - Circuits and methods for improving noise tolerance in memories are disclosed such as those that include biasing a data line above a normal threshold voltage, either by providing a higher data line charge voltage with a voltage source, or by providing a higher data line charge voltage with a current source. | 10-15-2009 |
20090257289 | INTERNAL VOLTAGE GENERATOR AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME - A semiconductor device including an internal voltage generator circuit that provides an internal voltage having a different level depending on the operation speed is provided. The semiconductor device includes an internal voltage generator circuit configured to receive operation speed information to generate an internal voltage having a different level depending on the operation speed; and an internal circuit operated using the internal voltage. | 10-15-2009 |
20090262587 | Semiconductor memory device - A semiconductor memory device includes a plurality of memory cell array blocks connected to word lines, source lines, and bit lines, each memory cell array including memory cells each having a transistor with a floating body, a reference voltage generator configured to have a reference memory cell and generate a reference voltage for bit line sensing corresponding to a current flowing into a reference memory cell during a data read operation, first and second prechargers configured to precharge a bit line connected to non-selected memory cells to the reference voltage in response to first and second precharge control signals during the data read operation, and a sense amplifier configured to sense and amplify a voltage difference between a bit line connected to the selected memory cells and a bit line connected to the non-selected memory cells during the data read operation. | 10-22-2009 |
20090273988 | CIRCUIT AND METHODS TO IMPROVE THE OPERATION OF SOI DEVICES - According to the present invention, a circuit and methods for enhancing the operation of SOI fabricated devices are disclosed. In a preferred embodiment of the present invention, a pulse discharge circuit is provided. Here, a circuit is designed to provide a pulse that will discharge the accumulated electrical charge on the body of the SOI devices in the memory subarray just prior to the first access cycle. As explained above, once the accumulated charge has been dissipated, the speed penalty for successive accesses to the memory subarray is eliminated or greatly reduced. With a proper control signal, timing and sizing, this can be a very effective method to solve the problem associated with the SOI loading effect. Alternatively, instead of connecting the bodies of all SOI devices in a memory circuit to ground, the bodies of the N-channel FET pull-down devices of the local word line drivers can be selectively connected to a reference ground. This would enable the circuit to retain most of the speed advantages associated with SOI devices while overcoming the loading problem described above. With this preferred embodiment of the present invention, the major delay caused by the bipolar loading effect is minimized while the speed advantage due to providing a lower, variable V | 11-05-2009 |
20090279368 | CIRCUIT AND METHOD FOR GENERATING PUMPING VOLTAGE IN SEMICONDUCTOR MEMORY APPARATUS AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME - A circuit for generating a pumping voltage in a semiconductor memory apparatus includes a control signal generation block configured to generate a first control signal obtained by level-shifting a voltage level of a test signal to a first driving voltage level, a voltage application section configured to supply an external voltage to a first node in response to a first transmission signal, a first charge pump configured to raise a voltage level of the first node by a first predetermined level in response to an oscillator signal, and a first pumping voltage output section configured to select at least one of a first connection unit and a second connection unit in response to the first control signal, and to interconnect the first node with a second node using the selected connection unit when a second transmission signal is enabled, wherein a first pumping voltage is output through the second node. | 11-12-2009 |
20090285036 | Fuse data read circuit having control circuit between fuse and current mirror circuit - A fuse data read circuit includes a fuse data holding unit which holds fuse data, a fuse data read unit which detects fuse data, and a bias voltage generating circuit which generates a bias voltage. The fuse data read unit includes a current mirror circuit and a control circuit provided between the current mirror circuit and the fuse data holding unit. The bias voltage generating circuit applies the bias voltage to the control circuit. | 11-19-2009 |
20090285037 | INTERLEAVING CHARGE PUMPS FOR PROGRAMMABLE MEMORIES - Systems and methods, including computer software for performing operations enable interleaving of charging operations in a charging pump. A first charge pump is charged to a predetermined level, and a first operation is performed using a charge stored in the first charge pump after it reaches the predetermined level. A second charge pump is charged during a time that overlaps with performing the first operation. A second operation is performed using a charge stored in the second charge pump as a result of charging the second charge pump. | 11-19-2009 |
20090285038 | INTERLEAVING CHARGE PUMPS FOR PROGRAMMABLE MEMORIES - Systems and methods, including computer software for performing operations enable interleaving of charging operations in a charging pump. A first charge pump is charged to a predetermined level, and a first operation is performed using a charge stored in the first charge pump after it reaches the predetermined level. A second charge pump is charged during a time that overlaps with performing the first operation. A second operation is performed using a charge stored in the second charge pump as a result of charging the second charge pump. | 11-19-2009 |
20090296497 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a logic circuit supplied with a first supply voltage; a cell array supplied with a second supply voltage higher than the first supply voltage and including plural mutually intersecting word lines and bit lines and plural memory cells connected at intersections thereof; and a word line driver operative to drive the word lines. The word line driver includes plural pull-up circuits connected between the supply terminal of the first supply voltage and the drive terminal of the word line and between the supply terminal of the second supply voltage and the drive terminal of the word line, and a pull-down circuit connected between the drive terminal of the word line and the ground terminal, and drives the word line with an intermediate voltage between the first and second supply voltages in accordance with a driving force ratio between the plural pull-up circuits at the time of driving the word line. | 12-03-2009 |
20090303803 | Independent Bi-Directional Margin Control Per Level and Independently Expandable Reference Cell Levels for Voltage Mode Sensing - A memory system includes reference level generators that may provide programmable margins, and programmable verify voltage levels. The reference levels may be shifted within a range of voltages with varying differences between reference voltage levels and with different margins and verify levels. | 12-10-2009 |
20090316498 | CIRCUIT AND METHOD FOR VDD-TRACKING CVDD VOLTAGE SUPPLY - Circuit and methods for providing the CVDD supply to the cells in an SRAM array while maintaining a desired VDD voltage. A circuit is described for tracking the VDD supply voltage and providing a CVDD supply for the SRAM cells that maintains an offset above VDD until a maximum voltage for the CVDD voltage is reached. The CVDD voltage supplies the word line drivers and the cells in an SRAM array, while the bit line precharge and the remaining circuitry is operated on the VDD supply. By maintaining a maximum offset between the voltage CVDD and the supply voltage VDD, the SRAM will have the required static noise margins for reliable operation, while a lowered VDD_min voltage may also be obtained. A method for supplying a CVDD voltage to an SRAM cell array is disclosed where the CVDD voltage tracks a VDD supply voltage plus a predetermined offset voltage. | 12-24-2009 |
20090323438 | CIRCUIT AND METHOD FOR GENERATING WORD LINE OFF VOLTAGE - A circuit and method for generating a word line off voltage which can minimize a leakage current by actively adjusting a level of the word line off voltage. The circuit includes a current information provider for providing information about an amount of current flowing through a cell transistor, and a voltage generator for generating a word line off voltage with a varying level depending on the information. | 12-31-2009 |
20100008160 | Temperature sensor capable of reducing test mode time - A temperature sensor includes a temperature sensing unit for producing a sensing level by sensing an internal temperature in a semiconductor memory device, a reference level generating unit for setting up a reference level by selecting one of a plurality of reference voltages, which are set up according to the internal temperature of the semiconductor memory device, in response to a test mode signal and a temperature detecting signal, wherein the reference level generating unit includes fuse, and a comparison unit for comparing the sensing level to the reference level and producing the temperature detecting signal. | 01-14-2010 |
20100008161 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a charge pumping circuit, a level sensor, an oscillator, and a pumping control signal generator. The charge pumping circuit performs a negative-pumping operation to an external power in order to generate an internal voltage having a level lower than the external power. The level sensor senses a level of the internal voltage corresponding to a level of an adjusted reference voltage during a refresh mode. The oscillator generates a period signal in response to a sensing signal of the level sensor. The pumping control signal generator controls the operation of the charge pumping circuit in response to the period signal. | 01-14-2010 |
20100020622 | ONE-TRANSISTOR TYPE DRAM - A one-transistor type DRAM including a floating body storage element connected between a bit line and a source line and controlled by a word line comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a plurality of clamp bit lines and reference bit lines arranged in a column direction, a cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a clamp cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a reference cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, and a sense amplifier and a write driving unit connected to the bit line and configured to receive a clamp voltage and a reference voltage. | 01-28-2010 |
20100020623 | CIRCUIT AND METHOD OF GENERATING VOLTAGE OF SEMICONDUCTOR MEMORY APPARATUS - A circuit for generating a voltage of a semiconductor memory apparatus includes a control unit that outputs a driving control signal in response to an enable signal and a burn-in signal, a first voltage generating unit that generates and outputs a first voltage in response to the enable signal, and a voltage maintaining unit that maintains the first voltage in response to the driving control signal. | 01-28-2010 |
20100034031 | Semiconductor memory device - A semiconductor memory device includes a voltage level selection unit configured to output a plurality of voltage level selection signals according to a fuse program in response to a self-refresh command signal and a reference voltage generator configured to receive a reference voltage and output a target reference voltage having a different voltage level depending on a normal mode or a self-refresh mode in response to the voltage level selection signals. | 02-11-2010 |
20100046306 | Semiconductor storage device - It has been conventionally difficult to make circuits operate faster. The present invention is a semiconductor storage device including a reference voltage circuit that supplies a reference voltage, and first and second memory circuits, that performs a read/write operation when one of the first and second memory circuits is selected, wherein the first and second memory circuits each include a plurality of memory cells, a plurality of bit line pairs, a precharge circuit that connects a reference voltage circuit to a plurality of bit lines, a sense amplifier circuit that amplifies, when making a selection, a plurality of bit line pairs and a pull-down circuit that lowers any one of the plurality of bit line pairs below the reference voltage, the pull-down circuit of the second memory circuit lowers the bit line pair for a read/write operation period during which the first and second memory circuits are selected or non-selected and the precharge circuits of the first and second memory circuits connect a plurality of bit line pairs to the reference voltage circuit respectively during a precharge period. | 02-25-2010 |
20100046307 | SEMICONDUCTOR MEMORY AND SYSTEM - A word driver supplies a high level voltage to a word line when a memory cell is accessed and supplies low level voltage which is a negative voltage to the word line when the memory cell isn't accessed. A precharge circuit lowers a precharge voltage-supplying capacity to a bit line at least during a standby period when the memory cell is not accessed. A substrate voltage of an nMOS transistor with source or drain connected to the bit line is set to the low level voltage or lower of the word line. Therefore, when the word line and the bit line fails short and the voltage of the bit line changes to the low level voltage of the word line during the standby period, a substrate current can be prevented from flowing between the source of the nMOS transistor and a substrate or the drain and the substrate. | 02-25-2010 |
20100046308 | ONE-TRANSISTOR TYPE DRAM - A one-transistor type DRAM includes a floating body storage element connected between a bit line and a source line and controlled by a word line. The DRAM comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a plurality of reference bit lines arranged in a column direction, a cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a reference cell array including the floating body storage element, formed in a region where the source line, the word line and the bit line are crossed and configured to output a reference current having a plurality of levels, a plurality of reference voltage generating units connected to the reference bit lines and configured to generate a plurality of reference voltages corresponding to the reference current having a plurality of levels, and a sense amplifier and a write driving unit connected to the bit line and configured to receive the plurality of reference voltages. | 02-25-2010 |
20100054050 | APPARATUS AND METHOD FOR PROVIDING POWER IN SEMICONDUCTOR MEMORY DEVICE - An apparatus for applying power in a semiconductor memory device includes a first power pin for receiving a first power at a first voltage from an external device, a second power pin for receiving a second power at the first voltage, a memory array block connected to the first power pin, the memory array block writing input data, outputting read data, and refreshing regularly to sustain stored data, a peripheral logic block connected to the first power pin for receiving the first power and communicating with the memory array block to perform data write and read operations, a data output driver connected to the second power pin and driving a data output pin, and a switch for electrically connecting the first power pin and the second power pin by performing a switching operation during a refresh operation of the memory array block. | 03-04-2010 |
20100061162 | CIRCUIT AND METHOD FOR OPTIMIZING MEMORY SENSE AMPLIFIER TIMING - A memory has an array of memory cells, a word line driver, a sense amplifier, and a sense enable circuit. Each memory cell has a coupling transistor for coupling a storage portion to a bit line. The coupling transistors have an average threshold voltage and a maximum threshold voltage. The word line driver is coupled to the array and is for enabling a selected row of memory cells in the array. The sense amplifier detects a state of a memory cell in the selected row in response to a sense enable signal. The sense enable circuit provides the sense enable signal at a time based on the maximum threshold voltage. This timing enables the sense amplifier sufficiently late for low temperature operation while providing for faster operation at high temperature than would normally be achieved using just the average threshold voltage in providing timing of the sense enable signal. | 03-11-2010 |
20100061163 | APPARATUS FOR GENERATING PUMPING VOLTAGE - An apparatus for generating pumping voltage of a multiple Chip Select (CS) mode semiconductor memory apparatus includes a high speed pumping control unit configured to produce a pumping enable signal regardless of the level of a pumping voltage to actuate the pumping unit when a plurality of banks of the semiconductor apparatus operated by different CS signals are continuously actuated. | 03-11-2010 |
20100074033 | Bandgap Voltage and Temperature Coefficient Trimming Algorithm - A circuit and corresponding method for providing a reference voltage are presented. The circuit includes a current source having a magnitude with positive temperature correlation connected to a node, and a diode element connected between the node and ground, where the reference voltage is provided from the node. The circuit also includes a variable resistance connected to receive an input indicative of the circuit temperature and through which the diode element is connected to the node. The value of the variable resistance is adjusted based upon the circuit temperature input. The circuit is useful for application as a peripheral circuitry, such as on a flash or other non-volatile memory and other circuits requiring an on-chip reference voltage source. | 03-25-2010 |
20100074034 | VOLTAGE REGULATOR WITH REDUCED SENSITIVITY OF OUTPUT VOLTAGE TO CHANGE IN LOAD CURRENT - A voltage regulator is disclosed. The voltage regulator has a voltage generation circuit that outputs a regulated voltage and a load current. The voltage regulation circuit has a sensing circuit that senses a peak magnitude of the load current and stores a peak signal that is based on the peak load current magnitude. The sensing circuit receives at least one signal that is input to the voltage regulation circuit and senses the peak magnitude of the load current. The voltage regulation circuit has a current generation circuit that generates a compensation current that has a magnitude that is proportional to the peak load current magnitude. The current generation circuit generates the compensation current based on the peak signal. The compensation current is provided during a time interval that is defined by at least one signal that is input to the voltage regulation circuit. | 03-25-2010 |
20100085817 | Semiconductor memory device to reduce off-current in standby mode - A semiconductor memory device capable of reducing off-current in a standby mode is provided. The semiconductor memory device includes an enable signal generating unit configured to receive a plurality of address decoding signals and generate a first enable signal to select a first cell block and a second enable signal to select a second cell block, and an internal voltage generating unit for generating an internal voltage by controlling a supply of a first voltage in accordance with the first or second enable signals. | 04-08-2010 |
20100118622 | 1-TRANSISTOR TYPE DRAM CELL, A DRAM DEVICE AND MANUFACTURING METHOD THEREFORE, DRIVING CIRCUIT FOR DRAM, AND DRIVING METHOD THEREFOR - The present invention relates to an 1-transistor DRAM cell, a DRAM device and a manufacturing method therefor, a driving circuit for a DRAM, a driving method therefore, and a driving method for an 1-transistor DRAM, and a double-gate type 1-transistor DRAM. The present invention comprises a data hold process biasing a word line at a negative voltage level and biasing a sensing line and a bit line at a first constant voltage level; a data purging process resetting data by biasing the word line and the bottom word line at a second constant voltage level and biasing the sensing line and the bit line at the first constant voltage level; and a data write process biasing the word line and the bottom word line at the second constant voltage level and supplying a write data to the bit line. | 05-13-2010 |
20100142289 | Nonvolatile semiconductor memory and method for testing the same - A nonvolatile semiconductor memory includes a nonvolatile memory array, a voltage generator circuit that generates a drive voltage which changes depending on a supply voltage and a trimming code, a control circuit that applies the generated drive voltage to the nonvolatile memory array, and a trimming code output circuit that outputs any one of plural trimming codes to the voltage generator circuit. The plural trimming codes include a test trimming code in addition to an appropriate trimming code for generating a desired drive voltage. The test trimming code is different from the appropriate trimming code, and used only in the test state. In the test state, the trimming code output circuit outputs the test trimming code to the voltage generator circuit, and the voltage generator circuit generates the drive voltage according to the test trimming code. In states other than the test state, the trimming code output circuit outputs the appropriate trimming code to the voltage generator circuit, and the voltage generator circuit generates the drive voltage according to the appropriate trimming code. | 06-10-2010 |
20100149884 | REDUCTION OF POWER CONSUMPTION IN A MEMORY DEVICE DURING SLEEP MODE OF OPERATION - The present disclosure relates to a system comprising memory device with a power switch where the system comprises a first voltage controlled switch coupling positive power supply to positive supply terminal of memory device core; a second voltage controlled switch coupling negative power supply to negative supply terminal of the memory device core; a first reference voltage coupled to the substrate terminal of said first voltage controlled switch; and a second reference voltage coupled to the substrate terminal of said second voltage controlled switch. This helps maintain a sufficient RNM for efficient performance by the system. | 06-17-2010 |
20100157692 | Distributed VDC for SRAM Memory - An integrated circuit structure includes a memory. The memory includes a first memory macro and a second memory macro identical to the first memory macro. A first power block is connected to the first memory macro and is configured to provide a regulated voltage to the first memory macro. The first power block has a first input and a first output. A second power block substantially identical to the first power block is connected to the second memory macro and is configured to provide the regulated voltage to the second memory macro. The second power block has a second input and a second output. The first input and the second input are interconnected. The first output and the second output are interconnected. | 06-24-2010 |
20100157693 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises a memory cell array including a plurality of word lines, a plurality of bit lines intersecting the plurality of word lines, and a plurality of binary-data holding memory cells arranged at the intersections of the word lines and the bit lines; and a control unit operative to change in the storage capacity of the memory cell array and change in the address space required for access to the memory cell based on a control signal. | 06-24-2010 |
20100157694 | LOW COUPLE EFFECT BIT-LINE VOLTAGE GENERATOR - A bit-line voltage generator is provided. The bit-line voltage generator includes a discharge enhanced bias source and a switch unit. The switch unit includes a clamp transistor having a source, a gate connected to the discharge enhanced bias source, and a drain receiving a voltage; a switch transistor having a gate receiving a control signal, a drain connected to the source of the clamp transistor, and a source connected to a memory array, wherein a parasitic capacitor exists between the gate and the source of the clamp transistor; a resistor having a first terminal connected to the drain of the switch transistor, and a second terminal connected to ground; and a capacitor having a first terminal connected to the drain of the switch transistor, and a second terminal connected to ground, wherein a charge in the parasitic capacitor, when the switch transistor is turned on, is almost identical to that when the switch transistor is turned off, so that a couple effect between the switch unit and the discharge enhanced bias source is reduced, thereby stabilizing a bias applied to the memory array. | 06-24-2010 |
20100165752 | LEVEL SHIFTER - A level shifter circuit includes first and second supply inputs for receiving a first supply voltage and a second supply voltage, respectively. The level shifter circuit further comprises a shifting circuit configured to receive an input voltage and output a selected one of the first supply voltage and the second supply voltage according to the value of the input voltage. The shifting circuit includes a circuit branch connected between the first supply input and the second supply input. The circuit branch includes a plurality of series-connected electronic devices and a voltage dropper device connected in series with the plurality of electronic devices for introducing a voltage drop. The level shifter circuit includes a bias generator configured to generate a bias voltage for the voltage dropper device according to values of the first supply voltage and the second supply voltage, said voltage drop depending on the bias voltage. | 07-01-2010 |
20100172192 | REFERENCE VOLTAGE GENERATION CIRCUIT AND SEMICONDUCTOR MEMORY - A reference voltage generation circuit includes a first node settable at a reference voltage to be any one of a plurality of voltage levels, a second node set at a pre-charge voltage, first and second switches connected in series between the first and second nodes, a plurality of capacitors, each capacitor comprising a first end connected to a connection node between the first and second switches and a second end settable at an independent voltage level, a switch controller configured to turn off the first switch and turn on the second switch in an initial state, and then to turn off the second switch, and then to turn on the first switch, and a voltage controller configured to individually set a voltage at the second end of each capacitor after the first switch is turned on. | 07-08-2010 |
20100172193 | Semiconductor memory device and method of reducing consumption of standby current therein - A semiconductor memory device comprises a memory array including a plurality of bit lines and a plurality of dummy bit lines, a bias application unit configured to supply bias voltages having a plurality of voltage levels to the plurality of dummy bit lines, a standby current measuring unit configured to measure a value of at least one of standby currents between at least one of the plurality of bit lines and at least one of the plurality of dummy bit lines. Each of the standby currents is generated by each of the bias voltages applied by the bias application unit. | 07-08-2010 |
20100182851 | Refresh control circuit and semiconductor memory device and memory system including the same - A semiconductor memory device includes a refresh control circuit and a memory cell array. The refresh control circuit generates an internal auto refresh control signal based on a chip select signal and an external self refresh control signal. The memory cell array is refreshed in response to the internal auto refresh control signal. Because the semiconductor memory device internally generates the internal auto refresh control signal performing auto refresh operations, the semiconductor memory device may not be required to transmit to external devices for performing the auto refresh operations, and thus pins or pads for transmitting signals may be reduced and operation time may become faster. | 07-22-2010 |
20100182852 | Oscillation Circuit and Semiconductor Memory Device Including the Same - An oscillation circuit includes an internal voltage generator and an oscillator. The internal voltage generator receives an external voltage and generates an internal voltage based on the external voltage. The internal voltage varies in linearly with an operational temperature. The oscillator generates a variable oscillation signal based on the internal voltage. A period of the variable oscillation signal varies in linearly with the operational temperature. | 07-22-2010 |
20100195415 | Semiconductor memory device and reading method therefor - A memory device is configured such that, in a read access: a first switch and a second switch are turned on in a pre-charge period before a memory cell is accessed so that charges of a bit line charge voltage generating circuit are distributed to a bit line and a reference bit line, to thereby charge the bit line and the reference bit line to an initial voltage. After the charge, a selected memory cell is connected to the bit line, the reference bit line is connected to a reference voltage generating circuit, and a voltage differential type sense amplifier amplifies a difference voltage between a voltage of the bit line decreased by discharge of the selected memory cell and a voltage of the reference bit line generated by the reference voltage generating circuit, to thereby read out memory cell data. | 08-05-2010 |
20100208529 | MEMORY WITH REDUCED POWER SUPPLY VOLTAGE FOR A WRITE OPERATION - A memory includes a selection circuit and a write assist circuit. The selection circuit has a first input, a second input coupled to a first power supply voltage terminal, an output coupled to a power supply terminal of each of a plurality of memory cells, and a control input for receiving a write assist control signal. The write assist circuit is coupled to the first input of the selection circuit for reducing a voltage at the power supply terminal of each of the plurality of memory cells during a write operation and in response to an asserted write assist enable signal. The write assist circuit comprises a P-channel transistor and a bias voltage generator. The P-channel transistor is for reducing the voltage at the power supply terminal of each of the plurality of memory cells during the write operation. The bias voltage generator is for providing a variable bias voltage to the P-channel transistor. | 08-19-2010 |
20100220535 | NON-VOLATILE MEMORY DEVICE - A non-volatile memory device includes a feedback circuit and a precharge switching transistor. The feedback circuit generates a feedback signal based on a voltage level of a bitline during a precharge operation. The precharge switching transistor, in response to the feedback signal, controls a precharge current for precharging the bitline. The speed of the precharge operation may be increased and/or mismatch of the bias signals in precharging a plurality of bitlines may be reduced. | 09-02-2010 |
20100232236 | SRAM LEAKAGE REDUCTION CIRCUIT - A method and system are provided for maintaining a virtual ground node of an SRAM memory array at a minimum level sufficient for maintaining data retention. A circuit can maintain the virtual ground node at a virtual ground reference voltage of V | 09-16-2010 |
20100238742 | APPARATUS AND METHOD FOR OUTPUTTING DATA OF SEMICONDUCTOR MEMORY APPARATUS - An apparatus for outputting data of a semiconductor memory apparatus, which is capable of varying the slew rate and the data output timing, includes a bias generator that generates a bias having a level corresponding to a set value, a slew rate controller that controls a pull-up slew rate or a pull-down slew rate of input data on the basis of the bias generated by the bias generator, and a data outputting unit that outputs data on the basis of the slew rate controlled by the slew rate controller. Therefore, it is possible to satisfy various operational conditions without changing the structure of the circuit and to correspond rapidly and appropriately whit a change in the system, which enables the applied range of the products to be extended. | 09-23-2010 |
20100246282 | VOLTAGE GENERATOR FOR MEMORY ARRAY - A high voltage may be generated for programming memory cells in a memory array. A middle voltage may also be generated for reading memory cells in the memory array. Control logic and switches may be used to select between the high voltage and the middle voltage. A first oscillator generates clock signals at a high frequency for generating the voltages, and a low frequency oscillator may be used to generate pulses at a lower frequency than the first oscillator to allow the first oscillator to operate only during such pulses to conserve power during a stand-by mode of operation to maintain the middle or medium voltage. | 09-30-2010 |
20100246283 | REFERENCE POTENTIAL GENERATING CIRCUIT OF SEMICONDUCTOR MEMORY - There is provided a reference potential generating circuit of a semiconductor memory, including: a first MOS transistor group that includes a plurality of first MOS transistors that are connected in series; a second MOS transistor that is connected in series to the first MOS transistor group; a third MOS transistor that is connected in parallel to the circuit in which the first MOS transistor group and the second MOS transistor are connected in series, has a gate connected to a connection point of the first MOS transistor group and the second MOS transistor, and corrects a reference potential from a connection point of the first MOS transistors; and a fourth MOS transistor that is connected to the gate of the third MOS transistor, and decreases the potential of the gate of the third MOS transistor when a permission signal to supply power to the semiconductor memory is input. | 09-30-2010 |
20100246284 | SEMICONDUCTOR MEMORY HAVING ELECTRICALLY FLOATING BODY TRANSISTOR - A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; a gate positioned between said first and second regions; and a back-bias region configured to inject charge into or extract charge out of said floating body region to maintain said state of the memory cell. Application of back bias to the back bias region offsets charge leakage out of the floating body and performs a holding operation on the cell. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. | 09-30-2010 |
20100271885 | Reduced complexity array line drivers for 3D matrix arrays - A method of biasing a nonvolatile memory array. The nonvolatile memory array includes a first and second plurality of Y lines, a plurality of X lines, a first and second plurality of two terminal memory cells. Each first and second memory cell is coupled to one of the first or second plurality of Y lines and one of the plurality of X lines, respectively. Substantially all of the first plurality and second plurality of Y lines are driven to a Y line unselect voltage. At least one selected Y line of the first plurality of Y lines is driven to a Y line select voltage while floating remaining Y lines of the first plurality of Y lines and while driving substantially all of the second plurality of Y lines to the Y line unselect voltage. | 10-28-2010 |
20100277988 | INTERNAL SOURCE VOLTAGE GENERATION CIRCUIT AND GENERATION METHOD THEREOF - An internal source voltage generation circuit includes main source voltage driving means configured to drive an internal source voltage terminal to a predetermined voltage level; and additional source voltage driving means configured to additionally drive the internal source voltage terminal in response to a data strobe signal. | 11-04-2010 |
20100302878 | SENSE AMPLIFIER AND DRIVING METHOD THEREOF, AND SEMICONDUCTOR MEMORY DEVICE HAVING THE SENSE AMPLIFIER - The semiconductor memory device includes a bank having a cell array and a sense amplifier. A back bias voltage generating unit supplies a back bias voltage to the cell array of the bank. A negative drive voltage generating unit generates negative driving voltages including a normal pull-up voltage, an overdrive voltage, a normal pull-down voltage, and a negative voltage and supplies the negative driving voltages to the sense amplifier of the bank. A switching unit opens a connection between the back bias voltage generating unit and the negative drive voltage generating unit when in active mode and shares the back bias voltage between the back bias voltage generating unit and the negative drive voltage generating unit when in a refresh mode, in response to an external command. | 12-02-2010 |
20100302879 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells. | 12-02-2010 |
20100309735 | INTERNAL POWER SUPPLY CIRCUIT, SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - An internal power supply circuit supplies a power supply voltage to an internal circuit of a semiconductor device via an internal power supply line. The internal power supply circuit includes a reference potential generating circuit that is configured to generate a plurality of reference potentials having different temperature dependencies from each other, an internal voltage generating circuit that generates the power supply voltage with reference to a reference potential generated by the reference potential generating circuit, and a control circuit that selects a reference potential to be generated by the reference potential generating circuit. | 12-09-2010 |
20100315888 | SEMICONDUCTOR DEVICE - A semiconductor device includes first and second bit lines, and a transistor coupled between the first and second bit lines. The semiconductor device further includes a substrate bias control circuit that supplies one of a first substrate bias voltage and a second substrate bias voltage to the transistor. By controlling the substrate bias voltage of the transistor, high-speed equalization is performed, and an increase in leak current at times of standby and activation is prevented. | 12-16-2010 |
20100322019 | REFERENCE VOLTAGE REGULATOR FOR EDRAM WITH VSS-SENSING - A reference voltage regulator for an embedded dynamic random access memory (eDRAM) employing VSS-sensing with a reference level includes an oscillator, a control block, a reference generator, a comparator, a pulse generator, a driver, and a reference voltage output, where the oscillator sends requests for sampling and correction to the control block between accesses of the eDRAM, the control block sends a pulse defining a time interval during which sampling and correction occurs to the pulse generator, the reference generator provides the reference level for comparison by the comparator with a sampling of the reference voltage output, the comparator decides if the reference voltage output requires correction and sends a correction request to the pulse generator if necessary, the pulse generator produces a correction pulse for the driver according to the correction request from the comparator, and the driver adjusts the reference voltage output during the correction pulse. | 12-23-2010 |
20110002177 | NONVOLATILE MEMORY DEVICE HAVING A PLURALITY OF MEMORY BLOCKS - A nonvolatile memory device | 01-06-2011 |
20110007578 | TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE - Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first region and a second region. The apparatus may also include a body region disposed between the first region and the second region and capacitively coupled to a plurality of word lines, wherein each of the plurality of word lines is capacitively coupled to different portions of the body region. | 01-13-2011 |
20110007579 | INTERNAL VOLTAGE GENERATOR - An internal voltage generator according to an embodiment generates a reference voltage used for detecting data stored in a semiconductor memory. A first AD converter is configured to convert an external voltage supplied to the semiconductor memory into a first digital value. A second AD converter is configured to convert a temperature characteristic voltage that changes depending on a temperature of the semiconductor memory into a second digital value. An adder is configured to receive a reference voltage trimming address that specifies the reference voltage, the first digital value, and the second digital value, and to output a third digital value obtained by performing a weighted addition of the reference voltage trimming address, the first digital value, and the second digital value. A driver is configured to output the reference voltage responding to the third digital value. | 01-13-2011 |
20110026333 | BULK BIAS VOLTAGE GENERATING DEVICE AND SEMICONDUCTOR MEMORY APPARATUS INCLUDING THE SAME - A bulk bias voltage generating device is configured to generate a first bulk bias voltage in a deep power down mode and a second bulk bias voltage in a normal mode. The first bulk bias voltage comprises an internal voltage level, and the second bulk bias voltage comprises an external voltage level. | 02-03-2011 |
20110032776 | MEMORY CIRCUIT AND VOLTAGE DETECTION CIRCUIT INCLUDING THE SAME - Provided are a memory circuit having a small circuit scale and a voltage detection circuit including the memory circuit. An NMOS transistor ( | 02-10-2011 |
20110032777 | Semiconductor memory circuit - The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized. | 02-10-2011 |
20110044118 | Semiconductor Device having variable parameter selection based on temperature and test method - A semiconductor device that may include temperature sensing circuits is disclosed. The temperature sensing circuits may be used to control various parameters, such as internal regulated supply voltages, internal refresh frequency, or a word line low voltage. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without compromising performance at normal operating temperatures. Each temperature sensing circuit may include a selectable temperature threshold value as well as a selectable temperature hysteresis value. In this way, temperature performance characteristics may be finely tuned. Furthermore, a method of testing the temperature sensing circuits is disclosed in which a current value may be monitored and temperature threshold values and temperature hysteresis values may be thereby determined. | 02-24-2011 |
20110051532 | REFERENCE LEVEL GENERATION WITH OFFSET COMPENSATION FOR SENSE AMPLIFIER - An approach that provides reference level generation with offset compensation for a sense amplifier is described. In one embodiment, an arbitrary reference level is generated to provide an offset that compensates for device mismatch and voltage threshold of a sense amplifier. | 03-03-2011 |
20110051533 | INTERNAL VOLTAGE GENERATOR CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME - An internal voltage generator circuit is disclosed. The internal voltage generator circuit includes a comparator configured to compare a first voltage with a reference voltage and to output a comparison signal. The circuit further includes an internal voltage driver configured to receive an external voltage and the comparison signal and to output an internal voltage at an internal voltage output terminal, based on the comparison signal. The circuit further includes a voltage divider circuit including first and second resistor units and a first voltage output terminal between the first and second resistor units, configured to receive the internal voltage, and configured to output the first voltage based on the resistance values of the first and second resistor units, the first and second resistor units connected in series, and the first voltage being output through the first voltage output terminal. The circuit further includes a control signal generator circuit configured to generate at least one resistor control signal for controlling the resistance value of the first resistor unit and at least one resistor control signal for controlling the resistance value of the second resistor unit, on the basis of the comparison signal and a precharge command. | 03-03-2011 |
20110069562 | LOW CONSUMPTION VOLTAGE REGULATOR FOR A HIGH VOLTAGE CHARGE PUMP, VOLTAGE REGULATION METHOD, AND MEMORY DEVICE PROVIDED WITH THE VOLTAGE REGULATOR - A voltage regulator for a regulated voltage generator configured to generate an operating voltage and including a variable comparison voltage generator, a comparison voltage, a partition branch including a plurality of active devices of a resistive type to receive the operating voltage and supply an intermediate voltage correlated to the operating voltage, and a comparator, to receive the comparison voltage and the intermediate voltage and supply a regulation signal for the regulated-voltage generator. | 03-24-2011 |
20110090745 | SENSE AMPLIFIER WITH FAST BITLINE PRECHARGE MEANS - The disclosure relates to a sense amplifier comprising a cascode transistor and means for biasing the cascode transistor, supplying a control voltage to a gate terminal of the cascode transistor. The means for biasing the cascode transistor comprise means for isolating the gate terminal of the cascode transistor from the output of the voltage generator during a first period of the precharge phase, so as to boost the bitline voltage, then for linking the gate terminal to the output of the voltage generator during a second period of the precharge phase. Application in particular to sense amplifiers for non-volatile memories. | 04-21-2011 |
20110090746 | DEVICE AND METHOD GENERATING INTERNAL VOLTAGE IN SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device and a method of generating an internal voltage in the semiconductor memory device are provided. The semiconductor memory device includes a controller configured to activate a sensing enable signal when an active command is applied from outside, inactivate the sensing enable signal when a precharge command is applied, and output the sensing enable signal, and an array internal voltage generator configured to output an active array power supply voltage as an array power supply voltage when the sensing enable signal is activated, output an external array power supply voltage and a standby array power supply voltage as the array power supply voltage when the sensing enable signal is inactivated, and output the standby array power supply voltage alone as the array power supply voltage when the sensing enable signal is inactivated for at least a specific period. | 04-21-2011 |
20110096612 | METHOD, SYSTEM, AND COMPUTER READABLE MEDIUM FOR READING AND PROGRAMMING FLASH MEMORY CELLS - A system, method and computer readable medium for programming and reading flash memory cells. Respective first and second read operations may be performed while supplying respective first and second bias voltage to multiple flash memory cells, to provide respective first and second read results, where the first bias voltage may be higher then the second bias voltage, and providing a read outcome that may be responsive to the first read results and to the second read results. A programming method may include performing first and second programming operations while supplying respective first and second bias voltages to multiple flash memory cells. The programming method may further include performing the first programming operation while programming information mapped to a highest least significant bit positive lobe, and performing the second programming operation while programming information mapped to at least one other least significant bit positive lobe. | 04-28-2011 |
20110110168 | SEMICONDUCTOR MEMORY DEVICE, SEMICONDUCTOR MEMORY MODULE AND SEMICONDUCTOR MEMORY SYSTEM INCLUDING THE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device, a semiconductor memory module, and a semiconductor memory system including the same, the semiconductor memory device including a command/address input buffer that receives a command/address signal and a command/address reference voltage signal, wherein the command/address input buffer is configured to amplify a difference between the command/address signal and the command/address reference voltage signal, and is further configured to output the amplified difference between the command/address signal and the command/address reference voltage signal, and a chip selection input buffer that receives a chip selection signal and a chip selection reference voltage signal, wherein the chip selection input buffer is configured to amplify a difference between the chip selection signal and the chip selection reference voltage signal, and is further configured to output the amplified difference between the chip selection signal and the chip selection reference voltage signal, wherein a voltage level of the command/address reference voltage signal is different from a voltage level of the chip selection reference voltage signal. | 05-12-2011 |
20110122711 | BITLINE PRECHARGE VOLTAGE GENERATOR, SEMICONDUCTOR MEMORY DEVICE COMPRISING SAME, AND METHOD OF TRIMMING BITLINE PRECHARGE VOLTAGE - A bitline precharge voltage generator comprises a leakage trimming unit and a bitline precharge voltage providing unit. The leakage trimming unit applies a leakage current to an output node to place a bitline precharge voltage at an edge of a dead zone. The bitline precharge voltage providing unit provides the bitline precharge voltage to the output node, and sets the bitline precharge voltage to a target level. The bitline precharge voltage generator generates the bitline precharge voltage having a distribution including the dead zone. | 05-26-2011 |
20110128798 | POWER SOURCE CIRCUIT AND SEMICONDUCTOR MEMORY CIRCUIT USING THE SAME - A semiconductor memory circuit includes: a plurality of memory regions; a plurality of driving units configured to be enabled in response to a plurality of enable signals, respectively, and generate a predetermined voltage used for operations of the plurality of memory regions; and an enable control unit configured to count a control pulse and activate one or more enable signals among the plurality of enable signals. | 06-02-2011 |
20110141827 | METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING VOLTAGE REFERENCE TO OPTIMIZE AN I/O SYSTEM - Described herein is an apparatus for dynamically adjusting a voltage reference level for optimizing an I/O system to achieve a certain performance metric. The apparatus comprises: a voltage reference generator to generate a voltage reference; and a dynamic voltage reference control unit, coupled with the voltage reference generator, to dynamically adjust a level of the voltage reference in response to an event. The apparatus is used to perform the method comprising: generating a voltage reference for an input/output (I/O) system; determining a worst case voltage level of the voltage reference; dynamically adjusting, via a dynamic voltage reference control unit, the voltage reference level based on determining the worst case voltage level; and computing a center of an asymmetrical eye based on the dynamically adjusted voltage reference level. | 06-16-2011 |
20110141828 | SEMICONDUCTOR SYSTEM - To provide a semiconductor system including a plurality of core chips and an interface chip that controls the core chips. Each of the core chips includes an internal voltage generating circuit. The interface chip includes an unused chip information holding circuit that stores therein unused chip information of the core chips. The core chips respectively receive the unused chip information from the unused chip information holding circuit. When the unused chip information indicates an unused state, the internal voltage generating circuits are inactivated, and when the unused chip information indicates a used state, the internal voltage generating circuits are activated. With this configuration, unnecessary power consumption by the unused chips is reduced. | 06-16-2011 |
20110141829 | Circuits for Reducing Power Consumption of Memory Components - An integrated circuit including one or more data links. A respective data link includes a precharge circuit, a voltage generator circuit, and a transmitter circuit. The precharge circuit is configured to precharge a data line to a predefined voltage level between transmission of symbols on the data line. The voltage generator circuit is configured to generate one or more transmit voltage levels, wherein a respective transmit voltage level represents a respective symbol to be transmitted on the data line and provide current from a voltage source to a transmitter circuit to drive the data line to a transmit voltage level representing a symbol to be transmitted, wherein the current drawn from the voltage source is independent of previously transmitted symbols. The transmitter circuit is configured to receive the symbol to be transmitted and drive the data line to the transmit voltage level using the current provided by the voltage generator circuit. | 06-16-2011 |
20110170363 | BIT LINE PRECHARGE VOLTAGE GENERATION CIRCUIT FOR SEMICONDUCTOR MEMORY APPARATUS - Various embodiments of a bit line precharge voltage generation circuit for a semiconductor memory apparatus are disclosed. In one exemplary embodiment, a bit line precharge voltage generation circuit may include a voltage division block for dividing an internal voltage to generate a first division voltage and a second division voltage, wherein a level of the second division voltage is higher than a level of the first division voltage; a pull-up amplification block for comparing the level of the first division voltage with a level of a bit line precharge voltage on a bit line precharge voltage line, to raise the level of the bit line precharge voltage; and a pull-down amplification block for comparing the level of the second division voltage with the level of the bit line precharge voltage to lower the level of the bit line precharge voltage. | 07-14-2011 |
20110176373 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - A semiconductor integrated circuit device includes: a memory cell array composed of electrically rewritable memory cells; an internal voltage generating circuit having a boosting circuit for generating a voltage boosted from a supply voltage, and a voltage detecting circuit for detecting an output voltage of the boosting circuit as a monitor voltage and controlling on/off of the boosting circuit for holding the output voltage of the boosting circuit at a specified level, the internal voltage generating circuit outputting the output voltage of the boosting circuit as an internal voltage; a control circuit for controlling the internal voltage generating circuit; and a writing circuit for applying the internal voltage to the memory cell as a writing voltage when writing data into the memory cell, wherein the control circuit controls the internal voltage to a first voltage necessary for writing data into the memory cell when writing data into the memory cell, and to a second voltage lower than the first voltage in a write verify operation following the data write operation. | 07-21-2011 |
20110188325 | Semiconductor device and data processing system - A semiconductor device comprises a bit line transmitting a signal to be sensed, a single-ended sense amplifier sensing and amplifying the signal transmitted from the bit line to the input node, and a reference voltage supplying circuit outputting a reference voltage. The sense amplifier includes a first transistor for charge transfer between the bit line and an input node, and the voltage value of the reference voltage is controlled in association with a threshold voltage of the first transistor. The reference voltage is set to a first logical value of the transfer control signal which controlled to be first and second logical values. | 08-04-2011 |
20110194361 | SEMICONDUCTOR DEVICE - An array configuration capable of supplying a necessary and sufficient current in a small area is achieved and a reference cell configuration suitable to temperature characteristics of a TMR element is achieved. In a memory using inversion of spin transfer switching, a plurality of program drivers are arranged separately along one global bit line, and one sense amplifier is provided to one global bit line. A reference cell to which “1” and “0” are programmed is shared by two arrays and a sense amplifier. | 08-11-2011 |
20110222355 | Control voltage generation circuit and nonvolatile storage device having the same - Disclosed herein is a control voltage generation circuit including: a reference voltage generation circuit adapted to generate a reference voltage; and a voltage conversion circuit adapted to generate, based on the reference voltage, a control voltage to be supplied to the gate of a clamping transistor connected between a bit line and a sense amplifier to adjust the voltage of the bit line, wherein the voltage conversion circuit outputs a voltage, which is the sum of a voltage proportional to the reference voltage and a voltage equivalent to the threshold voltage of the clamping transistor, to the gate of the clamping transistor as the control voltage. | 09-15-2011 |
20110235441 | High voltage generating circuit and semiconductor memory device having the same and method thereof - A high voltage generating circuit may include a pulse signal generator, a counter, a plurality of transmitters, and/or a plurality of pumpers. The pulse signal generator may be configured to be enabled in response to a refresh command signal to output a pulse signal. The counter may be configured to count the pulse signal and sequentially output a plurality of selection signals. The plurality of transmitters may be configured to be sequentially enabled in response to individual selection signals of the plurality of selection signals to transmit the pulse signal. The plurality of pumpers may correspond to the plurality of transmitters. Each of the plurality of pumpers may be configured to collectively generate a high voltage based on the transmitted pulse signal from a corresponding transmitter of the plurality of transmitters. | 09-29-2011 |
20110249515 | DIMM Memory Module Reference Voltage Switching Circuit - A non-volatile memory module includes a volatile memory circuit and a reference voltage generator coupled to supply a reference voltage to the volatile memory circuit. The reference voltage provides a level by which the volatile memory and external devices may communicate reliably at high speeds. The reference voltage is applied to an external interface of the non-volatile memory module through an isolation circuit. A control circuit coupled to the isolation interface and to a circuit which is adapted to detect when the non-volatile memory module no longer draws power from an external source. | 10-13-2011 |
20110249516 | INTERNAL VOLTAGE GENERATION DEVICE - An internal voltage generation device is disclosed which includes an internal voltage generator operated in response to an enable signal, the internal voltage generator generating an internal voltage using a reference voltage, and a sub-voltage generator for driving an output terminal of the internal voltage generator to a predetermined voltage level in response to a control signal. | 10-13-2011 |
20110249517 | WORDLINE DRIVING CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE - Wordline driving circuit of semiconductor memory device includes a bias generator configured to generate a threshold bias voltage for accessing data, an over-driver configured to increase the threshold bias voltage at an initial stage of a data accessing operation and a wordline driver configured to activate a wordline in response to the threshold bias voltage and a signal output from the over-driver. | 10-13-2011 |
20110261629 | Reduced Power Consumption in Retain-Till-Accessed Static Memories - Bias circuitry for a static random-access memory (SRAM) with a retain-till-accessed (RTA) mode. The memory is constructed of multiple memory array blocks, each including SRAM cells formed of array transistors; functional and other circuitry outside of the array are formed of core transistors, constructed differently from the array transistors. Bias devices are included within each memory array block, the bias devices constructed as one or more array transistors. The bias devices for a memory array block may be connected in parallel with one another. In the RTA mode, the bias devices drop the power supply voltage differential across each of the SRAM cells. In a normal operating mode, a core transistor serves as a switch, shorting out the bias devices so that the full power supply differential appears across the SRAM cells. | 10-27-2011 |
20110261630 | SEMICONDUCTOR DEVICE - A semiconductor device compares potential AF_G at an end of an anti-fuse element with potential VPPR. If potential AF_G is equal to or higher than potential VPPR, then the semiconductor device boosts potential VPPSVT of a power supply line that is connected to the end of the anti-fuse element. If the of the anti-fuse element and the other end thereof are connected to each other by the boosted potential, thereby making potential AF_G lower than potential VPPR, then the semiconductor device stops boosting potential VPPSVT. | 10-27-2011 |
20110267901 | SWITCHED CAPACITOR BASED NEGATIVE BITLINE VOLTAGE GENERATION SCHEME - A memory device includes an array of memory cells, the memory device including a bitline biasing circuit for biasing a bitline during a write operation. The bitline biasing circuit operating to provide a negative biasing voltage to the bitline. The magnitude of the negative biasing voltage is inversely proportional to a memory cell supply voltage level provided at a memory cell supply voltage node. | 11-03-2011 |
20110273939 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a nonvolatile memory and a controller unit for the nonvolatile memory. The nonvolatile memory and the controller unit include a first logic section and a second logic section, respectively. The nonvolatile memory includes a voltage detector configured to detect a power supply voltage externally supplied to the nonvolatile memory and the controller unit, and an output of the detection is supplied to the first logic section of the nonvolatile memory provided with the voltage detector, and also to the second logic section of the controller unit and/or a logic section of at least one added nonvolatile memory via a buffer amplifier, simultaneously. | 11-10-2011 |
20110280087 | CIRCUIT FOR SUPPLYING A REFERENCE VOLTAGE IN A SEMICONDUCTOR MEMORY DEVICE FOR TESTING AN INTERNAL VOLTAGE GENERATOR THEREIN - A reference voltage supplying circuit can include an internal reference voltage generating unit configured to generate an internal reference voltage, a pad configured to receive an external reference voltage, a switching unit selectively configured to supply the internal reference voltage or the external reference voltage to an internal voltage generator in a test mode. | 11-17-2011 |
20110286288 | DYNAMIC ADJUSTMENT OF REFERENCE VOLTAGE IN A COMPUTER MEMORY SYSTEM - A method provides improved signal quality in a computer memory system. In one embodiment, a digital signal is generated having a voltage interpreted with respect to a reference voltage. The reference voltage is dynamically adjusted as a function of the traffic intensity at which the digital signal is directed to a particular receiver. A training phase may be performed for each DIMM of the memory system, to construct a lookup table correlating suitable reference voltages with different traffic intensities. The lookup table may be referenced during a subsequent execution phase, to dynamically select a reference voltage according to changing traffic intensity. The dynamically selected reference voltage value may be enforced by using transistors to selectively recruit resistors of a resistor network. | 11-24-2011 |
20110310679 | DEVICES, SYSTEMS, AND METHODS FOR A POWER GENERATOR SYSTEM - Methods, devices, and systems are provided for a power generator system. The power generator system may include a control device configured to output a first reference voltage and a second reference voltage that define a dead band range. The control device may be configured to independently adjust the first reference voltage and the second reference voltage. The power generator system may also include a power generator operably coupled to the control device, and the power generator may be configured to receive the first reference voltage and the second reference voltage and to output a voltage that is greater than or substantially equal to the first reference voltage and less than or substantially equal to the second reference voltage. | 12-22-2011 |
20120002489 | SIGNAL DRIVER CIRCUIT HAVING ADJUSTABLE OUTPUT VOLTAGE FOR A HIGH LOGIC LEVEL OUTPUT SIGNAL - A signal driver circuit having an adjustable output voltage for a high-logic level output signal. The signal driver circuit includes a signal driver configured to output a first logic level signal having a first voltage and output a second logic level signal having a second voltage according to an input signal. A voltage controlled voltage supply coupled to the signal driver provides the first voltage for the first logic level signal. The magnitude of the first voltage provided by the voltage controlled voltage supply is based on a bias voltage. A bias voltage generator can be coupled to the voltage controlled voltage supply to provide the bias voltage. | 01-05-2012 |
20120026807 | SEMICONDUCTOR MEMORY CHIP AND INTEGRATED CIRCUIT - A semiconductor memory chip includes: a driving voltage reception unit configured to receive a power supply voltage and a ground voltage; a first data driving unit configured to be supplied with the power supply voltage and the ground voltage, and drive first data to output the driven first data through a first data line; a second data driving unit configured to be supplied with the power supply voltage and the ground voltage, and drive second data to output the driven second data through a second data line; and a MOS transistor coupled between the first data line and the second data line. | 02-02-2012 |
20120057416 | SRAM LEAKAGE REDUCTION CIRCUIT - A method and system are provided for maintaining a virtual ground node of an SRAM memory array at a minimum level sufficient for maintaining data retention. A circuit can maintain the virtual ground node at a virtual ground reference voltage of V | 03-08-2012 |
20120075936 | BIT LINE NEGATIVE POTENTIAL CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, a bit line negative potential circuit includes a bit line capacitance compensation capacitor which compensates the capacitance of a bit line and a peripheral capacitance compensation capacitor which compensates the peripheral capacitance of the bit line. After the bit line is switched to a low potential, the bit line is driven based on a charging voltage of the bit line capacitance compensation capacitor and the peripheral capacitance compensation capacitor. | 03-29-2012 |
20120092938 | SEMICONDUCTOR MEMORY - Semiconductor memory including a reference amplifier and a high-speed start-up circuit having four FETs. The reference amplifier supplies the reference voltage to a sense amplifier via a reference voltage supply line. The high-speed startup circuit has four FETs. The first FET is turned on to apply a first voltage onto a first line when the enable signal indicates deactivation. The second FET is turned on to apply ground potential onto the first line when the voltage on the reference voltage supply line is higher than a gate threshold voltage value. The third FET is turned on to generate the first voltage when the enable signal indicates activation. The fourth FET is turned off when the first line is at ground potential and is turned on to supply the first voltage from the third FET onto the reference voltage supply line when the first voltage is applied onto the first line. | 04-19-2012 |
20120099388 | INTERNAL VOLTAGE GENERATOR OF SEMICONDUCTOR MEMORY DEVICE - An internal voltage generator of a semiconductor memory device includes a proportional to absolute temperature (PTAT) current generator configured to generate a PTAT current having a varying current in proportion to a temperature change, a current control circuit configured to generate an internal current identical with the PTAT current and generate an internal voltage based on the internal current, and an offset circuit configured to control the internal voltage to a set voltage level. | 04-26-2012 |
20120106269 | MEMORY CIRCUIT AND METHOD OF OPERATING THE SAME - The present application discloses a memory circuit having a first data line configured to carry a first data line signal and a second data line configured to carry a second data line signal. Further, a first driver is coupled to the first data line and the second data line and configured to establish a first current path for the first data line responsive to the second data line signal. Similarly, a second driver is coupled to the first data line and the second data line and configured to establish a second current path for the second data line responsive to the first data line signal. The memory circuit further has a first driver enabling line configured to selectively enable the first driver and a second driver enabling line configured to selectively enable the second driver. | 05-03-2012 |
20120127807 | MEMORY INSTRUCTION INCLUDING PARAMETER TO AFFECT OPERATING CONDITION OF MEMORY - Subject matter disclosed herein relates to techniques to operate memory. | 05-24-2012 |
20120140580 | INTEGRATED CIRCUIT HAVING VOLTAGE GENERATION CIRCUITRY FOR MEMORY CELL ARRAY, AND METHOD OF OPERATING AND/OR CONTROLLING SAME - A method of generating a voltage on an integrated circuit device comprising a memory cell array including (i) a plurality of memory cells, arranged in a matrix of rows and columns, and (ii) a plurality of bit lines, wherein each bit line includes a plurality of memory cells. The integrated circuit device further comprises voltage generation circuitry, coupled to a plurality of the bit lines, to (i) apply a first voltage to a first group of associated bit lines, (ii) apply a second voltage to a second group of associated bit lines, (iii) generate a third voltage by connecting the first group of associated bit lines and the second group of associated bit lines, and (iv) output the third voltage. Also, disclosed is a method of operation and/or control of such an integrated circuit device as well as such voltage generation circuitry. | 06-07-2012 |
20120147679 | METHOD FOR CONDUCTING REFERENCE VOLTAGE TRAINING - A method for conducting reference voltage training includes setting levels of a reference voltage in response to code signals and receiving and storing data for the respective levels of the reference voltage, and simultaneously outputting the stored data. | 06-14-2012 |
20120188831 | POWER-OFF APPARATUS, SYSTEMS, AND METHODS - Some embodiments include apparatus, systems, and methods having a voltage generator to generate a voltage, a memory cell including a storage node associated with a storage node voltage, and a power controller to provide a signal to the voltage generator such that the voltage generated by the voltage generator rises from a voltage less than a reference voltage to a voltage less than the storage node voltage, and such that the voltage generated by the voltage generator is less than or equal to the storage node voltage, at least partially in response to the apparatus entering into a mode. Other embodiments are described. | 07-26-2012 |
20120224437 | NON-VOLATILE MEMORY DEVICE USING VARIABLE RESISTANCE ELEMENT WITH AN IMPROVED WRITE PERFORMANCE - A non-volatile memory device using a variable resistive element is provided. The non-volatile memory device includes a memory cell array having a plurality of non-volatile memory cells, a first voltage generator configured to generate a first voltage, a voltage pad configured to receive an external voltage that has a level higher than the first voltage, a write driver configured to be supplied with the external voltage and configured to write data to the plurality of non-volatile memory cells selected from the memory cell array; a sense amplifier configured to be supplied with the external voltage and configured to read data from the plurality of non-volatile memory cells selected from the memory cell array, and a row decoder and a column decoder configured to select the plurality of non-volatile memory cells included in the memory cell array, the row decoder being supplied with the first voltage and the column decoder being supplied with the external voltage. | 09-06-2012 |
20120275242 | VSS-SENSING AMPLIFIER - Some embodiments regard a circuit comprising a memory cell, a first data line, a second data line, a sensing circuit coupled to the first data line and the second data line, a node selectively coupled to at least three voltage sources via at least three respective switches, a fourth switch, and a fifth switch. A first voltage source is configured to supply a retention voltage to the node via a first switch. A second voltage source is configured to supply a ground reference voltage to the node via a second switch, and a third voltage source is configured to supply a reference voltage to the node via a third switch. The fourth switch and fifth switch are configured to receive a respective first control signal and second control signal and to pass a voltage at the node to the respective first data line and second data line. | 11-01-2012 |
20120300561 | MEMORY DEVICES AND PROGRAM METHODS THEREOF - Memory devices and program methods thereof, the memory devices including a memory cell array with a three-dimensional structure, a voltage generator configured to supply a pass voltage and a program voltage to the memory cell array, and a control logic configured to make the rising slope of the pass voltage variable with a program loop during a program operation. The memory device may improve a program speed by adjusting the rising slope of the pass voltage according to the program loop. | 11-29-2012 |
20120307573 | SEMICONDUCTOR DEVICE - A semiconductor device includes first and second bit lines, and a transistor coupled between the first and second bit lines. The semiconductor device further includes a substrate bias control circuit that supplies one of a first substrate bias voltage and a second substrate bias voltage to the transistor. By controlling the substrate bias voltage of the transistor, high-speed equalization is performed, and an increase in leak current at times of standby and activation is prevented. | 12-06-2012 |
20120314514 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes word lines stacked over a substrate having a plurality of memory block regions, select lines arranged over the word lines, vertical channel layers formed to penetrate through the select lines and the word lines and extending to the substrate, and a charge trap layer disposed between the word lines and the vertical channel layers, wherein the stacked word lines are separated by memory block groups that each include two or more memory block regions. | 12-13-2012 |
20120314515 | SEMICONDUCTOR MEMORY DEVICE - In a semiconductor memory device, the output of a regulator is coupled to the inputs of first and second switches, the output of the first switch is coupled to a path for supplying the drain voltage of a memory cell in the first mode, and the output of the second switch is coupled to a path for supplying the gate voltage of the memory cell in the second mode. A fourth switch is placed in parallel with the second switch: the output of the fourth switch is coupled to the output of the second switch, to supply the gate voltage of the memory cell in the first mode. Thus, one regulator is used as both the regulator for the drain voltage of the memory cell and the regulator for the gate voltage of the memory cell. | 12-13-2012 |
20130003468 | MEMORY MODULE BUS TERMINATION VOLTAGE (VTT) REGULATION AND MANAGEMENT - Embodiments of the present disclosure describe memory module bus termination voltage (VTT) regulation and management techniques and configurations. A method includes receiving, by a register, a signal that is driven over a bus to a memory device comprising a plurality of memory cells and setting, within the register, a termination voltage (VTT) for the bus based on the signal. Other embodiments may be described and/or claimed. | 01-03-2013 |
20130051161 | APPARATUSES AND METHODS INCLUDING MEMORY WRITE OPERATION - Some embodiments include apparatuses and methods having memory cells and access lines coupled to the memory cells. In one such apparatus, the access lines include a first access line and a second access line. The first access line can be adjacent to the second access line. The memory cells include a memory cell associated with the second access line. A module can be configured to apply a voltage to the first access line during an operation of accessing the memory cell associated with the second access line, and to place the second access line in a floating state during at least a portion of a time interval within the operation. Other embodiments including additional apparatus and methods are described. | 02-28-2013 |
20130064021 | SENSE AMPLIFIER WITH FAST BITLINE PRECHARGE MEANS - The disclosure relates to a sense amplifier comprising a cascode transistor and means for biasing the cascode transistor, supplying a control voltage to a gate terminal of the cascode transistor. The means for biasing the cascode transistor comprise means for isolating the gate terminal of the cascode transistor from the output of the voltage generator during a first period of the precharge phase, so as to boost the bitline voltage, then for linking the gate terminal to the output of the voltage generator during a second period of the precharge phase. Application in particular to sense amplifiers for non-volatile memories. | 03-14-2013 |
20130070541 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes a plurality of memory blocks vertically arranged, first and second row decoder groups configured to couple first and second local global word lines and the word lines of upper memory blocks among the plurality of memory blocks, third and fourth row decoder groups configured to couple third and fourth local global word lines and the word lines of lower memory blocks among the plurality of memory blocks, a first local decoder switch configured to couple a plurality of global lines and the first or second local global word lines, a second local decoder switch configured to couple the plurality of global lines and the third or fourth local global word lines, and a high voltage generator configured to supply operating voltages to the plurality of global word lines. | 03-21-2013 |
20130094305 | DEVICE FOR SUPPLYING A HIGH ERASE PROGRAM VOLTAGE TO AN INTEGRATED CIRCUIT - The disclosure relates to a device for supplying to at least one integrated circuit a high voltage for erasing and/or programming of a memory. The device includes at least one contact terminal linked to at least one contact terminal of the integrated circuit, a monitor for monitoring a data signal received by the integrated circuit and detecting in the data signal a write command of the memory, and a voltage supplier for applying the high voltage to a terminal of the integrated circuit when a write command of the memory has been detected by the monitor. | 04-18-2013 |
20130107641 | SEMICONDUCTOR SYSTEM INCLUDING SEMICONDUCTOR DEVICE | 05-02-2013 |
20130107642 | VOLTAGE GENERATOR OF NONVOLATILE MEMORY DEVICE | 05-02-2013 |
20130135945 | DIMM Memory Module Reference Voltage Switching Circuit - “A non-volatile memory module includes a volatile memory circuit; an interface to a reference voltage source external to the module providing an external reference voltage to the volatile memory circuit by which the volatile memory circuit and external devices may communicate reliably at high speeds; an internal reference voltage generator; and a control circuit adapted to cause the volatile memory circuit to be decoupled from using the external reference voltage and coupled to using a reference voltage from the internal reference voltage generator upon the non-volatile memory module ceasing to draw power from an external power source.” | 05-30-2013 |
20130148439 | MEMORY CIRCUITS, SYSTEMS, AND OPERATING METHODS THEREOF - A memory circuit including at least one memory cell connected to a bit line. The memory circuit further includes a means for providing a bit line reference voltage VBL | 06-13-2013 |
20130155787 | Digital Voltage Boost Circuit - A digital voltage boost circuit, optionally working in parallel with an analog voltage regulator, periodically injects a constant amount of current each cycle into the bit line of a high density memory array to eliminate the bias voltage reduction which would otherwise occur. This results in a much faster recovery time and reduces the semiconductor real estate required. A pulse generator in the boost circuit generates one or more current modulation signals which control corresponding current supply devices in a current source. The boost circuit drives a constant amount of current to the bias voltage node each memory cycle. | 06-20-2013 |
20130188431 | TEMPERATURE COMPENSATION OF CONDUCTIVE BRIDGE MEMORY ARRAYS - Methods for operating a semiconductor memory array including dynamically adjusting control line voltages (e.g., unselected word line or unselected bit line voltages) based on one or more array conditions associated with the semiconductor memory array are described. The one or more array conditions may include a temperature associated with the semiconductor memory array or a particular number of write cycles associated with the semiconductor memory array. In some embodiments, an intermediate voltage is generated based on the one or more array conditions and applied to the unselected word lines and the unselected bit lines of the semiconductor memory array. The one or more intermediate voltages may be generated such that a first voltage difference across unselected memory cells sharing a selected word line is different from a second voltage difference across other unselected memory cells sharing a selected bit line based on the one or more array conditions. | 07-25-2013 |
20130188432 | INTERNAL VOLTAGE GENERATION CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE, AND SEMICONDUCTOR MEMORY DEVICE - An internal voltage generation circuit includes a vblh voltage generation circuit that generates a voltage vblh that is supplied as a high-voltage power supply of a sense amplifier, and a voltage distribution control circuit that has a first current source that pulls down an output node and a second current source that pulls up the output node. The output node is pulled down by the first current source operating, and the voltage thereof is maintained at a voltage that corresponds to a lower limit of a detection voltage value. The output node is pulled up by the second current source operating, and the voltage thereof is maintained at a voltage that corresponds to an upper limit of the detection voltage value. | 07-25-2013 |
20130201768 | INTERNAL VOLTAGE GENERATING CIRCUIT, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND METHOD OF GENERATING INTERNAL VOLTAGE - An internal voltage generating circuit and a semiconductor memory device including the internal voltage generating circuit are disclosed. The internal voltage generating circuit includes a first voltage generating circuit, a second voltage generating circuit, and a third voltage generating circuit. The first voltage generating circuit stabilizes a first external supply voltage to generate a first internal voltage. The second voltage generating circuit stabilizes the first external supply voltage and a second external supply voltage to generate a second internal voltage having a voltage level higher than the first internal voltage. The third voltage generating circuit stabilizes the second internal voltage to generate a third internal voltage having a voltage level lower than the second internal voltage. Accordingly, the semiconductor memory device may be insensitive to a change in an external supply voltage and have small power consumption. | 08-08-2013 |
20130208550 | SUPPLY INDEPENDENT DELAYER - Electronic apparatus, systems, and methods can include a delayer having an inverter chain, where each inverter of the chain can be operatively regulated using current generators to control variation of the delay time of the delayer. In various embodiments, current generators can be arranged to provide reference voltages to each inverter stage of an inverter chain. Additional apparatus, systems, and methods are disclosed. | 08-15-2013 |
20130235678 | NON-VOLATILE MEMORY ARRAY ARCHITECTURE OPTIMIZED FOR HI-RELIABILITY AND COMMERCIAL MARKETS - A sense amplifier arrangement includes a first sense amplifier having a first input and a second input. A second sense amplifier has a first input and a second input. A switching circuit is configured to selectively couple the first input of the first sense amplifier to a first bit line in the array and the second input of the first sense amplifier to a first bit line in the array to selectively couple the first input of the first sense amplifier to the first bit line in the array, the first input of the second sense amplifier to the second bit line in the array, and the second inputs of the first and second sense amplifiers to a reference voltage. | 09-12-2013 |
20130242675 | NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF PROGRAMMING - A three-dimensional nonvolatile memory device comprises a plurality of cell strings arranged perpendicular to a substrate. The nonvolatile memory device is programmed by identifying a selected word line and a plurality of unselected word lines connected to at least one of the cell stings, and sequentially applying a negative voltage and a pass voltage to the selected and unselected word lines, and then applying a program voltage to the selected word line while continuing to apply the pass voltage to the unselected word lines. | 09-19-2013 |
20130250702 | SEMICONDUCTOR MEMORY AND VOLTAGE OUTPUT MEASURING METHOD OF THE SEMICONDUCTOR MEMORY - A semiconductor memory device includes a first comparative device, to which first and second voltages are input; a first capacitor, which accumulates the electrical potential of a first node; a power source, which outputs the first electric current to a second node; a resistor, which generates a third voltage in the second node; a second capacitor, which accumulates the electric potential of the second node; first switches, which make a common connection at a third node possible for the first node and the second node, to which the first capacitor and the second capacitor are connected respectively; and a second comparison device, which uses as an input voltage a fourth voltage, which is obtained as a result of the charge share between the first and the second capacitors and the electrical potential of a fourth node, and equalizes the electrical potential of the fourth node with the fourth voltage. | 09-26-2013 |
20130258789 | SEMICONDUCTOR MEMORY AND METHOD OF OPERATING SEMICONDUCTOR MEMORY - Deterioration of holding characteristics due to fluctuations in power supply voltage VDD is prevented. During ting ending in one of memory circuits, a pair of bit lines in the other memory circuit is controlled to a dummy-bit-line voltage ranging from a ground voltage to ½×VDD. In a subsequent precharge period, a pair of bit lines in one of the memory circuits and the pair of bit lines in the other memory circuit are coupled to a reference voltage generating circuit. | 10-03-2013 |
20130294177 | MEMORY DEVICES AND CONTROL METHODS THEREOF - A memory device is provided. The memory device includes a first signal line, a memory cell array, first and second voltage adjustment circuits. The memory cell array is divided into first and second areas and includes first memory cells in the first area and second memory cells in the second area. The first and second memory cells are coupled the first signal line. Each of the first and second memory cells has a reference node. The first voltage adjustment circuit adjusts voltages at the reference nodes of the first memory cells. The second voltage adjustment circuit adjusts voltages at the reference nodes of the second memory cells. The reference nodes of the first memory cells are coupled to a ground through the first voltage adjustment circuit. The reference nodes of the second memory cells are coupled to the ground through the second voltage adjustment circuit. | 11-07-2013 |
20130301365 | DEDICATED REFERENCE VOLTAGE GENERATION CIRCUIT FOR MEMORY - A memory includes a data pin, an address pin, and a reference voltage generation circuit. The reference voltage generation circuit includes a first reference voltage generation circuit and a second reference voltage generation circuit. The first reference voltage generation circuit is electronically connected to the data pin, and supplies a reliable first reference voltage to the data pin. The second reference voltage generation circuit is electronically connected to the address pin, and supplies a reliable second reference voltage to the address pin. | 11-14-2013 |
20130308396 | DRIVER FOR SEMICONDUCTOR MEMORY AND METHOD THEREOF - A driver for a semiconductor memory includes: a selection controller configured to output a target charge current select signal and a bucket charge current select signal in response to an inputted memory cell address and a target charge current value and a bucket charge current value, which are to be applied to a memory cell of the memory cell address; a current supply unit configured to supply a target charge current to the memory cell of the memory cell address in response to the target charge current select signal; and a bucket charge current supply unit configured to supply a bucket charge current to the memory cell of the memory cell address, in order to pre-charge the memory cell of the memory cell address in response to the bucket charge current select signal. | 11-21-2013 |
20130322185 | Memory Decoder Circuit - A decoder circuit includes high voltage and low voltage transistors. The decoder circuit uses the high voltage transistors during modify operations to provide a high voltage, e.g., a boosted voltage, to memory cells to change memory cell status or perform other operations. The decoder circuit uses the low voltage transistors during read operations. | 12-05-2013 |
20130322186 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes a plurality of mats each having a plurality of memory cells coupled to intersections between a plurality of word lines and bit lines which are arranged to cross each other, wherein a word line boosting voltage or negative word line voltage is driven onto a word line, depending on whether the corresponding word line is selected or not, and the negative word line voltage driven to a mat including the selected word line has a lower level than the negative word line voltage driven to a mat which does not include the selected word line. | 12-05-2013 |
20140003164 | MEMORY ARRAY WITH ON AND OFF-STATE WORDLINE VOLTAGES HAVING DIFFERENT TEMPERATURE COEFFICIENTS | 01-02-2014 |
20140003165 | SEMICONDUCTOR MEMORY APPARATUS | 01-02-2014 |
20140029356 | TEMPERATURE COMPENSATION OF CONDUCTIVE BRIDGE MEMORY ARRAYS - Methods for operating a semiconductor memory array including dynamically adjusting control line voltages (e.g., unselected word line or unselected bit line voltages) based on one or more array conditions associated with the semiconductor memory array are described. The one or more array conditions may include a temperature associated with the semiconductor memory array or a particular number of write cycles associated with the semiconductor memory array. In some embodiments, an intermediate voltage is generated based on the one or more array conditions and applied to the unselected word lines and the unselected bit lines of the semiconductor memory array. The one or more intermediate voltages may be generated such that a first voltage difference across unselected memory cells sharing a selected word line is different from a second voltage difference across other unselected memory cells sharing a selected bit line based on the one or more array conditions. | 01-30-2014 |
20140036604 | NONVOLATILE MEMORY DEVICE AND OPERATING METHOD THEREOF - A nonvolatile memory device including a memory cell arranged at a region where a word line and a bit line cross each other; a control signal generator configured to be enabled while the nonvolatile memory device operates in a test mode, and generate control signals which are not provided from an external device, based on a reference signal provided from the external device; and a control logic configured to control an operation for the memory cell according to the generated control signals. | 02-06-2014 |
20140056084 | INTEGRATED CIRCUIT AND MEMORY DEVICE - An integrated circuit includes a plurality of internal circuits, an e-fuse array circuit configured to store a data used by the internal circuits, and a fuse circuit configured to store a trimming data to set the e-fuse array circuit. | 02-27-2014 |
20140063980 | SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF - An operation method of a semiconductor memory device includes forming a first data distribution by performing a first programming operation during a first write operation, outputting a predetermined data by detecting the first data distribution on the basis of a first reference voltage corresponding to the first programming operation during a first read operation, forming a second data distribution by performing a second programming operation during a second write operation, and outputting data that is the same as the predetermined data corresponding to the first data distribution during the first read operation by detecting the second data distribution on the basis of a second reference voltage corresponding to the second programming operation during a second read operation. | 03-06-2014 |
20140063981 | VOLTAGE GENERATING CIRCUIT - A circuit includes a first transistor of a first type, a second transistor of a second type, a sense amplifier, a first data line, and a second data line. The second type is different from the first type. The first data line is coupled with a first terminal of the sense amplifier. The second data line is coupled with a second terminal of the sense amplifier. A first terminal of the first transistor is configured to receive a supply voltage. A second terminal of the first transistor, a third terminal of the first transistor, a second terminal of the second transistor, a third terminal of the second transistor are coupled together and are configured to carry a voltage. A first terminal of the second transistor is configured to receive a reference supply voltage. The first and second data lines are configured to receive a voltage value of the voltage. | 03-06-2014 |
20140063982 | METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING VOLTAGE REFERENCE TO OPTIMIZE AN I/O SYSTEM - Described herein is an apparatus for dynamically adjusting a voltage reference level for optimizing an I/O system to achieve a certain performance metric. The apparatus comprises: a voltage reference generator to generate a voltage reference; and a dynamic voltage reference control unit, coupled with the voltage reference generator, to dynamically adjust a level of the voltage reference in response to an event. The apparatus is used to perform the method comprising: generating a voltage reference for an input/output (I/O) system; determining a worst case voltage level of the voltage reference; dynamically adjusting, via a dynamic voltage reference control unit, the voltage reference level based on determining the worst case voltage level; and computing a center of an asymmetrical eye based on the dynamically adjusted voltage reference level. | 03-06-2014 |
20140104963 | MEMORY DEVICE WITH REDUCED ON-CHIP NOISE - In some examples, a memory device includes multiple memory banks equipped with an isolation switch and dedicated power supply pins. The isolation switch of each memory bank is configured to isolate the memory bank from global signals. The dedicated power supply pins are configured to connect each of the memory banks to a dedicated local power supply pads on the package substrate to provide local dedicated power supplies to each of the memory banks and to reduce voltage transfer between memory banks over conductors on the device, the device substrate, or the package substrate of the memory device. | 04-17-2014 |
20140104964 | LOW TEMPERATURE DRIFT VOLTAGE REFERENCE CIRCUIT - A voltage reference circuit includes a first enhancement-mode PMOS transistor, a first enhancement mode NMOS transistor, and a first depletion-mode PMOS transistor coupled in series between a voltage supply and a ground. A second depletion-mode PMOS transistor is coupled to the first enhancement PMOS transistor to form a feedback circuit. A first resistive device is coupled between the voltage supply and the second depletion-mode PMOS transistor, and a second resistive device is coupled between the second depletion-mode PMOS transistor and the ground. A bias circuit is coupled to a gate of the first enhancement-mode NMOS transistor. The first enhancement-mode PMOS transistor and the first depletion-mode PMOS transistor are configured to operate in saturation region. A first reference voltage across the first resistor and a second reference voltage across the second resistor are configured to be independent of the magnitude of the voltage supply and have low temperature drift. | 04-17-2014 |
20140119136 | METHOD AND APPARATUS FOR SHARING INTERNAL POWER SUPPLIES IN INTEGRATED CIRCUIT DEVICES - A method, system and apparatus for sharing internal power supplies in integrated circuit devices is described. A multiple device integrated circuit | 05-01-2014 |
20140119137 | METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING VOLTAGE REFERENCE TO OPTIMIZE AN I/O SYSTEM - Described herein is an apparatus for dynamically adjusting a voltage reference level for optimizing an I/O system to achieve a certain performance metric. The apparatus comprises: a voltage reference generator to generate a voltage reference; and a dynamic voltage reference control unit, coupled with the voltage reference generator, to dynamically adjust a level of the voltage reference in response to an event. The apparatus is used to perform the method comprising: generating a voltage reference for an input/output (I/O) system; determining a worst case voltage level of the voltage reference; dynamically adjusting, via a dynamic voltage reference control unit, the voltage reference level based on determining the worst case voltage level; and computing a center of an asymmetrical eye based on the dynamically adjusted voltage reference level. | 05-01-2014 |
20140133250 | CURRENT SENSE AMPLIFIER WITH REPLICA BIAS SCHEME - Some embodiments of the present disclosure relate to a sense amplifier architecture that facilitates fast and accurate read operations. The sense amplifier architecture includes a folded cascode amplifier for its first sense amplifier stage, and a pre-charge circuit to establish a pre-charge condition for a senseline and a reference senseline of the sense amplifier. The pre-charge circuit and the folded cascode amplifier each include one or more cascode transistors of the same size and which receive the same bias voltage on a gate thereof. This architecture provides fast and accurate read operations in a relatively small footprint, thereby providing a good blend of cost and performance. | 05-15-2014 |
20140146620 | METHODS AND APPARATUSES FOR COMPENSATING FOR SOURCE VOLTAGE - Apparatuses and methods for compensating for source voltage is described. An example apparatus includes a source coupled to a memory cell and a read-write circuit coupled to the memory cell. The apparatus further includes a sense current generator coupled to a node of the source and to the read-write circuit, the sense current generator configured to control provision of a sense current by the read-write circuit responsive to a voltage of the node of the source. | 05-29-2014 |
20140153344 | SEMICONDUCTOR MEMORY DEVICE, SYSTEM HAVING THE SAME AND METHOD FOR GENERATING REFERENCE VOLTAGE FOR OPERATING THE SAME - A semiconductor memory device and a method for generating a reference voltage needed for operating the same are disclosed. The semiconductor memory device includes a first decoder configured to generate a default set signal in response to a reset signal and a clock enable signal, a second decoder configured to generate a reference voltage set signal in response, and a reference voltage provider configured to generate an internal reference voltage. | 06-05-2014 |
20140160863 | SEMICONDUCTOR DEVICE HAVING TRANSISTOR AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME - Semiconductor device capable of preventing off-leakage of the transistor may include a pulse voltage generator configured to generate a pulse voltage, and a transistor configured to have a gate provided with the pulse voltage. The transistor is in an off state in response to the pulse voltage. | 06-12-2014 |
20140160864 | SEMICONDUCTOR DEVICE INCLUDING CURRENT COMPENSATOR - The present technology relates to an electronic device, and more particularly, to a semiconductor device. The semiconductor device includes a peripheral circuit, a power output line connected to the peripheral circuit and configured to transmit an operation voltage to the peripheral circuit, a current compensator including an OP-amplifier connected to the power output line, and a capacitor connected between an output terminal of the OP-amplifier and the power output line. | 06-12-2014 |
20140169107 | INTEGRATED CIRCUIT HAVING VOLTAGE GENERATION CIRCUITRY FOR MEMORY CELL ARRAY, AND METHOD OF OPERATING AND/OR CONTROLLING SAME - A method of generating a voltage as well as an integrated circuit device (e.g., a logic device or a memory device) having a memory cell array which includes (i) a plurality of memory cells, wherein each memory cell array including (i) a plurality of memory cells, arranged in a matrix of rows and columns, and (ii) a plurality of bit lines, wherein each bit line includes a plurality of memory cells. The integrated circuit further includes voltage generation circuitry, coupled to a plurality of the bit lines, to (i) apply a first voltage to a first group of associated bit lines, and (ii) apply a second voltage to a second group of associated bit lines, and (iii) generate a third voltage by connecting the first group of associated bit lines and the second group of associated bit lines, and (iv) output the third voltage. | 06-19-2014 |
20140198587 | PRE-CHARGE VOLTAGE GENERATION AND POWER SAVING MODES - A system includes a voltage generator to produce a pre-charge voltage signal for pre-charging one or more signals in a memory circuit. The one or more signals can be data bus lines used to access memory. The voltage generator can include an input indicating whether the memory circuit is set to a power-saving mode. According to one embodiment, the input adjusts a magnitude of the pre-charge voltage signal produced by the voltage generator. Such an embodiment is useful over conventional methods because adjusting the pre-charge voltage can result in power savings. As an example, when in the power-saving mode, the voltage generator circuit can adjust the pre-charge voltage to a value that reduces an amount of leakage current associated with a pre-charge voltage. Reducing the leakage with respect to the pre-charge voltage means that the saved power can be used for other useful purposes. | 07-17-2014 |
20140211573 | MEMORY FOR A VOLTAGE REGULATOR CIRCUIT - A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. Comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein output data are storage data stored in a plurality of memory units of the memory array processed by a program operation according to the input data, and comparison result indicates the number of different bits existing between the output data and the input data. Voltage level control unit is configured to generate a control signal according to the comparison result. Voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided. | 07-31-2014 |
20140233326 | LOW-VOLTAGE CURRENT SENSE AMPLIFER - In one embodiment, an integrated programmable device has a plurality of current sense amplifiers for reading data from non-volatile memory and a reference generator that provides common bias reference voltages to the sense amplifiers. The sense amplifiers can read data from the non-volatile memory at low power supply voltage levels (e.g., 750 mV) relative to the nominal supply level (e.g., 1.2V). Each sense amplifier has a trans-impedance amplifier that converts a memory bit-line current into a voltage level indicative of whether a selected memory cell is programmed or erased. The trans-impedance amplifier has a current mirror with a high-threshold regeneration device that lowers the sense amplifier's range of operating voltages. Each sense amplifier also has a level-shifted inverter that further lowers the sense amplifier's operating voltage range. The reference generator generates a ground-referenced bias voltage that each sense amplifier or group of sense amplifiers converts into a local, supply-referenced bias voltage. | 08-21-2014 |
20140233327 | COMPENSATION SCHEME FOR NON-VOLATILE MEMORY - Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell. | 08-21-2014 |
20140233328 | SEMICONDUCTOR DEVICE - A control logic unit generates a control signal which is activated while a power supply normally operates. A charge circuit is connected to a first node on a voltage control line supplied with a voltage generated by a voltage generation circuit, so that its capacitive element is charged with electric charge. A first discharge circuit is connected to a charge storage node of the charge circuit and discharges the stored electric charge when the control signal is activated. A second discharge circuit discharges the first node when the charge storage node has a potential exceeding a predetermined potential. | 08-21-2014 |
20140241075 | MEMORY ELEMENTS WITH SERIES VOLATILE AND NONVOLATILE SWITCHES - A memory element includes a nonvolatile switch to be set to a first low resistance state by applying a voltage higher than a positive threshold voltage and to a second high resistance state by applying another voltage more negative than a negative threshold voltage. The memory element further includes a volatile switch in series with the nonvolatile switch, the nonvolatile switch to be set to a third low resistance state by applying a current higher than a threshold current and to fourth high resistance state by applying a current lower than the threshold current. A method for operating a memory array with memory elements with series volatile and nonvolatile switches is also provided. | 08-28-2014 |
20140241076 | SEMICONDUCTOR MEMORY DEVICE, METHOD OF TESTING THE SAME AND METHOD OF OPERATING THE SAME - A method of testing a semiconductor memory device is provided. Data is written to a plurality of memory cells disposed in a memory cell block of the semiconductor memory device. A first driving voltage is applied to a first group of word lines. A second driving voltage is applied to a second group of word lines. Each word line of the first group of the word lines is interposed between two neighboring word lines of the second group of the word lines. The first driving voltage has a voltage level different from that of the second driving voltage. The data is read from first memory cells coupled to the first group to determine whether each of the first memory cells is defective. | 08-28-2014 |
20140293714 | Low-Power, High-Accuracy Current Reference For Highly Distributed Current References For Cross Point Memory - A highly distributed current reference for a solid-state memory comprises a centrally located current digital-to-analog converter (IDAC) and a plurality of remotely located tile current references. The IDAC comprises a first active device that generates a reference current, and a device that forms a first source degeneration resistance for the first active device. The IDAC outputs a voltage signal that represents a magnitude of the reference current. A remotely located tile current reference comprises a second active device and a device that forms a second source degeneration resistance for the second active device. The source degeneration resistances and capacitance coupled to the voltage signal output from the IDAC compensate for current, temperature, supply and process variations. | 10-02-2014 |
20140307513 | SEMICONDUCTOR MEMORY DEVICE AND BODY BIAS METHOD THEREOF - A semiconductor memory device is provided which includes a function block including a plurality of transistors; a body bias control unit configured to detect a command and to generate a body bias selection signal according to the detection result; and a body bias generator configured to generate a body voltage according to the body bias selection signal and to provide the body voltage to bodies of the plurality of transistors, wherein the body bias generator down-converts a power supply voltage supplied from an external device to generate the body voltage. | 10-16-2014 |
20140321220 | SEMICONDUCTOR MEMORY APPARATUS AND METHOD OF CONTROLLING EXTERNAL VOLTAGE USING THE SAME - A semiconductor memory apparatus according to the embodiment includes: an external connection terminal configured to supply an external voltage; a fuse unit configured to perform a fuse rupture operation; and an interruption circuit unit configured to respond to a test signal to determine whether the external connection terminal is connected to the fuse unit. | 10-30-2014 |
20150016197 | SEMICONDUCTOR MEMORY DEVICE THAT DOES NOT REQUIRE A SENSE AMPLIFIER - A semiconductor memory device that does not require a sense amplifier includes a memory cell group having at least one memory cell, a buffer unit, and a bias voltage unit. The buffer unit includes a tri-state buffer that has an input terminal coupled to the memory cell group, and an output terminal coupled to a data line unit. The tri-state buffer is operable to switch between a conducting state and a non-conducting state. The bias voltage unit controls supply of a preset bias voltage to the input terminal of the tri-state buffer. By using the tri-state buffer, the parasitic capacitance attributed to the memory cell can be reduced, such that no sense amplifier is required to ensure proper operation, thereby reducing power consumption. | 01-15-2015 |
20150016198 | Multiple Power Domain Circuit and Related Method - A method comprises providing a trigger signal, generating an input pulse according to the trigger signal, inverting the input pulse to generate an inverted input pulse and pulling down an output voltage using the inverted input pulse, wherein the inverted pulse is applied to a transistor of a high threshold voltage circuit. | 01-15-2015 |
20150023113 | COMPENSATION SCHEME FOR NON-VOLATILE MEMORY - Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell. | 01-22-2015 |
20150029799 | CANARY CIRCUIT WITH PASSGATE TRANSISTOR VARIATION - A canary circuit with passgate transistor variation is described herein. The canary circuit includes a memory canary circuit that has a plurality of bitcells. Each bitcell has at least a passgate transistor that is driven by a wordline voltage. The canary circuit further includes a regulator circuit that outputs a wordline voltage that accounts for a predetermined offset of a threshold voltage of the passgate transistor. In an embodiment, the regulator circuit is a subtractor circuit that generates the wordline voltage from a reference voltage based in part on the threshold voltage variation of the passgate transistor. | 01-29-2015 |
20150071012 | SUPPLY INDEPENDENT DELAYER - Electronic apparatus, systems, and methods can include a delayer having an inverter chain, where each inverter of the chain can be operatively regulated using current generators to control variation of the delay time of the delayer. In various embodiments, current generators can be arranged to provide reference voltages to each inverter stage of an inverter chain. Additional apparatus, systems, and methods are disclosed. | 03-12-2015 |
20150092501 | DRIVER FOR A SEMICONDUCTOR MEMORY AND METHOD THEREOF - A driver for semiconductor memory, comprising: a storage unit configured to match and store a memory cell address and bucket charge current data corresponding to the memory cell address; a selection controller configured to receive the memory cell address and a target charge current data, and output a bucket charge current select signal and a target charge current select signal corresponding to the bucket charge current data and the target charge current data, respectively, by referring to the storage unit; and a current supply unit configured to supply a bucket charge current and a target charge current in response to the bucket charge current select signal and the target charge current select signal, respectively. | 04-02-2015 |
20150098281 | SEMICONDUCTOR CHIP AND SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING THE SAME - A semiconductor chip includes an internal voltage generation circuit suitable for generating an internal voltage having a predetermined level, a target internal circuit suitable for performing a predetermined operation using the internal voltage, and a control circuit suitable for checking operating speed of the target internal circuit based on an operation result signal generated from the target internal circuit, and generating the control signal based on the checked operating speed, wherein a voltage level of the internal voltage for target internal circuit is controlled based on the control signal. | 04-09-2015 |
20150340073 | VOLATILE MEMORY DEVICE AND SYSTEM-ON-CHIP INCLUDING THE SAME - A volatile memory device includes a memory cell array configured to be supplied with a first power supply voltage through a first power supply line, and configured to store data based on the first power supply line; and a peripheral circuit configured to be supplied with a second power supply voltage through a second power supply line, and configured to control the memory cell array based on the second power supply line, the peripheral circuit including a self timing pulse circuit configured to determine an operation timing of the peripheral circuit, the self timing pulse circuit configured to be supplied with the first power supply voltage through the first power supply line, and the self timing pulse circuit being configured to adjust the operation timing of the peripheral circuit according to the voltage level of the first power supply voltage. | 11-26-2015 |
20160012870 | STATIC MEMORY APPARATUS AND DATA READING METHOD THEREOF | 01-14-2016 |
20160027496 | SEMICONDUCTOR DEVICE EMPLOYING DVFS FUNCTION - Disclosed herein is a device that includes: a memory cell array including a plurality of memory cells, the memory cell array operates on a first internal voltage; a peripheral circuit accessing selected one or ones of the memory cells, the peripheral circuit operates on a second internal voltage; a first internal voltage generation circuit that supplies the first internal voltage to the memory cell array; and a second internal voltage generation circuit that supplies the second internal voltage to the peripheral circuit. The second internal voltage generation circuit sets the second internal voltage to a first voltage value in a first mode, and to a second voltage value that is different from the first voltage value in a second mode. The first internal voltage generation circuit sets the first internal voltage to a third voltage value in both the first and second modes. | 01-28-2016 |
20160071554 | VOLTAGE GENERATING CIRCUIT - A circuit includes a first transistor of a first type, a second transistor of a second type, a sense amplifier, a first data line coupled with a first terminal of the sense amplifier, and a second data line coupled with a second terminal of the sense amplifier. The second type is different from the first type. A first terminal of the first transistor is configured to receive a supply voltage. A second terminal of the first transistor, a third terminal of the first transistor, a second terminal of the second transistor, a third terminal of the second transistor are coupled together and are configured to carry a voltage. A first terminal of the second transistor is configured to receive a reference supply voltage. The first and second data lines are configured to receive a voltage value of the voltage. | 03-10-2016 |
20160071555 | Current-Mode Sense Amplifier and Reference Current Circuitry - An electronic circuit comprising is provided with a current sense amplifier. The amplifier comprises a reference current input terminal, a sense current input terminal, and a first output terminal. The electronic circuit includes a reference current source. The reference current source includes two reference n-FET stacks connected in series, and the reference current input terminal is coupled to a ground terminal via the two reference n-FET stacks. The electronic circuit includes a plurality of memory cells each coupled in parallel via a respective sense n-FET stack to the sense current input terminal. The amplifier is configured to generate a first logical value at the first output terminal of the amplifier in response to a sense current of the sense current input terminal being lower than a reference current of the reference current input terminal. The amplifier is further configured to generate a second logical value at the first output terminal of the amplifier in response to the sense current being higher than the reference current. | 03-10-2016 |
20160086653 | SEMICONDUCTOR DEVICE HAVING TRANSISTOR AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME - Semiconductor device capable of preventing off-leakage of the transistor may include a pulse voltage generator configured to generate a pulse voltage, and a transistor configured to have a gate provided with the pulse voltage. The transistor is in an off state in response to the pulse voltage. | 03-24-2016 |
20160155481 | METHODS AND APPARATUSES FOR COMPENSATING FOR SOURCE VOLTAGE | 06-02-2016 |
20160163358 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE - In a configuration including a memory cell that retains multilevel data by controlling the on/off state of a transistor, correct data can be read out even if a potential of data retained by turning off the transistor is changed. The memory cell controls writing or retention of data corresponding to one of a plurality of potentials by controlling an on/off state of the transistor. The write voltage generator circuit outputs a first write voltage of data to be written to the memory cell. The write voltage generator circuit obtains a read voltage of the data by reading the first write voltage written to the memory cell. The write voltage generator circuit generates a second write voltage by correcting a change of the first write voltage caused by turning off the transistor, and outputs the second write voltage to the memory cell. | 06-09-2016 |
20160180894 | DIFFERENTIAL SENSING CIRCUIT WITH DYNAMIC VOLTAGE REFERENCE FOR SINGLE-ENDED BIT LINE MEMORY | 06-23-2016 |
20160197550 | MEMORY APPARATUS, CHARGE PUMP CIRCUIT AND VOLTAGE PUMPING METHOD THEREOF | 07-07-2016 |
20160254034 | INTERNAL VOLTAGE GENERATING CIRCUIT | 09-01-2016 |
20160379694 | CAPACITIVE WORDLINE BOOSTING - In some embodiments, disclosed is a wordline boosting technique using a self-timed capacitive charge boosting approach. | 12-29-2016 |
20190147920 | METHOD FOR CONTROLLING OPERATIONS OF MEMORY DEVICE, ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF, AND ASSOCIATED ELECTRONIC DEVICE | 05-16-2019 |