| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 365189200 | Using different memory types | 21 |
| 20090034342 | MEMORY DEVICE, CONTROL METHOD FOR THE SAME, CONTROL PROGRAM FOR THE SAME, MEMORY CARD, CIRCUIT BOARD AND ELECTRONIC EQUIPMENT - A memory device includes a single or a plurality of memory chips. In the memory device (memory module), the single memory chip or each of the plurality of memory chips has a memory part storing control data such as specification data and function data, and control data stored on the memory part is rewritable. Control data stored on the memory part separately disposed on each memory chip enables separate use of the memory chip, which improves compatibility and flexibility of the memory. | 02-05-2009 |
| 20090279366 | HYBRID SOLID-STATE MEMORY SYSTEM HAVING VOLATILE AND NON-VOLATILE MEMORY - A hybrid solid-state memory system is provided for storing data. The solid-state memory system comprises a volatile solid-state memory, a non-volatile solid-state memory, and a memory controller. Further, a method is provided for storing data in the solid-state memory system. The method comprises the following steps. A write command is received by the memory controller. Write data is stored in the volatile memory in response to the write command. Data is transferred from the volatile memory to the non-volatile memory in response to a data transfer request. | 11-12-2009 |
| 20090285031 | SYSTEM AND METHOD FOR SIMULATING AN ASPECT OF A MEMORY CIRCUIT - A system and method are provided for simulating an aspect of a memory circuit. Included is an interface circuit that is in communication with a plurality of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the system for simulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. In accordance with various embodiments, such aspect may include a signal, a capacity, a timing, and/or a logical interface. | 11-19-2009 |
| 20090316492 | MEMORY CELLS, MEMORY CELL ARRAYS, METHODS OF USING AND METHODS OF MAKING - A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region. | 12-24-2009 |
| 20090323433 | DATA SENSING METHOD FOR DYNAMIC RANDOM ACCESS MEMORY - A data sensing method for a dynamic random access memory including a storage capacitor configured to store data, a bit line, a transistor connecting the storage capacitor and the bit line, a reference bit line, and a sense amplifier connecting the bit line and the reference bit line. The data sensing method comprises the steps of turning off the transistor when the stored data is a predetermined value before enabling the sense amplifier to sense the voltage of the bit line and the reference bit line, and turning on the transistor when the stored data is opposite to the predetermined value such that a charge sharing process occurs between the storage capacitor and a parasitic capacitor of the bit line before enabling the sense amplifier to sense the voltage of the bit line and the reference bit line. | 12-31-2009 |
| 20090323434 | COMBINATION MEMORY DEVICE AND SEMICONDUCTOR DEVICE - A combination memory device including a static random access memory (SRAM) and a read only memory (ROM) comprises first memory cells and second memory cells arranged in rows and columns, in which each of the first memory cells includes an SRAM cell and a ROM cell and is arranged adjacent to at least one of the second memory cells, and each of the second memory cells includes an SRAM cell and does not include a ROM cell. | 12-31-2009 |
| 20100091579 | NON-VOLATILE SEMICONDUCTOR MEMORY APPARATUS - A non-volatile semiconductor memory apparatus includes a first memory area configured to include a plurality of non-volatile memory cells, a second memory area configured to include a plurality of memory cells whose write speed is faster than the plurality of non-volatile memory cells, and a host interface configured to control the first and second memory areas, wherein the first and second memory areas are configured to be provided with the same address signal and command signal from the host interface. | 04-15-2010 |
| 20100172190 | Processor Arrays Made of Standard Memory Cells - Standard memory circuits are used for executing a sum-of-products function between data stored in the memory and data introduced into the memory. The sum-of-products function is executed in a manner substantially similar to a standard memory read operation. The memory circuits are standard or slightly modified SRAM and DRAM cells, or computing memory arrays (CAMs). | 07-08-2010 |
| 20110141822 | Source Bias Shift for Multilevel Memories - The threshold voltage range of a multilevel memory cell may be increased without using a negative voltage pump. In one embodiment, an added positive voltage may be applied to the source of the selected cell. A boost voltage may be applied to the output of a sense amplifier. Non-ideal characteristics of a buffer that supplies the voltage to the selected cell may be compensated for in some embodiments. | 06-16-2011 |
| 20110299344 | A NEW LOW VOLTAGE AND LOW POWER MEMORY CELL BASED ON NANO CURRENT VOLTAGE DIVIDER CONTROLLED LOW VOLTAGE SENSE MOSFET - A memory cell has at least two word lines and at least two bit lines. The cell also has a first select device being connected to at least one word line and one bit line and a gate capacitor element connected to at least one word line and the first select device. The cell also has a sense device being connected in series to the gate capacitor element and the first select device. The sense device is connected to at least two bit lines. | 12-08-2011 |
| 20120002486 | NONVOLATILE MEMORY APPARATUS AND METHOD FOR PROCESSING CONFIGURATION INFORMATION THEREOF - A nonvolatile memory apparatus includes a memory device including a configuration information storage block for storing configuration data groups. A configuration information processing circuit is configured to determine majorities of configuration data groups, which are outputted from the memory device during a first period as an initial stage of a power-up operation, under the control of a first control clock signal. The configuration information processing circuit is also configured to determine majorities of configuration data groups, which are outputted from the memory device during a second period after the first period, under the control of a second control clock signal having a cycle shorter than the first control clock signal. | 01-05-2012 |
| 20120002487 | NONVOLATILE MEMORY APPARATUS AND METHOD FOR PROCESSING CONFIGURATION INFORMATION THEREOF - A nonvolatile memory apparatus includes a memory device having a configuration information storage block for storing a first configuration data group and a second configuration data group having fewer bits than the first configuration data group and a configuration information processing circuit configured to determine a majority of the first configuration data group outputted from the memory device, during a first period of a power-up operation, and determine a majority of the second configuration data group outputted from the memory device, during a second period after the first period. | 01-05-2012 |
| 20120026802 | MANAGED HYBRID MEMORY WITH ADAPTIVE POWER SUPPLY - Subject matter disclosed herein relates to a memory device, and more particularly to a managed hybrid memory that includes a power supply. | 02-02-2012 |
| 20120063239 | Circuitry And Method For Indicating A Memory - Circuitry and a method for indicating a multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory types. The memory blocks can be configured into a plurality of vertically stacked memory planes. The vertically stacked memory planes may be used to increase data storage density and/or the number of memory types that can be emulated by the multiple-type memory. Each memory plane can emulate one or more memory types. The control logic blocks can be formed in a substrate (e.g., a silicon substrate including CMOS circuitry) and the memory blocks or the plurality of memory planes can be positioned over the substrate and in communication with the control logic blocks. The multiple-type memory may be non-volatile so that stored data is retained in the absence of power. | 03-15-2012 |
| 20120092935 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first memory device formed on a semiconductor substrate, including a first storage unit, a source, and a drain, a second memory device, including a second storage unit, and a bit line, wherein the second memory device is connected in series between the bit line and the drain. | 04-19-2012 |
| 20120127804 | Memory Write Error Correction Circuit - Memory circuit includes; an array, row decoder, column decoder, addressing circuit to receive an address of the data bit, control logic receiving commands and transmitting control signals to memory system blocks, and sensing and write driver circuits coupled to a selected column. A hidden read compare circuit couples between the sensing circuit and write driver, which couples an error flag to the control logic circuit responsive to a comparison between a data bit in the input latch and a data-out read from the memory array. A write error address tag memory is responsive to the error flag and is coupled to the addressing circuit via a bidirectional bus. A data input output circuit having first and second bidirectional buses to transmit and receive said data bit is provided. Write error address tag memory stores the address if the error flag is set and provides the address during a re-write operation. | 05-24-2012 |
| 20120243340 | SIGNAL PROCESSING CIRCUIT - To provide a signal processing circuit including a nonvolatile memory circuit with a novel structure, the signal processing circuit includes an arithmetic portion, a memory, and a control portion for controlling the arithmetic portion and the memory. The control portion includes a set of a volatile memory circuit and a first nonvolatile memory circuit for storing data held in the volatile memory circuit, the memory includes a plurality of second nonvolatile memory circuits, and the first nonvolatile memory circuit and the second nonvolatile memory circuit each include a transistor having a channel in an oxide semiconductor layer and a capacitor in which one of a pair of electrodes is electrically connected to a node which is set in a floating state when the transistor is turned off. | 09-27-2012 |
| 20120257460 | METHOD FOR INDICATING A NON-FLASH NONVOLATILE MULTIPLE-TYPE THREE-DIMENSIONAL MEMORY - Circuitry and a method for indicating a multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory types. The memory blocks can be configured into a plurality of vertically stacked memory planes. The vertically stacked memory planes may be used to increase data storage density and/or the number of memory types that can be emulated by the multiple-type memory. Each memory plane can emulate one or more memory types. The control logic blocks can be formed in a substrate (e.g., a silicon substrate including CMOS circuitry) and the memory blocks or the plurality of memory planes can be positioned over the substrate and in communication with the control logic blocks. The multiple-type memory may be non-volatile so that stored data is retained in the absence of power. | 10-11-2012 |
| 20140369137 | EMBEDDED MEMORY DEVICE AND MEMORY CONTROLLER INCLUDING THE SAME - An embedded memory device includes a mask ROM including a plurality of mask ROM cells and an address decoder configured to decode an address of the plurality of mask ROM cells; and an e-fuse memory configured to replace a part of data stored in the mask ROM with replacement data, the e-fuse memory including, a plurality of e-fuse memory cells configured to store the replacement data, and an e-fuse address selector configured to decode an address of the plurality of e-fuse memory cells and to selectively cause data of one or more of the plurality of e-fuse memory cells to be output based on the decoding result. | 12-18-2014 |
| 20160078911 | SEMICONDUCTOR MEMORY DEVICE HAVING COUNT VALUE CONTROL CIRCUIT - A device includes a data storing cell array including a plurality of groups of data storing cells each configured to be accessed responsive to the input of the corresponding one of the row addresses and a count value control circuit coupled to each of the groups of the data storing cells. The count value control circuit is configured to update a count value stored in each of the groups of data storing cells by a first value responsive to the input of the corresponding one of the row addresses in a first operation mode and to set the count value stored in each of the groups of the data storing cells to a second value responsive to the input of the corresponding one of the row addresses in a second operation mode. | 03-17-2016 |
| 20160148673 | FIRST DATA IN RESPONSE TO SECOND READ REQUEST - First and second read requests are received. First data is fetched in response to the first read request. The fetched first data is then stored. The fetched first data corresponds to an address of the first read request. The fetched first data is returned in response to the second read request. | 05-26-2016 |
