| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 365189180 | Bidirectional bus | 8 |
| 20100149888 | REDUCED SIGNAL INTERFACE MEMORY DEVICE, SYSTEM, AND METHOD - A memory has a serial interface. The serial interface is programmable to either use separate dedicated input and output pads, or to use one bidirectional pad. When one bidirectional pad is used, the interface signal count is reduced by one. | 06-17-2010 |
| 20110032780 | Semiconductor device - The semiconductor device includes a first pair of data lines, a second pair of data lines, a third pair of data lines, a first amplifier (SA) connected to the first pair of data lines, a first switch that controls connection between the first pair of data lines and the second pair of data lines, a second switch that controls connection between the second pair of data lines and the third pair of data lines, a second amplifier that amplifies data on the second pair of data lines, for output to the third pair of data lines, a third amplifier connected to the third pair of data lines, and a control circuit that controls the second switch forming a pair of switches. When two data lines constituting the third pair of data lines both assume a first state, the control circuit controls the second switch to be turned off, thereby controlling the second pair of data lines and the third pair of data lines to be disconnected. Output data of the first amplifier is then output to the second pair of data lines via the first switch. When the two data lines constituting the third pair of data lines assume a second state different from the first state according to data output from the third amplifier, the second switch is controlled to be turned on, thereby controlling the second pair of data lines and the third pair of data lines to be connected. Then, the first amplifier receives the data output from the first amplifier. | 02-10-2011 |
| 20110069567 | Memory device having data paths with multiple speeds - A memory device has multiple bi-directional data paths. One of the multiple bi-directional data paths is configured to transfer data at one speed. Another one of the multiple bi-directional data paths is configured to transfer data at another speed. | 03-24-2011 |
| 20110182128 | ASYNCHRONOUS/SYNCHRONOUS INTERFACE - The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode. | 07-28-2011 |
| 20110188330 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor storage device includes: a plurality of memory cell arrays; a plurality of bidirectional data buses provided in correspondence with respective ones of the plurality of memory cell arrays; a plurality of bidirectional buffer circuits, which are provided in correspondence with respective ones of the memory cell arrays, capable of connecting adjacent bidirectional data buses serially so as to relay data in the bidirectional data buses; and a control circuit for controlling activation of the bidirectional buffer circuits. The bidirectional buffer circuit is arranged so as to invert logic and the bidirectional buffer circuit is arranged so as not to invert logic. | 08-04-2011 |
| 20120039136 | CIRCUITS AND METHODS FOR REDUCING NOISE IN THE POWER SUPPLY OF CIRCUITS COUPLED TO A BIDIRECTIONAL BUS - Circuits and methods for reducing noise in the power supply of circuits coupled to a bidirectional bus are presented. The circuits and methods are responsive to an idle condition on the bidirectional bus. The control signal is applied to and changes an electrical characteristic within the receiver to generate a voltage offset. The voltage offset prevents unintended voltage transitions in the power supply of circuits coupled to the bidirectional bus from generating a signal transition on an output signal connection of the receiver. | 02-16-2012 |
| 20120314517 | ASYNCHRONOUS/SYNCHRONOUS INTERFACE - The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode. | 12-13-2012 |
| 20140003169 | CONFIGURATION OF DATA STROBES | 01-02-2014 |
