| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 365189140 | Common read and write circuit | 85 |
| 20080205168 | APPARATUS AND METHOD FOR USING A PAGE BUFFER OF A MEMORY DEVICE AS A TEMPORARY CACHE - An apparatus and method are provided for using a page buffer of a memory device as a temporary cache for data. A memory controller writes data to the page buffer and later reads out the data without programming the data into the memory cells of the memory device. This allows the memory controller to use the page buffer as temporary cache so that the data does not have to occupy space within the memory controller's local data storage elements. Therefore, the memory controller can use the space in its own storage elements for other operations. | 08-28-2008 |
| 20080232175 | CONTENT DATA STORAGE DEVICE AND ITS CONTROL METHOD - A content data storage device which stores content data which includes a wide-band content and a narrow-band content includes a buffer memory temporarily storing the content data to be externally input, a storage unit including a plurality of nonvolatile memories configured to be written for each page and storing in turn the content data to be output from the buffer memory, and a controller controlling an output from the buffer memory so as to output content data of one page to the storage unit when the content data of not less than one page is stored in the buffer memory, wherein the controller adds dummy data to the narrow-band content as the content data of one page, if the narrow-band content stored in the buffer memory reaches the prescribed capacity. | 09-25-2008 |
| 20080232176 | Portable Information Terminal - The present invention provides a portable information terminal having installed therein an IC chip. The portable information terminal includes an internal memory disposed within the IC chip driven by using power supplied via a reader/writer, which is impossible to be accessed from outside the IC chip, an external memory driven by using power from an external power source installed outside the IC chip and a data management unit that controls data write processing or data read processing executed to write data into or read data from the internal memory or the external memory in correspondence to the power supply state pertaining to the external memory. The data management unit selects data with a high access frequency or a high priority among a plurality of sets of data recorded in the external memory and records the selected data into the internal memory. | 09-25-2008 |
| 20080259698 | HIGH SPEED DUAL PORT MEMORY WITHOUT SENSE AMPLIFIER - A system includes at least one word line decoder to select word lines to activate, and a memory cell array having a plurality of memory cell devices to store data received through one or more write bit lines. At least one of the memory cell devices including a memory cell to store data received over one or more write bit lines, and a sensing inversion device coupled to the memory cell and word lines. The sensing inversion device can read data stored by the memory cell and provide the read data to one or more read bit lines when at least one of the word lines is activated for read operations. | 10-23-2008 |
| 20080291754 | Semiconductor memory device with low standby current - In an SRAM according to the present invention, an internal power supply voltage for a memory cell is applied to a back gate of each of P-channel MOS transistors included in an equalizer, a write driver, and a column select gate. Therefore, even if an internal power supply voltage for a peripheral circuit is shut off to reduce current consumption during standby, a threshold voltage of each of the P-channel MOS transistors is maintained at a high level, and hence a leakage current is small. | 11-27-2008 |
| 20080316840 | Input/output line sense amplifier and semiconductor memory device using the same - An input/output (I/o) line sense amplifier includes a buffer unit, a sense amplifier, and a precharge unit. The buffer unit is driven by a first level voltage to buffer a strobe signal, and the sense amplifier is driven by a second level voltage to amplify a signal of an I/O line in response to an output signal of the buffer unit. The precharge unit is driven by the first level voltage to precharge an output signal of the sense amplifier in response to the output signal of the buffer unit. | 12-25-2008 |
| 20090003092 | DEVICE SELECTION CIRCUIT AND METHOD - Embodiments of the invention take advantage of an unused state of an interface protocol (or specification), such as the ONFI specification, to control a selector circuit to assert one of a plurality of relatively localized device selection signals (e.g., chip enable signals). | 01-01-2009 |
| 20090021992 | MEMORY WITH DATA CONTROL - In an embodiment, a memory device comprises memory, a first data link, a first input, a second input, a second data link, a first output and a second output. The first data link is configured to input one or more packets into the memory device. The first input is configured to input command strobe signals into the memory device that delineate command packets that are input into the memory device via the first data link. The second input is configured to input data strobe signals into the memory device that delineate data packets that are input into the memory device via the first data link. The first and second outputs are configured to output the command strobe signal and data strobe signal, respectively. The second data link is configured to output packets from the memory device. | 01-22-2009 |
| 20090021993 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device has a command decoder responsive to a plurality of commands to set the semiconductor memory device to a normal mode, for generating control signals corresponding to the commands, respectively, and a row address prelatch circuit for holding a row address except for a bank address input together with a precharge command, and outputting the row address to a row address latch circuit, when the semiconductor memory device is in a test mode. The row address latch circuit holds the row address output from the row address prelatch circuit in synchronism with a control signal which is generated when an active command is input. The column address latch circuit holds the column address which has already been input when the active command is input, in synchronism with a control signal which is generated when either a read command or a write command is input. | 01-22-2009 |
| 20090027976 | Threshold device for a memory array - A threshold device including a plurality of adjacent tunnel barrier layers that are in contact with one another and are made from a plurality of different dielectric materials is disclosed. A memory plug having first and second terminals includes, electrically in series with the first and second terminals, the threshold device and a memory element that stores data as a plurality of conductivity profiles. The threshold device is operative to impart a characteristic I-V curve that defines current flow through the memory element as a function of applied voltage across the terminals during data operations. The threshold device substantially reduces or eliminates current flow through half-selected or un-selected memory plugs and allows a sufficient magnitude of current to flow through memory plugs that are selected for read and write operations. The threshold device reduces or eliminates data disturb in half-selected memory plugs and increases S/N ratio during read operations. | 01-29-2009 |
| 20090034345 | Eight Transistor SRAM Cell with Improved Stability Requiring Only One Word Line - An SRAM cell that is accessed by a single word line and separate access transistors for read and write operations. A pair of write bit line transfer devices provide respectively access to the right and left sides of cross coupled pull-up, pull-down transistor pairs for a write operation, and a single read bit line transistor in series with the word line transistor, when selected, reads the content of the cell. | 02-05-2009 |
| 20090052262 | SEMICONDUCTOR MEMORY DEVICE - A multiple-port semiconductor memory device capable of achieving a smaller circuit area is provided. A power supply line supplying an operation voltage of a memory cell is formed in an identical metal interconnection layer where word lines are formed and it is provided adjacent to and between corresponding first word line and second word line. Then, for example, when the same memory cell row is accessed, a voltage level of the power supply line is raised by a coupling capacitance of the word lines. Thus, even in identical-row-access, static noise margin in identical-row-access can be maintained to be as great as that in different-row-access. Therefore, for example, even when a size or the like of a driver transistor is not made larger, deterioration of static noise margin can be suppressed and a circuit area can be made smaller. | 02-26-2009 |
| 20090059688 | Single-ended read and differential write scheme - A method to read and write at least one static memory cell is provided, said cell comprising a cross-coupled inverter pair and two pass-devices wherein said method is characterized in that during read only one of the two pass-devices is selected, while for write both pass-devices are selected. Furthermore, a circuit to read and write at least one static memory cell is described, said cell comprising a cross-coupled inverter pair and two pass-devices. Said circuit is characterized in that for each pass-device of the cell an individual wordline is connected with a gate of the particular pass-device, wherein both wordlines are selected for write and a single wordline is selected for read. | 03-05-2009 |
| 20090097336 | PHASE CHANGE MEMORY DEVICE WITH IMPROVED PERFORMANCE THAT MINIMIZES CELL DEGRADATION - A phase change memory device having an improved performance that minimizes cell degradation is presented. The phase change memory device includes: a cell array, a sense amplifier, a write driving unit, and a reference level selecting unit. The cell array has a phase change resistor is configured to read/write data. The sense amplifier is configured to compare a reference voltage with a sensing voltage received from the cell array. The write driving unit is configured to supply a driving voltage corresponding to write data to the cell array. The reference level selecting unit is configured to select a read reference voltage in a read mode so as to output the reference voltage, and to select a reference voltage corresponding to input data in a write verifying mode so as to output the reference voltage. | 04-16-2009 |
| 20090116308 | Memory device and method of operating such a memory device - A memory device and method of operation is provided, the memory device having a plurality of memory cells arranged in at least one column, with each column having at least one bit line and a supply voltage line associated therewith. A capacitance exists between the supply voltage line and associated at least one bit line for each column. Control circuitry is used to control, for each column, connection of a voltage source to the associated supply voltage line. For a predetermined period during a memory access operation, the control circuitry disconnects the supply voltage line for at least the selected column from the voltage source, such that a voltage level on that supply voltage line changes in response to any change in voltage on the associated at least one bit line. This basic mechanism can be used to provide a variety of assist mechanisms, such as a write assist mechanism, a bit flip assist mechanism and a read assist mechanism. The technique of the present invention provides a particularly simple and power efficient technique for providing such assist mechanisms. | 05-07-2009 |
| 20090129176 | High Speed Array Pipeline Architecture - A memory device comprising a memory array having a plurality of memory cells, and a plurality of peripheral devices for reading data out of and writing data into the memory array, the peripheral devices include a first write driver connected to a first input/output line, the first input/output line being associated with a digitline connected to certain of the plurality of memory cells, a first read amplifier connected to the first input/output line, a first input/output device responsive to a first column select signal for connecting the first input/output line to the digitline, a second write driver connected to a second input/output line, the second input/output line being associated with the digitline, a second read amplifier connected to the second input/output line, and a second input/output device responsive to a second column select signal for connecting the second input/output line to the digitline. | 05-21-2009 |
| 20090154260 | SCAN SENSING METHOD THAT IMPROVES SENSING MARGINS - Systems and methods for improving memory cell sensing margins by utilizing an optimal reference stimulus. A stimulus component applies a plurality of different reference stimuli to a plurality of memory cells of a memory device. A sense component senses a characteristic of each memory cell of the plurality of memory cells as a function of the serially applied plurality of different reference stimuli. An analysis component computes an optimal reference stimulus by selecting one of the plurality of different reference stimuli, the one of the plurality of different reference stimuli associated with an absolute minima of number of memory cell characteristics that changed state as a function of the applied plurality of different reference stimuli | 06-18-2009 |
| 20090175097 | Method for detecting erroneous word lines of a memory array and device thereof - A method detects if a word line of a memory array is broken. The method includes writing a first datum to a memory cell when coupling a corresponding word line to a voltage source, writing a second datum different from the first datum to the memory cell when the coupling between the corresponding word line and the voltage source is decoupled, reading the stored data of the memory cell, and determining if the word line is broken according to the read data, the first datum, and the second datum. | 07-09-2009 |
| 20090175098 | SEMICONDUCTOR MEMORY DEVICE INCLUDING FLOATING BODY TRANSISTOR MEMORY CELL ARRAY AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes a memory cell array including a plurality of memory cells, where each memory cell includes a transistor with a floating body region in which majority carriers are accumulated in a steady state. In write and read operations, a first data state corresponding to the steady state is written to and read from at least one selected memory cell of the memory cell array by supplying a first bipolar current through the at least one selected memory cell, and a second data state is written to and read from the at least one selected memory cell by supplying a second bipolar current which is smaller than the first bipolar current through the at least one selected memory cell. In a refresh operation, memory cells of the memory cell array storing the second data state are refreshed | 07-09-2009 |
| 20090185435 | Method and Circuit for Implementing Enhanced SRAM Write and Read Performance Ring Oscillator - A method and circuit for implementing an enhanced static random access memory (SRAM) read and write performance ring oscillator, and a design structure on which the subject circuit resides are provided. A plurality of SRAM base blocks is connected together in a chain. Each of the plurality of SRAM base blocks includes a SRAM cell, such as an eight-transistor (8T) static random access memory (SRAM) cell, and a local evaluation block coupled to the SRAM cell. The SRAM cell includes independent left wordline input and right wordline input. The SRAM cell includes a read wordline connected high, and a true and complement write bitline pair connected low. In the local evaluation circuit, one input of a NAND gate receiving the read bitline input is connected high. A control signal is combined with an inverted feedback signal to start and stop the ring oscillator. | 07-23-2009 |
| 20090190415 | Read-write circuit for short bit line DRAM - A read-write circuit serving as a global sense amp for SBL (short bit line) DRAM is realized, wherein the read-write circuit includes a common line, such that the common line is used for connecting a read circuit, a latch circuit, a write circuit, a left select circuit and a right select circuit in the global sense amp for transferring write data to memory cells through a local sense amp and reading a stored data from the memory cells through the local sense amp. In doing so, the common line is useful for realizing a layout more effectively within a limited pitch, and also reducing area of the layout. And the read-write circuit is efficiently connected to a local sense amp in the short bit line memory architecture for reading and writing data. In addition, alternative circuits are described for implementing the read-write circuit for the short bit line DRAM. | 07-30-2009 |
| 20090201748 | REMOVABLE NONVOLATILE MEMORY SYSTEM WITH DESTRUCTIVE READ - A removable nonvolatile memory system is provided including storing read data onto a memory portion of a memory device; and accessing the memory portion including reading the read data from the memory portion, and writing predetermined data onto the memory portion after reading the memory portion. | 08-13-2009 |
| 20090207675 | WAK Devices in SRAM Cells for Improving VCCMIN - A memory circuit includes a bit line; a word line; a first power supply node having a first power supply voltage; a first power supply line connected to the first power supply node; a second power supply node selected from a group consisting of a floating node and a node having a second power supply voltage lower than the first power supply voltage; a second power supply line configured to switch connections between the first and the second power supply nodes; a write-assist-keeper (WAK) device coupling the first and the second power supply lines; and a static random access memory (SRAM) cell connected to the bit line, the word line and the second power supply line. | 08-20-2009 |
| 20090262590 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device has a command decoder responsive to a plurality of commands to set the semiconductor memory device to a normal mode, for generating control signals corresponding to the commands, respectively, and a row address prelatch circuit for holding a row address except for a bank address input together with a precharge command, and outputting the row address to a row address latch circuit, when the semiconductor memory device is in a test mode. The row address latch circuit holds the row address output from the row address prelatch circuit in synchronism with a control signal which is generated when an active command is input. The column address latch circuit holds the column address which has already been input when the active command is input, in synchronism with a control signal which is generated when either a read command or a write command is input. | 10-22-2009 |
| 20090290437 | CIRCUIT FOR AND AN ELECTRONIC DEVICE INCLUDING A NONVOLATILE MEMORY CELL AND A PROCESS OF FORMING THE ELECTRONIC DEVICE - A circuit for a nonvolatile memory cell can include a charge-altering terminal and an output terminal. The circuit can also include a first transistor having a gate electrode that electrically floats and an active region including a current-carrying electrode, wherein the current-carrying electrode is coupled to the output terminal. The circuit can further include a second transistor having a first electrode and a second electrode, wherein the first electrode is coupled to the gate electrode of the first transistor, and the second electrode is coupled to the charge-altering terminal. When changing the state of the memory cell, the second transistor can be active and no significant amount of charge carriers are transferred between the gate electrode of the first transistor and the active region of the first transistor. Other embodiments can include the electronic device itself and a process of forming the electronic device. | 11-26-2009 |
| 20090290438 | SEMICONDUCTOR MEMORY DEVICE INCLUDING WRITE SELECTORS - A semiconductor memory device includes: static memory cells arranged in a matrix; a read bit line for transmitting data read from one of the memory cells; a write bit line for transmitting data to be written to one of the memory cells; an input data line for transmitting data which is received from outside and is to be written in one of the memory cells; and a selector for selectively transmitting data of the read line or the input data line to the write bit line. | 11-26-2009 |
| 20090316500 | Memory Cell Employing Reduced Voltage - A memory array is provided having a memory cell coupled to a read word line and a write word line of the memory array and peripheral circuits for reading and writing to the memory cell. The memory cell comprises a storage element for storing a logical state of the memory cell powered at a reduced voltage during at least one functional operation and a write access circuit configured to connect the storage element to at least a first write bit line in the memory array in response to a write signal on the write word line for writing the logical state to the memory cell. The memory cell further comprises a read access circuit including an input node connected to the storage element and an output node connected to a read bit line of the memory array. The read access circuit is enabled and configured to read the logic state of the storage element in response to a read signal on the read word line. The reduced voltage is a voltage that is reduced relative to a peripheral operating voltage of at least one peripheral circuit associated with reading and/or writing of the memory cell. | 12-24-2009 |
| 20100039874 | MEMORY WITH SHARED READ/WRITE CIRCUIT - A memory includes memory cells arranged as a matrix of rows and columns between word lines and bit lines, and a set of differential read/write amplifiers for reading and writing of the memory cells and for communicating with local bit lines common to at least some of the memory cells. A read/write circuit is common to the set of differential read/write amplifiers, and a set of selection gateways selectively transfer data between the common read/write circuit and a selected differential read/write amplifier. | 02-18-2010 |
| 20100074035 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device and method to perform a read operation and a write operation effectively. The semiconductor memory device and method includes: performing a first operation for inputting and outputting data in response to a first clock signal having a first frequency; and performing a second operation for storing and reading out the data in a core block in response to a second clock signal having a second frequency, wherein the first frequency is different from the second frequency. | 03-25-2010 |
| 20100080071 | DATA STORAGE USING READ-MASK-WRITE OPERATION - Method and apparatus for writing data to a storage array, such as but not limited to an STRAM or RRAM memory array, using a read-mask-write operation. In accordance with various embodiments, a first bit pattern stored in a plurality of memory cells is read. A second bit pattern is stored to the plurality of memory cells by applying a mask to selectively write only those cells of said plurality corresponding to different bit values between the first and second bit patterns. | 04-01-2010 |
| 20100091587 | Device selection circuit and method - Embodiments of the invention take advantage of an unused state of an interface protocol (or specification), such as the ONFI specification, to control a selector circuit to assert one of a plurality of relatively localized device selection signals (e.g., chip enable signals). | 04-15-2010 |
| 20100128542 | Reference Clock and Command Word Alignment - A memory system includes a memory controller that issues command signals and a reference-clock signal to a memory device. The edge rate of the reference-clock signal is lower than the bit rate of the command signals, so the memory device multiplies the reference clock signal to develop a command-recovery clock signal with which to sample the incoming command signals. The memory controller issues the command signals as a series of multi-bit command words aligned with edges of the reference-clock signal so that the memory device can use edges of the reference clock signal for command-word alignment. | 05-27-2010 |
| 20100149885 | Memory circuit and method of writing data to and reading data from memory circuit - A disclosed memory circuit includes first and second latch circuits, each writing a write data at a timing of a clock signal and retaining the write data, the write data having been input in each of the first and second latch circuits, a data input circuit supplying the write data to each of the first and second latch circuits when a write enable signal indicates a state allowing the write data to be written, a write back circuit supplying the write data retained in the second latch circuit to the first latch circuit when the write enable signal indicates a state preventing the write data from being written, wherein a robustness against noise in the second latch circuit is more improved than that in the first latch circuit. | 06-17-2010 |
| 20100214854 | SHIFT REGISTER PROVIDING GLITCH FREE OPERATION IN POWER SAVING MODE - Disclosed is a shift register including a plurality of flip-flops configured in series to shift input data in response to an applied clock, and a drive operation controller. The drive operation controller includes; a first logic gate configured to receive and logically combine selected outputs from selected ones of the plurality of flip-flops to generate a gate output signal, a drive operation controller flip-flop configured to receive the gate output signal and retime the gate output signal in response to a first clock applied to a clock terminal of a first flip-flop in the plurality of flip-flops to generate a clock enable signal, an inverter configured to receive the clock enable signal and generate an inverted clock enable signal, and a second logic gate configured to receive and logically combine the first clock and the inverted clock enable signal to generate a second clock, wherein the second clock signal is applied to a clock terminal of at least one later stage flip-flop following the first flip-flop in the plurality of flip-flops. | 08-26-2010 |
| 20100246286 | Nonvolatile memory device, method, system including the same, and operating method thereof - In a method of operating a nonvolatile memory device, data is read using a read level, and a range of logic values for erasure-decoding the read data is set. The bits of the read data corresponding to the set range of logic values are set as erasure bits, and an erasure decoding operation is performed. | 09-30-2010 |
| 20100277992 | SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF - A semiconductor memory device includes output enable signal generation means configured to be reset in response to an output enable reset signal, count a DLL clock signal and an external clock signal, and generate an output enable signal in correspondence to a read command and an operating frequency; and activation signal generation means configured to generate an activation signal for inactivating the output enable signal generation means during a write operation interval. | 11-04-2010 |
| 20100296349 | NON-VOLATILE SEMICONDUCTOR MEMORY CIRCUIT WITH IMPROVED RESISTANCE DISTRIBUTION - Disclosed is a non-volatile semiconductor memory circuit with an improved resistance spread characteristic distinguishing set data and reset data. The non-volatile semiconductor memory circuit includes a memory cell array, and a read/write circuit block configured to differentiate the current drivability based on the mode of operation, wherein the current drivability is provided in response to a bias signal based on set or reset state of data. | 11-25-2010 |
| 20110026336 | Data Storage Using Read-Mask-Write Operation - Method and apparatus for writing data to a storage array, such as but not limited to an STRAM or RRAM memory array, using a read-mask-write operation. In accordance with various embodiments, a first bit pattern stored in a plurality of memory cells is read. A second bit pattern is stored to the plurality of memory cells by applying a mask to selectively write only those cells of said plurality corresponding to different bit values between the first and second bit patterns. | 02-03-2011 |
| 20110051534 | Semiconductor storage device and its control method - A semiconductor storage device, in which successive reading and successive writing of data having a predetermined length from and to a memory cell specified by a certain address are performed, includes a plurality of memory cells, address input terminals through which the address is input, data output terminals through which read data having the predetermined length is output, and data input terminals through which write data having the predetermine length is input. Part of the address input terminals are also used as the data output terminals. In this way, the operation of successive reading and successive writing performed in succession at the same address can be made faster without increasing the number of terminals. | 03-03-2011 |
| 20110063928 | SEMICONDUCTOR MEMORY DEVICE - A dummy cell array is provided in a memory cell array, and an intermediate buffer is provided between input/output circuits, whereby control signals to the input/output circuits can be operated at high speed and with a high frequency while the area increasing effect is reduced even in a memory with a large bit width. | 03-17-2011 |
| 20110069565 | MEMORY CELL EMPLOYING REDUCED VOLTAGE - A memory array is provided having a memory cell coupled to a read word line and a write word line of the memory array and peripheral circuits for reading and writing to the memory cell. The memory cell comprises a storage element for storing a logical state of the memory cell powered at a reduced voltage during at least one functional operation and a write access circuit configured to connect the storage element to at least a first write bit line in the memory array in response to a write signal on the write word line for writing the logical state to the memory cell. The memory cell further comprises a read access circuit including an input node connected to the storage element and an output node connected to a read bit line of the memory array. The read access circuit is enabled and configured to read the logic state of the storage element in response to a read signal on the read word line. The reduced voltage is a voltage that is reduced relative to a peripheral operating voltage of at least one peripheral circuit associated with reading and/or writing of the memory cell. | 03-24-2011 |
| 20110103160 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus is provided. The semiconductor memory apparatus comprises: first and second memory banks located a predetermined distance from each other in a first direction; a common column selection control unit located at an outside region in the first and second memory banks in the first direction, and configured to commonly control access to column areas in the first and second memory banks and generate a column selection signal that controls data access to the corresponding memory cells in the first and second memory banks; a first data read/write unit configured to sense and amplify read data transferred from the first memory bank and transfer write data to the first memory bank; and a second data read/write unit configured to sense and amplify read data transferred from the second memory bank and transfer write data to the second memory bank. The first data read/write unit and the second data read/write unit are located so as to be spaced from each other in the first direction with the memory bank interposed therebetween. | 05-05-2011 |
| 20110211400 | GLOBAL BIT SELECT CIRCUIT INTERFACE WITH FALSE WRITE THROUGH BLOCKING - A global to local bit line interface circuit for domino SRAM devices includes a pair of complementary global write bit lines in selective communication with an array of SRAM cells through corresponding local write bit lines, the complementary global write bit lines configured to write a selected SRAM cell with data presented on a pair of complementary write data input lines; a pair of complementary global read bit lines in selective communication with the array of SRAM cells through corresponding local read bit lines, the complementary global read bit lines configured to read data stored in a selected SRAM cell and present the read data on a pair of complementary read data output lines; and blocking logic configured to prevent, during a write operation, propagation of stored data from the SRAM cells out on the complementary read data output lines prior to completion of the write operation. | 09-01-2011 |
| 20110211401 | GLOBAL BIT SELECT CIRCUIT INTERFACE WITH SIMPLIFIED WRITE BIT LINE PRECHARGING - A global to local bit line interface circuit for domino SRAM devices includes a pair of complementary global write bit lines in selective communication with an array of SRAM cells through local write bit lines, the global write bit lines configured to write a selected SRAM cell with data presented on a pair of write data input lines; a pair of complementary global read bit lines in selective communication with the array through local read bit lines, the global read bit lines configured to read data stored in a selected cell and present the read data on a pair of read data output lines; and write control logic configured to control precharging of the global write bit lines independently with respect to the global read bit lines, and wherein a pulse width of write data on the global write bit lines is determined only by a global column select signal. | 09-01-2011 |
| 20110216608 | TECHNIQUES FOR READING FROM AND/OR WRITING TO A SEMICONDUCTOR MEMORY DEVICE - Techniques for reading from and/or writing to a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as an apparatus including a first memory cell array having a first plurality of memory cells arranged in a matrix of rows and columns and a second memory cell array having a second plurality of memory cells arranged in a matrix of row and columns. The apparatus may also include a data sense amplifier latch circuitry having a first input node and a second input node. The apparatus may further include a first bit line input circuitry configured to couple the first memory cell array to the first input node of the data sense amplifier latch circuitry and a second bit line input circuitry configured to couple the second memory cell array to the second input node of the data sense amplifier latch circuitry. | 09-08-2011 |
| 20110261632 | Combined Write Assist and Retain-Till-Accessed Memory Array Bias - Bias circuitry for a static random-access memory (SRAM) with a retain-till-accessed (RTA) mode and with write assist bias in a normal operating mode. The memory is constructed of multiple memory array blocks of SRAM cells. Bias devices are associated with each memory array block, and associated with one or more columns. Each bias device includes a diode-connected transistor in parallel with a shorting transistor, between a power supply voltage and a power supply bias node for cells in its column or columns. The shorting transistor receives control signals from control logic so that the diode-connected transistor for each column is shorted during read cycles, and in write cycles in which its columns are not selected; in write cycles in which its columns are selected, the shorting transistor in the bias device is turned off, so that a reduced power supply voltage is applied to the selected column. The shorting transistors for all columns in the block are turned off in the RTA mode. An additional transistor in series with the diode-connected transistor may be included, to enable a floating power supply bias mode. | 10-27-2011 |
| 20110273942 | Memory Array Having a Programmable Word Length, and Method of Operating Same - A memory cell array and device having a memory cell array (i.e., an integrated circuit device, for example, a logic device (such as, a microcontroller or microprocessor) or a memory device (such as, a discrete memory)) including electrically floating body transistors in which electrical charge is stored in the body of the transistor, and techniques for reading, controlling and/or operating such memory cell array and such device. The memory cell array and device include a variable and/or programmable word length. The word length relates to the selected memory cells of a selected row of memory cells (which is determined via address data). In one embodiment, the word length may be any number of memory cells of a selected row which is less than or equal to the total number of memory cells of the selected row of the memory array. In one aspect, write and/or read operations may be performed with respect to selected memory cells of a selected row of the memory array, while unselected memory cells of the selected row are undisturbed. | 11-10-2011 |
| 20110305095 | System and Method for Memory Array Decoding - A memory system including a memory array, and a read write/module. The memory includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells, in which each memory cell is formed at a corresponding intersection of a bit line and a word line in the memory array. The read/write module is configured to control activation of at least two memory cells in the memory array during a read operation or a write operation, wherein the at least two memory cells activated by the read/write module are located on a different word line and a different bit line in the memory array, and wherein each memory cell coupled to a same bit line of the plurality of bit lines is configured to be written to or read from based on selection of the bit line. | 12-15-2011 |
| 20110317501 | SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREOF - A semiconductor device in accordance with an aspect of the present invention includes first and second power-supply circuits each of which generates an internal power-supply voltage by converting a voltage value of a power-supply voltage into a different voltage value, a first internal circuit that receives a supply of the internal power-supply voltage from the first power-supply circuit through a first line, a second internal circuit that receives a supply of the internal power-supply voltage from the second power-supply circuit through a second line, an inter-block line that connects the first and second lines to each other, and a control circuit that operates the first and second internal circuits in a predetermined operating cycle, and controls a length of a period during which the first and second internal circuits operate simultaneously. | 12-29-2011 |
| 20120014194 | Memory Cell with Equalization Write Assist in Solid-State Memory - A solid-state memory in which write assist circuitry is implemented within each memory cell. Each memory cell includes a storage element, such as a pair of cross-coupled inverters, and an equalization gate connected between the storage nodes of the storage element. The equalization gate may be realized by two transistors in series, or as a double-gate transistor. The equalization gate is controlled by a word line indicating selection of the row containing the cell in combination with a column select signal indicating selection of the column containing the cell in a write cycle. Upon a write to a selected cell, both gates are turned on, connecting the storage nodes of the cell to one another and assisting the write of the opposite date state from that previously stored. | 01-19-2012 |
| 20120014195 | SRAM with buffered-read bit cells and its testing - An SRAM with buffered-read bit cells is disclosed (FIGS. | 01-19-2012 |
| 20120033509 | Memory data reading and writing technique - A novel circuit for reading data in solid state memory cells is presented. It can be used for any type of memory cell array but more specifically it is particularly suited for volatile memories like SRAM and DRAM. It is based on sensing the current in the ground line of the memory cell when the data is being read. This eliminates the need for detecting large voltage swings on the bit line resulting in large delays or complex sense amplification circuits. It offers the advantages of being very small in silicon area, very fast and very efficient. The read and write static noise margins are increased with respect to conventional techniques. The current can be amplified and converted to a voltage signal by a transimpedance amplifier ac coupled to a sense resistor on the ground line. The signal can be successively latched. The same technique can be used to detect when the writing of a cell has been successfully carried out. | 02-09-2012 |
| 20120075938 | Adaptive and Dynamic Stability Enhancement for Memories - Adaptive and dynamic stability enhancement for memories is described. In one example, the enhancement includes a plurality of sensors each located near a plurality of memory cells to provide a sensor voltage, a controller to receive the sensor voltage and provide a control signal based thereon, and a read/write assist circuit coupled to the controller to adjust a parameter applied to reading from and writing to a memory cell of the plurality of memory cells in response to the control signal. | 03-29-2012 |
| 20120120740 | Nonvolatile Memory Devices, Erasing Methods Thereof and Memory Systems Including the Same - Disclosed are erase methods for a memory device which includes a substrate and a plurality of cell strings provided on the substrate, each cell string including a plurality of cell transistors stacked in a direction perpendicular to the substrate. The erase method includes applying a ground voltage to a ground selection line connected with ground selection transistors of the plurality of cell strings; applying a ground voltage to string selection lines connected with selection transistors of the plurality of cell strings; applying a word line erase voltage to word lines connected with memory cells of the plurality of cell strings; applying an erase voltage to the substrate; controlling a voltage of the ground selection line in response to applying of the erase voltage; and controlling voltages of the string selection lines in response to the applying of the erase voltage. | 05-17-2012 |
| 20120120741 | NONVOLATILE MEMORY DEVICE, READ METHOD FOR NONVOLATILE MEMORY DEVICE, AND MEMORY SYSTEM INCORPORATING NONVOLATILE MEMORY DEVICE - A method of performing a read operation on nonvolatile memory device comprises receiving a read command, receiving addresses, detecting a transition of a read enable signal, generating a strobe signal based on the transition of the read enable signal, reading data corresponding to the received addresses, and outputting the read data after the strobe signal is toggled a predetermined number of times. | 05-17-2012 |
| 20120120742 | SEMICONDUCTOR DEVICE - An object is to provide a semiconductor device having a memory which can efficiently improve a yield by employing a structure which facilitates the use of a spare memory cell. The semiconductor device includes a memory cell array having a memory cell and a spare memory cell, a decoder connected to the memory cell and the spare memory cell, a data holding circuit connected to the decoder, and a battery which supplies electric power to the data holding circuit. The spare memory cell operates in accordance with an output from the data holding circuit. | 05-17-2012 |
| 20120236661 | SEMICONDUCTOR STORAGE DEVICE - According to one embodiment, when a row address of a port A matches a row address of a port B, a memory cell is accessed only from the port A by controlling a word line potential of the port A based on a third clock, and data is exchanged between a bit line of the port A and the port A based on a first clock and data is exchanged between the bit line of the port A and the port B based on a second clock. | 09-20-2012 |
| 20120257465 | Non-volatile Memory Device With Plural Reference Cells, And Method Of Setting The Reference Cells - A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality of comparators. Each of the comparators is connectable to one of the first plurality of non-volatile memory reference cells and to one of a third plurality of memory cells from among the array of non-volatile memory cells. | 10-11-2012 |
| 20120287732 | APPARATUS AND METHODS OF DRIVING SIGNAL - Apparatus and methods for driving a signal are disclosed. An example apparatus includes a pre-driver circuit and a driver circuit. The pre-driver circuit includes a step-down transistor and the driver circuit includes a pull-down transistor configured to be coupled to a reference voltage. In a first mode, the step-down transistor is configured to reduce a voltage provided to the pull-down transistor to less than a supply voltage, and in a second mode, the step-down transistor configured to provide the voltage of the supply voltage to the pull-down transistor. The pre-driver circuit of the example signal driver circuit may further include a step-up transistor configured to increase a voltage provided to a pull-up transistor of the driver circuit to greater than the reference voltage, and in the second mode, the step-up transistor configured to provide the voltage of the reference voltage to the pull-up transistor. | 11-15-2012 |
| 20120307574 | SRAM READ and WRITE Assist Apparatus - A SRAM READ and WRITE assist apparatus comprises a bit line voltage tracking block, a READ assist timer, a READ assist unit, a WRITE assist unit a WRITE control unit. The bit line voltage tracking block detects a voltage on a tracking bit line coupled to a plurality of tracking memory cells. In response to the voltage drop on the tracking bit line, the READ assist timer generates a READ assist pulse. When the READ assist pulse has a logic high state, an activated word line is pulled down to a lower voltage. Such a lower voltage helps to improve the robustness of SRAM memory circuits so as to avoid READ and WRITE failures. | 12-06-2012 |
| 20120320690 | SEMICONDUCTOR MEMORY DEVICE, INFORMATION PROCESSING SYSTEM INCLUDING THE SAME, AND CONTROLLER - A semiconductor device that includes a semiconductor substrate. First and second mode registers are provided on the semiconductor substrate and store information, respectively. First and second circuits are provided on the semiconductor substrate. The first and second circuits have substantially the same configuration. The first and second circuits perform an operation in response to the information of the first and second mode registers, respectively. | 12-20-2012 |
| 20130003471 | MEMORY CELL EMPLOYING REDUCED VOLTAGE - A memory array has a memory cell that comprises a storage element storing a logical state at a reduced voltage during at least one functional operation and a write access circuit configured to connect the storage element to at least a first write bit line in response to a write signal on the write word line for writing the logical state to the memory cell. The memory cell further comprises a read access circuit including an input node connected to the storage element and an output node connected to a read bit line of the memory array. The read access circuit is enabled and configured to read the logic state of the storage element in response to a read signal on the read word line. The reduced voltage is reduced relative to an operating voltage of at least one peripheral circuit associated with reading and/or writing of the memory cell. | 01-03-2013 |
| 20130021856 | SEMICONDUCTOR DEVICE - Disclosed herein is a device including a transistor that is connected between a bit line and a data line and turned ON by a first level in date read mode and by a second level in data write mode, the first and second levels being different from each other. The device further includes a write driver that includes an output node coupled to the data line. The write driver drives the output node in data write mode without assertion of data masking, but brings the output node into a high-impedance state in data write mode with assertion of data masking. | 01-24-2013 |
| 20130039134 | SEMICONDUCTOR DEVICE INCLUDING MEMORY CAPABLE OF REDUCING POWER CONSUMPTION - A semiconductor device includes a plurality of memory arrays and a plurality of memory array control circuits. Each of the plurality of memory array control circuits includes a read/write control circuit for controlling a read/write operation for the memory array, and a selection circuit for selecting and activating the memory array based on a clock signal and an output signal from the read/write control circuit. | 02-14-2013 |
| 20130064023 | Memory Systems and Methods for Dynamically Phase Adjusting A Write Strobe and Data to Account for Receive-Clock Drift - A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write data strobe to compensate for timing drift at the memory device. The memory controller uses read signals as a measure of the drift. | 03-14-2013 |
| 20130070543 | SEMICONDUCTOR MEMORY DEVICE INCLUDING DATA TRANSFER BUS AND DATA TRANSFER METHOD OF THE DEVICE - According to one embodiment, a semiconductor memory device includes a memory cell array, a data bus, a transfer controller, column blocks, and a column selector. The data bus is divided into stages. The transfer controller serially transfers data such that the data are respectively allocated to the stages. The column blocks temporarily stores the data. The column selector selects a column block for each of the stages from the column blocks, and transfers the data parallel between the stages and the column blocks selected for the stages. The data bus extends from one end to the other in a direction in which the column blocks are arranged, and returns from the other end to the one end. | 03-21-2013 |
| 20130077415 | CIRCUIT FOR MEMORY CELL RECOVERY - An apparatus and method for combating the effects of bias temperature instability (BTI) in a memory cell. Bit lines connecting to a memory cell contain two alternate paths criss-crossing to connect a lower portion of a first bit line to an upper portion of a second bit line, and to connect a lower portion of the second bit line to an upper portion of the first bit line. Alternative to activating transistors on the bit lines to read and write to the memory cell, transistors on the alternative paths may be activated to read and write to the memory cell from the opposite bit lines. The memory cell may be read through the bit lines to a sense amplifier, the transistors on the bit lines are subsequently deactivated and the transistors on the alternate paths are activated to write transposed bit values to the memory cell, thereby reversing the biases. | 03-28-2013 |
| 20130107644 | STORAGE DEVICE, CONTROL METHOD OF STORAGE DEVICE, AND CONTROL METHOD OF STORAGE CONTROL DEVICE | 05-02-2013 |
| 20130121090 | SEMICONDUCTOR MEMORY DEVICE, OPERATING METHOD THEREOF, AND DATA STORAGE APPARATUS INCLUDING THE SAME - A semiconductor memory device includes memory cells arranged at regions where word lines and bit lines cross each other; a randomizing and de-randomizing circuit configured to perform a first randomizing operation on data to be programmed to the memory cells, based on a seed value, so as to generate first randomized data; a data reading/writing circuit configured to perform a second randomizing operation on the first randomized data using a data inverting operation so as to generate second randomized data and program the second randomized data to the memory cells; and a control logic configured to control the randomizing and de-randomizing circuit and the data reading/writing circuit. | 05-16-2013 |
| 20130121091 | SYSTEM WITH CONTROLLER AND MEMORY - According to the system of the present invention, data (DQ) signals are outputted/received between a controller | 05-16-2013 |
| 20130141992 | VOLATILE MEMORY ACCESS VIA SHARED BITLINES - A memory includes an array of memory cells that form rows and columns. The rows of the array include memory cell pairs. The memory cells may include two cross-coupled inverters and two pass-devices that couple to alternate sides of the cross-coupled inverters. The two memory cells of a memory cell pair share a common intra-pair bitline. Adjacent memory cell pairs share a common inter-pair bitline. To perform a data read operation on a particular memory cell in a memory cell pair in the rows and columns of the array, wordline drive circuitry transmits wordline activate signals to select both the row for the data read operation and a particular one of the pair of memory cells for the data read operation. | 06-06-2013 |
| 20130194879 | Early Read After Write Operation Memory Device, System And Method - A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write data, and a read address. A memory core is coupled to the interface and includes a first memory section having a first data path and a first address path and a second memory section having a second data path and a second address path. In an embodiment of the present invention, the first data and first address path is independent of the second data and second address path. The first write data is provided on the first data path responsive to the first write address being provided on the first address path while a read data is provided on the second data path responsive to the read address being provided on the second address path. | 08-01-2013 |
| 20130201773 | NONVOLATILE MEMORY DEVICE - A nonvolatile memory device includes an operation control unit, a reference voltage generating unit, and a sensing unit. The operation control unit is configured to select a unit cell from unit cells to perform reading and writing operations. The reference voltage generating unit is configured to voltage-divide a read voltage using series-connected resistors and generate a reference voltage based on the voltage-divided read voltage. The sensing unit is configured to compare a size of a voltage through an e-fuse of the selected unit cell based on the read voltage with the reference voltage, and sense data of the e-fuse of the selected unit cell. The nonvolatile memory device also includes a read current supply unit configured to output the read voltage to the unit cells during a reading operation of the nonvolatile memory device. | 08-08-2013 |
| 20130272077 | CIRCUIT FOR MEMORY CELL RECOVERY - An apparatus and method for combating the effects of bias temperature instability (BTI) and other variability in a memory cell. Bit lines connecting to a memory cell contain two alternate paths that criss-cross to connect a lower portion of a first bit line to an upper portion of a second bit line, and to connect a lower portion of the second bit line to an upper portion of the first bit line. Alternative to activating transistors on the bit lines to read and write to the memory cell, transistors on the alternative paths may be activated to read and write to the memory cell from the opposite bit line. In this fashion, the memory cell may be read through the bit lines to a sense amplifier where the bit values are latched. While the bit values remain latched in the sense amplifier, the transistors on the bit lines are deactivated and the transistors on the alternate paths are activated. When the word line is accessed, the bit values will be written into the opposite sides of the memory cell, reversing the biases. | 10-17-2013 |
| 20130279277 | CAPACITORLESS DRAM ON BULK SILICON - A method of forming capacitorless DRAM over localized silicon-on-insulator comprises the following steps: A silicon substrate is provided, and an array of silicon studs is defined within the silicon substrate. An insulator layer is defined atop at least a portion of the silicon substrate, and between the silicon studs. A silicon-over-insulator layer is defined surrounding the silicon studs atop the insulator layer, and a capacitorless DRAM is formed within and above the silicon-over-insulator layer. | 10-24-2013 |
| 20130343136 | SRAM WITH BUFFERED-READ BIT CELLS AND ITS TESTING - An SRAM with buffered-read bit cells is disclosed (FIGS. | 12-26-2013 |
| 20140003167 | NONVOLATILE MEMORY DEVICE, OPERATING METHOD THEREOF, AND DATA STORAGE DEVICE HAVING THE SAME | 01-02-2014 |
| 20140063986 | SRAM LOCAL EVALUATION AND WRITE LOGIC FOR COLUMN SELECTION - An SRAM includes a first SRAM column having first SRAM cells and a first local evaluation logic coupled to a global bit line and a second SRAM column having second SRAM cells and a second local evaluation logic coupled to the same global bit line. The first SRAM column is selected with a first write line and the second SRAM column is selected with a second write line. | 03-06-2014 |
| 20140119138 | MEMORY ARCHITECTURE - A memory circuit includes a memory cell and a data circuit. In a write operation of the memory cell, the data circuit is configured to provide a first write logical value to the first output of the data circuit and to provide a second write logical value to the second output of the data circuit. The first write logical value is different from the second write logical value. In a read operation of the memory cell, the data circuit is configured to provide a same logical value to the first output and the second output of the data circuit. | 05-01-2014 |
| 20140140148 | SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME AND METHOD OF OPERATING THE SAME - A method of operating a semiconductor memory device includes performing a pre-read and a first main read to selected memory cells in response to a read request, and performing a second main read to the selected memory cells in response to a re-read request. | 05-22-2014 |
| 20140177353 | NONVOLATILE MEMORY APPARATUS - A nonvolatile memory apparatus includes a read/write control unit and a voltage generation unit and the memory cell. The read/write control circuit is configured to supply a bias voltage in response to a read control signal, a write control signal and data. The voltage generation unit is configured to compare a level of the bias voltage with a voltage level of a sensing node and drive the sensing node at voltage having a constant level based on a result of the comparison. The memory cell coupled with the sensing node and configured to receive the voltage having the constant level. | 06-26-2014 |
| 20140198590 | MULTIPORT MEMORY WITH MATCHING ADDRESS CONTROL - In a multiple port SRAM, a first bit cell is coupled to first and second word lines and a first and second bit line pair. A second bit cell is coupled to the first and second word lines and a third and fourth bit line pair. A first data line pair is coupled to the first bit line pair via first switching logic and to the third bit line pair via second switching logic, and a second data line pair is coupled to the second bit line pair via third switching logic and to the fourth bit line pair via fourth switching logic. If a match exists between at least portions of a first and second access address, a state of the third and forth switching logic is set such that the second bit line pair and the fourth bit line pair remains decoupled from the second data line pair. | 07-17-2014 |
| 20140204689 | APPARATUS AND METHODS OF DRIVING SIGNAL FOR REDUCING THE LEAKAGE CURRENT - Apparatus and methods for driving a signal are disclosed. An example apparatus includes a pre-driver circuit and a driver circuit. The pre-driver circuit includes a step-down transistor and the driver circuit includes a pull-down transistor configured to be coupled to a reference voltage. In a first mode, the step-down transistor is configured to reduce a voltage provided to the pull-down transistor to less than a supply voltage, and in a second mode, the step-down transistor configured to provide the voltage of the supply voltage to the pull-down transistor. The pre-driver circuit of the example signal driver circuit may further include a step-up transistor configured to increase a voltage provided to a pull-up transistor of the driver circuit to greater than the reference voltage, and in the second mode, the step-up transistor configured to provide the voltage of the reference voltage to the pull-up transistor. | 07-24-2014 |
| 20140334238 | Low Power Memory Device - A method of operation within a memory device is disclosed. The method comprises receiving address information and corresponding enable information in association with a memory access request. The address information includes a row address that specifies a row of storage cells within a storage array of the memory device, and the enable information includes first and second enable values that correspond respectively to first and second storage locations within the row of storage cells. The method involves selectively transferring data between the first and second storage locations and sense amplifier circuitry according to states of the first and second enable values. This includes transferring data between the first storage location and the sense amplifier circuitry if the first enable value is in an enable state and transferring data between the second storage location and the sense amplifier circuitry if the second enable value is in the enable state. The states of the first and second enable values may be separately controlled. | 11-13-2014 |
| 20140362651 | MEMORY DEVICE AND METHOD OPERABLE TO PROVIDE MULTI-PORT FUNCTIONALITY THEREOF - A memory device operable to provide multi-port functionality, which may comprise a single-port memory having a first operating frequency that is at least twice of a second operation frequency of a multi-port memory, a read synchronization module that synchronizes a set of read signals from the second operation frequency to the first operating frequency, a write synchronization module that synchronizes a set of write signals from the second operation frequency to the first operating frequency, a read/write signal selector that integrates a set of synchronized read signals and a set of synchronized write signals into a set of input control signals of the single-port memory, and a read out data synchronization module configured to synchronize a set of read out data from the single-port memory with the second operation frequency of the multi-port memory. | 12-11-2014 |
