| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 365189170 | Data transfer circuit | 70 |
| 20080239840 | SEMICONDUCTOR MEMORY DEVICE INCLUDING A GLOBAL INPUT/OUTPUT LINE OF A DATA TRANSFER PATH AND ITS SURROUNDING CIRCUITS - A semiconductor memory device includes an input/output line of a data transfer path and its surrounding circuits, comprising a controller which generates a control signal corresponding to command and address input in read and write operation; and a repeater which selects any one of the plurality of bank groups as the control signal to control data transfer between the selected bank group and an input/output pad. | 10-02-2008 |
| 20080266988 | MULTI- PORT MEMORY DEVICE FOR BUFFERING BETWEEN HOSTS AND NON-VOLATILE MEMORY DEVICES - A multi-port volatile memory device can include a first port that is configured for data transfer to/from an external host system and the device. A volatile main memory core is configured to store data received thereat and read requested stored data thereform. A volatile sub memory core can be configured to store data received thereat and read requested stored data therefrom. A main interface circuit can be coupled to the first port and can be configured to provide data to/from the volatile main memory core and the first port in a master mode and can be configured to provide data to/from the volatile sub memory core and the first port in a slave mode. A second port can be configured for data transfer to/from an external non-volatile memory device and the device and a sub interface circuit can be coupled to the second port and configured to provide data to/from the volatile sub memory core and the second port in the slave mode. | 10-30-2008 |
| 20080285363 | Self-feedback control pipeline architecture for memory read path applications - A memory reading apparatus transfers digital data from a memory array that is independent of external clocking rate, where the data transmission time is not limited by the external clock period, and the internal timing of controls permits flexible column selection and no conflicts in the timing between external clock signals and internal bit line sensing ready signal. The memory read apparatus has a data read path circuit and a memory read control apparatus. The data read path circuit is in communication with the memory to acquire the selected data read from the memory, synchronize the selected data, and transfer the selected data from the memory. The memory read control apparatus is in communications with the data read path circuit for selecting the data to be read from the memory, for providing self-feedback signals for synchronizing the selected data for transfer from the memory. | 11-20-2008 |
| 20080316841 | MEMORY DEVICE HAVING DATA PATHS WITH MULTIPLE SPEEDS - A memory device has multiple bi-directional data paths. One of the multiple bidirectional data paths is configured to transfer data at one speed. Another one of the multiple bidirectional data paths is configured to transfer data at another speed. | 12-25-2008 |
| 20090010082 | DATA TRANSFER APPARATUS IN SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME - A data transfer apparatus in a semiconductor memory device includes a DQ pad, a DQS pad, a DQ driver for transferring the data signal to the DQ pad according to a driver select signal, and a DQS driver for transferring data strobe signal to the DQS pad according to the driver select signal. Any one of the DQ driver and the DQS driver is activated by the driver select signal, and the driver select signal is generated by one of EMRS control code, MRS control code and test mode code. | 01-08-2009 |
| 20090027978 | Semiconductor device and semiconductor signal processing apparatus - A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width. | 01-29-2009 |
| 20090034349 | SEMICONDUCTOR DEVICE - A memory module fast in random accesses, large in capacity, and low in fabricating cost. And the memory module can assure high security. The memory module consists of a flash memory, a dynamic random access memory, and a control circuit. The control circuit enables data transfer between the flash memory and the dynamic random access memory only with a read operation for a specific address in the memory module. When reading data from the memory module, the control circuit refreshes the dynamic random access memory. Thus the present invention can realize a large capacity and low cost memory module capable of reading data fast reading and assuring high security. | 02-05-2009 |
| 20090059689 | Apparatus and method for transmitting/receiving signals at high speed - A semiconductor memory device includes: a data transferrer configured to transfer data; a main driver configured to apply the data to the data transferrer in response to a control signal; and a pre-driver configured to decrease a voltage level of the data transferrer when the voltage level of the data transferrer is higher than a logic threshold voltage, and to increase the voltage level of the data transferrer when the voltage level of the data transferrer is lower than the logic threshold voltage prior to activation of the control signal. | 03-05-2009 |
| 20090080270 | MEMORY DEVICE HAVING TERMINALS FOR TRANSFERRING MULTIPLE TYPES OF DATA - A memory device includes terminals for transferring input data and output data to and from a memory array. The memory device also includes an auxiliary circuit for receiving input auxiliary information associated with the input data and for generating output auxiliary information associated with the output data. The input and output auxiliary information include inverting codes, parity codes, temperature information and time delay information. The input and output auxiliary information are transferred to and from the memory device on the same terminals that the input data and the output data are transferred. | 03-26-2009 |
| 20090147597 | SEMICONDUCTOR MEMORY DEVICE - A first input buffer receives sequentially inputted first data. A first data selector selectively transfers the first data from the first input buffer in accordance with a data input mode. A first data alignment circuit aligns and outputs the data from the first data selector. A second input buffer receives sequentially inputted second data in accordance with the data input mode. A second data selector selectively transfers the data of the first input buffer or of the second input buffer, in accordance with the data input mode. A first data alignment circuit aligns and outputs the data from the second data selector. | 06-11-2009 |
| 20090168560 | CIRCUIT AND METHOD FOR CONTROLLING LOCAL DATA LINE IN SEMICONDUCTOR MEMORY DEVICE - The present invention relates to a semiconductor memory device, and more particularly, to a circuit and method for controlling local data lines, which can reduce loading on local data lines LIO. The circuit and method for controlling local data lines in accordance with the present invention is characterized by having different line loading of local data lines depending on positions of cell mats. In addition, local data lines between arrays are connected by a switch. Accordingly, the switch is turned on/off by address information about cell mat arrays, thereby preventing unnecessary line loading of local data lines to completely remove unnecessary loading. Moreover, the present invention reduces line loading, thereby improving data processing speed. | 07-02-2009 |
| 20090175100 | METHOD AND APPARATUS FOR STORAGE DEVICE WITH A LOGIC UNIT AND METHOD FOR MANUFACTURING SAME - Method and apparatus that relate to a storage device comprising a plurality of memory cells, an interface device configured to connect the storage device to a host system and configured to transmit signals to read and write data from the host system to the memory cells via a first and second data path, and a logic unit. The logic unit is configured to read and write data from the plurality of memory cells via the second data path, and configured to perform logic operations on data stored in the plurality of memory cells. When performing read and write operations, the first data path excludes the logic unit, and the second data path includes the logic unit. Furthermore, the logic unit is communicatively coupled between the interface device and the plurality of memory cells. Additionally, a method for manufacturing the memory device is provided. | 07-09-2009 |
| 20090175101 | Self-feedback control pipeline architecture for memory read path applications - A memory reading apparatus transfers digital data from a memory array that is independent of external clocking rate, where the data transmission time is not limited by the external clock period, and the internal timing of controls permits flexible column selection and no conflicts in the timing between external clock signals and internal bit line sensing ready signal. The memory read apparatus has a data read path circuit and a memory read control apparatus. The data read path circuit is in communication with the memory to acquire the selected data read from the memory, synchronize the selected data, and transfer the selected data from the memory. The memory read control apparatus is in communications with the data read path circuit for selecting the data to be read from the memory, for providing self-feedback signals for synchronizing the selected data for transfer from the memory. | 07-09-2009 |
| 20090196110 | INTEGRATED CIRCUIT, AND METHOD FOR TRANSFERRING DATA - An integrated circuit and a method for transferring data is provided. One embodiment provides a method for transferring data in an integrated circuit. The method includes driving a first line in accordance with data to be transferred. The data is transmitted from the first line to a second line based on a capacitive coupling. | 08-06-2009 |
| 20090196111 | PAGE BUFFER CIRCUIT OF MEMORY DEVICE AND PROGRAM METHOD - A page buffer circuit of a memory device including a plurality of Multi-Level Cells (MLCs) connected to at least a pair of bit lines includes a Most Significant Bit (MSB) latch, a Least Significant Bit (LSB) latch, a data I/O circuit, an inverted output circuit, a MSB verification circuit, and a LSB verification circuit. The MSB latch is configured to sense a voltage of a sensing node in response to a control signal and store an upper sensing data, and output an inverted upper sensing data, or store an input data and output an inverted input data. The LSB latch is configured to sense a voltage of the sensing node in response to the control signal, and store and output a lower sensing data, or store and output an input data received through the MSB latch. The data I/O circuit is connected to the MSB latch and a data I/O line, and is configured to perform the input and output of a sensing data or the input and output of a program data. | 08-06-2009 |
| 20090201750 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF MEASURING A MAXIMUM DELAY - A semiconductor integrated circuit includes a memory, a master interface circuit that performs one of receiving a data transfer request from the memory and outputting a data transfer request to the memory, a slave interface circuit that performs one of receiving data from the memory and outputting data to the memory in response to the data transfer requests, and a delay circuit that delays a data transfer end signal that indicates one of an end of a data transfer from the memory and an end of a data transfer to the memory. | 08-13-2009 |
| 20090231936 | MEMORY DEVICE HAVING STROBE TERMINALS WITH MULTIPLE FUNCTIONS - A memory device has data transceivers, write strobe transceivers, and read strobe transceivers. The data transceivers transfer input data to the memory device and transfer output data from the memory device. The write strobe transceivers transfer timing information of the input data. The read strobe transceivers transfer timing information of the output data. The memory device also has an auxiliary circuit for generating auxiliary information. The auxiliary information includes information different from the timing information of the input data and the output data. The auxiliary circuit uses the write and read transceivers to transfer the auxiliary information to and from the memory device. | 09-17-2009 |
| 20090273990 | SEMICONDUCTOR DEVICE - There is provided a semiconductor memory device, including: a plurality of bank groups each comprising a plurality of banks; a plurality of data pads grouped by a predetermined number for receiving data for the bank groups, wherein the data pads are divided into a plurality of first pad groups receiving data and a plurality of second pad groups selectively receiving data according to a data input/output option value; a first driving unit configured to drive data input via the first pad group to transfer the data input via the first pad group to the bank group corresponding to the first pad group; a second driving unit configured to drive data input via the second pad group to transfer the data input via the second pad group to the bank group corresponding to the second pad group; and a third driving unit configured to drive data input via the first pad group to transfer the data input via the first pad group to the bank group corresponding to the second pad group in response to the data input/output option value. | 11-05-2009 |
| 20090296499 | SEMICONDUCTOR MEMORY DEVICE INCLUDING A GLOBAL INPUT/OUTPUT LINE OF A DATA TRANSFER PATH AND ITS SURROUNDING CIRCUITS - A semiconductor memory device includes an input/output line of a data transfer path and its surrounding circuits, comprising a controller which generates a control signal corresponding to command and address input in read and write operation; and a repeater which selects any one of the plurality of bank groups as the control signal to control data transfer between the selected bank group and an input/output pad. | 12-03-2009 |
| 20090316501 | MEMORY MALFUNCTION PREDICTION SYSTEM AND METHOD - A memory malfunction prediction system and method, such as those that sequentially stress each row of memory cells in an array by decreasing the refresh rate of the row. Prior to doing so, the data stored in the row can be copied to a holding row, and a CRC value for the data can be generated and stored. After the test, the data stored in the row being tested can be read, and a CRC value for the data can then be generated. This after test CRC value can be compared to the stored pre-test CRC value. In the event of a match, the row can be considered to be functioning properly, and the next row can then be tested. If the CRC values do not match, a predicted malfunction of the row can be considered to exist, and corrective action can be taken, such as by repairing the row by substituting a redundant row of memory cells. | 12-24-2009 |
| 20100074036 | CURRENT MODE MEMORY APPARATUS, SYSTEMS, AND METHODS - Some embodiments include a first circuit to drive signals at first circuit output nodes, and a second circuit to generate output signals at second circuit output nodes. The second circuit includes a first transistor coupled between a supply node and a first node of the second circuit output nodes and a second transistor coupled between the supply node and a second node of the second circuit output nodes. Each of the first and second transistors includes a gate coupled to one of the first and second nodes. Other embodiments including additional apparatus, systems, and methods are disclosed. | 03-25-2010 |
| 20100142292 | LOW POWER MEMORY DEVICE - A method of operation within a memory device is disclosed. The method comprises receiving address information and corresponding enable information in association with a memory access request. The address information includes a row address that specifies a row of storage cells within a storage array of the memory device, and the enable information includes first and second enable values that correspond respectively to first and second storage locations within the row of storage cells. The method involves selectively transferring data between the first and second storage locations and sense amplifier circuitry according to states of the first and second enable values. This includes transferring data between the first storage location and the sense amplifier circuitry if the first enable value is in an enable state and transferring data between the second storage location and the sense amplifier circuitry if the second enable value is in the enable state. The states of the first and second enable values may be separately controlled. | 06-10-2010 |
| 20100202222 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes first and second sub-memory-cell areas configured to form a memory cell matrix and include a first bit line and a second bit line respectively to form a data transfer path corresponding to a predetermined memory cell, an additional bit line configured to cross the first sub-memory-cell area and form a data transfer path by being connected with the second bit line and a sensing and amplifying unit configured to sense and amplify data inputted through the additional bit line and the first bit line. | 08-12-2010 |
| 20100254202 | SYSTEM HAVING A PLURALITY OF MEMORY DEVICES AND DATA TRANSFER METHOD FOR THE SAME - The control section performs a write operation, in synchronism with a clock signal, for transferring write data to one of the plurality of memory devices, utilizing: (i) an identification information transmission period during which the control section sends the identification information of a single memory device to all of the plurality of memory devices through the data line to select the single memory device; (ii) a write data transmission period during which the control section sends a single set of write data having a prescribed size to the selected single memory device; and (iii) a response period during which the selected single memory device responds to the control section with a response signal indicating presence or absence of communication error in relation to the received set of write data. Communications between the control section and the selected memory device during the write data transmission period and the response period are repeatedly performed for each transmission of one of plural sets of write data having the prescribed size. The control section sets a frequency of the clock signal during the response period to a lower value than that of the clock signal during the write data transmission period. | 10-07-2010 |
| 20100265776 | DATA BUS POWER-REDUCED SEMICONDUCTOR STORAGE APPARATUS - In one or more of the disclosed embodiments, the number of times toggle operations of a data bus are performed at the time of a data transmission in a semiconductor storage apparatus is reduced, thereby reducing the power consumption. For example, a semiconductor storage apparatus according to one embodiment of the present invention comprises a DRF bus, a DR | 10-21-2010 |
| 20100302882 | Random Access Memory for Use in an Emulation Environment - A Random Access Memory (RAM) and method of using the same are disclosed. The RAM includes a plurality of memory cells arranged in columns and in rows with each memory cell coupled to at least one word line and at least one bit line. The RAM includes a plurality of switches with at least one of the switches coupled between two of the memory cells to allow data to be copied from one of the two memory cells to the other of the two memory cells. | 12-02-2010 |
| 20100322020 | Data Storage Systems and Methods Using Data Attribute-Based Data Transfer - Some embodiments of the present invention provide data storage systems including a plurality of memories and a control circuit coupled to the plurality of memories by a common channel. The control circuit is configured to sequentially transfer respective units of data to respective memories within each of a plurality of predetermined groups of the plurality of memories over the common channel and to transition from transferring units of data to a first one of the groups to transferring units of data to a second one of the groups based on an attribute of the units of data. The attribute may be related to a programming time associated with a unit of data. For example, the attribute may include a bit significance of the unit of data. | 12-23-2010 |
| 20110007583 | Semiconductor memory device and internal data transmission method thereof - In a semiconductor memory device and an internal data transmission method thereof, the device includes a memory controller, a pair of data lines, and a plurality of memory banks. During an internal data transmission operation, the memory controller externally receives and stores a source address and a target address in response to an externally applied command and outputs an internal control signal and an internal address signal using the source address and the target address. The internal control signal includes an internal write signal and an internal read signal. Transmission data is transmitted on the pair of data lines during the internal data transmission operation. The plurality of memory banks read the transmission data stored in a region corresponding to the source address in response to the internal read signal, transmit the transmission data on the pair of data lines, and write the transmission data transmitted on the pair of data lines in response to the internal write signal. During the internal data transmission operation, the transmission data is transmitted from the region corresponding to the source address to a region corresponding to the target address, and is not output external to the semiconductor memory device | 01-13-2011 |
| 20110075494 | DATA TRANSFER CIRCUIT - A data transfer circuit includes: an asynchronous memory to which transfer data is written from a first clock domain with a first clock and from which the written transfer data is read to a second clock domain with a second clock; a scan flip-flop whose input terminal is connected to a first position located on a data path, of the transfer data, from the asynchronous memory to the second clock domain, and whose output terminal is connected to a second position located on a data path, of the transfer data, from the asynchronous memory to the first position; and a clock selector which selects a clock to drive the scan flip-flop from the first clock and the second clock. | 03-31-2011 |
| 20110080794 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device allows a read command to be inputted thereto after a passage of a relatively short time period from a point in time where a write command has been inputted thereto. A method of operating the semiconductor memory device includes inputting a write command, inputting a read command in a preset period of time after the write command has been inputted, loading read data of a memory cell onto a data bus in response to the read command; and loading write data from outside of the semiconductor memory device onto the data bus in response to the write command. | 04-07-2011 |
| 20110085391 | Memory with improved read stability - A static random access memory is disclosed. The SRAM comprises: at least one data line for transferring data to and from the memory and at least one reset line; a plurality of storage cells each being arranged for connection to the at least one data line and the at least one reset line, each storage cell comprising: an asymmetric feedback loop, the feedback loop comprising a first access node for holding a data value when the feedback loop stores the data value and a second access node for holding a complementary version of the data value when the feedback loop stores the data value; an access device for selectively providing a connection between the at least one data line and the first access node; a reset device for selectively providing a connection between the at least one reset line and the second access node; the memory further comprising: data access control circuitry for generating control signals in response to data access requests for independently controlling the access device and the reset device to provide the connections; wherein: the data control circuitry is configured to: generate a data access control signal to trigger the access device to provide the connection between the first access node and the at least one data line in response to a write request to write a predetermined value to the storage cell, and in response to a read request to read a stored value from the storage cell; and generate a reset control signal to trigger the reset device to provide the connection between the at least one reset line and the second access node in response to a write request to write the complementary predetermined value to the storage cell. | 04-14-2011 |
| 20110222359 | APPARATUS AND METHOD FOR TRANSMITTING/RECEIVING SIGNALS AT HIGH SPEED - A semiconductor memory device includes: a data transferrer configured to transfer data; a main driver configured to apply the data to the data transferrer in response to a control signal; and a pre-driver configured to decrease a voltage level of the data transferrer when the voltage level of the data transferrer is higher than a logic threshold voltage, and to increase the voltage level of the data transferrer when the voltage level of the data transferrer is lower than the logic threshold voltage prior to activation of the control signal. | 09-15-2011 |
| 20110292746 | DATA TRANSFER CIRCUIT, METHOD THEREOF, AND MEMORY DEVICE INCLUDING DATA TRANSFER CIRCUIT - A data transfer circuit includes a first driver configured to drive a first line with data, a pattern alteration unit configured to change a pattern of the data transferred through the first line and produce a pattern-changed data, a second driver configured to drive a second line with the pattern-changed data; and a pattern restoration unit configured to receive the pattern-changed data transferred through the second line and restore the pattern of the data before the pattern change. | 12-01-2011 |
| 20110310681 | SEMICONDUCTOR DEVICE - A semiconductor device includes a bidirectional first bus arranged in common for a plurality of memory array basic units transferring write data and read data, a second bus transferring address/command, a plurality of first buffer circuits receiving addresses/command transferred to the second bus, wherein a control delay for generating the address/command and preparing write data to the first bus for write access and an output delay for outputting read data are both set to a length greater than or equal to a selection time for writing or reading of data to a memory cell of a selected area. | 12-22-2011 |
| 20120002492 | DATA TRANSFER CIRCUIT OF SEMICONDUCTOR APPARATUS - Various embodiments of a data transfer circuit of a semiconductor apparatus are disclosed. In one exemplary embodiment, the data transfer circuit may include a first data line, a second data line, a first transfer unit configured to amplify data on the first data line in response to a first control signal and transfer amplified data to the second data line, and a second transfer unit configured to electrically connect the first data line to the second data line in response to a second control signal. | 01-05-2012 |
| 20120026811 | Integrated semiconductor device - Disclosed herein is an integrated semiconductor device including: a first semiconductor device having a clock generation section, first data storage sections storing input data as transfer data, data output terminals provided, one for each of the first data storage sections, and a clock output terminal adapted to output a transfer clock; and a second semiconductor device having data input terminals which receive the transfer data, a clock input terminal adapted to receive the transfer clock, second data storage sections associated with the data input terminals respectively to store input data, and selection sections associated with the second data storage sections respectively to select either the transfer data or data shifted and output to the associated second data storage section in a first series circuit which is formed by connecting the second data storage sections in series, the selection sections supplying the selected data to the associated second data storage section. | 02-02-2012 |
| 20120106270 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME - A semiconductor memory device includes first and second memory groups that each comprise memory cells and redundancy memory cells; first main page buffers assigned to the first memory group and second main page buffers assigned to the second memory group; first main page buffers and a first redundancy page buffer coupled between the first memory group and first internal data lines and configured to store data for the program or read operation of the memory cells and the redundancy memory cells; and a data transfer circuit configured to transfer data from a first main page buffer of the first main page buffers that corresponds to the defective column of the first memory group to the at least one second redundancy page buffer before the program operation and transfer data of the at least one second redundancy page buffer to the first main page buffer. | 05-03-2012 |
| 20120218839 | DATA INTERFACE CIRCUIT, NONVOLATILE MEMORY DEVICE INCLUDING THE SAME AND OPERATING METHOD THEREOF - A data interface unit is used in a semiconductor memory device and includes a data alignment unit configured to separate consecutive input data into rising data and falling data, and a data transfer unit configured to selectively transfer the rising data and falling data to an even column line and an odd column line in response to a start column address. | 08-30-2012 |
| 20120218840 | INTEGRATED CIRCUIT - An integrated circuit includes a plurality of data lines on which data aligned by a plurality of pulse signals are loaded, a plurality of transfer lines, a data transfer unit configured to transfer the data of the plurality of data lines to the plurality of transfer lines in response to a correlation signal, a data output unit configured to output the data of the transfer line corresponding to a transmission signal activated among a plurality of transmission signals, a correlation signal generation unit configured to generate the correlation signal using a latency value and a logic value of one of the plurality of transmission signals when a command is inputted to the correlation signal generation unit, and a pulse signal generation unit configured to sequentially activate the plurality of pulse signals when the command is inputted. | 08-30-2012 |
| 20120281488 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATION THE SAME - A semiconductor memory device includes a first plane and a second plane each configured to include a plurality of memory cells, and a data transfer circuit configured to transfer first data, stored in the memory cells of the first plane, to the second plane and transfer second data, stored in the memory cells of the second plane, to the first plane when a copyback operation is performed and to transfer the first data or the second data to an I/O circuit when a read operation is performed. | 11-08-2012 |
| 20120294098 | LOCAL IO SENSE ACCELERATOR - A memory array includes: at least one differential local bit line pair; at least one differential global bit line pair; at least a column selection signal, for charging the differential local bit line pair to a predetermined voltage; at least an enable signal for coupling the differential local bit line pair to the differential global bit line pair when a voltage of the differential local bit line pair reaches a specific value; and a local sense accelerator, coupled to the differential local bit line pair, for determining a voltage of the differential local bit line pair, and enabling an accelerator signal for latching one of the differential local bit line pair and pulling the other low when the voltage reaches the specific value. | 11-22-2012 |
| 20120320692 | RANDOM ACCESS MEMORY FOR USE IN AN EMULATION ENVIRONMENT - A Random Access Memory (RAM) and method of using the same are disclosed. The RAM includes a plurality of memory cells arranged in columns and in rows with each memory cell coupled to at least one word line and at least one bit line. The RAM includes a plurality of switches with at least one of the switches coupled between two of the memory cells to allow data to be copied from one of the two memory cells to the other of the two memory cells. | 12-20-2012 |
| 20130003473 | STACKED DEVICE REMAPPING AND REPAIR - Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described. | 01-03-2013 |
| 20130033945 | SYSTEM AND METHOD FOR INTERFACING BURST MODE DEVICES AND PAGE MODE DEVICES - A burst read control circuit acts as an interface to allow a burst-read capable device to execute burst reads from a page-mode capable memory device. The burst read control circuit coordinates burst read requests from the burst-read capable device and subsequent responses from the page-mode capable memory device by accessing subsequent and contiguous memory locations of the page-mode capable memory device. | 02-07-2013 |
| 20130148447 | Reducing Power Consumption in a Memory System - Components of a memory system, such as a memory controller or memory device, that operate in different power states to reduce the overall power consumption of the memory system. In some of the power states, distribution circuitry that distributes a timing signal within the components may be powered on when the output of the distribution circuitry is needed. In other power states, the distribution circuitry may be powered off when the output of the distribution circuitry is not needed. Additionally, power states in the memory device may be triggered off memory access commands issued by the memory controller. | 06-13-2013 |
| 20130163352 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a plurality of repair fuse units configured to program repair target addresses respectively for repair target memory cells, wherein at least one of the repair fuse units is programmed with data information used for different purposes from the repair target addresses, a plurality of address comparison units each configured to compare an access target address with a corresponding address of the repair target addresses and determine whether to perform a repair operation or not, and a data transfer unit configured to transfer the data information to a corresponding circuit of the semiconductor memory device. | 06-27-2013 |
| 20130176797 | DATA OUTPUT CIRCUIT - A data output circuit includes a control signal generation block configured to generate a first transfer control signal which is produced in a first read operation and a second transfer control signal which is produced in a second read operation, where the first transfer control signal and the second transfer control signal are generated upon entry into a test mode; and an enable signal generation unit configured to generate first and second enable signals for generating first and second internal clocks, in response to the first and second transfer control signals. | 07-11-2013 |
| 20130258792 | SEMICONDUCTOR DEVICE HAVING COMPENSATION CAPACITOR TO STABILIZE POWER SUPPLY VOLTAGE - Disclosed herein is a device that includes: first and second memory cell arrays arranged in a first direction; a plurality of first bump electrodes disposed between the first and second memory cell arrays and arranged in line in a second direction crossing the first direction; a plurality of second bump electrodes disposed between the first bump electrodes and the second memory cell arrays and arranged in line in the second direction; a first area being between the first and second bump electrodes; a plurality of third bump electrodes disposed in the first area; and a first capacitor formed in the third area. | 10-03-2013 |
| 20130336074 | Hierarchical Multi-Bank Multi-Port Memory Organization - A memory system includes multiple (N) memory banks and multiple (M) ports, wherein N is greater than or equal to M. Each of the memory banks is coupled to each of the ports. Access requests are transmitted simultaneously on each of the ports. However, each of the simultaneous access requests specifies a different memory bank. Each memory bank monitors the access requests on the ports, and determines whether any of the access requests specify the memory bank. Upon determining that an access request specifies the memory bank, the memory bank performs an access to an array of single-port memory cells. Simultaneous accesses are performed in multiple memory banks, providing a bandwidth equal to the bandwidth of one memory bank times the number of ports. An additional level of hierarchy may be provided, which allows further multiplication of the number of simultaneously accessed ports, with minimal area overhead. | 12-19-2013 |
| 20130343138 | CIRCUIT AND METHOD FOR REDUCING LEAKAGE CURRENT - A circuit includes an input/output (IO) circuit, a first node configured to have a first voltage level, a second node configured to have a second voltage level, a third node, and a switching circuit. The IO circuit has a set of transistors, and the third node is coupled to bulks of the set of transistors. The switching circuit is configured to couple the first node to the third node when the IO circuit is operated in an active mode; and couple the second node to the third node when the IO circuit is operated in an inactive mode. The first voltage level causes the set of transistors to have a first threshold voltage, the second voltage level causes the set of transistors to have a second threshold voltage, and an absolute value of the second threshold voltage is greater than that of the first threshold voltage. | 12-26-2013 |
| 20140063990 | MULTI-CHIP SEMICONDUCTOR APPARATUS - A multi-chip semiconductor apparatus includes a plurality of semiconductor chips which are electrically connected through a plurality of through-chip vias (TSVs) and stacked, wherein each of the semiconductor chips includes: a first data input/output line configured to transmit data for a first memory bank; a second data input/output line configured to transmit data for a second memory bank; and a data transmitting/receiving (TX/RX) unit configured to electrically connect any one of the first and second data input/output lines to a first TSV in response to selected memory bank information, during read and write operations for the corresponding semiconductor chip. | 03-06-2014 |
| 20140104967 | INTER-MEMORY DATA TRANSFER CONTROL UNIT - A data transfer device that transfers data to a memory according to an instruction from a processor via a bus through which a response indicating completion of data writing in the memory is not sent back, comprises an inter-memory data transfer control unit including an operation start trigger receiving unit, a parameter acquiring unit, a read unit, and a write unit. When the write unit detects switching of a write destination memory, the write unit confirms write completion as to the memory by a procedure different from writing. When a data transfer instructed by the processor is completed, the write unit confirms write completion as to the write destination memory at the end of the data transfer by the procedure different from writing. The inter-memory data transfer control unit notifies the processor of completion of an inter-memory data transfer based on the confirmation of the write completion. | 04-17-2014 |
| 20140112083 | RANDOM ACCESS MEMORY FOR USE IN AN EMULATION ENVIRONMENT - A Random Access Memory (RAM) and method of using the same are disclosed. The RAM includes a plurality of memory cells arranged in columns and in rows with each memory cell coupled to at least one word line and at least one bit line. The RAM includes a plurality of switches with at least one of the switches coupled between two of the memory cells to allow data to be copied from one of the two memory cells to the other of the two memory cells. | 04-24-2014 |
| 20140177358 | ADDRESS COUNTING CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME - A semiconductor apparatus includes a first memory die; a second memory die; and a processor configured to provide an external command, an external start address and an external end address which are associated with a read operation, to the first memory die, and provide an external command, an external start address and an external end address, which are associated with a write operation, to the second memory die, in the case where data stored in the first memory die is to be transferred to and stored in the second memory die. | 06-26-2014 |
| 20140185395 | METHODS OF COPYING A PAGE IN A MEMORY DEVICE AND METHODS OF MANAGING PAGES IN A MEMORY SYSTEM - A method of copying a page in a memory device having a plurality of memory blocks and a plurality of sets of bit lines is disclosed, wherein each of the plurality of memory blocks includes a plurality of pages, and each set of bit lines corresponds to a respective memory block, wherein first bit lines of a source memory block that includes a source page are respectively coupled to second bit lines of a target memory block that includes a target page. The method includes disconnecting between the first bit lines of thea source memory block including a source page and from the second bit lines of a the target memory block including a target page; transferring data stored in the source page to the first bit lines of the source memory block; transferring the data from the first bit lines of the source memory block to the second bit lines of the target memory block; and writing the data transferred to the second bit lines of the target memory block into the target page. | 07-03-2014 |
| 20140355363 | MEMORY CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME - A memory chip includes a data processing block suitable for serial-parallel converting data inputted and for parallel-serial converting data to be outputted, a write data transmitting unit suitable for transmitting the data serial-parallel converted by the data processing block to a write data interlayer channel, a write data receiving unit suitable for receiving data from the write data interlayer channel, the data to be written to a core area, a read data receiving unit suitable for receiving data from a read data interlayer channel, the data to be parallel-serial converted by the data processing block, and a read data transmitting unit suitable for transmitting data read from the core area to the read data interlayer channel. | 12-04-2014 |
| 20140355364 | MEMORY AND MEMORY SYSTEM - A memory may include first to N | 12-04-2014 |
| 20140369142 | DATA TRANSFER DEVICE, BUFFERING CIRCUIT, AND BUFFERING METHOD - A data transfer device | 12-18-2014 |
| 20150016201 | SEMICONDUCTOR DEVICE - A semiconductor device includes first and second bank groups coupled to first and second data lines which are electrically isolated from each other. The semiconductor device includes a register unit suitable for providing predetermined data to the second data line in a specific mode, a data transfer and output unit suitable for externally outputting the predetermined data loaded onto the second data line and simultaneously transferring the predetermined data to the first data line in the specific mode, and a data output unit suitable for externally outputting the predetermined data loaded onto the first data line in the specific mode. | 01-15-2015 |
| 20150085589 | DATA MOVEMENT IN MEMORY DEVICES - Apparatus, systems, and methods for data movement in a memory device are described. In one embodiment, a memory controller comprises logic to move a row of data from a first row of a memory in a first section of a memory device to a second row of memory in a second section of the memory device without passing the data through a communication interface. Other embodiments are also disclosed and claimed. | 03-26-2015 |
| 20150109869 | MEMORY WITH TERMINATION CIRCUIT - Provided is a semiconductor integrated circuit according to an exemplary aspect of the present invention including first and second transmitter-receivers that execute transmission and reception of data through a signal line. The first transmitter-receiver includes a first termination circuit that includes a first resistor and a first switch, the first resistor being provided between a first power supply terminal and the signal line, the first switch controlling a current flowing through the first resistor to be turned on and off, and a control circuit that outputs a first control signal to the first termination circuit so that the first switch is turned on when the first transmitter-receiver receives data, the first switch is turned off when the first transmitter-receiver transmits the data, and the first switch is continuously on during a first predetermined period after receiving the data when the first transmitter-receiver further receives another data after receiving the data. | 04-23-2015 |
| 20160005443 | MEMORY AND MEMORY SYSTEM - A memory may include first to N | 01-07-2016 |
| 20160012878 | SEMICONDUCTOR INTEGRATED CIRCUIT | 01-14-2016 |
| 20160020771 | DATA PROCESSING DEVICE AND CONTROL METHOD THEREFOR - A data processing device includes a data processing unit including a plurality of elements and wiring groups that connect the plurality of elements, wherein respective elements in the plurality of elements include: a logic element; an acquisition unit that switches on and off an input side of the logic element for any wire out of the wiring groups on a cycle-by-cycle basis to latch input data; and a post unit that switches on and off an output side of the logic element for any wire out of the wiring groups on a cycle-by-cycle basis, and the data processing unit also includes a timing control unit that controls logic executed by the logic element and functions of the acquisition unit and the post unit on a cycle-by-cycle basis. | 01-21-2016 |
| 20160027484 | DATA TRANSFER CIRCUIT AND DATA TRANSFER METHOD - A data transfer circuit includes: a first power domain; a nonvolatile memory configured to store first data; a holding circuit; a readout circuit configured to read the first data from the nonvolatile memory and write the first data into the holding circuit at a time of chip reset; and a first controller configured to transfer the first data written into the holding circuit to the first power domain and make the holding circuit keep the first data at the time of chip reset, wherein the readout circuit, at a time of reset of the first power domain after the chip reset, does not read the first data from the nonvolatile memory, and the first controller transfers the first data held in the holding circuit to the first power domain. | 01-28-2016 |
| 20160035399 | METHOD AND APPARATUS FOR ASYNCHRONOUS FIFO CIRCUIT - The disclosure provides an asynchronous FIFO circuit that includes a data memory which is coupled to a write data path and a read data path. The data memory receives a write clock and a read clock. A FIFO write pointer counter receives a write enable signal and the write clock. The FIFO write pointer counter provides a FIFO write pointer signal to the data memory. A FIFO read pointer counter receives a read enable signal and the read clock. The FIFO read pointer counter provides a FIFO read pointer signal to the data memory. A control circuit receives the write enable signal, the read enable signal, the FIFO write pointer signal, the FIFO read pointer signal, the write clock and the read clock. The control circuit generates a memory full signal when the data memory is full and a memory empty signal when the data memory is empty. | 02-04-2016 |
| 20160104517 | SEMICONDUCTOR APPARATUS AND SYSTEM CAPABLE OF REDUCING PEAK CURRENT IN TRANSMITTING SIGNALS - A semiconductor apparatus includes a first output control unit and a second output control unit. The first output control unit includes a plurality of non-inversion pipes and a plurality of inversion pipes. The non-inversion pipes non-invert input signals and output the non-inverted input signals to a signal transmission line as transmission signal, and the inversion pipes invert input signals and output the inverted input signals to the signal transmission line as the transmission signals. The second output control unit includes a plurality of non-inversion pipes and a plurality of inversion pipes. The non-inversion pipes non-invert the transmission signals and output the non-inverted transmission signals, and the inversion pipes invert the transmission signals and output the inverted transmission signals. | 04-14-2016 |
| 20160155489 | MEMORY WITH TERMINATION CIRCUIT | 06-02-2016 |
| 20160180897 | DRIVER STRUCTURE FOR CHIP-TO-CHIP COMMUNICATIONS | 06-23-2016 |
| 20160204782 | INTEGRATED CIRCUIT AND STORAGE DEVICE INCLUDING THE SAME | 07-14-2016 |
