Entries |
Document | Title | Date |
20080198674 | Method of testing an integrated circuit, method of determining defect resistivity changing cells, testing device, and computer program adapted to perform a method for testing an integrated circuit - A method for testing an integrated circuit having an array of resistivity changing cells, wherein the method includes selecting a plurality of cells, setting the state of each selected cell to a defined state, measuring a resistance value being dependent on the resistances of the selected cells, comparing the resistance value with a resistance target value, and classifying the integrated circuit in dependence on the result of the comparison. | 08-21-2008 |
20080198675 | Semiconductor device including a plurality of memory units and method of testing the same - In a semiconductor device including a plurality of memory units and a method of testing the same, the semiconductor device includes a plurality of memory units each comprising a plurality of input lines; and an input unit configured to provide a plurality of test signals to the input lines, respectively, included in each of the memory units in response to a test enable signal. A data input/output unit can be configured to receive Z-bit data from test equipment and to distribute the Z-bit data to the plurality of memory units in response to the test enable signal, where Z is a natural number. The data input/output unit outputs K-bit data, which are output from each of the plurality of memory units, through data input/output lines included in the plurality of memory units in response to the test enable signal, where K≦Z and K is a natural number. | 08-21-2008 |
20080205172 | DESIGN-FOR-TEST MICRO PROBE - Systems and techniques for testing a device having first and second interconnected chips that are internal to the device include selecting a site on a communication pathway along which an internal signal travels inside the device between the first and second chips, and connecting a test probe to the site. | 08-28-2008 |
20080205173 | Method and System for Testing an Integrated Circuit - An integrated circuit comprising:
| 08-28-2008 |
20080205174 | Semiconductor memory device and test method thereof - Example embodiments disclose a semiconductor memory device and a test method thereof. The semiconductor memory device includes a memory cell array that provides first and second data groups at a first data rate and an output circuit, in a normal mode of operation, serially outputs the first and second data groups at a first data rate on an external terminal. In a test mode of operation, the output circuit outputs the first data group or the second data group at a second data rate on the external terminal in response to control signals, without switching the test mode. The second data rate may be lower than the first data rate. | 08-28-2008 |
20080212383 | Circuit and method for parallel test of memory device - A test circuit in a memory device includes a first compression unit configured to compress data of a plurality of cells to transmit first compressed data to a plurality of input/output lines, and a second compression unit configured to compress the first compressed data on the plurality of input/output line to output second compressed data to at least one output pin, wherein the second compression unit operates in a low compressing mode and a high compressing mode in response to a data compression selecting signal. | 09-04-2008 |
20080219069 | DEVICE THRESHOLD CALIBRATION THROUGH STATE DEPENDENT BURNIN - Disclosed are embodiments of a method for reducing and/or eliminating mismatch. The embodiments sample the bias of one or more circuit sub-components that require a balanced state (e.g., sampling the bias of the cross-coupled transistors in each memory cell and/or sense amp in a memory array) before chip burn-in, by initiating a burn-in process during which an individually selected state is applied to each of the devices in the circuit. This fatigues the devices away from their preferred states and towards a balanced state. The bias is periodically reassessed during the burn-in process to avoid over-correction. By using this method both memory cell and sense-amplifier mismatch can be reduced in memory arrays, resulting in smaller timing uncertainty and therefore faster memories. | 09-11-2008 |
20080219070 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes: memory cells respectively arranged on intersecting points of a plurality of word lines and a plurality of data lines, and respectively having a capacitor for storing data; a sense amplifier provided in between the data lines forming a data line pair so as to amplify an electric potential difference between the data lines and to perform data reading; and a test memory cell arranged on each of the data lines and having a test capacitor with a capacitance value set smaller than the above capacitor, and when performing a test for a memory cell, inversed data of the data to be stored into a target memory cell of a test target is pre-written into the test memory cell. | 09-11-2008 |
20080225615 | PULSED RING OSCILLATOR CIRCUIT FOR STORAGE CELL READ TIMING EVALUATION - A pulsed ring oscillator circuit for storage cell read timing evaluation provides read strength information. A pulse generator is coupled to a bitline to which the storage cell to be measured is connected. The storage cell thereby forms part of the ring oscillator and the read strength of the storage cell is reflected in the frequency of oscillation. A pulse regeneration circuit is included in the ring so that the storage cell read loading does not cause the oscillation to decay. Alternatively, a counter may be used to count the number of oscillations until the oscillations decay, which also yields a measure of the read strength of the storage cell. The pulse generator may have variable output current, and the current varied to determine a change in current with the storage cell enabled and disabled that produces the same oscillation frequency. The read current is the difference between currents. | 09-18-2008 |
20080232181 | SEMICONDUCTOR MEMORY DEVICE - This disclosure concerns a semiconductor memory device comprising: a memory cell array having memory cells arrayed two-dimensionally; word lines connected to the memory cells of rows of the memory cell array; bit lines connected to the memory cells of columns of the memory cell array; sense amplifiers connected to the bit lines, and detecting data stored in the memory cells; a test pad passing a predetermined reference current from a power source, and transmitting a reference voltage based on the reference current; and test circuits connected between the power source and the test pad and intervening between the power source and the bit lines, the test circuits passing test currents according to the reference voltage via the bit lines. | 09-25-2008 |
20080247247 | FLASH MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - Provided are a flash memory device and a method of driving the same for improving reliability of stored set information. The method of driving the flash memory device includes applying power to the flash memory device, the flash memory device having a memory cell array for storing set information regarding operation environment settings, where the set information includes at least one bit. The method further includes performing an initial read operation on the memory cell array and judging a status of data, corresponding to the set information, read during the initial read operation to determine whether the initial read operation has passed or failed. Each bit of the set information is extended to n bits (where n is an integer equal to or greater than 2). The n bits are respectively stored in different input/output regions in the memory cell array. | 10-09-2008 |
20080253207 | METHOD AND APPARATUS FOR TESTING THE FUNCTIONALITY OF A PAGE DECODER - A method and apparatus for testing correct operation of a page decoder in a memory is provided. In one implementation, the method includes erasing the memory to reset all memory cells associated with each of the N pages in the memory, and iteratively generating a unique bit sequence of M bits and programming the unique bit sequence into a plurality of the N pages at a given time until each of the N pages contains a unique bit sequence relative to other pages in the memory. Responsive to each of the N pages having a unique bit sequence, the method further includes using the page decoder to read out each unique bit sequence associated with the N pages to verify correct operation of the page decoder. | 10-16-2008 |
20080253208 | SEMICONDUCTOR INTEGRATED CIRCUIT AND MEMORY CHECKING METHOD - The semiconductor integrated circuit includes a memory for storing secret data, a memory BIST circuit for executing a memory. BIST, a first selector for switching between a path for a memory isolation test via an external terminal and a path from the memory BIST circuit, a second selector for switching between a path from the output of the first selector and a path from a normal circuit and having an output coupled to the memory, and a third selector for switching between a path from the output of the memory and a path for receiving a pseudo signal and receiving a check completion signal outputted from the memory BIST circuit as a selection signal. In this semiconductor integrated circuit, after the memory is initialized by executing the memory BIST, the memory can be accessed from the external terminal via the path for the memory isolation test. | 10-16-2008 |
20080253209 | Semiconductor memory device and method of testing same - Disclosed is a semiconductor memory device in which a cell is connected to word lines of at least first and second ports, and control of timing of activation of the word lines of the first and second ports is performed based upon first and second clock signals, respectively, comprising first and second test control signals in correspondence with the first and second clock signals that control the respective timings of activation of the word lines of the first and second ports. With regard to the cell with the first and second ports being selected, when the first test control signal is in an activated state and the second test control signal is in a deactivated state, control is exercised so as to mask the second clock signal and, responsive to the first clock signal, activate the first and second word lines simultaneously. When the second test control signal is in an activated state and the first test control signal is in a deactivated state, control is exercised so as to mask the first clock signal and, responsive to the second clock signal, activate the first and second word lines. | 10-16-2008 |
20080259702 | STATE-MONITORING MEMORY ELEMENT - Embodiments of the invention relate to a state-monitoring memory element. The state-monitoring memory element may have a reduced ability to retain a logic state than other regular memory elements on an IC. Thus, if the state-monitoring memory elements fails or loses state during testing, it may be a good indicator that the IC's state retention may be in jeopardy, possibly requiring the IC to be reset. The state-monitoring memory element may be implemented by degrading an input voltage supply to the state-monitoring memory element across a diode and/or a transistor. One or more current sources may be used to stress the state-monitoring memory element. A logic analyzer may be used to analyze the integrity of the state-monitoring memory element and trigger appropriate actions in the IC, e.g., reset, halt, remove power, interrupt, responsive to detecting a failure in the state-monitoring memory element. Multiple state-monitoring memory elements may be distributed in different locations on the IC for better coverage. | 10-23-2008 |
20080259703 | SELF-TIMED SYNCHRONOUS MEMORY - A memory device includes a memory array having a plurality of memory cells arranged in a row-column format, where the memory array is configured to designate at least one of the memory cells as a test memory cell. The memory system also includes a sense amplifier to read the test memory cell and to evaluate a validity of the memory array responsive to reading the test memory cell. | 10-23-2008 |
20080259704 | SEMICONDUCTOR DEVICE IN WHICH A PLURALITY OF MEMORY MACROS ARE MOUNTED, AND TESTING METHOD THEREOF - According to the present invention, an intra-macro match determining circuit | 10-23-2008 |
20080259705 | HARDWARE AND SOFTWARE PROGRAMMABLE FUSES FOR MEMORY REPAIR - The present invention relates to a system and method for increasing the manufacturing yield of a plurality of memory cells used in cell arrays. A programmable fuse, having both hardware and software elements, is used with the plurality of memory cells to indicate that at least one memory cell is unusable and should be shifted out of operation. The software programmable element includes a programmable register adapted to shift in an appropriate value indicating that at least one of the memory cells is flawed. The hardware element includes a fuse gated with the programmable register. Shifting is indicated either by software programmable fuse or hard fuse. Soft fuse registers may be chained together forming a shift register. | 10-23-2008 |
20080266990 | Flexible redundancy replacement scheme for semiconductor device - A redundancy replacement scheme for repairing a faulty memory cell including memory cells arranged in memory blocks containing word lines and column select lines. The redundancy replacement scheme including replacing the faulty memory cell in a second memory block with a spare memory cell in the second memory block based on a decoded address of a first memory block. | 10-30-2008 |
20080273407 | CIRCUIT AND METHOD TO FIND WORDLINE-BITLINE SHORTS IN A DRAM - Method and apparatus for testing for a short between a wordline being tested and a bitline in a memory device. The method includes applying a first voltage to the bitline using a first voltage source and applying a second voltage to the wordline being tested using a second voltage source. The method further includes disconnecting the wordline being tested from the second voltage source; and after disconnecting the wordline being tested from the second voltage source, activating the wordline being tested, thereby connecting the wordline being tested to a wordline power supply line. A determination is made of whether a voltage of the wordline power supply line indicates a short between the wordline being tested and the bitline. The determination is based on the voltage of the wordline power supply line relative to the first voltage and the second voltage. | 11-06-2008 |
20080273408 | SYSTEM FOR BITCELL AND COLUMN TESTING IN SRAM - A system comprises a storage cell coupled to multiple bitlines and a transistor that couples to the multiple bitlines in parallel with the storage cell. The transistor is activated while the storage cell is read. | 11-06-2008 |
20080279021 | MULTI-WORDLINE TEST CONTROL CIRCUIT AND CONTROLLING METHOD THEREOF - A multi-wordline test control circuit in a semiconductor integrated device for performing a multi-wordline test in a specified cell mat among a plurality of cell mats. The multi-wordline test control circuit comprises a multi-test control block for receiving a multi-wordline test signal and outputting a first test signal and a second test signal, and a multi-wordline test block for performing the multi-wordline test in a specified cell mat among a plurality of cell mats in response to the first test signal and the second test signal. | 11-13-2008 |
20080279022 | SEMICONDUCTOR DEVICE WITH SELF REFRESH TEST MODE - A semiconductor device includes a memory array that has dynamic memory cells. In a self refresh test mode, a self refresh test mode controller monitors and/or controls various blocks and internal signals in the semiconductor device. The self refresh test mode controller may communicate with a remote testing device through various conductors including one or more DQ lines and/or one or more address lines. | 11-13-2008 |
20080279023 | Semiconductor integrated circuit with full-speed data transition scheme for DDR SDRSM at internally doubled clock testing application - The present invention provides a circuit and a method for the full speed testing of semiconductor memory chips. The invention provides a full-speed data transition scheme for double data rate (DDR) synchronous dynamic random access memory (SDRAM). For high speed or double speed stress testing of DDR SDRAM, the internal clock is double the speed of the external clock. During high speed test, this causes the data to be written or presented to the data path two times. This invention provides a circuit and method for creating a full-speed data transition scheme to overcome this double speed testing problem. | 11-13-2008 |
20080285366 | TEST APPARATUS, PROGRAM, AND TEST METHOD - There is provided a test apparatus that tests a device under test. The test apparatus includes an address generating circuit that generates a physical address to be supplied to a memory block inside the device under test, a plurality of mask registers being provided in correspondence with a plurality of memory input bits constituting at least a part of a memory input address to be supplied to the device under test, where the plurality of mask registers set values indicating whether a plurality of physical bits constituting the physical address is masked every the physical bit, a plurality of mask arithmetic circuits being provided in correspondence with each of the plurality of memory input bits, where the plurality of mask arithmetic circuits respectively mask the physical address in accordance with the value of the mask register corresponding to this memory input bit, a plurality of logical operation circuits being provided in correspondence with each of the plurality of memory input bits, where the plurality of logical operation circuits respectively output bit data obtained by performing a predetermined logical operation on a masking result by the mask arithmetic circuit as the memory input bit, and an address supplier that supplies the input address including the plurality of memory input bits output from the plurality of logical operation circuits to the device under test. | 11-20-2008 |
20080291761 | Burn-in test apparatus - A burn-in test apparatus and a semiconductor device using the same are disclosed. The burn-in test apparatus includes a flag signal generating unit configured to receive an external input signal and an external address externally inputted for a burn-in test and generate a flag signal, and a burn-in test unit configured to receive the flag signal, generate a toggled output enable signal, and drive an input/output line to toggle a signal on the input/output line. | 11-27-2008 |
20080298147 | Semiconductor memory - To arrange data input/output PADs of a semiconductor memory on a narrower pitch without enhancing a required positional accuracy for a probe in a probe check. A semiconductor memory includes: a memory cell array including memory cells; signal terminals; a power source terminal of a power source supplied to output circuits of the signal terminals; test-purpose signal terminals fewer than the signal terminals; a selection portion which, as data to be written to the memory cells, selects data input from the signal terminals or data input from the test-purpose signal terminals, and repetitively allocates inputs of the test-purpose signal terminals to inputs of the signal terminals based on an arrangement of the signal terminals; and a test-purpose power source terminal connected to the power source terminal, and arrangement intervals of the test-purpose signal terminals and the test-purpose power source terminal are larger than an arrangement interval of the signal terminals. | 12-04-2008 |
20080298148 | Semiconductor memory device and test method therefor - There is disclosed a semiconductor memory device in which, activation timing control of a plurality of word lines of a plurality of ports is managed based on a plurality of clock signals, test signals are provided in association with the plurality of clock signals respectively controlling the activation timings of the word lines of the plurality of ports. If, with the cell, with the plurality of ports selected, the one test signal is in an activated state and the other test signal is in a non-activated state, activation of word lines of the plurality of ports is controlled in response to one clock signal, with the other clock signal being then masked. The timing difference, inclusive of the zero timing difference, between the activation timing of the plurality of word lines of the plurality of port may be finely adjusted by a delay control signal. | 12-04-2008 |
20080304343 | METHOD AND APPARATUS FOR TESTING A CIRCUIT - A system and method for testing a memory array are disclosed which may include establishing a stored data vector, including a plurality of data bits, within at least one circuit; applying one or more logical operations on the stored data vector to generate a succession of original data vectors at the at least one circuit; transmitting the succession of original data vectors through a memory array to provide a succession of exercised data vectors; comparing the succession of exercised data vectors to the succession of respective original data vectors; and determining whether the memory array passes or fails based on the comparing step. | 12-11-2008 |
20080304344 | Word line driving circuit, semiconductor memory device including the same, and method for testing the semiconductor memory device - A semiconductor memory device in accordance with the present invention is able to facilitate detecting whether a word line fails or not by floating the word line. The semiconductor memory device includes a word line driver, and a floating controller. The word line driver is configured to control a word line to be enabled/disabled. The floating controller is configured to control the word line driver to float the word line in response to a word line floating signal. | 12-11-2008 |
20080304345 | Semiconductor memory device with reduced number of channels for test operation - A semiconductor memory device includes a plurality of memory banks, a data pin for inputting and outputting data, and input/output buffers connected to the data pin. Each of the memory banks has a plurality of memory cells for storing the data. The data pin is enabled and disabled by a pin selection signal. The data pin performs a normal data input/output operation when the pin selection signal is enabled and a termination resistor connected to the data pin is off when the pin selection signal is disabled. The input/output buffers make a termination resistor connected to the data pin off when the pin selection signal is disabled. | 12-11-2008 |
20080316846 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF STORING DATA OF VARIOUS PATTERNS AND METHOD OF ELECTRICALLY TESTING THE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device to which information of different data bits can be written, and a method of electrically testing the semiconductor memory device are provided. In a mode for testing a memory cell array of the semiconductor memory device, the semiconductor memory comprises a control signal generation pad capable of writing non-identical data to data input/output pads of each group when data is written to the memory cell array. | 12-25-2008 |
20090003099 | MEMORY TEST MODE FOR CHARGE RETENTION TESTING - One embodiment includes a dynamic memory operable in different refresh modes including an autonomous refresh mode in which the refresh rate is set by an internal self refresh timer circuit on the memory circuit die, and a test refresh mode in which the refresh rate is set by a timer circuit external to the memory circuit die. Other embodiments are described and claimed. | 01-01-2009 |
20090003100 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF INPUTTING ADDRESSES THEREIN - A semiconductor memory device is capable of reducing a test time by sharing input pins of addresses for the test, thereby reducing test costs also. The semiconductor memory device includes first and second address buffer units. The first address buffer unit is configured to transmit a plurality of normal addresses to an internal circuit and store one or more of the received normal addresses. The second address buffer unit is configured to transmit one or more external bank addresses to the internal circuit as internal bank addresses in a normal mode and transmit addresses stored in the first address buffer unit to the internal circuit as the internal bank addresses in a test mode. | 01-01-2009 |
20090003101 | APPARATUS AND METHOD OF SETTING TEST MODE IN SEMICONDUCTOR INTEGRATED CIRCUIT - An apparatus for setting a test mode in a semiconductor integrated circuit includes a test mode control block that generates a coding control signal according to whether or not a control fuse is cut, and a test mode coding block that sets default values of a multi-bit test code in response to the coding control signal. | 01-01-2009 |
20090003102 | METHOD FOR TESTING SEMICONDUCTOR MEMORY DEVICE - A method for testing a semiconductor memory device is provided. The semiconductor memory device includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells. Each word line is controlled by a corresponding control line and a corresponding driving line. The method includes selecting a plurality of word lines controlled by one driving line; enabling a plurality of control lines respectively corresponding to the selected word lines; actuating one of the selected word lines; and adding a disturbing signal on the actuated word line and measuring signals on the plurality of bit lines. | 01-01-2009 |
20090003103 | SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY TESTER - A semiconductor device, a semiconductor memory tester, and a multi-chip package are provided. The semiconductor device includes a plurality of nonvolatile semiconductor memories; a boosting circuit which generates a boosted voltage for operating the plurality of nonvolatile semiconductor memories; and a boosting circuit controller which controls the operation of the boosting circuit to generate the boosted voltage on the basis of an operation sequence of the plurality of nonvolatile semiconductor memories. | 01-01-2009 |
20090003104 | Test circuit and method for use in semiconductor memory device - A test circuit and method for use in a semiconductor memory device is provided. The test method for use in a semiconductor memory device including a plurality of memory blocks may include sequentially enabling a plurality of word lines by applying a stress to the wordlines and performing a test operation, in response to sequentially applied test addresses, each of the word lines being sequentially selected from the plurality of memory blocks and enabled. | 01-01-2009 |
20090016130 | MEMORY DEVICE AND METHOD OF TESTING A MEMORY DEVICE - In a method of testing a memory device, an output path of the memory device and an input path of the memory device are coupled to each other. A signal is transmitted, controlled by a test pattern, via the output path of the memory device. The signal is received via the input path of the memory device and evaluated. | 01-15-2009 |
20090022000 | SEMICONDUCTOR STORAGE DEVICE AND TEST METHOD THEREFOR - Disclosed is a semiconductor device including a BIST provided with a plurality of scan FFs (flip-flops), a data address signal generation circuit unit which respectively generates a data signal and an address signal based on a set value of a scan FF, WEB generation circuit unit which generates a signal WEB which controls writing to and reading data from the semiconductor memory based on an scan FF value, and a test signal control circuit unit which controls the data address signal generation circuit unit and the WEB generation circuit unit, based on a received control signal, controls selectors, and selects and controls, as data and address signals to be supplied to the memory, data signal and address signals from the data address signal generation circuit unit or data and address signals via a user defined circuit. | 01-22-2009 |
20090027981 | METHOD OF TESTING DATA PATHS IN AN ELECTRONIC CIRCUIT - A method of testing a complex electronic circuit, comprising a plurality of transfer operators DMA | 01-29-2009 |
20090027982 | SEMICONDUCTOR MEMORY AND TEST SYSTEM - A cell array has a word line and a bit line coupled to memory cells, and a redundancy word line and a redundancy bit line coupled to redundancy memory cells. A read unit reads data held in the memory cell. A defect detection input unit receives a defect detection signal from a test apparatus. A dummy defect output unit outputs a dummy defect signal during a predetermined period of time after the defect detection input unit receives the defect detection signal. A data output unit inverts a logic of the read data output from the read unit during an activation of the dummy defect signal. Accordingly, an artificial defect can be generated by the semiconductor memory without changing the test apparatus or a test program. As a result of this, a relief efficiency can be enhanced and a test cost can be reduced. | 01-29-2009 |
20090040849 | SEMICONDUCTOR MEMORY, TEST METHOD OF SEMICONDUCTOR MEMORY AND SYSTEM - Each program circuit outputs an operating specification signal indicating a first or second operating specification according to a program state. Each specification changing circuit is set by a corresponding block selection signal and outputs an operating specification signal indicating a second operating specification. Each timing control circuit changes an output timing of a precharge control signal for a bit line according to the operating specification signal. By the operating specification signal from the specification changing circuit, a failure can be detected in each memory block before programming a program circuit. Thereafter, the failure can be relieved by the program circuit. The output timing of the precharge control signal can be set for each memory block by a block selection signal without wiring a dedicated signal line for setting each specification changing circuit. Accordingly, increase in chip size can be minimized. | 02-12-2009 |
20090040850 | SEMICONDUCTOR MEMORY, TEST METHOD OF SEMICONDUCTOR MEMORY AND SYSTEM - An address switch circuit receives a row address signal supplied to a first address terminal group and a column address signal supplied to a second address terminal group. Further, the address switch circuit receives the row address signal supplied to the second address terminal group and thereafter receives the column address signal supplied to the second address terminal group and supplies the received row address signal and the received column address signal to the row decoder and the column decoder during a second operation mode. The number of semiconductor memories that are tested at once can be increased by executing an operation test of the semiconductor memories in the second operation mode. In addition, it becomes possible to test a semiconductor memory using test assets for other semiconductor memories. Consequently, the test efficiency can be improved, and the test cost can be reduced. | 02-12-2009 |
20090040851 | SEMICONDUCTOR MEMORY, TEST METHOD OF SEMICONDUCTOR MEMORY AND SYSTEM - Each sub word line is coupled to a gate of a transfer transistor of a memory cell. A first switch of a sub word decoder couples the sub word line to a high level voltage line when a main word line is in an activation level. A second switch couples the sub word line to a low level voltage line when the main word line is in an inactivation level. A third switch couples the sub word line to the low level voltage line when a word reset signal line is in an activation level. A reset control circuit disables the inactivation of the main word line or the activation of the word reset signal line during a test mode. One of the second and third switches is forcibly turned off, and thereby, an operation failure of a sub word decoder can be detected easily. | 02-12-2009 |
20090040852 | Semiconductor Device and System - First and second data output circuits obtain corresponding parts of read data of a storage circuit to output to first and second input/output pads in a second test mode. First and second data input circuits obtain output data of the first and second data output circuits via the first and second input/output pads to output in the second test mode. A comparison object selection circuit selects output data of the first and second data input circuits to output in the second test mode. A judging circuit performs a test judgment by comparing output data of the comparison object selection circuit with expected value data and outputs a test result signal in the second test mode. | 02-12-2009 |
20090046524 | MULTI-COLUMN DECODER STRESS TEST CIRCUIT - The embodiments described herein are directed to providing a multi-column decoder stress test circuit capable of reducing a column stress test time while sufficiently performing a stress test by using column selection signals. The multi-column decoder stress test circuit comprising a control unit configured to receive at least one column test signal and to generate a multi-column enable signal, and a multi-enable decoding unit configured to receive the multi-column enable signal and to generate a plurality of enabled column selection signals. | 02-19-2009 |
20090046525 | WAFER BURN-IN TEST CIRCUIT - A wafer burn-in test circuit includes an address toggle signal generating unit for generating an address toggle signal in response to address signals having a constant time period, a reset signal generating unit for receiving a wafer burn-in mode activation signal, the address signals, and a reset determination signal among the address signals and then generating a reset signal, a refresh test mode signal generating unit for receiving the address toggle signal and the reset signal and then generating a refresh test mode signal, and a refresh period signal generating unit for receiving the address toggle signal and the refresh test mode signal and then generating a refresh period signal. | 02-19-2009 |
20090046526 | WORD LINE DRIVING CIRCUIT AND METHOD OF TESTING A WORD LINE USING THE WORD LINE DRIVING CIRCUIT - A method of testing a word line using a word line driving circuit comprising: activating a word line by activating a word line driving signal; floating the word line by activating a test mode signal after the activating of the word line; recording data having a predetermined logic value into a memory cell by inputting a write command while the word line is floated; and reading out data from the memory cell by inputting a read command after the recording of data. | 02-19-2009 |
20090052263 | Write driving circuit - A write driving circuit is provided to drive a global input/output line to write same data to memory cells according to a combination of a first test data signal and a second test data signal in a test mode, regardless of input data signals. | 02-26-2009 |
20090052264 | Refresh characteristic testing circuit and method for testing refresh using the same - A refresh characteristic test circuit is provided, in a recessed semiconductor device, that is capable of verifying whether a refresh failure is caused by the neighbor/passing gate effect or not and a method for testing the refresh characteristic. The refresh characteristic test circuit includes a select signal generating unit for receiving first address signals and a test mode signal and generate select signals to select cell blocks, a main word line signal generating unit for receiving second address signals and the test mode signal and generate main word lines signals to select main word lines of the selected cell block, and a sub word line signal generating unit for receiving third address signals and the test mode signal and enable sub word lines of the selected main word line. | 02-26-2009 |
20090059697 | METHOD AND APPARATUS FOR IMPLEMENTING SRAM CELL WRITE PERFORMANCE EVALUATION - A SRAM cell write performance evaluation circuit includes a SRAM core where each wordline is connected to only one bit column. A ring oscillator circuit is used to generate wordline pulses. A state machine controls operations for the SRAM cell write performance evaluation circuit including the ring oscillator circuit and the SRAM core. A control signal is applied to the state machine to select a first write operation, where the circuit simultaneously writes all the cells to a known state with wide wordlines to ensure all cells are written. Then a second write operation is selected, and all the wordlines are launched simultaneously to write the cells to the opposite state. From these write operations, a required wordline pulse width to write the cell is identified. | 03-05-2009 |
20090059698 | METHOD FOR TESTING MEMORY - A method for testing a memory includes the following steps. First, data is read from the memory and stored to a first temporary memory. Meanwhile, expected data corresponding to the data from the memory is written into a second temporary memory from a tester. Thereafter, the data in the first temporary memory and the expected data in the second temporary memory are compared with each other to judge whether the memory has an enough operation window. | 03-05-2009 |
20090059699 | Semiconductor memory device and its test method - A test circuit is connected to a memory core integrated unit of SRAM. When the memory core integrated unit is to be tested, a test start signal is set to a high level so that one of a bit line and an inverted bit line is used for data write and the test circuit sets data to this selected bit line. The other bit line is used for data read, and the written data is set to this bit line in the normal operation. Whether each memory core is not defective is judged by EOR which confirms data set to the bit line and data set to the inverted bit line are mutually inverted each other. A test method is realized which can test a defect of each memory core of a semiconductor memory such as SRAM in a short time. | 03-05-2009 |
20090067271 | SEMICONDUCTOR DEVICE - A word line WLA of A port is activated based on a clock signal ACLK, and a word line WLB of B port is activated based on a port setting signal RDXA indicating that A port is a selected state. In addition thereto, a bit line of B port is precharged. A state in a simultaneous access operation is reproduced by activating the word line WLB during a time period of activating the word line WLA regardless of a delay difference of the clock signal and maintaining Vds of an access transistor of A port at a constant value. | 03-12-2009 |
20090067272 | MEMORY COMPILER REDUNDANCY - An improved redundancy architecture for embedded memories in an ASIC chip includes one or more compiler-generated embedded memory instances. Each embedded memory instance has a universal register for storing an address of a defective subunit of the memory instance from a variety of sources. A control block is located on the ASIC chip outside of the memory instances. The control block has a defective memory register for storing an address of a defective memory subunit. The address of a defective memory subunit from the defective memory register in the control block is transferred to the universal interface register in the memory instance. In one embodiment, the control block includes fuses for storing a defective subunit address in binary form. A fuse array is located outside of the memory instances and contains laser fuses that represent address of defective subunits for each memory instance. Alternatively, the control block includes a BISTDR (built-in, self-test, diagnostic, and repair) system that provides an address of a defective memory subunit. Means are provided in the memory instances for comparing incoming memory addresses to address bits for defective memory subunits stored in each memory-instance register. | 03-12-2009 |
20090073789 | METHOD AND APPARATUS FOR TESTING A MEMORY DEVICE - Disclosed is a method for testing a memory device with a long-term clock signal by automatically performing precharge only after activation. In this method, a signal for precharging the banks of the memory device is automatically generated only at the falling edge of an external signal when a signal for activating the banks is applied. Accordingly, the present invention ensures a stable test of the memory device, reducing the testing time. | 03-19-2009 |
20090086558 | Multi-port memory device with serial input/output interface - A multi-port memory device includes a plurality of serial I/O data pads; a plurality of parallel I/O data pads; a plurality of first ports for performing a serial I/O data communication with external devices through the serial I/O data pads; a plurality of banks for performing a parallel I/O data communication with the first ports via a plurality of first data buses; and a second port for performing a parallel I/O data communication with the external devices through the parallel I/O data pads and a serial I/O data communication with the first ports via a plurality of second data buses, during a test mode. | 04-02-2009 |
20090097342 | BUILT-IN SELF REPAIR CIRCUIT FOR A MULTI-PORT MEMORY AND METHOD THEREOF - A built-in self repair (BISR) circuit for a multi-port memory and a method thereof are provided. The circuit includes a test-and-analysis module (TAM) and a defect locating module (DLM) coupled to the TAM. The TAM tests a repairable multi-port memory to generate a fault location and determines whether the test generates a port-specific fault candidate according to the fault location. If a port-specific fault candidate is generated, the DLM generates a defect location based on the fault location and provides the defect location to the TAM so that the TAM can determine how to repair the repairable multi-port memory according to the defect location. If no port-specific fault candidate is generated in the test, the TAM determines how to repair the repairable multi-port memory according to the fault location. | 04-16-2009 |
20090097343 | METHOD AND SYSTEM FOR TESTING ADDRESS LINES - Method and systems are described for testing an address line inter- coupling a processor and a memory. The contents of a first address in the memory are initially compared with the contents of a second address in the memory, wherein each of the first and second addresses are addressable in the memory by a different value applied on the address line. If the contents of the first and second addresses match, the contents of either one of the first and second addresses are changed, and a subsequent comparison of the contents of the first and second memory addresses is performed. If the second comparison determines that contents of the first and second memory address still match, then a fault condition associated with the address line is identified. | 04-16-2009 |
20090097344 | SEMICONDUCTOR MEMORY TESTING DEVICE AND METHOD OF TESTING SEMICONDUCTOR USING THE SAME - The semiconductor memory testing device includes a test signal decoder decoding burn-in test mode signals which generates a first test signal for use in controlling entire main wordlines and which generates a second test signal for use in controlling sub wordlines. When the first and second test signals are in an disabled state, the semiconductor memory testing device also includes a plurality of bank control units generating a multi wordline test mode signal as a multi wordline test signal corresponding to a bank control signal, and simultaneously enabling a plurality of wordlines in accordance to the multi wordline test signal to perform a test. The semiconductor memory testing device reduces a testing time and current consumption and thus enhances a more stable voltage drop when performing continuous multi wordline test on a per bank basis. | 04-16-2009 |
20090097345 | Method, device and system for regulating access to an integrated circuit (IC) device - A circuit block access module (ICAM) residing on an integrated circuit and adapted to access a circuit block on the integrated circuit, the module comprising control logic adapted to extract data from a serial data line into two or more parallel data lines, wherein at least one of the parallel data lines is associated with a circuit block address line; and the control logic is further adapted to override or bypass at least a portion of a primary control circuit of said integrated circuit. | 04-16-2009 |
20090103380 | SYSTEM AND METHOD FOR DATA READ OF A SYNCHRONOUS SERIAL INTERFACE NAND - A method and system is disclosed for operating a NAND memory device. The NAND memory device is operated by transmitting serial peripheral interface signals from a host to a NAND memory device, whereby the signals are communicated to a NAND memory in the NAND memory device without modifying the signals into a standard NAND memory format. Similarly, a method and system is disclosed for receiving signals from the NAND memory device without modifying the signals from a standard NAND format into a serial format. The system also incorporates error detection and correction techniques to detect and correct errors in data stored in the NAND memory device. | 04-23-2009 |
20090109774 | TEST METHOD AND SEMICONDUCTOR DEVICE - A test method and a semiconductor device is disclosed. One embodiment provides sending out a test signal by a semiconductor device. A reflected signal generated in reaction is compared to the test signal with a first threshold value. The reflected signal is compared with a second threshold value differing from the first threshold value. | 04-30-2009 |
20090116320 | Methods and Apparatus for Screening Bit Line of a SRAM - Methods and apparatus provide for testing an SRAM cell, the SRAM cell including an anti-parallel storage circuit operable to store a logic high or low value across a true node and a complementary node, where the true node and complementary node are coupled to a true bit line (BLT) and a complementary bit line (BLC), by first and second transistors, respectively, the method comprising: preventing a write driver circuit from significantly pulling the BLT towards a supply voltage; preventing a pre-charge circuit from significantly pulling the BLT towards the supply voltage; preventing the first transistor from significantly pulling the BLT towards the voltage stored in the SRAM cell; and comparing the voltage of the BLT under the foregoing conditions to a threshold voltage. | 05-07-2009 |
20090116321 | Apparatus and method for detection of address decoder open faults - An apparatus and method are provided for performing a test sequence to detect address decoder open faults in a memory device. The apparatus comprises base address generation circuitry for generating a plurality of base addresses, and derived address generation circuitry, responsive to a base address portion of each base address, to generate an associated series of derived addresses. Each derived address is different to any other derived address in that associated series and has a derived address portion that differs from the corresponding base address portion by a single address bit value. Read/write sequence generator circuitry is then responsive to each base address in turn, to write in said memory device a first data value at the base address and a second data value at each derived address in the associated series of derived addresses. Further, the read/write sequence generator circuitry is arranged to read a data value stored at the base address each time the second data value is written to one of the derived addresses, and to detect an address decoder open fault if the read data value is the second data value. Such an apparatus can automatically perform the required test sequence for any configuration of memory device, hence providing a simple and efficient mechanism for detecting address decoder open faults. | 05-07-2009 |
20090116322 | Semiconductor memory device having wafer burn-in test mode - A semiconductor memory device includes an enable signal generator configured to generate an enable signal in response to a plurality of burn-in test signals; a test mode signal generator configured to generate a plurality of peripheral region test mode signals and a plurality of core region test mode signals corresponding to the burn-in test signals in response to the enable signal; a core region controller configured to control circuits in a core region in response to the core region test mode signals; and a peripheral region controller configured to control circuits in a peripheral region in response to the peripheral region test mode signals. | 05-07-2009 |
20090116323 | SCANNED MEMORY TESTING OF MULTI-PORT MEMORY ARRAYS - A system for at-functional-clock-speed continuous scan array built-in self testing (ABIST) of multiport memory is disclosed. During ABIST testing, functional addressing latches from a first port are used as shadow latches for a second port's addressing latches. The arrangement reduces the amount of test-only hardware on a chip and reduces the need to write complex testing software. Higher level functions may be inserted between the shadow latches and the addressing latches to automatically provide functions such as inversions. | 05-07-2009 |
20090122625 | SEMICONDUCTOR MEMORY DEVICE HAVING TEST CIRCUIT - A semiconductor memory device including a test circuit capable of reducing test time includes a test circuit for generating leakage current in the semiconductor memory device in a standby state in response to a test mode signal and a standby signal that provides standby state information of the semiconductor memory device. | 05-14-2009 |
20090129183 | METHOD AND DEVICE FOR HIGH SPEED TESTING OF AN INTEGRATED CIRCUIT - An integrated circuit and a method for testing an integrated circuit. The method includes providing a first high frequency clock signal sequence to a first group of components of an integrated circuit during a test sequence; characterized by receiving, by a first memory circuit within the integrated circuit, at a low reception rate, a first high frequency signal pattern information and a first low frequency signal pattern information; generating the first high frequency clock signal sequence in response to a first high frequency clock signal and in response to the first high frequency signal pattern information; wherein the first high frequency signal pattern information is being retrieved at a first high retrieval rate from the first memory circuit; and generating a first low frequency clock signal sequence in response a first low frequency clock signal and in response to the first low frequency signal pattern information; wherein the first high frequency signal pattern information is being retrieved at a low retrieval rate from the first memory circuit. | 05-21-2009 |
20090129184 | METHODS AND SYSTEMS FOR FAILURE ISOLATION AND DATA RECOVERY IN A CONFIGURATION OF SERIES-CONNECTED SEMICONDUCTOR DEVICES - A method of identifying at least one anomalous device in a configuration of series-connected semiconductor devices, comprising: selecting a device in the configuration; sending a command to the selected device, the command for placing the selected device into a recovery mode of operation; attempting to elicit identification data from the selected device while in the recovery mode of operation; if the attempt is successful, selecting a next device in the configuration of series-connected semiconductor devices and repeating the sending and the attempting to elicit; and if the attempt is unsuccessful, concluding that the selected device is an anomalous device. Also, a method of recovering data from a configuration of series-connected semiconductor memory devices having undergone a failure, comprising: placing an operable device of the configuration into a recovery mode of operation; while the operable device is in the recovery mode of operation, retrieving data currently stored by the operable device; and storing the retrieved data in an alternate memory facility. | 05-21-2009 |
20090129185 | SEMICONDUCTOR CIRCUITS CAPABLE OF SELF DETECTING DEFECTS - A digital circuit and a method for operating the same. The digital circuit includes (a) M×N regular cells electrically arranged in M rows and N columns, (b) N reference cells corresponding one-to-one to the N columns, and (c) N comparing circuits corresponding one-to-one to the N columns. Each regular cell is electrically coupled to a comparing circuit. Each reference cell is electrically coupled to the associated comparing circuit. Each regular cell includes a first tap node. Each reference cell includes P tap nodes. If a first voltage of the first tap node of a regular cell is between two voltages of two tap nodes of the P tap nodes of the associated reference cell, then the associated comparing circuit is capable of generating a first signal. If the first voltage is not between the two voltages, then the associated comparing circuit is capable of generating a second signal. | 05-21-2009 |
20090129186 | SELF-DIAGNOSTIC SCHEME FOR DETECTING ERRORS - The present invention is generally related to integrated circuit devices, and more particularly, to methods and systems of a multi-chip package (MCP) containing a self-diagnostic scheme for detecting errors in the MCP. The MCP generally comprises a controller, at least one volatile memory chip having error detection logic, at least one non-volatile memory chip, and at least one fail signature register for storing fail signature data related to memory errors detected in the MCP. The controller can poll the fail signature register for fail signature data related to memory errors stored therein. Upon detection of fail signature data, the controller can store the fail signature data on a fail signature register located on a non-volatile memory. | 05-21-2009 |
20090141573 | System and Method for Better Testability of OTP Memory - A system for testing logic circuits for executing writing and reading operations in a one-time programmable (OTP) memory having an array of memory cells is disclosed, the system comprising a column of testing cells having the same number of cells as that of an entire column of the array of memory cells, a row of testing cells having the same number of cells as that of an entire row of the array of memory cells, wherein both the column and row of testing cells are first written to and then read out from during a testing operation, and can never be accessed during non-testing operations of the OTP memory. | 06-04-2009 |
20090154270 | FAILING ADDRESS REGISTER AND COMPARE LOGIC FOR MULTI-PASS REPAIR OF MEMORY ARRAYS - An integrated circuit having an integrated circuit and method for moving a failing address into a next available FAR by utilizing the functional compare circuitry during BIST of redundant memory elements. A method of is disclosed that includes: providing a set of FARs and an associated set of redundant elements, wherein each FAR maps to a corresponding redundant element; testing a set of elements and placing an address of each failing element into a FAR; testing each redundant element and marking a FAR as bad when a redundant element corresponding to the FAR fails; and readdressing the set of elements and placing an address of an element being readdressed in a new FAR when the address of the element being readdressed matches an address in a FAR that has been marked as bad. | 06-18-2009 |
20090154271 | Semiconductor memory device and method for testing the same - Semiconductor memory device and method for testing the same includes a unit for characterized in that a burst length is increased in a test of a read operation and a write operation and a unit for connecting a plurality of banks to one data pad by sequentially and outputting the data. | 06-18-2009 |
20090154272 | FUSE APPARATUS FOR CONTROLLING BUILT-IN SELF STRESS AND CONTROL METHOD THEREOF - A fuse apparatus for controlling a built-in self stress unit including a built-in self stress configured to repeatedly generate any stress test pattern in a test mode, and generate a one-cycle end signal when one cycle for the generated stress test pattern has ended, and a fuse configured to record a operation state of the built-in self stress according to the one-cycle end signal. | 06-18-2009 |
20090154273 | MEMORY INCLUDING A PERFORMANCE TEST CIRCUIT - A memory includes a plurality of memory cells each including a true data input connected to a true bit line and complementary data input connected to a complementary bit line, and two inverters connected head-to-tail firstly to the true data input and secondly to the complementary data input. The memory also includes a test circuit includes a plurality of test cells, each test cell includes a true data input connected to a complementary data input of the preceding test cell and a complementary data input connected to the true data input of the following test cell, the complementary data input of the last test cell being connected to the true data input of the first test cell, each test cell comprising a first inverter connected between the true data input and the complementary data input. The looped chain thus formed propagates a signal whose period is a function of the performance of the storage cells. | 06-18-2009 |
20090161459 | Dynamic Random Access Memory With Low-Power Refresh - A technique to reduce refresh power in a DRAM is disclosed. In one embodiment, all of the DRAM memory cells are refreshed at a first rate and a subset of the memory cells are refreshed a second rate greater than the first rate. In another embodiment, the DRAM has a refresh controller that generates a refresh address and controls the refresh of the memory cells addressed by the refresh address. A marker memory is used by the refresh controller to determine which of the memory cells requires refreshing at a rate faster than the refresh rate of the remaining memory cells. Also disclosed is a method to determine which of the memory cells are to be refreshed at the faster rate and to store the results in the marker memory. | 06-25-2009 |
20090161460 | RETENTION TEST SYSTEM AND METHOD FOR RESISTIVELY SWITCHING MEMORY DEVICES - A retention test system and method for resistively switching memory devices is disclosed. One embodiment provides a plurality of memory cells configured to be changed over between a first state of high electrical resistance and a second state of low electrical resistance, wherein the system is configured to apply a bias voltage to at least one memory cell of the memory device to be tested. | 06-25-2009 |
20090168573 | ADAPTIVE MEMORY ARRAY VOLTAGE ADJUSTMENT - In some embodiments a sensor is to sense a temperature of a memory occurring in the memory during active use of the memory. A controller is to adjust a voltage supply of the memory during active use of the memory in response to the sensed temperature. In some embodiments a monitor is to monitor errors occurring in a memory during active use of the memory, and a controller is to adjust a voltage supply of the memory during active use of the memory in response to the monitored errors. Other embodiments are described and claimed. | 07-02-2009 |
20090175105 | Semiconductor memory device that includes an address coding method for a multi-word line test - Example embodiments relate to a semiconductor memory device that includes an address coding method for a multi-word line test, for example, an address coding method to test a semiconductor memory device having a cell block row selection circuit. The semiconductor memory device may include a plurality of memory cell blocks, where each memory cell block may include memory cells coupled to a bit line. The method may include coding row addresses of the memory cell block by dividing one or more row addresses corresponding to cell blocks of the memory cell block to create sub-cell blocks and adding the sub-cell blocs into the main cell blocks to create a logical memory block, which enables word lines of the main cell blocks and sub-cell blocks at the same time. | 07-09-2009 |
20090175106 | APPARATUS FOR IMPLEMENTING EFUSE SENSE AMPLIFIER TESTING WITHOUT BLOWING THE EFUSE - Apparatus implements effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a valid “0” and “1” before programming the eFuse. A first precharge device and a second precharge device that normally respectively precharge a true sense node and a complement sense node to a high voltage are driven separately. For testing, one of the precharge devices is conditionally held off to insure the sense amplifier results in a “0” and “1”. This allows the testing of the sense amplifier devices as well as down stream connected devices. Once testing is complete, both precharge devices are controlled in tandem. | 07-09-2009 |
20090196114 | Semiconductor storage device - A semiconductor storage device includes: a plurality of I/O terminals configured in a block, and including a representative I/O terminal and a non-representative I/O terminal; a plurality of memory cells each associated with the plurality of I/O terminals to store data; a data input portion to which data to be stored in the plurality of memory cells is input; and a data output portion which outputs data stored in the plurality of memory cells, the data input portion including a branch circuit which distributes the data input to the representative I/O terminal to all of the plurality of memory cells when the data to be stored in the plurality of memory cells is input while in test mode, and the data output portion including: a selection circuit which is connected to the representative I/O terminal, and which selects one of the data output from the plurality of memory cells and outputs the selected data from the representative I/O terminal when the data stored in the plurality of memory cells is output while in the test mode; and a dummy circuit which is provided between the non-representative I/O terminal and the memory cell associated with the non-representative I/O terminal. | 08-06-2009 |
20090207678 | Memory writing interference test system and method thereof - The present invention is a memory writing interference test system and method thereof. The test system comprises a memory, a progressing unit, a write-in unit, a read-out unit, and a discriminating unit. By sequentially writing data and then reading out the written data from one memory block after one through the whole memory, determines if the memory has the memory writing interference. | 08-20-2009 |
20090219773 | Integrated Circuit, Method for Acquiring Data and Measurement System - An embodiment of an integrated circuit comprises a plurality of cells. Each cell comprises a first supply node, a second supply node, a series connection with a first transistor, a second transistor and an electrical element. The series connection is coupled between the first and the second supply node. The electrical element includes a first and a second node. A third transistor is coupled between the first node of the electrical element and a first output node of the cell and a fourth transistor is coupled between the second node of the electrical element and the second output node of the cell. A control terminal of the first, the third and the fourth transistor is coupled to a first control node of the cell and a control terminal of the second transistor is coupled to a second control node of the cell. | 09-03-2009 |
20090219774 | SEMICONDUCTOR MEMORY DEVICE AND PARALLEL TEST METHOD OF THE SAME - Semiconductor memory device and parallel test method of the same. The test includes writing data into multiple memory banks simultaneously, reading the data from a portion of the memory banks, compressing the read data and outputting the compressed data to the outside of a chip. | 09-03-2009 |
20090219775 | Semiconductor memory device - Semiconductor memory device includes a cell array including a plurality of unit cells; and a test circuit configured to perform a built-in self-stress (BISS) test for detecting a defect by performing a plurality of internal operations including a write operation through an access to the unit cells using a plurality of patterns during a test procedure carried out at a wafer-level. | 09-03-2009 |
20090238018 | Integrated circuit including Built-In Self Test circuit to test memory and memory test method - An integrated circuit includes multiple memory circuits including memory cell arrays different in size, a BIST circuit which has a cell sequential transition test processor and which outputs a test cell address, a transition direction specification signal and an active signal. The integrated circuit has adjustment circuits which are provided respectively for the memory circuits and which replace the test cell address with the test cell address in a memory cell array area, or which convert the active signal into a signal indicating non-execution when the test cell address outputted from the BIST circuit corresponds to a cell in a virtual cell array being in an area outside the memory cell array. | 09-24-2009 |
20090244999 | Clock control during self-test of multi port memory - A multiport memory | 10-01-2009 |
20090245000 | SEMICONDUCTOR INTEGRATED CIRCUIT - A one-hot data generating unit generates one-hot data for the maximum data bit width in which a state of one bit is exclusively inverted with respect to states of other bits while sequentially shifting a bit position to be inverted, and writes the one-hot data in an area of a memory designated by an address. A short defect between wirings connected to the memory is detected by comparing the one-hot data written in the memory with the one-hot data before being written. | 10-01-2009 |
20090245001 | INTEGRATED CIRCUIT AND METHOD FOR TESTING THE CIRCUIT - An integrated circuit includes a memory; a memory test circuit that tests the memory; and an input/output port, wherein the memory test circuit includes a latch circuit that outputs output of the memory, an address of the memory to be accessed is changed in accordance with a first clock signal, and output of the memory corresponding to the changed address is latched in accordance with a latch signal having a cycle of an integral multiple of the first clock signal, data of the latch circuit is output via the input/output port in a cycle of the latch signal, an address of a memory cell corresponding to the output of the memory to be latched by the latch circuit is changed, and the latch and the output is repeated. | 10-01-2009 |
20090268534 | SEMICONDUCTOR MEMORY DEVICE AND TEST METHOD THEREOF - A semiconductor memory device comprises a memory cell array having memory cells arranged at intersections of word lines and bit lines, a first sense amplifier connected to a bit line at a predetermined position of the bit lines, a second sense amplifier connected to a bit line adjacent to the bit line at the predetermined position, a supplying circuit for supplying a predetermined voltage to each bit line connected to the first or second sense amplifier, and a sense amplifier control circuit capable of controlling the first and second sense amplifiers independently. In the semiconductor memory device, the sense amplifier control circuit performs a control in which an operation of either of the first and second sense amplifiers is stopped, the predetermined voltage is supplied to the bit line connected to the stopped sense amplifier, and the other of the first and second sense amplifiers is operated. | 10-29-2009 |
20090273996 | Memory testing system and memory module thereof - A testing system with data compressing function includes a third data end, a first encoder, and a second encoder. The testing system receives testing data and testing address for testing if any memory cell fails in a memory. The memory includes a first data end, a second end, and an address end. The first encoder encodes the testing data to the data type of the first data end according to the testing address. The second encoder encodes the testing data to the data type of the second data end according to the testing address. In this way, the corresponding memory cells of the first data and second ends store same testing data. | 11-05-2009 |
20090285044 | TESTING A MEMORY DEVICE HAVING FIELD EFFECT TRANSISTORS SUBJECT TO THRESHOLD VOLTAGE SHIFTS CAUSED BY BIAS TEMPERATURE INSTABILITY - A supply voltage is set for a memory device at a first supply voltage level. Test data is written to the memory device at the first supply voltage level in response to setting the supply voltage. The supply voltage is decreased for the memory device to a second supply voltage level below the first supply voltage level in response to writing the test data. The test data is read from the memory device at the second supply voltage level in response to decreasing the supply voltage. The supply voltage is increased for the memory device to a third supply voltage level above the second supply voltage level in response to reading the test data. The test data is read from the memory device at the third supply voltage level in response to increasing the supply voltage. The test data written to the memory device at the first supply voltage level is compared to the test data read from the memory device at the third supply voltage level in response to reading the test data from the memory device at the third supply voltage level. | 11-19-2009 |
20090290441 | MEMORY BLOCK TESTING - A memory block of a memory device is tested by programming a plurality of pages of the memory block, passing the memory block if a number of pages, each programmed in a first programming time, is greater than or equal to a first predetermined number and a number of pages, each programmed in a second programming time, is less than or equal to a second predetermined number, and failing the memory block if a programming time of any one of the pages exceeds a predetermined programming time or if the number of pages programmed in the first programming time is less than the first predetermined number or if the number of pages programmed in the second programming time exceeds the second predetermined number. | 11-26-2009 |
20090290442 | METHOD AND CIRCUIT FOR CONFIGURING MEMORY CORE INTEGRATED CIRCUIT DIES WITH MEMORY INTERFACE INTEGRATED CIRCUIT DIES - A memory device comprises a first and second integrated circuit dies. The first integrated circuit die comprises a memory core as well as a first interface circuit. The first interface circuit permits full access to the memory cells (e.g., reading, writing, activating, pre-charging and refreshing operations to the memory cells). The second integrated circuit die comprises a second interface that interfaces the memory core, via the first interface circuit, an external bus, such as a synchronous interface to an external bus. A technique combines memory core integrated circuit dies with interface integrated circuit dies to configure a memory device. A speed test on the memory core integrated circuit dies is conducted, and the interface integrated circuit die is electrically coupled to the memory core integrated circuit die based on the speed of the memory core integrated circuit die. | 11-26-2009 |
20090296504 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF TESTING SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device may include a memory that stores data, an input/output unit and a loopback circuit. The input/output unit inputs and outputs data of a predetermined number of bits in synchronization with a clock signal. The input/output unit may include, but is not limited to, the same number of data input/output terminals as the predetermined number of bits. The loopback circuit performs loopback operation to read data of the predetermined number of bits out of a first optional area of the memory and to write the data into a second optional area of the memory. | 12-03-2009 |
20090296505 | Memory test method and memory test device - A memory test is performed by sequentially generating a number of n-bit addresses, whose first to k-th bits (1≦k≦n) are all set to one of two values, 0 or 1, and whose (k+1)th to n-th bits are all set to the other one of the two values, for all k's which range from 1 to n; writing first test data to each of the generated addresses in the memory; reading second test data from each of the addresses in the memory; and comparing the first test data with the second test data. | 12-03-2009 |
20090303817 | LEAKAGE TESTING METHOD FOR DYNAMIC RANDOM ACCESS MEMORY HAVING A RECESS GATE - A leakage testing method for a DRAM having a recess gate is provided. The method includes the steps of: programming to set the first storage unit and the second storage unit of a same memory cell with different storage statuses; and disturbing one of the word lines extending through the memory cells; then determining whether the DRAM is acceptable or not. When another one of the word lines extending through the memory cells is caused with a reading error by disturbing the one of the word lines extending through the memory cells, a failure is determined as occurred, and the failure is attributed to a leakage type of extended depletion region. When the another one of the word lines extending through the memory cells is not caused with a reading error by disturbing the one of the word lines extending through the memory cells, the DRAM is determined as acceptable. | 12-10-2009 |
20090303818 | TEST CIRCUIT DEVICE FOR SEMICONDUCTOR MEMORY APPARATUS - A test circuit device for a semiconductor memory device includes a main word line driving unit that generates a signal that swings between a driving voltage and one of a first voltage and a second voltage in response to a main decoding signal and a test mode signal, a local driving unit that generates a signal that swings between the driving voltage and one of the first voltage and the second voltage in response to a local decoding signal and the test mode signal, a driving voltage supplying unit that receives an output of the local driving unit and the test mode signal to supply a voltage that swings between the driving voltage and the first voltage, and a sub-word line driver that receives an output of the main word line driving unit and an output of the driving voltage supplying unit to determine whether the sub-word line is enabled or not. | 12-10-2009 |
20090310430 | METHODS FOR CHARACTERIZING DEVICE VARIATION IN ELECTRONIC MEMORY CIRCUITS - A circuit includes a comparator circuit configured such that its output toggles from a first digital logical level to a second digital logical level when its first and second inputs transition between a first state wherein the first input has an applied voltage greater than an applied voltage at the second input and a second state wherein the first input has an applied voltage less than an applied voltage at the second input. A plurality of cells each have at least one series-connected pair of field effect transistors interconnected at an output node intermediate the field effect transistors. Decoding logic is configured to select a given one of the cells for measurement, and selectively interconnect the output node of the given one of the cells to the first input of the comparator circuit. Voltage supply circuitry is configured to (i) apply voltages to the gates of the pair of transistors of the given one of the cells selected for measurement, such that the pair of transistors operate in a linear region, and have a variable voltage difference, Δ, between their gate-to-source voltages, and (ii) vary the Δ until the comparator circuit output toggles from the first digital logical level to the second digital logical level. | 12-17-2009 |
20090316506 | Serially Decoded Digital Device Testing - Testing of memories that decode a serial stream of address data to access the memory may be performed by either successively halving the number of selected word lines as each address bit is acquired, until a single word line is selected, or by rotating the selection bits in its shift register to select a new set of address lines. As such, a combination of incomplete addressing and rotation can efficiently test large memories by reading and/or writing groups of words. Similar techniques may also be applied to non-memory devices. | 12-24-2009 |
20090316507 | Generation Of Test Sequences During Memory Built-In Self Testing Of Multiple Memories - The present invention concerns an apparatus including a modular memory and an address locator circuit. The modular memory may be configured to generate a current address signal, a first data output signal and a second data output signal in response to a first port address signal, a second port address signal, an initial state parameter, a target state parameter, a first port enable signal, a second port enable signal, a write enable signal, a data input signal, a first location signal and a second location signal. The address locator circuit may be configured to generate the first location signal and the second location signal in response to the first port address signal, the second port address signal and the current address signal. | 12-24-2009 |
20090316508 | PRECISE tRCD MEASUREMENT IN A SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device is operable in normal and test operation modes. At the test operation, in response to a first active command, a row address signal that is input from the outside is captured in the row decoder, and in response to a first write/read command, a column address signal input from the outside is captured in the column decoder. At this time, a word line and a bit line are not selected. Thereafter, in response to a second active command, a word line corresponding to the row address signal is selected in the row decoder, and, in response to a second write/read command, a bit line that corresponds to the column address signal is selected in the column decoder. The time period from the time at which the second read/write command is input to the time at which the second active command is input, is measured as tRCD. | 12-24-2009 |
20090323445 | High Performance Read Bypass Test for SRAM Circuits - A design structure embodied in a machine readable medium used in a design process and an integrated circuit for high performance SRAM (Static Random Access Memory) read bypass for BIST (built-in self-test). The design structure and integrated structure includes a dynamic to static conversion unit for a read output of an SRAM array, and a test bypass unit integrated into the dynamic to static conversion unit, so as to allow the read output of the SRAM array to pass through in a non-test mode without impacting performance, and bypass the read output of the SRAM array and allow a test signal to pass though in a test mode. | 12-31-2009 |
20090323446 | MEMORY OPERATION TESTING - Test circuitry for determining whether a memory can operate at a lower operating voltage. The test circuitry includes a sense circuit having a delayed sensing characteristic as compared to other sense amplifier circuits of the memory. With this circuitry the test circuitry can determine if the sense circuit can provide valid data under more severe sensing conditions. In one example, the sense circuit includes a delay circuit in the sense enable signal path. If sense circuit can provide data at more server operating conditions, then the memory operating voltage can be lowered. | 12-31-2009 |
20090323447 | Apparatus for measuring data setup/hold time - An apparatus for measuring data setup/hold time is capable of effectively measuring a setup/hold time of data, and includes a data generating unit for delaying an external clock signal according to counting signals and generating an internal clock signal and data signals from the delayed external clock signal in response to test signals, a data latch unit for latching buffered data signals in synchronization with the internal clock signal, wherein the buffered data signals are produced by buffering the data signals, a flag signal generating unit for generating flag signals from the latched data signals latched in the data latch unit in response to the test signals, and a counter for producing the counting signals in response to the flag signals. | 12-31-2009 |
20100008170 | Semiconductor tester and testing method of semiconductor memory - The disclosure concerns a semiconductor tester for testing a memory under test. The semiconductor tester comprises a pattern generator generating address information on the pages and generating a test pattern; a waveform shaper shaping the test pattern and outputting a test signal based on the shaped test pattern to the memory cells in the page identified by the address information; a comparator comparing a result signal output from the memory under test receiving the test signal with an expectation value; and a bad block memory storing information on a bad block in the memory under test in advance, when the page identified by the address information is included in the bad block, the bad block memory outputting a bad signal used to skip from the address information on the page included in the bad block to the address information on the page included in a next block under test. | 01-14-2010 |
20100014368 | SYSTEM THAT INCREASES DATA EYE WIDTHS - One embodiment provides a system including an integrated circuit configured to receive a signal and invert first read data bits based on the signal. The integrated circuit provides inverted first read data bits that increase data eye widths of second read data bits adjacent the inverted first read data bits. | 01-21-2010 |
20100014369 | METHOD FOR TESTING A STATIC RANDOM ACCESS MEMORY - A method testing an SRAM having a plurality of memory cells is disclosed. In a first step, a bit value is written into a cell under test (CUT). Subsequently, the first and second enabling transistors are disabled and the bit lines are discharged to a low potential. Next, the word line (WL) coupled to the memory cell under test is activated for a predetermined period. During a first part of this period, one of the bit lines (BLB) is kept at the low potential to force the associated pull up transistor in the CUT into a conductive state, after which this bit line (BLB) is charged to a high potential. Upon completion of this period, the bit value of the first cell is determined. The method facilitates the detection of weak or faulty SRAM cells without requiring the inclusion of dedicated hardware for this purpose. | 01-21-2010 |
20100027359 | Memory test circuit which tests address access time of clock synchronized memory - A circuit for testing an access time of a clock synchronization type memory, includes a delay circuit, a sampling circuit and a coincidence detection circuit. The delay circuit generates a delayed clock obtained by delaying, by a time acceptable for a memory performance, a clock inputted to a memory. The sampling circuit takes in and outputs an output from the memory at the timing of the delayed clock. The coincidence detection circuit detects coincidence or non-coincidence by comparing the output from the sampling circuit with an expected value for the output from the memory. | 02-04-2010 |
20100034037 | Semiconductor testing device and method of testing semiconductor memory - The disclosure concerns a semiconductor tester for testing a MUT, comprising a pattern generator; a pattern formatter; a comparator comparing a result signal from the MUT with an expectation value; a bad block memory; an AFM pre-storing pass/fail information of each of memory cells; a data compressor compressing data of pass/fail information in the AFM; a compression failure buffer memory storing data compressed; a good block register storing an address number of a good block prepared; and an address generator, wherein when the block to be compressed is a good one, the good block register sends a address number of the good block to the compress failure buffer memory. | 02-11-2010 |
20100034038 | INTEGRATED CIRCUIT INCLUDING SELECTABLE ADDRESS AND DATA MULTIPLEXING MODE - An integrated circuit includes a memory array, first pads, and second pads. The integrated circuit is configured to operate in a first mode and in a second mode. The first mode includes receiving data signals on the first pads and address signals on the second pads to access the memory array. The second mode includes receiving multiplexed data signals and address signals on the first pads to access the memory array. | 02-11-2010 |
20100039876 | Functional Float Mode Screen to Test for Leakage Defects on SRAM Bitlines - A method and system for maintaining Static Random Access Memory (SRAM) functionality while simultaneously screening for leakage paths from bitline to ground during Float Mode operation. The SRAM configuration enables SRAM cell selection for a read or write operation. In response to the SRAM cell selection, a group of pre-charge (PCHG) signals are provided with a high value. When selection is made from a top sub-group of SRAM cells, a corresponding bitline, “BLT_TOP”, takes a value which reflects a state stored in the selected cell. In addition, the bitline corresponding to the bottom sub-group of cells, “BLT_BOT”, takes a high value. If there is a leakage defect, BLT_BOT drops to a low value. With no leakage defect, the data stored in the selected cell is determined based on the result of a logical NAND operation including the respective states indicated by the BLT_TOP and by the BLT_BOT. | 02-18-2010 |
20100054062 | Static random access memory (SRAM) and test method of the SRAM having precharge circuit to precharge bit line - An SRAM includes a memory cell and a precharge circuit. The precharge circuit precharges a bit line pair with a power supply voltage before writing a data in the memory cell or before reading a data therefrom at a time of a normal mode, and which feeds a power supply voltage to at least a low level data-holding node of a node pair of the memory cell at a time of a read test mode, between time for writing a data in the memory cell and time for reading a data therefrom. | 03-04-2010 |
20100054063 | SEMICONDUCTOR MEMORY DEVICE, TEST METHOD THEREOF AND SEMICONDUCTOR DEVICE - A semiconductor memory device comprises a memory cell array having memory cells including a plurality of memory cells, and also comprises a first bit line, a first sense amplifier circuit and a control circuit. A signal is read out from a selected memory cell of the memory cell array through the first bit line. The first sense amplifier circuit has a single-ended configuration and includes an amplifying element amplifying a signal voltage of the first bit line so as to convert the signal voltage into an output current. The control circuit controls a test operation to measure a current flowing in the first sense amplifier circuit independently of currents flowing in other circuit portions. | 03-04-2010 |
20100085826 | Test circuit for measuring resistance distribution of Memory cells and semiconductor system including the same - The test circuit for measuring a resistance distribution of memory cells includes a sensing circuit and a digital value generation circuit. The sensing circuit compares a reference voltage with a voltage of a sensing node receiving a voltage of a bit line connected with a resistive element and generates a sensing signal. The digital value generation circuit generates a digital value corresponding to a resistance-capacitance (RC) delay of the bit line in response to the sensing signal from the sensing circuit. | 04-08-2010 |
20100091595 | INTEGRATED CIRCUIT WITH CONTROL CIRCUIT FOR PERFORMING RETENTION TEST - An integrated circuit includes an array of memory cells, a clock generator configured to generate a clock signal, and a control circuit configured to perform a retention test on the array of memory cells based on the clock signal. A period of the clock signal defines a retention period for the retention test. | 04-15-2010 |
20100091596 | SOLID STATE DRIVE SYSTEMS AND METHODS OF REDUCING TEST TIMES OF THE SAME - Example embodiments of the inventive concept are directed to solid state device systems and methods of reducing test times of the same. | 04-15-2010 |
20100097872 | WAFER TEST TRIGGER SIGNAL GENERATING CIRCUIT OF A SEMICONDUCTOR MEMORY APPARATUS, AND A WAFER TEST CIRCUIT USING THE SAME - A wafer test trigger signal generating circuit of a semiconductor memory apparatus includes an enable timing control unit configured to generate an enable signal by using a plurality of address signals, and a trigger signal generating unit configured to generate a test trigger signal, which designates a decoding timing of a test mode defined by the plurality of address signals, in response to the enable signal. | 04-22-2010 |
20100110811 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first data input circuit configured to align data inputted to a first data pad in parallel for transferring the aligned data to a first global bus and for transferring the aligned data to a second global bus in a test mode; and a second data input circuit configured to align data inputted to a second data pad in parallel for transferring the aligned data to the second global bus and to not receive data in the test mode. | 05-06-2010 |
20100110812 | SEMICONDUCTOR DEVICE - A semiconductor device includes a test circuit that generates a pulse signal from a timing signal. The test circuit outputs the pulse signal and a first set of address signals in response to a first type transition of the timing signal. The test circuit outputs the pulse signal and a second set of address signals in response to a second type transition of the timing signal. The second set of address signals is different from the first set of address signals. | 05-06-2010 |
20100128544 | Bit line bridge detecting method in semiconductor memory device - The method of detecting the bit line bridge in a semiconductor memory device includes enabling a sensing state for an even bit line connected to an even sense amplifier and an odd bit line connected to an odd sense amplifier, where the odd bit line is adjacent to the even bit line, first changing the odd bit line to a pre-charge state to pre-charge the odd bit line while maintaining the sensing state of the even bit line, second changing the odd bit line to a floating state, and applying a pause time period. | 05-27-2010 |
20100135093 | OPERATING VOLTAGE TUNING METHOD FOR STATIC RANDOM ACCESS MEMORY - An operating voltage tuning method for a static random access memory is disclosed. The static random access memory receives a periphery voltage and a memory cell voltage. The steps of the method mentioned above are shown as follows. First, perform a shmoo test on the static random access memory to obtain a shmoo test plot and a minimum operating voltage. Compare the minimum operating voltage with a preset specification. Position a specification position point on the line which the periphery voltage is equal to the memory cell voltage in the shmoo test plot corresponding to the preset specification. Fix one of the memory cell voltage and the periphery voltage and gradually decrease the other to test the static random access memory and obtain a failure bits distribution. Finally, tune process parameters of the static random access memory according to the specification position point and the failure bits distribution. | 06-03-2010 |
20100142300 | Semiconductor Memory Device And Methods Of Performing A Stress Test On The Semiconductor Memory Device - A semiconductor memory device and method of performing a stress test on a semiconductor memory device are provided. In an example, the semiconductor memory device includes a multiplexer arrangement configured to switch a timing signal that controls an internal timing of the semiconductor memory device from an internal signal to an external signal during a stress mode, and further includes one or more word lines of the semiconductor memory device receiving a stress voltage during the stress mode, a duration of the stress mode based upon the external signal. In another example, the semiconductor memory device includes one or more word lines configured to receive a stress voltage during a stress mode, and a precharge circuit configured to provide a precharge voltage to a bit line of the semiconductor memory device during the stress mode. | 06-10-2010 |
20100142301 | SEMICONDUCTOR MEMORY DEVICE AND SELF REFRESH TEST METHOD - A semiconductor memory device includes a memory cell array that includes a plurality of memory cells, an SR timer that determines a cycle of self refresh of the memory cell, a refresh counter that generates an internal address signal of the memory cell which is a target of the self refresh, and a circuit that outputs a pulse active signal to continuously execute refresh operation in one cycle of the self refresh. | 06-10-2010 |
20100142302 | SEMICONDUCTOR MEMORY DEVICE AND TESTING METHOD THEREFOR - A semiconductor memory device includes memory blocks, a redundancy determining circuit that can enter in a parallel test mode in which the both memory blocks are simultaneously accessed, and a verifying circuit that verifies data read from the memory blocks. When accessing normal cell areas of the memory blocks simultaneously, in response to a fact that at least one of the memory blocks is replaced by a redundancy memory cell, the redundancy determining circuit supplies pass signals indicating a memory block in which replacement is performed to the verifying circuit. Based on the pass signals, the verifying circuit passes verification of data read from the memory block in which the replacement is performed. | 06-10-2010 |
20100182859 | Method and Apparatus for Testing a Memory Device - Techniques for testing a semiconductor memory device are provided. The memory device includes a plurality of memory cells and a plurality of row lines and column lines connected to the memory cells for selectively accessing one or more of the memory cells. The method includes the steps of: applying a first voltage to at least a given one of the row lines corresponding to at least a given one of the memory cells to be tested, the first voltage being selected to stress at least one performance characteristic of the memory device, the first voltage being different than a second voltage applied to the given one of the row lines for accessing at least one of the memory cells during normal operation of the memory device; exercising the memory device in accordance with prescribed testing parameters; and identifying whether the memory device is operable within prescribed margins of the testing parameters. | 07-22-2010 |
20100195426 | Semiconductor memory device and method of testing the same - A device and a method controlling the device are provided. A first command is supplied to the device in synchronization with a clock signal of a first frequency. The first command is to have the device perform a first operation. The frequency of the clock signal is changed from the first frequency to a second frequency higher than the first frequency. The device performs the first operation in synchronization with the clock signal of the second frequency following changing the frequency of the clock signal. | 08-05-2010 |
20100208536 | Structure and Methods for Measuring Margins in an SRAM bit - Methods for measuring the read margin, write margin, and stability margin of SRAM bits with operational circuitry that includes effects of the SRAM array architecture and circuit design. In addition, methods for measuring the read margin, write margin, and stability margin of SRAM that excludes the effects of SRAM array architecture and circuit design. | 08-19-2010 |
20100208537 | DYNAMIC RANDOM ACCESS MEMORY (DRAM) REFRESH - A method for refreshing a Dynamic Random Access Memory (DRAM) includes performing a refresh on at least a portion of the DRAM at a first refresh rate, and performing a refresh on a second portion of the DRAM at a second refresh rate. The second portion includes one or more rows of the DRAM which do not meet a data retention criteria at the first refresh rate, and the second refresh rate is greater than the first refresh rate. | 08-19-2010 |
20100226190 | SRAM AND TESTING METHOD OF SRAM - An SRAM includes a memory cell; and a control circuit configured to change a signal level of a signal which is used in an ordinary mode for access to the memory cell in a test mode to apply a disturbance to the memory cell. The control circuit can change the signal level to set a level of the disturbance optionally. | 09-09-2010 |
20100232242 | Method for Constructing Shmoo Plots for SRAMS - A method of preparing Shmoo plots where both the number of failures and also the failure type is specified at each test voltage measurement point. A method that uses the operational SRAM array circuitry to determine the type of failure that may have occurred at each test voltage measurement point. | 09-16-2010 |
20100246300 | SEMICONDUCTOR MEMORY DEVICES INCLUDING BURN-IN TEST CIRCUITS - A semiconductor memory device includes a memory cell array including a first memory cell coupled to a first bit line and a word line, and a second memory cell coupled to a second bit line and the word line and disposed adjacent to the first memory cell. A controller circuit is configured to provide first and second precharge voltages to the first and second bitlines, respectively. The first precharge voltage is provided as a positive power supply voltage and the second precharge voltage is provided as a negative stress voltage during a burn-in test operation. Related methods of operation are also discussed. | 09-30-2010 |
20100246301 | METHOD FOR TESTING A MAIN MEMORY - A method for testing a working memory which includes a matrix of memory cells, an address bus/address coder and a write circuit/read circuit, consists of two method parts with which in one step, at least a part of the address bus/address coder is tested with regard to address faults and in another step at least a part of the memory cells are tested with regard to cell faults. The testing steps are temporally independent of one another and may thus be effected also during the operation. | 09-30-2010 |
20100260001 | MEMORY DEVICE AND METHODS THEREOF - A device includes a memory configured so that, in the event that one pass-gate transistor associated with a bit cell is determined to be excessively weak such that reading the bit cell could be undesirably difficult, a second pass-gate transistor can be configured to support a read operation. For example, during a manufacturing test procedure, the access speed of each bit cell at a memory device is determined. If a bit cell fails to achieve a desired access speed, the column of the memory that includes the defective bit cell can be configured to access information stored at the bit cell using the second bit line associated with the second pass-gate transistor. | 10-14-2010 |
20100277995 | SEMICONDUCTOR MEMORY DEVICE CAPABLE OF OPTIMIZING SIGNAL TRANSMISSION POWER AND POWER INITIALIZING METHOD THEREOF - A semiconductor memory device can automatically control signal transmission power on-chip based on a wireless signal transmission. The semiconductor memory device can have a multi-chip stack structure. A power initializing method of the semiconductor memory device can comprise providing a test signal generated by a signal-providing chip to a first chip, checking whether the test signal provided to the first chip has an error, providing the checking result to the signal-providing chip, setting the power of a first signal provided to the first chip according to the checking result, and setting the power of a signal provided to a second chip adjacent to the first chip and close to the signal-providing chip using the power of the first signal. | 11-04-2010 |
20100296353 | SEMICONDUCTOR DEVICE - Provided is a semiconductor device capable of effectively testing whether memory cells and a memory cell array are defective. The semiconductor device may include a memory cell array having a plurality of memory cells and an external test pad connected to an internal test pad. A test voltage may be applied to the plurality of word lines connected to the plurality of memory cells via the external test pad and the internal test pad in a test mode, wherein the test voltage disables the plurality of word lines. | 11-25-2010 |
20100302888 | DYNAMIC RANDOM ACCESS MEMORY DEVICE AND INSPECTION METHOD THEREOF - A memory cell potentially including a retention fault attributable to a random change over time of data retention capability is screened by applying a bias to a gate electrode such that holes are accumulated on an interface of a substrate that is a component of a memory cell transistor on the side of the gate electrode and, after applying the bias, performing a pause-refresh test for inspecting the data retention capability of the memory cell. | 12-02-2010 |
20100309738 | SEMICONDUCTOR MEMORY APPARATUS AND TEST METHOD THEREOF - A semiconductor memory apparatus includes a bit line pair electrically connected to a memory cell and a bit line sense amplifier for detecting and amplifying voltage levels of the bit line pair. The semiconductor memory apparatus is configured to perform a test to determine the occurrence of leakage current by deactivating the bit line sense amplifier and applying a test voltage to the bit line pair when the semiconductor memory apparatus is in test mode. | 12-09-2010 |
20100309739 | SEMICONDUCTOR MEMORY APPARATUS AND PROBE TEST CONTROL CIRCUIT THEREFOR - Disclosed probe test control circuit includes: a bank active circuit configured to generate a bank active signal in response to a bank address and bank-by-bank test control signals; and a mat active circuit configured to generate a mat-by-mat sub-wordline selection signal and provide the mat-by-mat sub-wordline selection signal to a selected memory bank, in response to a row address signal, a row address enable signal and a mat-by-mat test control signal. | 12-09-2010 |
20100329054 | Memory Built-In Self-Characterization - A memory circuit includes an operational memory and a monitor circuit comprising a circuit element in the operational memory and/or a circuit element substantially identical to a corresponding circuit element in the operational memory. The monitor circuit is operative to measure at least one functional characteristic of the operational memory. A control circuit coupled to the monitor circuit is operative to generate a control signal which varies as a function of the measured characteristic of the operational memory. The memory circuit further includes a programmable voltage source coupled to the operational memory which is operative to generate at least a voltage and/or a current supplied to at least a portion of the operational memory which varies as a function of the control signal. | 12-30-2010 |
20100329055 | MEASURING ELECTRICAL RESISTANCE - A circuit having a first circuit configured to receive an input voltage and generate a first voltage that generates a first current flowing through a resistive device and a second voltage that generates a second current; a node electrically coupled to the resistive device and having a third voltage that generates a third current; and a second circuit configured to generate a fourth voltage having a logic state indicating a logic state of the resistive device. | 12-30-2010 |
20110013470 | Structure and Method for Screening SRAMS - An integrated circuit containing an SRAM that provides a switch to decouple the SRAM wordline voltage from the SRAM array voltage during screening and that also provides different wordline and array voltages during a portion of the SRAM bit screening test. A method for screening SRAM bits in an SRAM array in which the wordline voltage is different than the array voltage during a portion of the screening test. | 01-20-2011 |
20110019492 | TEST DEVICE AND TEST METHOD FOR RESISTIVE RANDOM ACCESS MEMORY AND RESISTIVE RANDOM ACCESS MEMORY DEVICE - A first write enable signal that changes with a constant period and a second write enable signal that changes at a time portion in which a limit time between activation/deactivation control of word lines and activation/deactivation control of bit lines is checked are input, a plurality of core control signals in which a time interval with which the core control signals change is locally shorter than a period of the first write enable signal based on the first write enable signal and the second write enable signal that are input is generated, and an operation verification of the resistive random access memory is performed by using the generated core control signals, whereby a cycle time in an arbitrary test cycle is locally and arbitrary adjusted. | 01-27-2011 |
20110026339 | Semiconductor memory device performing refresh operation and method of testing the same - A semiconductor memory device includes a mask information storage circuit that stores therein mask information indicating an area for which the self refresh operation is not performed among a plurality of areas in a memory cell array, a mask determining circuit that is activated by a self refresh command and generates a match signal in response to a detection of a match between a refresh address and the mask information, and a refresh operation control circuit that disables the self refresh operation in response to an activation of the match signal. When a test mode signal is activated, the mask determining circuit is also activated by the auto refresh command. With this configuration, it is possible to perform a test of a partial array self refresh function without actually entering a self refresh mode. | 02-03-2011 |
20110026340 | MEMORY TEST CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT AND MEMORY TEST METHOD - A memory test circuit tests a memory including an actual array portion and a redundancy portion. The memory test circuit includes: an input data selector outputting first test data excluding data for the redundancy portion in test data representing data for the actual array portion and the redundancy portion as input selecting data in a redundancy BIST mode (RBM); an input data switching circuit outputting the test data as output test data to the memory in a direct BIST mode (DBM), and outputting data obtained by adding redundancy bits to the input selecting data as the output test data to the memory based on the input selecting data and output redundancy codes representing redundancy codes in the RBM; an output data switching circuit outputting data obtained by removing the redundancy bits from read data as output selecting data based on the read data from the memory and the output redundancy codes in the RBM; and a memory BIST comparator checking a value of the read data with a checking expectation value to output a checking result as a test result in the DBM, and checking a value of the output selecting data with an expectation value for the actual array portion in the checking expectation value to output a checking result as the test result in the RBM. | 02-03-2011 |
20110026341 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes memory banks, each having sub banks. The semiconductor memory apparatus is configured to allocate same test input/output line to a certain sub bank of one memory bank and a certain sub bank of another memory bank during a multi-bit test. | 02-03-2011 |
20110026342 | MULTI-PORT MEMORY DEVICE - A multi-port memory device includes: a bank having a plurality of matrices; a plurality of test data input/output units where data is input/output using a test mode for detecting a defective memory cell; a plurality of ports converted into a decoding device for decoding a command/address at the test mode; a plurality of data transfer lines for transferring data between the matrices and the test data I/O units, wherein the data transfer lines is grouped into the number of matrices; and a plurality of temporary storing units included between the data transfer lines and the matrices for temporarily storing data. | 02-03-2011 |
20110026343 | BIST DDR MEMORY INTERFACE CIRCUIT AND METHOD FOR TESTING THE SAME - An apparatus and method for self-testing a DDR memory interface are disclosed. In one aspect, a built-in-self-test (BIST) memory interface circuit includes a signal multiplier for receiving a first clock signal from a tester and outputs a multiplied clock signal. A first multiplexer is used for selecting between a test mode and a normal operating mode and provides an output signal. A delay magnitude generator is coupled to the signal multiplier to receive the multiplied clock signal and provides a second clock signal and a phase control signal. A plurality of digitally controlled delay line blocks are used for each receiving the second clock signal and the phase control signal and outputting a phase shifted data strobe output signal in response to receiving an internal data strobe input signal. A second multiplexer selects one of the internal data strobe input signals and a third multiplexer selects the phase shifted data strobe output signal that corresponds to the selected internal data strobe input signal. A phase detector determines a phase difference between the selected internal data strobe input signal and the selected phase shifted data strobe output signal and outputs a phase difference value. | 02-03-2011 |
20110032782 | Test method and device for memory device - Provided is a test method for a memory device including a plurality of storage regions and an SPO recovery unit. The test method stores data in the plurality of storage regions. The test method shuts off supply of power to the memory device and resupplies the power to the memory device. The test method determines an operational state of the SPO recovery unit after the resupplying step based on the stored data. | 02-10-2011 |
20110038218 | Memory Chip and Method for Operating the Same - A memory chip and method for operating the same are provided. The memory chip includes a number of pads. The method includes inputting a number of first test signals to the pads respectively, wherein the first test signals corresponding to two physically-adjacent pads are complementary; inputting a number of second test signals, respectively successive to the first test signals, to the pads, wherein the first test signal and the second test signal corresponding to each of the pads are complementary; and outputting expected data from the memory chip if the first test signals and the second test signals are successfully received by the memory chip. | 02-17-2011 |
20110044119 | Semiconductor Device having variable parameter selection based on temperature and test method - A semiconductor device that may include temperature sensing circuits is disclosed. The temperature sensing circuits may be used to control various parameters, such as internal regulated supply voltages, internal refresh frequency, or a word line low voltage. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without compromising performance at normal operating temperatures. Each temperature sensing circuit may include a selectable temperature threshold value as well as a selectable temperature hysteresis value. In this way, temperature performance characteristics may be finely tuned. Furthermore, a method of testing the temperature sensing circuits is disclosed in which a current value may be monitored and temperature threshold values and temperature hysteresis values may be thereby determined. | 02-24-2011 |
20110051539 | Method and structure for SRAM VMIN/VMAX measurement - A parametric test circuit is disclosed (FIG. | 03-03-2011 |
20110051540 | Method and structure for SRAM cell trip voltage measurement - A parametric test circuit is disclosed (FIG. | 03-03-2011 |
20110051541 | Semiconductor device - A semiconductor device including a plurality of memory cells arranged in a matrix pattern, a write amplifier which writes write data to the memory cell in synchronization with a clock, a sense amplifier which reads out the write data written in the memory cell in synchronization with the clock, a plurality of column select switches which connect the plurality of the memory cells with the sense amplifier and the write amplifier, a column address decoder which makes the column select switch corresponding to one column among the plurality of the memory cells a conductive state based on a column address, a row address decoder which activates the memory cell of one row based on a row address, and a test write circuit which writes data corresponding to a logical level of a test signal to the memory cell based on a test mode signal. | 03-03-2011 |
20110075498 | SEMICONDUCTOR MEMORY APPARATUS AND TEST METHOD USING THE SAME - A semiconductor memory apparatus includes: a precharge voltage control unit configured to selectively output a bit line precharge voltage or a core voltage as a control voltage in response to a test signal; a bit line equalization unit configured to precharge a bit line to the control voltage; a sense amplifier driving control unit configured to generate a first voltage supply control signal, a second voltage supply control signal and a third voltage supply control signal in response to the test signal, a sense amplifier enable test signal, a first voltage supply signal, a second voltage supply signal and a third voltage supply signal; and a voltage supply unit configured to provide the core voltage, an external voltage and a ground voltage to a sense amplifier with an open bit line structure in response to the first to third voltage supply control signals. | 03-31-2011 |
20110103164 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR PERFORMING DATA COMPRESSION TEST OF THE SAME - A semiconductor memory device includes a plurality of data transmission lines, a plurality of parallel-to-serial conversion sections configured to receive, serially align, and output data from at least two of the plurality of data transmission lines, a plurality of data compression circuits configured to receive, compress, and output outputs of at least two of the plurality of parallel-to-serial conversion sections, and a plurality of data output circuits configured to output respective compression results of the plurality of data compression circuits to an outside of a chip. | 05-05-2011 |
20110103165 | SELF-REFRESH TEST CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS - A self-refresh test circuit includes a test clock generation unit, a pulse generation unit, a period signal selection unit, and a self-refresh pulse control unit. The test clock generation unit divides a clock signal to generate a plurality of divided clock signals having different periods when a test enable signal is enabled, and outputs one of the plurality of divided clock signals as a selected clock signal. The pulse generation unit generates a test period signal in response to the selected clock signal. The period signal selection unit outputs one of the test period signal and a self-refresh period signal as a selected period signal. The self-refresh pulse control unit generates a self-refresh pulse in response to a self-refresh exit signal and the selected period signal. | 05-05-2011 |
20110116332 | MEMORY DEVICE WITH TEST MECHANISM - A semiconductor memory device includes a plurality of memory cell transistors arranged in a matrix and each configured to store data, and a test circuit configured to output to outside the semiconductor memory device an output signal indicative of an amount of test current flowing through a selected one of the plurality of memory cell transistors, wherein the test circuit includes a plurality of reference cell transistors employed to successively produce varying amounts of currents, a comparison circuit configured to successively compare the amount of test current with each of the varying amounts of currents, and a code generating circuit configured to generate a code indicative of a result of the successive comparisons performed by the comparison circuit, wherein the code is output as the output signal. | 05-19-2011 |
20110116333 | MEMORY TEST APPARATUS AND TESTING METHOD - A refresh control circuit receives an interrupt signal, which is a request to refresh DRAM (Dynamic Random Access Memory) and which is asserted at predetermined timings. The refresh control circuit counts the number of times the interrupt signal is asserted, and asserts an interrupt subroutine start signal, which is an instruction to refresh the DRAM, in an idle state in which the DRAM is accessible from an external circuit, for a number of times that is equal to the number of times thus counted. When the interrupt subroutine start signal is asserted, a refresh circuit executes a predetermined interrupt subroutine, and supplies a refresh pattern to the DRAM. | 05-19-2011 |
20110122718 | Low Cost Testing and Sorting for Integrated Circuits - Methods of testing and sorting integrated circuits in clusters are disclosed. Each cluster has power and data terminals connected to common power and data busses providing a common power supply. Each integrated circuit has a first non-volatile memory storing an activation code and a second programmable non-volatile memory that is capable of storing the activation code. If an integrated circuit passes testing, the activation code stored in the first non-volatile memory is written into the second non-volatile memory. An integrated circuit is independently functional upon separation from the cluster if the codes in the first and second non-volatile memories match. Upon separation, integrated circuits are queried to determine which respond. Each integrated circuit includes logic adapted to determine whether the codes in the first and second non-volatile memories match. If the codes do not match, the logic permanently disables the integrated circuit upon separation from the cluster. | 05-26-2011 |
20110128804 | TEST CIRCUIT, SEMICONDUCTOR MEMORY APPARATUS USING THE SAME, AND TEST METHOD OF THE SEMICONDUCTOR MEMORY APPARATUS - A test circuit of a semiconductor memory apparatus includes: a test control signal generating unit configured to enable a control signal if an active signal is enabled after a test signal is enabled, and substantially maintain the control signal in an enable state until a precharge timing signal is enabled; and a precharge control unit configured to invert the control signal to output the inverted signal as a bit line precharge signal when a preliminary bit line precharge signal is in a disable state. | 06-02-2011 |
20110128805 | TEST CIRCUIT, NONVOLATILE SEMICONDUCTOR MEMORY APPRATUS USING THE SAME, AND TEST METHOD - A test circuit of a nonvolatile semiconductor memory apparatus includes a first switching unit, a second switching unit, and a third switching unit. The first switching unit is configured to selectively interrupt application of a pumping voltage for a sense amplifier to a sense amplifier input node. The second switching unit is configured to selectively decouple the sense amplifier input node and a sub input/output node. The sub input/output node is coupled with a data storage region. The third switching unit is configured to selectively connect a voltage applying pad and the sense amplifier input node. | 06-02-2011 |
20110128806 | SEMICONDUCTOR INTEGRATED CIRCUIT TEST METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT - In a semiconductor integrated circuit having multiple memory macros, a memory macro test is carried out with high accuracy within a short period of time. A semiconductor integrated circuit test method according to one aspect of the present invention is applicable to inspection of a semiconductor integrated circuit having multiple memory macros, wherein the number of memory macros to be selected in execution of a simultaneous read-out operation for simultaneously reading out written test data is smaller than the number of memory macros to be selected in execution of a simultaneous write-in operation for simultaneously writing in input test data. | 06-02-2011 |
20110158014 | BURST ADDRESS GENERATOR AND TEST APPARATUS INCLUDING THE SAME - A burst address generator includes a burst bit counter for receiving at least one burst bit, and increasing or decreasing the at least one burst bit, a burst bit splitter for receiving the increased or decreased at least one burst bit from the burst bit counter, and dividing the increased or decreased at least one burst bit into an X burst bit and a Y burst bit, and a selector for receiving an X address, a Y address, the X burst bit, and the Y burst bit, and generating an X burst address based on the X address and the X burst bit and a Y burst address based on the Y address and the Y burst bit. | 06-30-2011 |
20110158015 | DEVICE AND METHOD FOR GENERATING TEST MODE SIGNAL - A test mode signal generation device includes a pulse address generation unit configured to convert test address signals into pulse signals and generate pulse address signals, a pulse address split unit configured to generate converted test address signals in response to the pulse address signals, and a test mode signal generation unit configured to generate a test mode signal in response to the converted test address signals. | 06-30-2011 |
20110158016 | INTEGRATED SOLUTION FOR IDENTIFYING MALFUNCTIONING COMPONENTS WITHIN MEMORY DEVICES - A method for testing a memory device. The memory device includes a matrix of memory cells having a plurality of rows and columns; the matrix includes a plurality of rows of operative memory cells each one for storing a variable value and at least one row of auxiliary memory cells each one storing a fixed value. The memory device further includes writing circuitry for writing selected values into the operative memory cells, and reading circuitry for reading the values being stored from the operative or auxiliary memory cells. The method includes reading output values from the row of auxiliary memory cells, determining a malfunctioning of the memory device in response to a missing match of the output values with the fixed values, determining a cause of the malfunctioning according to a pattern of reading errors between the output values and the corresponding fixed values, and providing a signal indicative of the cause of the malfunctioning. | 06-30-2011 |
20110158017 | METHOD FOR MEMORY CELL CHARACTERIZATION USING UNIVERSAL STRUCTURE - A test method includes providing an integrated circuit, where the integrated circuit includes a memory base cell, where the memory base cell includes a first storage node set, a second storage node set, a set of other nodes, and a set of circuit elements each having a plurality of terminals, where the set of other nodes includes a first data node for accessing the first storage node set, a first access control node for controlling the access of the first storage node set, a first supply node for supplying the first storage node set, and a second supply node for supplying the second storage node set, where the first and second supply nodes are of the same sinking or sourcing type. The method further includes conducting a circuit element test on a circuit element in the set of circuit elements, where in the circuit element test the first and second supply nodes are not connected together, each terminal of the circuit element is directly forced with an electrical quantity, and an electrical quantity is directly measured from a terminal of the circuit element. Further, the method includes conducting at least one of a static noise margin test or a full cell test on the memory base cell. | 06-30-2011 |
20110158018 | Structure and Methods for Measuring Margins in an SRAM Bit - Methods for measuring the read margin, write margin, and stability margin of SRAM bits with operational circuitry that includes effects of the SRAM array architecture and circuit design. In addition, methods for measuring the read margin, write margin, and stability margin of SRAM that excludes the effects of SRAM array architecture and circuit design. | 06-30-2011 |
20110164464 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF TESTING THE SAME - A semiconductor device includes the following elements. A sense amplifier amplifies signal on a bit line. A column switch is between the bit line and a local input-output line. A sub-amplifier amplifies signal on the local input-output line. A write switch is between the local input-output line and a main input-output line. A write amplifier amplifies write data and supplies the amplified write data to the main input-output line when data write operation is performed. A test circuit activates the sense amplifier while the test circuit deactivating the sub-amplifier and the write amplifier when a data read operation is performed in test mode. The test circuit places the column switch and the write switch in conductive state. | 07-07-2011 |
20110228620 | TESTING METHOD FOR SEMICONDUCTOR MEMORY DEVICE - A method comprises simultaneously writing a test bit to a plurality of memory cells in the selected sections of a memory array corresponding to column address signals; individually and successively reading output bits from the memory cells in one of the selected sections of a designated row of the memory array corresponding to column address signals and row address signals; and error-checking the output bits with the test bit, wherein the memory array comprises the plurality of memory cells arranged in rows and columns and the memory cells of each row are divided into a plurality of sections. | 09-22-2011 |
20110228621 | SEMICONDUCTOR DEVICE AND METHOD FOR TESTING THE SAME - A semiconductor device and a method for testing the same are disclosed, relating to a technology for simultaneously screening an off-leakage-current fail caused by a passing gate effect and a neighbor gate effect. The semiconductor device includes a memory cell configured to read and write data; a sense amplifier configured to sense and amplify cell data received from the memory cell through a pair of bit lines; a bit line precharge unit configured to equalize the pair of bit lines to a level of a ground voltage in response to a bit line equalization signal; a precharge voltage generator configured to provide the ground voltage to the bit line precharge unit during a test mode; and a test controller configured to, during the test mode, maintain an activation state of the bit line equalization signal during a test mode period, and control the sense amplifier to be deactivated. | 09-22-2011 |
20110242918 | GLOBAL LINE SHARING CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE - A global line sharing circuit of a semiconductor memory device includes: a ZQ calibration unit configured to adjust an impedance of a DQ output driver; a test unit configured to control a test operation; and a shared global line coupled to and used in common by the ZQ calibration unit and the test unit. | 10-06-2011 |
20110242919 | Precharge Voltage Supplying Circuit - A precharge voltage supplying circuit comprises a transistor operating in response to a control signal, wherein the transistor is connected between a first node to which an internal voltage is supplied and a second node to which a precharge voltage is supplied, and a resistance element connected in parallel to the transistor between the first node and the second node. | 10-06-2011 |
20110255357 | DYNAMIC RANDOM ACCESS MEMORY (DRAM) REFRESH - A method for refreshing a Dynamic Random Access Memory (DRAM) includes performing a refresh on at least a portion of the DRAM at a first refresh rate, and performing a refresh on a second portion of the DRAM at a second refresh rate. The second portion includes one or more rows of the DRAM which do not meet a data retention criteria at the first refresh rate, and the second refresh rate is greater than the first refresh rate. | 10-20-2011 |
20110267911 | SEMICONDUCTOR MEMORY APPARATUS - A semiconductor memory apparatus includes: a line calibration unit configured to selectively output one signal from the group of code signals for calibrating termination resistance values and test mode signals for testing a chip of the semiconductor memory apparatus to a common global line based on the level of a line calibration signal. | 11-03-2011 |
20110273946 | UNIVERSAL TEST STRUCTURES BASED SRAM ON-CHIP PARAMETRIC TEST MODULE AND METHODS OF OPERATING AND TESTING - An integrated circuit on-chip parametric (OCP) test structure includes a static random access memory (SRAM) universal test structure (UTS) having UTS ports and an OCP controller configured to determine first and second UTS ports of the SRAM UTS for independent connection to first and second on-chip test pads, respectively. The integrated circuit OCP test structure further includes a UTS OCP router connected to the OCP controller and configured to connect the first and second UTS ports of the SRAM UTS to the first and second on-chip test pads, respectively. Methods of operating an integrated circuit OCP test structure and OCP testing of an integrated circuit are also included. | 11-10-2011 |
20110280092 | Multi-Bank Read/Write To Reduce Test-Time In Memories - Apparatuses and methods for multi-bank read/write architecture to reduce test time in memory devices are disclosed. A memory device can include a memory cell array including a plurality of memory banks. A bank decoding circuit can include logic configured to simultaneously select each of the plurality of memory banks. An Input/Output (IO) circuit can be coupled to the memory cell array and bank decoding circuit. The IO circuit can include failure detection logic configured to detect a failure in any of plurality of memory banks and selected IO simultaneously in one clock cycle. | 11-17-2011 |
20110299349 | Margin Testing of Static Random Access Memory Cells - A static random access memory (SRAM) and method of evaluating the same for cell stability, write margin, and read current margin. The memory is constructed so that bit line precharge can be disabled, and so that complementary bit lines for each column of cells can float during memory operations. The various tests are performed by precharging the bit lines for a column, then floating the bit lines, and while the bit lines are floating, pulsing the word lines of one or more selected cells to cause the voltage on one of the bit lines to discharge. The discharged bit line voltage is then applied to another cell, which is then read in a normal read operation to determine whether its state changed due to the discharged bit line voltage. The memory can be characterized for cell stability, write margin, and read current margin in this manner; the method can also be adapted into a manufacturing margin screen, or used in failure analysis. | 12-08-2011 |
20110310685 | MEMORY MODULE INCLUDING PARALLEL TEST APPARATUS - A memory module including a plurality of ranks. Each of the ranks includes a parallel test apparatus for simultaneous testing and a parallel test control unit. In response to a parallel test mode control signal, the parallel test apparatus generates first parity data for write data including a plurality of bits and generating first data obtained by replacing a bit value of at least one bit of the plurality of bits of the write data with the first parity data during a write operation, and generates second parity data for the first data and transmitting the second parity data as read data during a read operation. The parallel test control unit controls the write operation and the read operation in a parallel test mode by generating the parallel test mode control signal. Combinations of read data from the plurality of ranks correspond to different bits of the write data. | 12-22-2011 |
20110310686 | Method and Circuit for Configuring Memory Core Integrated Circuit Dies with Memory Interface Integrated Circuit Dies - A memory device comprises a first and second integrated circuit dies. The first integrated circuit die comprises a memory core as well as a first interface circuit. The first interface circuit permits full access to the memory cells (e.g., reading, writing, activating, pre-charging and refreshing operations to the memory cells). The second integrated circuit die comprises a second interface that interfaces the memory core, via the first interface circuit, an external bus, such as a synchronous interface to an external bus. A technique combines memory core integrated circuit dies with interface integrated circuit dies to configure a memory device. A speed test on the memory core integrated circuit dies is conducted, and the interface integrated circuit die is electrically coupled to the memory core integrated circuit die based on the speed of the memory core integrated circuit die. | 12-22-2011 |
20120002494 | TEST MODE CONTROL CIRCUIT IN SEMICONDUCTOR MEMORY DEVICE AND TEST MODE ENTERING METHOD THEREOF - A test mode control circuit is provided to strictly allow entry into a test mode or prevent a boot failure from occurring during a boot operation for a built-in parallel bit test. The test mode control circuit includes a latch, a real entry signal detector, an entry determinator, and a mode control signal generator. When a real entry signal is detected, the entry signal determinator generates an entry determination signal and a test mode control signal is obtained from the mode control signal generator. | 01-05-2012 |
20120002495 | MEMORY SYSTEM, MEMORY TEST SYSTEM AND METHOD OF TESTING MEMORY SYSTEM AND MEMORY TEST SYSTEM - A memory test system is disclosed. The memory system includes a memory device, a tester generating a clock signal and a test signal for testing the memory device, and an optical splitting module. The optical splitting module comprises an electrical-optical signal converting unit which converts each of the clock signal and the test signal into an optical signal to output the clock signal and the test signal as an optical clock signal and an optical test signal. The optical splitting unit further comprises an optical signal splitting unit which splits each of the optical clock signal and the optical test signal into n signals (n being at least two), and an optical-electrical signal converting unit which receives the split optical clock signal and the split optical test signal to convert the split optical clock signal and the split optical test signal into electrical signals used in the memory device. | 01-05-2012 |
20120008442 | SEMICONDUCTOR DEVICE AND METHOD OF TESTING THE SAME - A semiconductor device according to an aspect of the present disclosure includes a test mode signal generator configured to generate a test mode setup signal, and a controller configured to set a separated test operation in response to the test mode setup signal. | 01-12-2012 |
20120014197 | SEMICONDUCTOR DEVICE AND TEST METHOD THEREOF - A semiconductor device includes a plurality of memory mats, each of which includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells that are arranged at intersections of the word lines and the bit lines, and a plurality of dummy word lines, each of which is sandwiched between two corresponding ones of the word lines; a main dummy word line to which the dummy word lines included in the memory mats are commonly electrically connected; and a dummy-word-line control circuit that detects an electric potential of the main dummy word line when a test signal is activated, and outputs an error signal when the electric potential exceeds a predetermined threshold value. According to the present invention, because an electric potential of each of the dummy word lines is directly detected, an address of the word line, which has a short circuit with the dummy word line, can be reliably detected in a short time. | 01-19-2012 |
20120026817 | Low Cost Testing and Sorting of Integrated Circuits - Methods of testing and sorting integrated circuits in clusters are disclosed. Each cluster has power and data terminals connected to common power and data busses providing a common power supply. Each integrated circuit has a first non-volatile memory storing an activation code and a second programmable non-volatile memory that is capable of storing the activation code. If an integrated circuit passes testing, the activation code stored in the first non-volatile memory is written into the second non-volatile memory. An integrated circuit is independently functional upon separation from the cluster if the codes in the first and second non-volatile memories match. Upon separation, integrated circuits are queried to determine which respond. Each integrated circuit includes logic adapted to determine whether the codes in the first and second non-volatile memories match. If the codes do not match, the logic permanently disables the integrated circuit upon separation from the cluster. | 02-02-2012 |
20120033516 | WORD LINE DRIVING CIRCUIT, SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME, AND METHOD FOR TESTING THE SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device in accordance with the present invention is able to facilitate detecting whether a word line fails or not by floating the word line. The semiconductor memory device includes a word line driver, and a floating controller. The word line driver is configured to control a word line to be enabled/disabled. The floating controller is configured to control the word line driver to float the word line in response to a word line floating signal. | 02-09-2012 |
20120057420 | SEMICONDUCTOR MEMORY AND METHOD FOR TESTING THE SAME - A semiconductor memory in which arbitrary operation mode information is set in a plurality of CRs at test time. When a CR control circuit detects write commands to write to an address or read commands to read from the address in a predetermined order, the CR control circuit updates the operation mode information for each of the plurality of CRs on a time division basis. A command generation section generates the write commands, the read commands, or a test start command in response to a control signal from the outside. A data pad compression circuit changes the operation mode information to be written to the plurality of CRs by using test data inputted to part of data pads, after inverting the test data or in its original condition according to a code, as data for a rest of the data pads. | 03-08-2012 |
20120063248 | LOW COST COMPARATOR DESIGN FOR MEMORY BIST - A comparator determines the fidelity of a response vector received from a memory under test. The comparator includes a first logic gate configured to output a first value that is the logical OR of a first proper subset of bits of the response vector. A second logic gate is configured to output a second value that is the logical NAND of the proper subset of bits. A first multiplexer is configured to select between the first and second values based on the value of a first bit of a check vector corresponding to the response vector. | 03-15-2012 |
20120106279 | SEMICONDUCTOR MEMORY APPARATUS, MEMORY SYSTEM, AND PROGRAMMING METHOD THEREOF - Various embodiments of a semiconductor memory apparatus are disclosed. In one exemplary embodiment, the semiconductor memory apparatus includes a core block configured to receive and store external input data, a control unit configured to activate a control signal in response to a test mode signal and a command, when the external input data has a predetermined value, and a fuse circuit configured to perform fuse programming when the control signal is activated. | 05-03-2012 |
20120113734 | SEMICONDUCTOR DEVICE - A semiconductor device includes a bit line; a data bus line corresponding to the bit line; a selection transistor that controls electrical connection between the bit line and the data bus line; a write amplifier that writes data to the bit line through the data bus; and a test circuit. The test circuit sets the bit line to a first potential during a test period regardless of an operation of the write amplifier, sets the data bus line to a second potential and then sets the data bus line in a floating state to detect transition of the data bus line from the second potential to the first potential, with the selection transistor being activated to electrically connect the bit line and the data bus line. | 05-10-2012 |
20120127814 | SEMICONDUCTOR DEVICE PERFORMING STRESS TEST - A semiconductor device includes a memory cell array that is divided into a plurality of memory cell mats by a plurality of sense amplifier arrays. Each of the plurality of memory cell mats includes a plurality of word lines and a test circuit for performing a test control to activate, at one time, a plurality of word lines included in each of a plurality of selected memory cell mats that are not disposed adjacent each other in the plurality of memory cell mats. The memory cell mats with the plurality of activated word lines are distributed. Therefore, the load applied to a driver circuit for driving word lines and the load applied to a power supply circuit for supplying an operation voltage to the driver circuit are reduced | 05-24-2012 |
20120134224 | VERIFYING MULTI-CYCLE SELF REFRESH OPERATION OF SEMICONDUCTOR MEMORY DEVICE AND TESTING THE SAME - A semiconductor memory device includes a memory cell array, a tag information register, a refresh control circuit and a DQ pin. The memory cell array includes multiple memory cells divided into first cells and second cells according to corresponding data retention times. The tag information register stores refresh cycle information for each wordline connected to the first cells and the second cells. The refresh control circuit is configured to generate a refresh enable signal and a refresh address based on the refresh cycle information. The DQ pin is configured to output the refresh enable signal, the refresh address and data stored in the memory cell array. | 05-31-2012 |
20120155203 | SEMICONDUCTOR MEMORY DEVICE, METHOD OF TESTING THE SAME AND SYSTEM OF TESTING THE SAME - A method of testing a semiconductor memory device comprises receiving a clock, addresses, commands, and data from a test device through channels, generating an internal bank address in response to the addresses and the commands, performing a multi-bit parallel test for each of a plurality of banks based on the addresses, the commands, the data, and the internal bank address, and providing the test device with a test result signal. | 06-21-2012 |
20120163106 | REFRESH CONTROL CIRCUIT AND METHOD FOR SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a refresh counter for counting a refresh signal and outputting a refresh address in response to an active mode signal enabled in an active mode, an external address input buffer for buffering an external address to output an internal address in response to a mode selection signal enabled in an external address refresh mode, an address selector for outputting the refresh address from the refresh counter as a selection row address in a normal refresh mode and outputting the internal address from the external address input buffer as the selection row address in the external address refresh mode in response to the refresh signal and the mode selection signal, and a row address decoder for generating a row address selection signal for sequentially accessing word lines by decoding the selection row address. | 06-28-2012 |
20120163107 | MEMORY DEVICE CAPABLE OF OPERATION IN A BURN IN STRESS MODE, METHOD FOR PERFORMING BURN IN STRESS ON A MEMORY DEVICE, AND METHOD FOR DETECTING LEAKAGE CURRENT OF A MEMORY DEVICE - Activate one active word line of two active word lines formed between two isolation word lines to a logic-high voltage, and float another active word line of the two active word lines. Then activate a plurality of first memory cells corresponding to the active word line having the logic-high voltage to a logic “1” voltage, and write a logic “0” voltage to a plurality of second memory cells corresponding to the floating active word line. Then write the logic “1” voltage to a plurality of bit lines. Then, suspend for charge sharing for a third predetermined time. Finally, read a voltage of the floating active word line to check if any leakage path exists between the floating active word line and the active word line having the logic-high voltage. | 06-28-2012 |
20120163108 | NON-VOLATILE MEMORY DEVICE AND ELECTRONIC APPARATUS - A non-volatile memory device is provided, which includes a first block for storing a first data group including a test data, a second block for storing a second data group including a complementary data to the first data group, a differential sense amplifier for generating an output value based on a difference between two input signals, a diagnostic circuit for performing a failure diagnosis using a value from the differential sense amplifier, and a control circuit which performs control such that a signal based on the test data and the complementary data is set to the input signal of the differential sense amplifier and the diagnostic circuit executes a failure diagnosis of the differential sense amplifier. The non-volatile memory device performs a failure diagnosis with high reliability capable of distinguishing between a failure of sense amplifier and a failure of a memory cell. | 06-28-2012 |
20120176852 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF TESTING THE SAME - A device and a method controlling the device are provided. A first command is supplied to the device in synchronization with a clock signal of a first frequency. The first command is to have the device perform a first operation. The frequency of the clock signal is changed from the first frequency to a second frequency higher than the first frequency. The device performs the first operation in synchronization with the clock signal of the second frequency following changing the frequency of the clock signal. | 07-12-2012 |
20120201091 | MEMORY CARD TEST INTERFACE - A memory card and methods for testing memory cards are disclosed herein. The memory card has a test interface that allows testing large numbers of memory cards together. Each memory card may have a serial data I/O contact and a test select contact. The memory cards may only send data via the serial data I/O contact when selected, which may allow many memory cards to be connected to the same serial data line during test. Moreover, existing test socket boards may be used without adding additional external circuitry. Thus, cost effective testing of memory cards is provided. In some embodiments, the test interface allows for a serial built in self test (BIST). | 08-09-2012 |
20120206985 | STATIC RANDOM ACCESS MEMORY (SRAM) AND TEST METHOD OF THE SRAM HAVING PRECHARGE CIRCUIT TO PREPCHARGE BIT LINE - A method of testing a static random access memory (SRAM), the method including writing a data into the SRAM cell to store a first potential level at a first node and a second potential level greater than the first potential level at a second node, supplying a power supply voltage from a power supply terminal to first and second bit lines by activating first and second transistors and deactivating first and second transfer gates, and supplying the power supply voltage to the first bit line by activating the first transistor and activating the first and second transfer gates. | 08-16-2012 |
20120213022 | SIP SEMICONDUCTOR SYSTEM - A system in package (SIP) semiconductor system includes a memory device, a controller, a first input/output terminal, a test control unit, and a second input/output terminal. The controller communicates with the memory device. The first input/output terminal performs communication between the controller and a device external to the SIP semiconductor system. The test control unit controls a predetermined test mode of the memory device. The second input/output terminal performs communication between the test control unit and at least the device external to the SIP semiconductor system. | 08-23-2012 |
20120218845 | SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREOF - Disclosed herein is a semiconductor device comprising an array having a hierarchical bit line structure, global bit lines adjacent to each other, local bit lines corresponding to the global bit lines, hierarchical switches, precharge circuits precharging the global bit lines, precharge circuits precharging the local bit lines, and a control circuit. When performing a test of the array, precharge voltages for the global bit lines are set to potentials different from each other, and the control circuit controls the potentials to be applied to the local bit lines through the global bit lines and the hierarchical switches. | 08-30-2012 |
20120218846 | TEST CIRCUIT, SEMICONDUCTOR MEMORY APPARATUS USING THE SAME, AND TEST METHOD OF THE SEMICONDUCTOR MEMORY APPARATUS - A test circuit of a semiconductor memory apparatus includes: a test control signal generating unit configured to enable a control signal if an active signal is enabled after a test signal is enabled, and substantially maintain the control signal in an enable state until a precharge timing signal is enabled; and a precharge control unit configured to invert the control signal to output the inverted signal as a bit line precharge signal when a preliminary bit line precharge signal is in a disable state. | 08-30-2012 |
20120230137 | MEMORY DEVICE AND TEST METHOD FOR THE SAME - A memory device includes a first bank, a second bank, a plurality of interface pads, and a data output unit configured to output compressed data of the first bank through at least one interface pad among the plurality of interface pads and subsequently output compressed data of the second bank through the one interface pad. | 09-13-2012 |
20120250438 | Dynamic random access memory address line test technique - Verification of the address connections of a memory ( | 10-04-2012 |
20120263002 | TEST METHOD FOR SCREENING LOCAL BIT-LINE DEFECTS IN A MEMORY ARRAY - A method of detecting manufacturing defects at a memory array may include utilizing test circuitry to provide a selected voltage as drain bias on a bit-line of the memory array where the memory array is configured to employ a first voltage as the drain bias for a read operation and the selected voltage is higher than the first voltage, and determining whether a leakage current indicative of a manufacturing defect between the bit-line and another component of the memory array is present responsive to providing the selected voltage as the drain bias. A corresponding test device is also provided. | 10-18-2012 |
20120287738 | MEASURING DEVICE AND A MEASURING METHOD WITH HISTOGRAM FORMATION - A measuring device for the storage of test values and associated addresses provides a first storage region ( | 11-15-2012 |
20120307579 | MEMORY RELIABILITY VERIFICATION TECHNIQUES - Some embodiments of the present disclosure relate to improved reliability verification techniques for semiconductor memories. Rather than merely carrying out a BIST test by verifying whether a memory cell accurately stores a “1” or “0” under normal read/write conditions, aspects of the present invention relate to BIST tests that test the read and/or write margins of a cell. During this BIST testing, the read and/or write margins can be incrementally stressed until a failure point is determined for the cell. In this way, “weak” memory cells in an array can be identified and appropriate action can be taken, if necessary, to deal with these weak cells. | 12-06-2012 |
20120327729 | MEMORY TESTING DEVICE HAVING CROSS INTERCONNECTIONS OF MULTIPLE DRIVERS AND ITS IMPLEMENTING METHOD - Disclosed is a memory testing device having cross interconnections of multiple drivers, comprising a first wiring bus and a second wiring bus connected to a first device area and a third wiring bus and a fourth wiring bus connected to a second device area. A first I/O driver module bus is connected to the first wiring bus through a first driving bus. A second I/O driver module bus is connected to the third wiring bus through the second driving bus. The fourth wiring bus is Y-shaped connected to the node between the first wiring bus and first driving bus. And, the second wiring bus is Y-shaped connected to the node between the third wiring bus and the second driving bus. | 12-27-2012 |
20130010558 | Method of Detecting Connection Defects of Memory and Memory Capable of Detecting Connection Defects thereof - By inputting voltages to global word lines of a memory, and by detecting currents of corresponding global word lines, a relation function between the currents and the voltages can be generated, and connection defects on the global word lines can be determined according to various types of deviation of a relation curve corresponding to the relation function between the currents and voltages. | 01-10-2013 |
20130021862 | DRAM AND METHOD FOR TESTING THE SAME IN THE WAFER LEVEL BURN-IN TEST MODE - A dynamic random-access memory (DRAM) and a method for testing the DRAM are provided. The DRAM includes a memory cell, a bit line associated with the memory cell, a local buffer, and a bit line sense amplifier (BLSA). The local buffer receives a first power voltage as power supply. The local buffer provides a ground voltage to the bit line when a data signal is de-asserted and provides the first power voltage to the bit line when the data signal is asserted. The BLSA receives a second power voltage as power supply. The BLSA provides the second power voltage to the bit line when the data signal and a wafer level burn-in test signal are both asserted. The second power voltage may be higher than the first power voltage. The wafer level burn-in test signal is asserted when the DRAM is in a wafer level burn-in test mode. | 01-24-2013 |
20130021863 | TEST MODE INITIALIZATION DEVICE AND METHOD - A die includes: a plurality of efuses, for respectively generating a plurality of test-mode signals; a control unit, coupled to a first control signal, for generating a plurality of control bits; a multiplexer, coupled to the plurality of test-mode signals and the control unit, for muxing the plurality of test-mode signals in series in response to the plurality of control bits; at least an address block, for receiving a specific test-mode signal; and at least a local test-mode block coupled to the address block. The local test-mode block comprises: a latch, for latching a specific test-mode signal and releasing the latched test-mode signal to the address block in response to a second control signal; a first decoder, for releasing the specific test-mode signal to the latch in response to the plurality of control bits; and a second decoder, for generating the second control signal to the latch. | 01-24-2013 |
20130021864 | Array Power Supply-Based Screening of Static Random Access Memory Cells for Bias Temperature Instability - A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, separate ground voltage levels can be applied to the source nodes of the driver transistors, or separate power supply voltage levels can be applied to the source nodes of the load transistors (or both). Asymmetric bias voltages applied to the transistors in this manner will reduce the transistor drive current, and can thus mimic the effects of bias temperature instability (BTI). Cells that are vulnerable to threshold voltage shift over time can thus be identified. | 01-24-2013 |
20130028036 | Method of Screening Static Random Access Memories for Unstable Memory Cells - A screening method for testing solid-state memories for the effects of long-term shift and random telegraph noise (RTN). In the context of static random access memories (SRAMs), each memory cell in the array is functionally tested with a bias voltage (e.g., the cell power supply voltage) at a severe first guardband sufficient to account for worst case long-term shift and RTN effects. Cells failing the first guardband are then repeatedly tested with the bias voltage at a second guardband, less severe than the first guardband; if the tested cells pass this second guardband, the suspect cells are considered to not be vulnerable to RTN effects. Over-screening due to an unduly severe guardband is avoided, while still screening vulnerable memories from the population. | 01-31-2013 |
20130033948 | DEVICE AND METHOD FOR DETECTING RESISTIVE DEFECT - The invention provides a device and method for detecting a resistive defect in a static random access memory (SRAM) device. A first aspect of the invention provides a static random access memory (SRAM) device comprising: a bitline; a wordline; a bitline precharge circuit electrically connected to the bitline and adapted to provide to the bitline a first precharge voltage for precharging the bitline during normal operation of the SRAM device and a second precharge voltage less than the first precharge voltage for testing the SRAM device for a resistive defect between the bitline and the wordline. | 02-07-2013 |
20130039139 | Method of Stressing Static Random Access Memories for Pass Transistor Defects - A method of stressing and screening static random access memory (SRAM) arrays to identify memory cells with bit line side pass transistor defects. After writing initial data states into the memory array under nominal bias conditions, an elevated bias voltage is applied to the memory array, for example to its power supply node. Under the elevated bias voltage, alternating data patterns are written into and read from the memory array for a selected duration. The elevated bias voltage is reduced, and a write screen is performed to identify defective memory cells. The dynamic stress of the repeated writes and reads accelerates early life failures, facilitating the write screen. | 02-14-2013 |
20130039140 | MACRO AND COMMAND EXECUTION FROM MEMORY ARRAY - Methods and apparatus for executing internal operations of memory devices utilizing instructions stored in the memory array of the memory device are disclosed. Decode blocks adapted to interpret instructions and data stored in the memory device are also disclosed. Methods can be used to perform internal self-test operations of the memory device by executing test procedures stored in the memory array of the memory device performing a self-test operation. | 02-14-2013 |
20130058177 | Method of Screening Static Random Access Memory Cells for Positive Bias Temperature Instability - A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for n-channel transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, static noise margin and writeability (V | 03-07-2013 |
20130058178 | SYSTEM AND METHOD FOR TESTING INTEGRATED CIRCUITS BY DETERMINING THE SOLID TIMING WINDOW - Systems and methods are provided to determine a solid operating timing window for an integrated circuit device, the solid timing window used to determine a key timing index. The key timing index provides an indication of the quality of an integrated circuit over a range of operating conditions. In at least one embodiment a method is provided, the method comprising generating a plurality of combinations of operating parameters, for each of the plurality of combinations of operating parameters setting the respective combination of operating parameters, operating the integrated circuit under the set respective combination of operating parameters, and determining a data valid window for the integrated circuit. The solid operating timing window for the integrated circuit is then determined using the data valid windows for the plurality of combinations of operating parameters, where the solid operating timing window is the logical intersection of the determined data valid windows. | 03-07-2013 |
20130064027 | Memory and Method of Adjusting Operating Voltage thereof - By adjusting an operating voltage of a memory cell in a memory according to a measured capacitance result indicating capacitance of an under-test capacitor of the memory cell, an appropriate operating voltage for the memory cell can always be determined according to the measured capacitance result. The measured capacitance result indicates whether the capacitance of the under-test capacitor indicating the characteristic of the gate dielectric of the memory cell is higher or lower than a reference capacitor, and is generated by amplifying a difference between two voltages indicating capacitance of the reference capacitor and the capacitance of the under-test capacitor. | 03-14-2013 |
20130077421 | FAILURE DIAGNOSIS CIRCUIT - A failure diagnosis circuit includes a multiplexer and a controller. The multiplexer receives address signals, and selectively outputs one of the address signals to an addressable module in response to a selecting signal. The controller generates a first one of address signals and the selecting signal. A built-in self-test circuit generates the second address signal. The addressable module includes addressable components responsive to the address signal. The controller processes the output of the addressable module responsive to the address signal to make a failure diagnosis. The built-in self-test circuit performs signature analysis on the read out output of the addressable module. | 03-28-2013 |
20130077422 | INTEGRATED SOLUTION FOR IDENTIFYING MALFUNCTIONING COMPONENTS WITHIN MEMORY DEVICES - A method for testing a memory device. The memory device includes a matrix of memory cells having a plurality of rows and columns; the matrix includes a plurality of rows of operative memory cells each one for storing a variable value and at least one row of auxiliary memory cells each one storing a fixed value. The memory device further includes writing circuitry for writing selected values into the operative memory cells, and reading circuitry for reading the values being stored from the operative or auxiliary memory cells. The method includes reading output values from the row of auxiliary memory cells, determining a malfunctioning of the memory device in response to a missing match of the output values with the fixed values, determining a cause of the malfunctioning according to a pattern of reading errors between the output values and the corresponding fixed values, and providing a signal indicative of the cause of the malfunctioning. | 03-28-2013 |
20130094315 | STATIC RANDOM ACCESS MEMORY TEST STRUCTURE - A static random access memory (SRAM) test structure includes a p-type source/drain implant region comprising contacts (CAs), wherein the CAs in the p-type source/drain implant region comprise a first plurality of bit line, ground, and node CAs, and wherein the CAs in the p-type source/drain implant region are grounded during an inspection of the SRAM test structure; and an ungrounded region, the ungrounded region being distinct from the p-type source/drain implant region and being ungrounded during the inspection of the SRAM test structure, the ungrounded region comprising contacts (CAs) and rectangular contacts (CArecs) comprising a second plurality of bit line, ground, and node CAs, and further comprising a first plurality of V | 04-18-2013 |
20130100752 | METHOD OF RESTORING RECONSTRUCTED MEMORY SPACES - A method of restoring reconstructed memory spaces is applied for restoring usable memory spaces in an inked die to form the memory with a standardized or non-standardized memory capacity. The method comprises the steps of scanning at least one selected from a block, a page and a cell in a die (or a memory unit), and writing/reading/comparing testing data in each selected area for labeling the block, page and cell as normal and abnormal in each area. The aforementioned steps are executed in a loop to achieve the effects of scanning and testing the die completely, using the configured and collected area labeled as normal to reconstruct the memory with the standardized or non-standardized memory capacity, and providing the memory to any controller or server to access the memory capacity. | 04-25-2013 |
20130107649 | SEMICONDUCTOR DEVICE INCLUDING TEST CIRCUIT AND BURN-IN TEST METHOD | 05-02-2013 |
20130114360 | METHOD FOR DETECTING PERMANENT FAULTS OF AN ADDRESS DECODER OF AN ELECTRONIC MEMORY DEVICE - An embodiment of a method for detecting permanent faults of an address decoder of an electronic memory device including a memory block formed by a plurality of memory cells, including the steps of: selecting an address, which identifies a selected set of memory cells; writing at the selected address a code word generated on the basis of an information word, of the selected address, and of an error-correction code; and then detecting an error within a word stored at the selected address. The method moreover includes the steps of: selecting a set of excitation addresses; writing a test word at the selected address, and then writing an excitation word at each excitation address; and next comparing the test word with a new word stored at the selected address. | 05-09-2013 |
20130121097 | ADDRESS OUTPUT CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a signal generation unit configured to generate a toggling signal and first and second pulse signals in response to a test signal and a burst pulse signal. An address output unit may be configured to receive first to fourth input addresses and output sequentially first to fourth output addresses in response to the toggling signal and the first and second pulse signals. A repair unit may be configured to perform a repair operation on a word line selected by the first to fourth output addresses. | 05-16-2013 |
20130135952 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF TESTING THE SAME - A semiconductor memory device including an open bit line structure is disclosed. The semiconductor memory device including an open bit line structure includes a first mat, a second mat contiguous to the first mat, a first sense amplifier coupled to a first bit line of the first mat, a second sense amplifier coupled to a second bit line of the first mat and a third bit line of the second mat, a third sense amplifier coupled to a fourth bit line of the second mat, and a plurality of bit line precharge voltage providers for varying a level of a bit line precharge voltage provided to the first, second, and third sense amplifiers, selectively providing the resultant bit line precharge voltage level, and providing the same voltage as that of data of a selected cell to a non-selected sense amplifier during a read operation. | 05-30-2013 |
20130135953 | SEMICONDUCTOR MEMORY DEVICE - According to an embodiment, provided are a memory cell configured to store data, a word line configured to select the memory cell in each row, a bit line configured to transfer a signal read from a memory cell in each column, a self-test circuit configured to test an operation of the memory cell, and a regulator configured to set a voltage of the word line or a cell power supply voltage of the memory cell to accelerate a disturb failure of the memory cell, based on an acceleration command from the self-test circuit. | 05-30-2013 |
20130155795 | Methodology for Recovering Failed Bit Cells in an Integrated Circuit Memory - A method for recovering failed bit cells in an integrated circuit memory is disclosed. In one embodiment, the method includes stress testing an integrated circuit having a memory, wherein the memory includes a plurality of bit cells. The method further includes holding at least one internal node of the selected one of the plurality of bit cells at a first predetermined state for a period sufficient to cause a shift in a threshold voltage of a transistor in the selected one of the plurality of bit cells. | 06-20-2013 |
20130155796 | FABRICATION AND TESTING METHOD FOR NONVOLATILE MEMORY DEVICES - Provided is a plurality of master chips arranged in a row on the wafer, each master chip including a power supply circuit provides a power supply voltage, and a plurality of slave chips arranged in a column to at least one side of a corresponding master chip among the plurality of master chips, each slave chip including a memory cell array functionally operative in response to the power supply voltage provided by the corresponding master chip during wafer level testing. | 06-20-2013 |
20130163357 | Quantifying the Read and Write Margins of Memory Bit Cells - Yield loss from peripheral circuit failure while screening memory arrays for aging effects is prevented by operating the peripheral circuitry at nominal operating voltages during the screening for aging effects. An integrated circuit including one or more memory bit cells, includes circuitry to change the voltage applied to the supply rails of bit cells and the voltage applied to the word-line drivers relative to each other in order to facilitate improved screening for read and write margins. In normal operation the supply rails for word-line drivers and bit cells are nominally the same. In a write margin test mode the voltage on the supply rail of word-line drivers is lower than the voltage on the supply rail of the bit cells. In a read margin test mode the voltage on the supply rail of word-line drivers is higher than the voltage on the supply rail of the bit cells. | 06-27-2013 |
20130170307 | ELECTRONIC DEVICE AND METHOD FOR TESTING ENDURANCE OF MEMORY - An electronic device for endurance test of a memory includes an interface, a storage unit, an obtaining unit, and a control unit. The interface is for connecting the memory to the electronic device. The storage unit stores a variety of test packages for different storage capacities of memories and at least one test option associated with each test package. The test option defines a predetermined capacity of the associated memory to be tested. The obtaining unit obtains a storage capacity of the memory connected to the electronic device. The control unit selects one of the at least one test option associated with one of the test packages corresponding to the obtained storage capacity, selects a plurality of blocks according to the predetermined capacity of the selected test option, assigns corresponding logical addresses to the selected blocks, and then tests the endurance of the selected blocks. | 07-04-2013 |
20130170308 | SEMICONDUCTOR MEMORY TEST METHOD AND SEMICONDUCTOR MEMORY - A first erase test is performed by applying an erase pulse to series of memory cells which are included in a memory cell array and which are divided into a plurality of groups until the appearance of a group for which the determination that erase is completed is made. A second erase test is performed on other series of memory cells including the series of memory cells on the basis of the number of erase pulses at the time of detecting a group for which the determination that erase is completed is made first. | 07-04-2013 |
20130182518 | MEMORY CELL OF SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR DRIVING THE SAME - A semiconductor memory device includes a first fuse having one end coupled with a first bit line and configured to be programmed with a data, a second fuse having one end coupled with a second bit line and configured to be programmed with the data; a program controller coupled with the other ends of the first fuse and the second fuse and configured to perform a program operation on at least one of the first fuse and the second fuse in response to a program voltage, and a read controller coupled with the other ends of the first fuse and the second fuse and configured to perform a read operation on the first fuse and the second fuse in response to a read voltage. | 07-18-2013 |
20130194883 | OPERATING METHOD AND DATA READ METHOD IN NONVOLATILE MEMORY DEVICE - In a method of reading data in a nonvolatile memory device including data cells and monitoring cells. A first read operation applies a first read voltage to the data cells and monitoring cells. If a read fail occurs, a second read operation is performed using a red voltage level determined according to a number of ON-cells among the monitoring cells. | 08-01-2013 |
20130201776 | BUILT-IN TEST CIRCUIT AND METHOD - A method of testing a semiconductor memory includes performing a first test of a first type prior to packaging the semiconductor memory. The first test of the first type includes generating a first plurality of addresses, decoding the first plurality of addresses to generate a second plurality of decoded addresses at a first decoder, and activating one of a plurality of rows or a plurality of columns of the semiconductor memory based on the second plurality of decoded addresses. The semiconductor memory is packaged after performing the first test of the first type. | 08-08-2013 |
20130215696 | ANTI-FUSE CIRCUIT OF SEMICONDUCTOR DEVICE AND METHODS OF TESTING INTERNAL CIRCUIT BLOCK THEREOF - A method of testing an internal circuit block of anti-fuse circuit and a circuit for detecting a defect in the operation of the internal circuit block such as a defect in a sensing part or in a transfer part thereof. Forming a sensing part testing path in a sensing part connected to an output terminal of anti-fuse array; obtaining a sensing output signal through a sense amplifier in the sensing part by applying a test signal through the sensing part testing path while the anti-fuses in the anti-fuse array are not ruptured; detecting defects in the sensing part by comparing the sensing output signal with a reference data corresponding to the test signal. Defectively operating chips may be effectively repaired by adjusting control terminals within a specific control range upon detection of a defect of internal circuit block. | 08-22-2013 |
20130235685 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF SCREENING THE SAME - A semiconductor memory device may include a voltage comparator, a voltage generator, a counter, and a circuit. The voltage comparator may be configured to generate an enabling signal responsive to a comparison indicating that a first voltage is lower than a reference voltage. The voltage generator may be configured to generate oscillation signals and a boost voltage by boosting the first voltage and to feed the boost voltage back as the first voltage in response to the enabling signal. The counter may be configured to count the number of the oscillation signals, and to generate a count output signal having information corresponding to the number of the oscillation signals. The circuit may be configured to output the count output signal as a quality output signal indicating the counted number relative to a target set value. | 09-12-2013 |
20130250708 | MEMORY ELEMENT AND METHOD FOR DETERMINING THE DATA STATE OF A MEMORY ELEMENT - One embodiment of the present invention is directed to an electronic memory ( | 09-26-2013 |
20130250709 | TESTING SYSTEM AND TESTING METHOD THEREOF - A testing system for a wafer having a plurality of flash memory dies is provided. The testing system includes a testing apparatus and a probe card coupled to the testing apparatus via a specific transmission line. The testing apparatus provides a testing requirement. The probe card includes a plurality of probes and a controller. The probes contact with at least one of the flash memory dies of the wafer. The controller writes a testing data to the flash memory die according to the testing requirement and reads the testing data from the flash memory die via the probes. The controller provides a testing result to the testing apparatus according to the read testing data. | 09-26-2013 |
20130286759 | METHOD OF SELECTING ANTI-FUSES AND METHOD OF MONITORING ANTI-FUSES - For selecting anti-fuses in a semiconductor memory device, a decoder block may be enabled to receive selection information for selecting the anti-fuses. The selection information is decoded in the decoder block to select at least one of the anti-fuses. Target operation is performed on the selected anti-fuses. The decoder block is disabled. | 10-31-2013 |
20130308402 | TEST FLOW TO DETECT A LATENT LEAKY BIT OF A NON-VOLATILE MEMORY - A technique for detecting a leaky bit of a non-volatile memory includes erasing cells of a non-volatile memory. A bias stress is applied to the cells subsequent to the erasing. An erase verify operation is performed on the cells subsequent to the applying a bias stress to the cells. Finally, it is determined whether the cells pass or fail the erase verify operation based on whether respective threshold voltages of the cells are below an erase verify level. | 11-21-2013 |
20130336077 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR TESTING SAME - A semiconductor memory device includes data input/output terminals (DQ0 to DQ31), a memory cell array | 12-19-2013 |
20140003174 | INTEGRATED CIRCUIT CHIP AND MEMORY DEVICE HAVING THE SAME | 01-02-2014 |
20140029364 | BIT ERROR TESTING AND TRAINING IN DOUBLE DATA RATE (DDR) MEMORY SYSTEM - DDR PHY interface bit error testing and training is provided for Double Data Rate memory systems. An integrated circuit comprises a bit error test (BERT) controller that provides a bit pattern; and a physical interface having a plurality of byte lanes. A first byte lane is connected by a loopback path to a second byte lane and the BERT controller writes the bit pattern that is obtained using the loopback path to evaluate the physical interface. The evaluation comprises (i) a verification that the bit pattern was properly written and read; (ii) a gate training process to position an internal gate signal; (iii) a read leveling training process to position both edges of a strobe signal; and/or (iv) a write bit de-skew training process to align a plurality of bits within a given byte lane. | 01-30-2014 |
20140036609 | TESTING RETENTION MODE OF AN SRAM ARRAY - An embodiment of the invention discloses a method for testing the retention mode of an array of SRAM cells. A data pattern is written to the array. After the data pattern is written, a retention circuit is enabled for a period of time that drops the voltage on a supply line. During this period of time, a first current is drawn from the supply line by sources internal (i.e. leakage current) to the array. Also during this time period, current is drawn from the supply line by a discharge circuit. The second current is provided to shorten the time required to test the retention mode of the array. After the period of time has expired, the retention mode and the discharge circuit are disabled and the data pattern is read from the array and compared to the data pattern written to the array. | 02-06-2014 |
20140043927 | METHOD FOR OPTIMIZING REFRESH RATE FOR DRAM - A method for determining an optimized refresh rate involves testing a refresh rate on rows of cells, determining an error rate of the rows, evaluating the error rate of the rows; and repeating these steps for a decreased refresh rate until the error rate is greater than a constraint, at which point a slow refresh rate is set. | 02-13-2014 |
20140056088 | METHOD OF IDENTIFYING DAMAGED BITLINE ADDRESS IN NON-VOLATILE MEMORY DEVICE - A method of identifying a damaged bitline address in a non-volatile memory device is introduced. The non-volatile memory device includes a memory cell array and a plurality of bit lines crossing the memory cell array. Each bit line has a first end and a second end. The bit lines are divided into a first group and a second group. The method includes applying a source voltage (charging) or ground voltage (discharging) to a specific group of bit lines, testing the bit lines in two testing stages (open-circuit testing and short-circuit testing) by the principle that no damaged bit line can be charged or discharged, and acquiring an address data of a damaged bit line according to a status data stored in a page buffering circuit and related to whether a bit line is damaged, thereby dispensing with a calculation process for estimating the address of the damaged bit line. | 02-27-2014 |
20140063997 | DRAM REFRESH - A refresh of a DRAM having at least a fast and a slow refresh rate includes encoding a pointer on a row or rows with refresh information, reading the refresh information, and incrementing a fast refresh address counter with the refresh information. The refresh may be performed by encoding one or more cells on a row that may require a fast refresh, one or more cells on a group of rows that may require a fast refresh, or one or more cells on a row that may not require a fast refresh. | 03-06-2014 |
20140063998 | NONVOLATILE MEMORY DEVICE AND OPERATING METHOD THEREOF - A nonvolatile memory device includes a memory cell array including a main cell area and a retention flag cell area, a retention check unit configured to compare a read result for retention flag cells included in the retention flag cell area to a reference value, and determine a retention state of the retention flag cells according to a comparison result, and a control logic configured to provide a retention check result based on the retention state to the external device in response to a retention check request provided from an external device. | 03-06-2014 |
20140063999 | NON-VOLATILE MEMORY DEVICE AND ELECTRONIC APPARATUS - A non-volatile memory device is provided, which includes a first block for storing a first data group including a test data, a second block for storing a second data group including a complementary data to the first data group, a differential sense amplifier for generating an output value based on a difference between two input signals, a diagnostic circuit for performing a failure diagnosis using a value from the differential sense amplifier, and a control circuit which performs control such that a signal based on the test data and the complementary data is set to the input signal of the differential sense amplifier and the diagnostic circuit executes a failure diagnosis of the differential sense amplifier. The non-volatile memory device performs a failure diagnosis with high reliability capable of distinguishing between a failure of sense amplifier and a failure of a memory cell. | 03-06-2014 |
20140078843 | SEMICONDUCTOR DEVICE AND TEST METHOD THEREOF - A semiconductor chip includes a memory array including a plurality of memory cells, a plurality of terminals including a plurality of test terminals to output a result of a specific test, and a circuit that outputs the result to a selected one of the plurality of test terminals based on a chip identification data. | 03-20-2014 |
20140085994 | INTEGRATED CIRCUITRY, CHIP, METHOD FOR TESTING A MEMORY DEVICE, METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING A CHIP - In various embodiments an integrated circuit or chip is provided, the integrated circuit including a memory device including a plurality of memory cells, and with the memory cells being configured to store a data content, and a controller being configured to write a predefined data pattern in the memory cells of the memory device, reading the data content of the memory cells, mapping each read data content which corresponds to an expected data content depending on the predefined data pattern to a predefined instruction for the controller, with the predefined instruction causing the controller to carry out a predefined action which is representative for the accurate operation of the memory cells, determining that the memory device operates accurately, if the controller carries out the predefined action, and determining that the memory device does not operate accurately, if the controller does not carry out the predefined action. | 03-27-2014 |
20140085995 | METHOD, APPARATUS AND SYSTEM FOR DETERMINING A COUNT OF ACCESSES TO A ROW OF MEMORY - Techniques and mechanisms for determining a count of accesses to a row of a memory device. In an embodiment, the memory device includes a counter comprising circuitry to increment a value of the count in response to detecting a command to activate the row. Circuitry of counter may further set a value of the count to a baseline value in response to detecting a command to refresh the row. In another embodiment, the memory device includes evaluation logic to compare a value of the count to a threshold value. A signal is generated based on the comparison to indicate whether a row hammer event for the row is indicated. | 03-27-2014 |
20140085996 | READOUT CIRCUIT AND SEMICONDUCTOR DEVICE - Provided is a readout circuit capable of detecting inversion of retained data caused by a noise, such as static electricity. The readout circuit is configured to retain opposing data in a first latch circuit and a second latch circuit in a readout period so as to be capable of detecting an anomaly of the retained data by making use of the fact that the data in the first latch circuit and the second latch circuit are inverted in the same direction due to a noise, such as static electricity. | 03-27-2014 |
20140119144 | Technique to Operate Memory in Functional Mode Under LBIST Test - A method for testing an integrated circuit having memory comprises performing a structural test on the integrated circuit using data obtained from operating the memory in a functional mode. In another embodiment, an integrated circuit comprises a memory mode selection module, a memory module, and an output selection module. The memory mode selection module is configured to receive a functional mode signal and a test mode signal, and selectively transmit either the functional mode signal or the test mode signal based on a state of a control signal. The memory module is configured to receive the signal from the memory mode selection module and store data corresponding to signal to memory cells. The output selection module is configured to receive the data from the memory cells, and transmit the data to downstream circuitry, which may use the data to perform a structural test, such as a logic built-in self-test. | 05-01-2014 |
20140126312 | SENSE AMPLIFIER SOFT-FAIL DETECTION CIRCUIT - Embodiments of a sense amplifier test circuit are disclosed that may allow for detecting soft failures. The sense amplifier test circuit may include a voltage generator circuit, a sense amplifier, and a detection circuit. The voltage generator may be operable to controllably supply different differential voltages to the sense amplifier, and the detection circuit may be operable to detect an analog voltage on the output of the sense amplifier. | 05-08-2014 |
20140126313 | CHIP WITH EMBEDDED NON-VOLATILE MEMORY AND TESTING METHOD THEREFOR - A testing method for a chip with an embedded non-volatile memory and the chip is provided. A remapping circuit and the non-volatile memory are connected to a processor. The non-volatile memory has a test area and an area under test. The test area stores a test program, and the area under test stores data under test. When the processor tests the chip, the processor outputs an original instruction address, and the remapping circuit remaps the original instruction address to generate a remapped instruction address. The processor reads the test program in the test area, and executes the test program to read the data under test in the area under test and to perform a test of toggling the logic circuit. | 05-08-2014 |
20140133253 | System and Method for Memory Testing - An embodiment method of testing a memory includes writing a first logic state to a first cell in a first clock cycle and reading the first logic state in the first cell in a second clock cycle in a first phase, and reading the first logic state in the first cell and writing a second logic state to the first cell in the first clock cycle and reading the second logic state in the first cell in the second clock cycle in a second phase. As such, a concurrent read/write operation is performed at the same time and for the same memory bit (i.e., the first cell). | 05-15-2014 |
20140133254 | TEST METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR TEST APPARATUS - A test method of a semiconductor device and a semiconductor test apparatus. The test method includes providing a semiconductor device including a substrate having an active region and an isolation region, a volatile device cell including a gate insulation layer and a gate on the active region, a junction region in the active region, a capacitor connected to the junction region, and a passing gate on the isolation region, providing a first test voltage to the gate and a second test voltage greater than the first test voltage to the passing gate to deteriorate interfacial defects of the gate insulation layer, and measuring retention characteristics of the volatile device cell. | 05-15-2014 |
20140140156 | MEMORY OPERATIONS USING SYSTEM THERMAL SENSOR DATA - Memory operations using system thermal sensor data. An embodiment of a memory device includes a memory stack including one or more coupled memory elements, and a logic chip coupled with the memory stack, the logic chip including a memory controller and one or more thermal sensors, where the one or more thermal sensors include a first thermal sensor located in a first area of the logic chip. The memory controller obtains thermal values of the one or more thermal sensors, where the logic element is to estimate thermal conditions for the memory stack using the thermal values, the determination of the estimated thermal conditions for the memory stack being based at least in part on a location of the first thermal sensor in the first area of the logic element. A refresh rate for one or more portions of the memory stack is modified based at least in part on the estimated thermal conditions for the memory stack. | 05-22-2014 |
20140146626 | Addressing, Command Protocol, and Electrical Interface for Non-Volatile Memories Utilized in Recording Usage Counts - Electrical interfaces, addressing schemes, and command protocols allow for communications with memory modules in computing devices such as imaging and printing devices. Memory modules may be assigned an address through a set of discrete voltages. One, multiple, or all of the memory modules may be addressed with a single command, which may be an increment counter command, a write command, a punch out bit field, or a cryptographic command. The commands may be transmitted using a broadcast scheme or a split transaction scheme. The status of the memory modules may be determined by sampling a single signal that may be at a low, high, or intermediate voltage level. | 05-29-2014 |
20140153348 | Operation Scheme for Non-Volatile Memory - A method of operating an integrated circuit includes determining at least one characteristic of at least one memory cell and conducting an operation for the at least one memory cell, wherein based on the at least one characteristic determined a disturbance for at least one additional memory cell is adjusted. | 06-05-2014 |
20140177362 | Memory Interface Supporting Both ECC and Per-Byte Data Masking - A memory and a method of storing data in a memory are provided. The memory comprises a memory block comprising data bits and additional bits. The memory includes logic which, when receiving a first command, writes data into the data bits of the memory block, wherein the data is masked according to a first input. The logic, in response to a second command, writes data into the data bits of the memory block and writes a second input into the additional bits of the memory block. | 06-26-2014 |
20140177363 | METHOD AND SYSTEM FOR AUTOMATED DEVICE TESTING - Embodiments described herein provide enhanced testing of devices. For example, in an embodiment, an interposer for testing devices is provided. The interposer includes a substrate, a first plurality of connection elements located on a surface of the substrate, and a memory device electrically coupled to the first plurality of connection elements through the substrate. The first plurality of connection elements are configured to mate with a second plurality of connection elements located on a device under test. The memory device is configured to store information received from the device under test and to output stored information to the device under test. | 06-26-2014 |
20140177364 | ONE-TIME PROGRAMMABLE MEMORY AND TEST METHOD THEREOF - A one-time programmable memory device may include a normal cell array including a plurality of one-time programmable memory cells, which are programmable and accessible in the normal operation, a test cell array including one-time programmable memory cells, which are programmed at a given pattern in a test operation for determining a failed row and/or a failed column and are not accessible in the normal operation, a row circuit configured to control an operation of a row that is selected by a row address in the normal cell array, and a column circuit configured to access a column that is selected by a column address in the normal cell array. | 06-26-2014 |
20140177365 | SEMICONDUCTOR APPARATUS, TEST METHOD USING THE SAME AND MUTI CHIPS SYSTEM - A semiconductor apparatus includes a test unit including: a data determination unit configured to receive a plurality of data, determine whether the plurality of data are identical or not, and output the determination result as a compression signal; and an output control unit configured to output the compression signal as a test result in response to a test mode signal and a die activation signal. | 06-26-2014 |
20140185399 | TEST MEDIATION DEVICE AND SYSTEM AND METHOD FOR TESTING MEMORY DEVICE - A system for testing a memory device includes a memory device configured to include a plurality of memory cells, receive a test information having a first frequency, access memory cells corresponding to an address included in the test information, and activate a fail signal if fail occurs in the memory cells corresponding to the address, a test device configured to generate a test information having a second frequency different from the first frequency, and a test mediation device configured to generate the test information having the first frequency and the address based on the test information having the second frequency and the fall signal and store the address corresponding to the fail memory cells in response to the fail signal as a fail address. | 07-03-2014 |
20140211581 | PROCESS VARIATION SKEW IN AN SRAM COLUMN ARCHITECTURE - Aspects of the invention provide for a structure and method for determining a degree of process variation skew between a plurality of bit cells in a static random-access-memory (SRAM) column architecture. In one embodiment, a structure includes: a plurality of bit cells within a static random access memory (SRAM) column architecture; a digital-to-analog converter (DAC) connected to the bit cells through a pair of multiplexers; and a pre-charge circuit connected to the bit cells through the pair of multiplexers, wherein the DAC and the pre-charge circuit control and test the bit cells to determine a degree of process variation skew between each of the bit cells. | 07-31-2014 |
20140211582 | Semiconductor Device Performing Stress Test - A semiconductor device includes a memory cell array that is divided into a plurality of memory cell mats by a plurality of sense amplifier arrays, and each of the plurality of memory cell mats includes a plurality of word lines and a test circuit for performing a test control to activate, at a time, a plurality of word lines included in each of a plurality of selected memory cell mats that are not disposed adjacent to each other in the plurality of memory cell mats. According to the present invention, the memory cell mats with the plurality of activated word lines are distributed. Therefore, as compared with many word lines activated in one memory cell mat, the load applied to a driver circuit for driving word lines and the load applied to a power supply circuit for supplying an operation voltage to the driver circuit are reduced. As a result, more word lines can be activated at the same time. | 07-31-2014 |
20140233335 | SEMICONDUCTOR DEVICES - A plurality of memory chips each have an alert terminal that notifies the outside that the memory chip has detected a predetermined error. The plurality of memory chips are mounted on memory module 100. Memory module 100 has a first transmission line connected to an alert terminal of each of the plurality of memory chips, output terminal 101 being connected to one end of the first transmission line, and a first termination resistor being connected to another end of the first transmission line. | 08-21-2014 |
20140269124 | MEMORY WITH BIT LINE CURRENT INJECTION - Embodiments of a memory are disclosed that may allow for the detection of weak data storage cells or may allow operation of data storage cells under conditions that may represent the effects of transistor ageing. The memory may include data storage cells, a column multiplexer, a sense amplifier, and a current injector. The current injector may be configured to generate multiple current levels and may be operable to controllably select one of the current levels to either source current to or sink current from the input of the sense amplifier. | 09-18-2014 |
20140301149 | SEMICONDUCTOR MEMORY DEVICE HAVING COMPRESSION TEST MODE - A semiconductor memory device having a compression test mode is provided. The semiconductor memory device comprises a memory unit, i test pads, a timing circuit, a compression circuit, and a signal distribution circuit. The memory unit comprises m memory banks divided into n activating groups, wherein each bank comprises a plurality of sensing amplifiers for sensing and amplifying data in bit lines. The timing circuit sequentially generates n control signals each for activating a plurality of sensing amplifiers in one of the n activating groups. The compression circuit compresses data sensed and amplified by the plurality of sensing amplifiers in each bank in a compression test mode. The signal distribution circuit distributes signals output from the compression circuit among the i data pads in rotation. The integer n and the integer i are adjustable. | 10-09-2014 |
20140307515 | CIRCUIT ARRANGEMENT, A METHOD FOR TESTING A SUPPLY VOLTAGE PROVIDED TO A TEST CIRCUIT, AND A METHOD FOR REPAIRING A VOLTAGE SOURCE - A circuit arrangement may include: a memory, composed of a memory cell array, including a plurality of memory cells, and a peripheral circuitry; a voltage source configured to provide at least one supply voltage; a test circuit integrated with the memory cell array and the voltage source, wherein the test circuit receives the supply voltage; the test circuit including: at least one test memory cell; at least one failure detection circuit configured to detect a data retention failure in the at least one test memory cell. | 10-16-2014 |
20140313841 | INTEGRATED CIRCUIT WITH PROGRAMMABLE STORAGE CELL ARRAY AND BOOT-UP OPERATION METHOD THEREOF - An integrated circuit may include a first programmable storage cell group suitable for storing program validity information, second to N-th programmable storage cell groups suitable for storing a plurality of data, wherein N is an integer equal to or more than 3, and a validity determination unit suitable for determining whether the program validity information read from the first programmable storage cell group is valid or not so that read operations for the second to N-th programmable storage cell groups is performed or skipped based on the determined result. | 10-23-2014 |
20140340975 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF TESTING SEMICONDUCTOR INTEGRATED CIRCUIT - A semiconductor integrated circuit is provided with: a memory under test; a test-result-storage memory; a test-data generation part for generating in a sequential manner a test address signal and test data for supplying to the memory under test; and a control circuit. The control circuit includes a delay circuit, which, when the control circuit stores in a sequential manner in the test-result-storage memory a test result according to the test address signal and test data in the memory under test, delays the storage-destination address signal in the test-result-storage memory from the test address signal set in the memory under test, in accordance with a time delay that includes at the least the latency from the setting of the test address signal in the memory under test to the reading out of the test data. | 11-20-2014 |
20140347944 | METHODS AND APPARATUSES FOR STACKED DEVICE TESTING - Various embodiments include apparatus, systems, and methods having multiple dies arranged in a stack in which the dies or a logic chip in communication with the dies stores a flag for indicating whether a threshold number of cells of the dies have failed during test operations. | 11-27-2014 |
20140369145 | Semiconductor Device and Test Method Thereof - A semiconductor chip includes a memory array including a plurality of memory cells, a plurality of terminals including a plurality of test terminals to output a result of a specific test, and a circuit that outputs the result to a selected one of the plurality of test terminals based on a chip identification data. | 12-18-2014 |
20150029802 | APPARATUSES, INTEGRATED CIRCUITS, AND METHODS FOR MEASURING LEAKAGE CURRENT - Methods, apparatuses, and integrated circuits for measuring leakage current are disclosed. In one such example method, a word line is charged to a first voltage, and a measurement node is charged to a second voltage, the second voltage being less than the first voltage. The measurement node is proportionally coupled to the word line. A voltage on the measurement node is compared with a reference voltage. A signal is generated, the signal being indicative of the comparison. Whether a leakage current of the word line is acceptable or not can be determined based on the signal. | 01-29-2015 |
20150043291 | METHOD FOR TESTING SEMICONDUCTOR APPARATUS AND TEST SYSTEM USING THE SAME - This technique may include a semiconductor apparatus configured to perform data read/write operations in a test mode or a normal mode and a tester configured to simultaneously perform a data test and a leakage current test through a write operation using data read by a read operation in the normal mode after writing data into the semiconductor apparatus in the test mode. | 02-12-2015 |
20150043292 | MEMORY, MEMORY SYSTEM INCLUDING THE SAME AND METHOD FOR OPERATING MEMORY - A memory may include a plurality of word lines to which one or more memory cells are connected, and a control unit suitable for activating and precharging a first word line that is selected based on an address of a high-activated word line during a target refresh operation while sequentially activating and precharging the plurality of word lines in a refresh operation, wherein the control unit is suitable for writing a test data to one or more first memory cells connected to the first word line during the target refresh operation in a test mode, wherein the high-activated word line is a word line activated over a reference number or a reference frequency, among the plurality of word lines. | 02-12-2015 |
20150063045 | DEVICE AND METHOD TO PERFORM A PARALLEL MEMORY TEST - The invention relates to a semiconductor device including N memory modules, N being greater than or equal to three, each module having an array of memory cells arranged in rows and columns, a write circuit coupled to each module and configured to write data in the memory cells, a read circuit coupled to each module and configured to supply output data from the memory cells, a module selection circuit configured to individually select one memory module in a regular operation mode, and to collectively select two or more of the modules in a parallel mode, and a comparator circuit coupled to the N modules and configured to compare, in the parallel mode, the output data supplied by the N modules. | 03-05-2015 |
20150085591 | ESTIMATION OF LEVEL-THRESHOLDS FOR MEMORY CELLS - Methods and apparatus are provided for determining level-thresholds for q-level memory cells. A plurality of the memory cells are read to obtain respective read signal components. The read signal components are processed in dependence on signal level to produce a signal level vector, comprising a series of elements, indicative of the distribution of read signal components in order of signal level. The signal level vector is scanned with a sliding window of length greater than the spacing of successive window positions in the scan. At each window position, a metric Mi is calculated in dependence on the elements of the signal level vector in the window. A level-threshold for successive memory cell levels is then determined in dependence on variation of the metric over the scan. | 03-26-2015 |
20150092506 | METHOD AND APPARATUS FOR TESTING MEMORY - A method and an apparatus for testing a memory are provided, and the method is adapted for an electronic apparatus to test the memory. In the method, a left edge and a right edge of a first waveform of a clock signal for testing the memory are scanned to obtain a maximum width between two cross points of the left edge and the right edge. A central reference voltage of a data signal outputted by the memory is obtained, and a data width between two cross points of the central reference voltage and a left edge and a right edge of a second waveform of the data signal is obtained. Whether a difference between the data width and the maximum width is greater than a threshold is determined; if the difference is greater than the threshold, the memory is determined to be damaged. | 04-02-2015 |
20150146493 | NON-VOLATILE MEMORY VALIDITY - An embodiment provides a method, including: determining current validity timing of a non-volatile memory device having changing validity timing via: writing information to a non-volatile memory device; waiting a time after the writing; and reading the information written to the non-volatile memory device following the time. Other aspects are described and claimed. | 05-28-2015 |
20150294738 | TEST STRUCTURE AND METHOD OF TESTING A MICROCHIP - A tristate inverter array test structure and method of testing structures in a microchip are disclosed. The structure includes: a PFET stack in series with an NFET stack; an inverted wordline driving a PFET of the PFET stack; a worldline driving an NFET of the NFET stack; a data_in line connecting to an input of the PFET stack and the NFET stack; and a data_out line connecting to an output of the PFET stack and the NFET stack. | 10-15-2015 |
20150302937 | METHODS AND SYSTEMS FOR MITIGATING MEMORY DRIFT - A memory cell is read by measuring a parameter associated with the memory cell with a first resolution to determine a value stored in the memory cell. The parameter is also measured with a second resolution that is finer than the first resolution. The memory cell is reprogrammed to mitigate an offset between the parameter as measured with the second resolution and the parameter as measured with the first resolution. | 10-22-2015 |
20150302938 | DETECTING WRITE DISTURB IN MULTI-PORT MEMORIES - A circuit comprises a memory cell, a first circuit, and a second circuit. The memory cell has a first control line and a second control line. The first control line carries a first control signal. The second control line carries a second control signal. The first circuit is coupled with the first control line, the second control line, and a node. The second circuit is coupled to the node and is configured to receive a first clock signal and a second clock signal. The first circuit and the second circuit, based on the first control signal, the second control signal, the first clock signal and the second clock signal, are configured to generate a node signal on the node. A logical value of the node signal indicates a write disturb condition of the memory cell. | 10-22-2015 |
20150332786 | SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME - A semiconductor memory device includes a first address input block which receives first information applied from an exterior as a corresponding normal address in a normal mode and receives the first information as a test clock in a test mode, a second address input block which receives second information applied from an exterior as the corresponding normal address in the normal mode and receives the second information as a test code in the test mode, and a test signal generation block which synchronizes the test code with the test clock in the test mode and generates a test command, a test address and a test data in response to a synchronized test code. | 11-19-2015 |
20150371717 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a voltage supply part suitable for providing a predetermined test detection voltages to a pair of bit lines respectively, during a test operation for detecting a failure between a word line and the pair of bit lines; a column connection section suitable for electrically coupling the pair of bit lines and a pair of segment lines to each other, respectively, in response to a column selection signal; and a precharge section suitable for precharging the pair of segment lines to a precharge voltage corresponding to one of the test detection voltages during a failure detection time section while performing the test operation. | 12-24-2015 |
20160005493 | METHODS AND APPARATUS FOR TESTING AND REPAIRING DIGITAL MEMORY CIRCUITS - An ActiveTest solution for memory is disclosed which can search for memory errors during the operation of a product containing digital memory. The ActiveTest system tests memory banks that are not being accessed by normal memory users in order to continually test the memory system in the background. When there is a conflict between the ActiveTest system and a memory user, the memory user is generally given priority. | 01-07-2016 |
20160012919 | MEMORY COMPRISING A CIRCUIT FOR DETECTING A GLITCH ON A LINE OF THE MEMORY | 01-14-2016 |
20160019978 | DETECTING WRITE DISTURB IN MULTI-PORT MEMORIES - A circuit includes a memory cell having a first control line and a second control line, the first control line carrying a first control signal, the second control line carrying a second control signal. A first circuit is coupled to the first control line, the second control line, and a node, and a second circuit is coupled to the node and responds to a timing of the first control signal and the second control signal. The first circuit and the second circuit, based on the first control signal and the second control signal, are configured to generate a node signal on the node, and a logical value of the node signal indicates a write disturb condition of the memory cell. | 01-21-2016 |
20160019979 | METHOD AND DEVICE FOR EVALUATING A CHIP MANUFACTURING PROCESS - A method for evaluating a chip manufacturing process is described comprising measuring, for each of a plurality of chips manufactured in a chip manufacturing process, a bit failure rate of the chip, determining a distribution of bit failure rates from the measured bit failure rates; determining a maximum allowed bit failure rate from a given chip failure rate limit, determining a value representing the probability that a chip manufactured in the chip manufacturing process is below the maximum allowed bit failure rate and determining, based on the value, whether the chip manufacturing process is suitable for the chip failure rate limit. | 01-21-2016 |
20160071617 | VOLTAGE COMPARATOR CIRCUIT AND USAGE THEREOF - A method for testing a circuit comprising a memory element, a voltage comparator and a supply selector, the circuit is configured to be connected to two power supplies, the voltage comparator is configured to provide an output indicative of a voltage difference between the two power supplies above a predetermined threshold, the supply selector is configured to select a power supply to feed power to the memory element in response to the output from the voltage comparator. The method comprises connecting the two power supplies to the circuit, wherein said connecting comprises causing the two power supplies to drive power to the memory element and to another element of the circuit, wherein the voltage different between the two power supplies is above the predetermined threshold. The method further comprises that in response to said connecting, the supply selector of the circuit is invoked and disconnects one power supply from the memory element; whereby stress testing the circuit, the stress testing tests the memory element without a voltage difference condition, the stress testing tests the another element with the voltage difference condition. | 03-10-2016 |
20160093401 | INTEGRATED CIRCUITS WITH BUILT-IN SELF TEST MECHANISM - An embodiment of the invention provides an integrated circuit including a core circuit and a memory. The core circuit executes operations of the integrated circuit. The memory stores a subsystem and a repair system. When the repair system runs, the repair system detects whether there is a defect in the memory. When the repair system detects the defect, the repair system repairs the defect, and when the repair system does not detect the defect, a fake defect is injected in the memory to verify whether the repair system runs correctly. | 03-31-2016 |
20160118141 | METHOD AND DEVICE FOR EVALUATING A CHIP MANUFACTURING PROCESS - A method for evaluating a chip manufacturing process is described comprising measuring, for each of a plurality of chips manufactured in a chip manufacturing process, a bit failure rate of the chip, determining a distribution of bit failure rates from the measured bit failure rates; determining a maximum allowed bit failure rate from a given chip failure rate limit, determining a value representing the probability that a chip manufactured in the chip manufacturing process is below the maximum allowed bit failure rate and determining, based on the value, whether the chip manufacturing process is suitable for the chip failure rate limit. | 04-28-2016 |
20160125959 | HEALTH STATE OF NON-VOLATILE MEMORY - An embodiment relates to a method for determining a health state of a non-volatile memory comprising: determining the health state based on at least one indicator for determining a predictable failure of the non-volatile memory. | 05-05-2016 |
20160133341 | SIGNAL TRANSITION ANALYSIS OF A CIRCUIT - A first signal and a second signal associated with a circuit may be identified. A first count of a number of times that the second signal is associated with a transition when the first signal is at a first value may be determined. Furthermore, a second count of a number of times that the second signal is associated with a transition when the first signal is at a second value may be determined. A value corresponding to the dependence between the second signal and the first signal may be calculated based on the first count and the second count. | 05-12-2016 |
20160141011 | SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF - Provided is a semiconductor device and an operating method thereof. The operating method of the semiconductor device includes performing an erase operation on a memory block including bottom dummy cells, a plurality of memory cells, top dummy cells and selection transistors arranged in a vertical direction with respect to a pipe gate, increasing threshold voltages of the top and bottom dummy cells at substantially a same time by applying a first soft program voltage to a bottom dummy word line coupled to the bottom dummy cells and a second soft program voltage greater than the first soft program voltage to the top dummy word line coupled to the top dummy cells, verifying the top and bottom dummy cells, and repeatedly performing the erase operation and increasing the threshold voltages by gradually increasing the first and second soft program voltages until the verifying of the top and bottom dummy cells passes. | 05-19-2016 |
20160180965 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF TESTING THE SAME | 06-23-2016 |
20170236597 | SELECTORS ON INTERFACE DIE FOR MEMORY DEVICE | 08-17-2017 |
20190147970 | SEMICONDUCTOR APPARATUS | 05-16-2019 |