| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438618000 |
Contacting multiple semiconductive regions (i.e., interconnects)
| 772 |
| 438652000 |
Plural layered electrode or conductor
| 556 |
| 438612000 |
Forming solder contact or bonding pad
| 381 |
| 438666000 |
Specified configuration of electrode or contact
| 308 |
| 438674000 |
Selective deposition of conductive layer
| 286 |
| 438669000 |
And patterning of conductive layer
| 172 |
| 438660000 |
Including heat treatment of conductive layer
| 131 |
| 438680000 |
Utilizing chemical vapor deposition (i.e., CVD)
| 130 |
| 438598000 |
Selectively interconnecting (e.g., customization, wafer scale integration, etc.)
| 61 |
| 438602000 |
To compound semiconductor
| 36 |
| 438682000 |
Silicide
| 35 |
| 438678000 |
Electroless deposition of conductive layer
| 32 |
| 438685000 |
Refractory group metal (i.e., titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), or alloy thereof)
| 30 |
| 438608000 |
Oxidic conductor (e.g., indium tin oxide, etc.)
| 28 |
| 438610000 |
Conductive macromolecular conductor (including metal powder filled composition)
| 25 |
| 438658000 |
Altering composition of conductor
| 22 |
| 438687000 |
Copper of copper alloy conductor
| 22 |
| 438686000 |
Noble group metal (i.e., silver (Ag), gold (Au), platinum (Pt), palladium (Pd), rhodium (Rh), ruthenium (Ru), iridium (Ir), osmium (Os), or alloy thereof)
| 13 |
| 438607000 |
With epitaxial conductor formation
| 8 |
| 438684000 |
Electrically conductive polysilicon | 4 |
| 20080200031 | Method of fabricating gate electrode having polysilicon film and wiring metal film - A method of forming a gate electrode of a semiconductor device according to example embodiments that may include forming a polysilicon film on a semiconductor substrate. An interface control layer may be formed on the polysilicon film by repeating a unit cycle a plurality of times. The unit cycle may include forming an interface metal film and nitriding an upper surface portion of the interface metal film to form an interface metal nitride film on an upper surface portion of the interface metal film. A wiring metal film may be formed on the interface control layer. | 08-21-2008 |
| 20080233744 | CARBON NANOTUBE SWITCHES FOR MEMORY, RF COMMUNICATIONS AND SENSING APPLICATIONS, AND METHODS OF MAKING THE SAME - Switches having an in situ grown carbon nanotube as an element thereof, and methods of fabricating such switches. A carbon nanotube is grown in situ in mechanical connection with a conductive substrate, such as a heavily doped silicon wafer or an SOI wafer. The carbon nanotube is electrically connected at one location to a terminal. At another location of the carbon nanotube there is situated a pull electrode that can be used to electrostatically displace the carbon nanotube so that it selectively makes contact with either the pull electrode or with a contact electrode. Connection to the pull electrode is sufficient to operate the device as a simple switch, while connection to a contact electrode is useful to operate the device in a manner analogous to a relay. In various embodiments, the devices disclosed are useful as at least switches for various signals, multi-state memory, computational devices, and multiplexers. | 09-25-2008 |
| 20080280440 | METHOD FOR FORMING A PN DIODE AND METHOD OF MANUFACTURING PHASE CHANGE MEMORY DEVICE USING THE SAME - Disclosed is a method of forming a PN diode and a method of manufacturing a phase change memory device using the same. Formation of a PN diode includes forming a first conductivity type region in a surface of a semiconductor substrate. A polysilicon layer doped with second conductivity type impurities is then deposited on the semiconductor substrate formed with the first conductivity type region. Forming a plurality of second conductivity type regions by etching the polysilicon layer doped with the second conductivity type impurities completes the PN diode. Since the P-regions of a PN diode are formed through the deposition and etching of a polysilicon layer doped with second conductivity type impurities rather than an SEG process, a uniformity of resistance in the PN diode can be obtained. | 11-13-2008 |
| 20090104776 | METHODS FOR FORMING NESTED AND ISOLATED LINES IN SEMICONDUCTOR DEVICES - A method for forming lines for semiconductor devices including, depositing a shallow trench isolation (STI) film stack on a silicon substrate, depositing a layer of polysilicon on the STI film stack, depositing a layer of antireflective coating on the layer of polysilicon, developing a phototoresist on the antireflective coating, wherein the photoresist defines a line, etching the layer of antireflective coating and the layer of polysilicon using RIE with a low bias power, removing the photoresist, removing the layer of antireflective coating, etching the STI film stack to form the line, wherein the layer of polysilicon further defines the line. | 04-23-2009 |
| 438688000 |
Aluminum or aluminum alloy conductor | 4 |
| 20080305634 | Metal Film Separation Prevention Structure in Metal Film Forming Device, and Semiconductor Device Manufacturing Method Using Said Structure - The object of this invention is to prevent unwanted separation of a deposited metal film from a member, such as an anti-adhesion plate, in the chamber of a metal film forming device. In a sputtering device, metal particles sputtered from the surface of a target | 12-11-2008 |
| 20110230047 | METHOD OF ETCHING ORGANOSILOXANE DIELECTRIC MATERIAL AND SEMICONDUCTOR DEVICE THEREOF - In some embodiments, a method of etching an organosiloxane dielectric material can include: (a) providing the organosiloxane dielectric material; (b) providing a patterned mask over the organosiloxane dielectric material; and (c) reactive ion etching the organosiloxane dielectric material. Other embodiments are disclosed in this application. | 09-22-2011 |
| 20140004700 | MANUFACTURING METHOD FOR A SEMICONDUCTOR APPARATUS | 01-02-2014 |
| 20140377952 | WIRING FILM AND ACTIVE MATRIX SUBSTRATE USING THE SAME, AND METHOD FOR MANUFACTURING WIRING FILM - An Al wiring film having a tapered shape is obtained easily and in a stable manner. An Al wiring film has a double-layer structure including a first Al alloy layer made of Al or an Al alloy, and a second Al alloy layer laid on the first Al alloy layer and having a composition different from a composition of the first Al alloy layer by containing at least one element of Ni, Pd, and Pt. The second Al alloy layer is etched by an alkaline chemical solution used in a developing process of a photoresist, and an end portion of the second Al alloy layer recedes from an end portion of the photoresist. Thereafter, by performing wet etching using the photoresist as a mask, a cross section of the Al wiring film becomes a tapered shape. | 12-25-2014 |
| 438679000 |
Evaporative coating of conductive layer | 2 |
| 20080248647 | Method of depositing materials on a non-planar surface - A method of depositing materials on a non-planar surface is disclosed. The method is effectuated by rotating non-planar substrates as they travel down a translational path of a processing chamber. As the non-planar substrates simultaneously rotate and translate down a processing chamber, the rotation exposes the whole or any desired portion of the surface area of the non-planar substrates to the deposition process, allowing for uniform deposition as desired. Alternatively, any predetermined pattern is able to be exposed on the surface of the non-planar substrates. Such a method effectuates manufacture of non-planar semiconductor devices, including, but not limited to, non-planar light emitting diodes, non-planar photovoltaic cells, and the like. | 10-09-2008 |
| 20110318924 | METHOD FOR DEPOSITION OF AT LEAST ONE ELECTRICALLY CONDUCTING FILM ON A SUBSTRATE - The invention relates to a method for deposition of at least one electrically conducting film ( | 12-29-2011 |
| 438665000 |
Utilizing textured surface | 2 |
| 20100151678 | Wafer Backside Grinding with Stress Relief - A method of relieving stress in a semiconductor wafer and providing a wafer backside surface finish capable of hiding cosmetic imperfections. Embodiments of the invention include creating a wafer backside surface which can be used for all dies on the semiconductor wafer intended for different product applications and be deposited with backside metallization (BSM) material. The method provides a rough texture on the wafer backside followed by isotropic etching of the wafer backside to recover the wafer strength as well as to preserve the rough texture of the wafer backside. After wafer backside metallization, the rough texture of the wafer backside hides cosmetic imperfections introduced by subsequent processes. | 06-17-2010 |
| 20150093894 | SEMICONDUCTOR MANUFACTURING APPARATUS, SEMICONDUCTOR MANUFACTURING METHOD, AND PROCESS TUBE - According to one embodiment, a semiconductor manufacturing apparatus includes a process tube, a substrate supporting unit, and a heater. A surface processing area is provided in a portion of the outer surface of the process tube facing the heater. The surface processing area is processed to reduce the heat radiation passing compared to that of other areas of the outer surface. The surface processing area is provided in a range sandwiched by a straight line connecting the upper end of the heater and the upper end of the substrate supporting unit and a straight line connecting the lower end of the heater and the lower end of the substrate supporting unit. | 04-02-2015 |
| 438611000 |
Beam lead formation | 1 |
| 20100129999 | STRUCTURES AND METHODS FOR AN APPLICATION OF A FLEXIBLE BRIDGE - One embodiment of the present invention provides a system that facilitates high-bandwidth communication using a flexible bridge. This system includes a chip with an active face upon which active circuitry and signal pads reside, and a second component with a surface upon which active circuitry and/or signal pads reside. A flexible bridge provides high-bandwidth communication between the active face of the chip and the surface of the second component. This flexible bridge provides a flexible connection that allows the chip to be moved with six degrees of freedom relative to the second component without affecting communication between the chip and the second component. Hence, the flexible bridge allows the chip and the second component to communicate without requiring precise alignment between the chip and the second component. | 05-27-2010 |
| Entries |
| Document | Title | Date |
|---|
| 20080200022 | POST-SEED DEPOSITION PROCESS - A method involves pattern etching a photoresist that is located on a wafer that contains a deposited seed layer to expose portions of the seed layer, plating the wafer so that plating metal builds up on only the exposed seed layer until the plating metal has reached an elevation above the seed layer that is at least equal to a thickness of the seed layer, removing the solid photoresist, and removing seed layer exposed by removal of the photoresist and plated metal until all of the exposed seed layer has been removed. | 08-21-2008 |
| 20080206977 | METHODS OF FORMING WIRING TO TRANSISTOR AND RELATED TRANSISTOR - Methods of wiring to a transistor and a related transistor are disclosed. In one embodiment, the method includes a method of forming wiring to a transistor, the method comprising: forming a transistor on a semiconductor-on-insulator (SOI) substrate using masks that are mirror images of an intended layout, the forming including forming a gate and a source/drain region for each and a channel, the SOI substrate including a semiconductor-on-insulator (SOI) layer, a buried insulator layer and a silicon substrate; forming a dielectric layer over the transistor; bonding the dielectric layer to another substrate; removing the silicon substrate from the SOI substrate to the buried insulator layer; forming a contact to each of the source/drain region and the gate from a channel side of the gate; and forming at least one wiring to the contacts on the channel side of the gate. | 08-28-2008 |
| 20080213991 | Method of forming plugs - The present invention is a method of forming plugs for engaging with a socket on a substrate having pads thereon. The method including the steps of forming an insulation layer on the substrate, patterning the insulation layer to form openings for exposing the pads by a wet etching, respectively, forming conductive plugs in the openings to electrically connect with the pads, and partially removing the insulation layer. | 09-04-2008 |
| 20080233731 | Method of Forming Top Electrode for Capacitor and Interconnection in Integrated Passive Device (IPD) - A method of manufacturing a semiconductor device includes providing a substrate having a first conductive layer disposed on a top surface of the substrate. A high resistivity layer is formed over the substrate and the first conductive layer. A dielectric layer is deposited over the substrate, first conductive layer and high resistivity layer. A portion of the dielectric layer, high resistivity layer, and first conductive layer forms a capacitor stack. A first passivation layer is formed over the dielectric layer. A second conductive layer is formed over the capacitor stack and a portion of the first passivation layer. A first opening is etched in the dielectric layer to expose a surface of the high resistivity layer. A third and fourth conductive layer is deposited over the first opening in the dielectric layer and a portion of the first passivation layer. | 09-25-2008 |
| 20080299756 | METHOD AND APPARATUS FOR PLATING A SEMICONDUCTOR PACKAGE - A method of plating a plurality of semiconductor devices includes: applying an electrical power source to an anode terminal and a cathode terminal; placing the plurality of semiconductor devices on a non-conductive platform in a plating solution; moving conductive parts across surfaces of the semiconductor devices to be plated, wherein the conductive parts electrically connect the surfaces of the semiconductor devices to the cathode; and wherein plating particles connected to the anode terminal move to and plate the surfaces of the semiconductor devices. | 12-04-2008 |
| 20090004839 | METHOD FOR FABRICATING AN INTERLAYER DIELECTRIC IN A SEMICONDUCTOR DEVICE - In a method for fabricating an interlayer dielectric in a semiconductor device, conductive patterns are formed on a semiconductor substrate. A fluid dielectric is formed to cover the conductive patterns. The fluid dielectric is recessed. A buried dielectric is deposited on the conductive patterns exposed by the recessing process. The buried dielectric is denser than the fluid dielectric, thereby forming an interlayer dielectric including the fluid dielectric and the buried dielectric. | 01-01-2009 |
| 20090053886 | High density chalcogenide memory cells - A non-volatile memory cell is constructed from a chalcogenide alloy structure and an associated electrode side wall. The electrode is manufactured with a predetermined thickness and juxtaposed against a side wall of the chalcogenide alloy structure, wherein at least one of the side walls is substantially perpendicular to a planar surface of the substrate. The thickness of the electrode is used to control the size of the active region created within the chalcogenide alloy structure. Additional memory cells can be created along rows and columns to form a memory matrix. The individual memory cells are accessed through address lines and address circuitry created during the formation of the memory cells. A computer can thus read and write data to particular non-volatile memory cells within the memory matrix. | 02-26-2009 |
| 20090176360 | Methods for processing a substrate with a flow controlled meniscus - A method for processing a substrate is provided which includes applying fluid onto a surface of the substrate from a portion of a plurality of inlets and removing at least the fluid from the surface of the substrate where the removing being processed as the fluid is applied to the surface. The applying the fluid and the removing the fluid forms a segment of a fluid meniscus on the surface of the substrate. | 07-09-2009 |
| 20090176361 | SEMICONDUCTOR DEVICE PREVENTING ELECTRICAL SHORT AND METHOD OF MANUFACTURING THE SAME - A semiconductor device capable of preventing an electrical short between contacts and their adjacent contact pads and a method of manufacturing the same are provided. A first interlayer insulating layer is formed on the semiconductor substrate including the active region. Contact pads pass through the first interlayer insulating layer and contact with the active region. Contacts are formed on the contact pads and are connected to a conductive layer disposed above the contacts. The contact pads have a height lower than a top surface of the first interlayer insulating layer such that the contact pads have smaller thickness than the first interlayer insulating layer. | 07-09-2009 |
| 20090203206 | FABRICATION OF SEMICONDUCTOR DEVICES USING ANTI-REFLECTIVE COATINGS - Techniques are disclosed for fabricating a device using a photolithographic process. The method includes providing a first anti-reflective coating over a surface of a substrate. A layer which is transparent to a wavelength of light used during the photolithographic process is provided over the first anti-reflective coating, and a photosensitive material is provided above the transparent layer. The photosensitive material is exposed to a source of radiation including the wavelength of light. Preferably, the first anti-reflective coating extends beneath substantially the entire transparent layer. The complex refractive index of the first anti-reflective coating can be selected to maximize the absorption at the first anti-reflective coating to reduce notching of the photosensitive material. | 08-13-2009 |
| 20090203207 | Method for manufacturing semiconductor device - A contact hole, after hole etching, is subjected to light etching using a process gas containing a fluorocarbon-based gas and oxygen, with the oxygen being enriched, under condition without applying bias. Then, reaction products ( | 08-13-2009 |
| 20090253258 | SEMICONDUCTOR MANUFACTURING APPARATUS AND SEMICONDUCTOR MANUFACTURING METHOD - A plated film having a uniform film thickness is formed on a surface of a substrate. A semiconductor manufacturing apparatus includes: a holding mechanism for holding a substrate rotatably; a nozzle for supplying a processing solution for performing a plating process on a processing target surface of the substrate; a substrate rotating mechanism for rotating the substrate held by the holding mechanism in a direction along the processing target surface; a nozzle driving mechanism for moving the nozzle in a direction along the processing target surface at a position facing the processing target surface of the substrate held by the holding mechanism; and a control unit for controlling the supply of the processing solution by the nozzle and the movement of the nozzle by the nozzle driving mechanism. | 10-08-2009 |
| 20090280633 | METHOD OF FORMING SELF-ALIGNED CONTACTS AND LOCAL INTERCONNECTS - A method for simultaneous formation of a self-aligned contact of a core region and a local interconnect of a peripheral region of an integrated circuit includes etching a cap dielectric layer to simultaneously form a hole in the core region and a trench in the peripheral region of the cap dielectric layer, etching a dielectric layer to simultaneously form a hole in the core region and a trench in the peripheral region of the dielectric layer of the dielectric layer, etching a liner layer simultaneously on a shoulder of sidewall spacers associated with the hole and with the trench of the dielectric layer without etching the liner layer at a bottom area of the hole and the trench, performing an oxygen flushing to remove polymer residues, and etching simultaneously through the liner layer that lines the bottom area of the hole and the trench. | 11-12-2009 |
| 20090280634 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device is provided. The semiconductor device in which a field effect transistor utilizing a heterojunction is formed in a device formation region sectioned by a device separation region of a substrate comprising a semiconductor layer laminated while including a semiconductor layer having a heterojunction on a semiconductor substrate. The device separation region is composed of a layer in which a conductive impurity is introduced, and an electrode to which a positive voltage is to be applied is formed on the device separation region, specifically on the surface of at least a part of the device separation region in the periphery of the field effect transistor. | 11-12-2009 |
| 20090298276 | METHODS OF FORMING SEMICONDUCTOR DEVICE PATTERNS - A first mask layer pattern including a plurality of parallel line portions is formed on an etch target layer on a semiconductor substrate. A sacrificial layer is formed on the first mask layer pattern and portions of the etch target layer between the parallel line portions of the first mask layer pattern. A second mask layer pattern is formed on the sacrificial layer, the second mask layer pattern including respective parallel lines disposed between respective adjacent ones of the parallel line portions of the first mask layer pattern, wherein adjacent line portions of the first mask layer pattern and the second mask layer pattern are separated by the sacrificial layer. A third mask layer pattern is formed including first and second portions covering respective first and second ends of the line portions of the first mask layer pattern and the second mask layer pattern and having an opening at the line portions of the first and second mask layer patterns between the first and second ends. The sacrificial layer and the etch target layer are etched using the third mask layer pattern, the first mask layer pattern and the second mask layer pattern as a mask to thereby form a plurality of parallel trenches in the etch target layer between the line portions of the first and second mask layer patterns. Conductive lines may be formed in the trenches. | 12-03-2009 |
| 20100015791 | SUPPLY APPARATUS, SEMICONDUCTOR MANUFACTURING APPARATUS AND SEMICONDUCTOR MANUFACTURING METHOD - A film of uniform thickness can be formed on the entire surface of a substrate. A processing solution supply apparatus includes: a nozzle provided with a supply hole for discharging a plating solution toward a processing surface of a substrate held in a substantially horizontal direction; a temperature controller for accommodating therein the plating solution in an amount necessary for processing a preset number of substrates, for controlling a temperature of the accommodated plating solution up to a preset temperature; a heat insulator disposed between the nozzle and the temperature controller, for maintaining the plating solution, whose temperature has been controlled by the temperature controller, at the preset temperature; and a transporting mechanism for transporting the plating solution, whose temperature has been controlled up to the preset temperature by the temperature controller, toward the supply hole of the nozzle via the heat insulator. | 01-21-2010 |
| 20100055893 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device according to one embodiment includes: forming an interlayer sacrificial film and an insulating film located thereon above a semiconductor substrate having a semiconductor element, the interlayer sacrificial film having a wiring provided therein; etching the insulating film, or, etching the insulating film and the interlayer sacrificial film to form a trench reaching the interlayer sacrificial film; forming a gas permeable film in the trench; gasifying and removing the interlayer sacrificial film through the trench and the gas permeable film; and forming a sealing film on the gas permeable film for sealing the vicinity of an opening of the trench after removing the interlayer sacrificial film. | 03-04-2010 |
| 20100055894 | Method for Manufacturing Semiconductor Device - It is an object to form a conductive region between a front surface and a rear surface of an insulating film without forming contact holes in the insulating film. A method for manufacturing a semiconductor device is provided, in which an insulating film is formed over a semiconductor element and a first electrode electrically connected to the semiconductor element which are over a substrate, a first region having many defects is formed at a first depth in the insulating film by adding first ions into the insulating film at a first accelerating voltage; a second region having many defects is formed at a second depth which is different from the first depth in the insulating film by adding second ions into the insulating film at a second accelerating voltage which is different from the first accelerating voltage, a conductive material containing a metal element is formed over the first and second regions having many defects; and a conductive region which electrically connects the first electrode and the conductive material containing the metal element is formed in the insulating film by diffusing the metal element from the upper region to the lower region of the first and second regions having many defects. | 03-04-2010 |
| 20100144135 | Method of manufacturing a phase changeable memory unit - A phase changeable memory unit includes a lower electrode, an insulating interlayer structure having an opening, a phase changeable material layer and an upper electrode. The lower electrode is formed on a substrate. The insulating interlayer structure has an opening and is formed on the lower electrode and the substrate. The opening exposes the lower electrode and has a width gradually decreasing downward. The phase changeable material layer fills the opening and partially covers an upper face of the insulating interlayer structure. The upper electrode is formed on the phase changeable material layer. | 06-10-2010 |
| 20100167520 | Resist feature and removable spacer pitch doubling patterning method for pillar structures - A method of making a semiconductor device includes forming at least one layer over a substrate, forming at least two spaced apart features of imagable material over the at least one layer, forming sidewall spacers on the at least two features and filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature. The method also includes selectively removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other, and etching the at least one layer using the first feature, the filler feature and the second feature as a mask. | 07-01-2010 |
| 20100167521 | Semiconductor Processing Methods - Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the growth of the conductive contact regions over the front side. In some embodiments, plasma-enhanced atomic layer deposition may be utilized to for the deposition, and may be conducted at a temperature suitable to anneal passivation materials so that such annealing occurs simultaneously with the plasma-enhanced atomic layer deposition. | 07-01-2010 |
| 20100203718 | MITIGATION OF HIGH STRESS AREAS IN VERTICALLY OFFSET STRUCTURES - Alternative methods of constructing a vertically offset structure are disclosed. An embodiment includes forming a flexible layer having first and second end portions, an intermediate portion coupling the first and second portions, and upper and lower surfaces. The distance between the upper and lower surfaces at the intermediate portion is less than the distance between the upper and lower surfaces at the first and second end portions. The first end portion is bonded to a base member. The second end portion of the flexible layer is deflected until the second end portion contacts the base member. The second end portion is bonded to the base member. | 08-12-2010 |
| 20100267227 | Mask frame assembly for thin film deposition and associated methods - A mask frame assembly for thin film deposition including a frame having an opening portion and a support portion, and a mask having a deposition area in a position corresponding to the opening portion, wherein the mask includes a first layer including the deposition area and a peripheral portion disposed outside the deposition area and a second layer including a first surface and a second surface opposite to the first surface, at least a part of the first surface of the second layer faces the first layer and contacts the peripheral portion, and the second surface is welded to the support portion of the frame. | 10-21-2010 |
| 20110021015 | Formation of a Masking Layer on a Dielectric Region to Facilitate Formation of a Capping Layer on Electrically Conductive Regions Separated by the Dielectric Regions - A masking layer is formed on a dielectric region of an electronic device so that, during subsequent formation of a capping layer on electrically conductive regions of the electronic device that are separated by the dielectric region, the masking layer inhibits formation of capping layer material on or in the dielectric region. The capping layer can be formed selectively on the electrically conductive regions or non-selectively; in either case (particularly in the latter), capping layer material formed over the dielectric region can subsequently be removed, thus ensuring that capping layer material is formed only on the electrically conductive regions. Silane-based materials, such as silane-based SAMs, can be used to form the masking layer. The capping layer can be formed of an electrically conductive material (e.g., a cobalt alloy, a nickel alloy, tungsten, tantalum, tantalum nitride), a semiconductor material, or an electrically insulative material, and can be formed using any appropriate process, including conventional deposition processes such as electroless deposition, chemical vapor deposition, physical vapor deposition or atomic layer deposition. | 01-27-2011 |
| 20110053367 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - An etching stopper film is formed over a first insulating film. Then, a second insulating film is formed with a thickness that allows concave and convex portions formed due to a first gate electrode to remain. Then, anisotropic etching is performed using the etching stopper film as a stopper to remove the second insulating film over a second gate electrode and form a first side wall spacer of the first gate electrode. Then, the etching stopper film is removed. Then, anisotropic etching is performed on the first insulating film to form a second side wall spacer over the second gate electrode and form a third side wall spacer which is disposed inside the first side wall spacer over the first gate electrode. | 03-03-2011 |
| 20110104884 | HOT EDGE RING WITH SLOPED UPPER SURFACE - A hot edge ring with extended lifetime comprises an annular body having a sloped upper surface. The hot edge ring includes a step underlying an outer edge of a semiconductor substrate supported in a plasma processing chamber wherein plasma is used to process the substrate. The step includes a vertical surface which surrounds the outer edge of the substrate and the sloped upper surface extends upwardly and outwardly from the upper periphery of the vertical surface. | 05-05-2011 |
| 20110136332 | METHODS OF FORMING INTEGRATED CIRCUIT DEVICES WITH CRACK-RESISTANT FUSE STRUCTURES - A fuse base insulating region, for example, an insulating interlayer or a compensation region disposed in an insulating interlayer, is formed on a substrate. An etch stop layer is formed on the fuse base insulating region and forming an insulating interlayer having a lower dielectric constant than the first fuse base insulating region on the etch stop layer. A trench extending through the insulating interlayer and the etch stop layer and at least partially into the fuse base insulating region is formed. A fuse is formed in the trench. The fuse base insulating region may have a greater mechanical strength and/or density than the second insulating interlayer. | 06-09-2011 |
| 20110136333 | SEMICONDUCTOR MATERIALS AND METHODS OF PREPARATION AND USE THEREOF - Disclosed are new semiconductor materials prepared from dimeric perylene compounds. Such compounds can exhibit high n-type carrier mobility and/or good current modulation characteristics. In addition, the compounds of the present teachings can possess certain processing advantages such as solution-processability and/or good stability at ambient conditions. | 06-09-2011 |
| 20110201190 | COMPOSITION FOR PRINTING A SEED LAYER AND PROCESS FOR PRODUCING CONDUCTOR TRACKS - The invention relates to a composition for printing a seed layer for electrodeposition or electroless deposition of a metal for the production of full-area or structured metallic surfaces on a substrate, comprising 0.1 to 6% by weight of electrolessly and/or electrolytically coatable particles, 40 to 98.8% by weight of at least one solvent, 0 to 15% by weight of a crosslinker, 0.1 to 6% by weight of at least one dispersing additive, 0 to 5% by weight of at least one further additive and 1 to 20% by weight of at least one polymer, said at least one polymer being in the form of a dispersion. The invention further relates to a process for producing full-area or structured metallic surfaces on a substrate, and to a use of the process. | 08-18-2011 |
| 20120077338 | COMBINATORIAL PLASMA ENHANCED DEPOSITION TECHNIQUES - Combinatorial plasma enhanced deposition techniques are described, including designating multiple regions of a substrate, providing a precursor to at least a first region of the multiple regions, and providing a plasma to the first region to deposit a first material on the first region formed using the first precursor, wherein the first material is different from a second material formed on a second region of the substrate. | 03-29-2012 |
| 20120094478 | RESIST FEATURE AND REMOVABLE SPACER PITCH DOUBLING PATTERNING METHOD FOR PILLAR STRUCTURES - A method of making a semiconductor device includes forming a layer over a substrate, forming a plurality of spaced apart features of imagable material over the layer, forming sidewall spacers on the plurality of features and filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature. The method also includes removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other, and etching the layer using the first feature, the filler feature and the second feature as a mask. | 04-19-2012 |
| 20120100709 | PLATING APPARATUS AND PLATING METHOD - A plating apparatus allows a substrate holder to be serviced easily while ensuring easy access to the substrate holder and while a substrate is being processed in the plating apparatus. The plating apparatus includes a plating section for plating a substrate, a substrate holder for holding the substrate, a substrate holder transporter for holding and transporting the substrate holder, a stocker for storing the substrate holder, and a stocker setting section for storing the stocker therein. The stocker includes a moving mechanism for moving the stocker into and out of the stocker setting section. | 04-26-2012 |
| 20120108052 | ELECTRONIC APPARATUS CONTAINING LANTHANIDE YTTRIUM ALUMINUM OXIDE - Electronic apparatus and methods of forming the electronic apparatus include a lanthanide yttrium aluminum oxide dielectric film on a substrate for use in a variety of electronic systems. The lanthanide yttrium aluminum oxide film may be structured as one or more monolayers. The lanthanide yttrium aluminum oxide film may be formed by a monolayer or partial monolayer sequencing process such as using atomic layer deposition. | 05-03-2012 |
| 20120149189 | HYDROGEN PASSIVATION OF INTEGRATED CIRCUITS - An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping layer. Method for forming an integrated circuit having a hydrogen or deuterium releasing layer. Method for forming an integrated circuit having a passivation trapping layer. | 06-14-2012 |
| 20120190186 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method includes: forming a first insulating film over the surface of a semiconductor substrate having at least two adjacent protrusions in such a manner that the film thickness between the two protrusions is not less than 1.2 times the height of at least one of the two protrusions; and forming a second insulating film over the first insulating film, the second insulating film being harder than the first insulating film. | 07-26-2012 |
| 20120208361 | METHOD FOR FORMING FINE PATTERNS OF A SEMICONDUCTOR DEVICE - A method of forming fine patterns in a semiconductor device includes forming narrow-width patterns in a first region and wide-width patterns in a second region, where the widths of the narrow-width patterns are smaller than the resolution limitations in a photolithography process used to make the semiconductor device. The first and second regions may comprise cell array regions, with memory cells in the first region and peripheral circuits for operating the memory cells in the second region. The semiconductor device can be, for example, a NAND FLASH memory device. The semiconductor memory device can be variously classified according to the type of memory cells to be integrated in the cell array region, e.g., a DRAM, an SRAM, a PRAM, a RRAM, an MRAM, and a FRAM. In other embodiments, a MEMS device, an optoelectronic device, or a processor, such as CPU or DSP, may be provided on the semiconductor substrate. | 08-16-2012 |
| 20120214300 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SUBSTRATE PROCESSING APPARATUS - Provided are a semiconductor device manufacturing method and a substrate processing apparatus that are capable of increasing a work function of a film to be formed, in comparison with a related art. A cycle including (a) supplying a metal-containing gas into a processing chamber where a substrate is accommodated (b) supplying a nitrogen-containing gas into the processing chamber; and (c) supplying one of an oxygen-containing gas, a halogen-containing gas and a combination thereof into the processing chamber, is performed a plurality of times to form a metal-containing film on the substrate. | 08-23-2012 |
| 20120225548 | METHODS OF FORMING DIELECTRIC LAYERS AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME - To form a dielectric layer, an organometallic precursor is adsorbed on a substrate loaded into a process chamber. The organometallic precursor includes a central metal and ligands bound to the central metal. An inactive oxidant is provided onto the substrate. The inactive oxidant is reactive with the organometallic precursor. An active oxidant is also provided onto the substrate. The active oxidant has a higher reactivity than that of the inactive oxidant. | 09-06-2012 |
| 20120282766 | MITIGATION OF SILICIDE FORMATION ON WAFER BEVEL - A method for preventing formation of metal silicide material on a wafer bevel is provided, where the wafer bevel surrounds a central region of the wafer. The wafer is placed in bevel plasma processing chamber. A protective layer is deposited on the wafer bevel. The wafer is removed from the bevel plasma processing chamber. A metal layer is deposited over at least part of the central region of the wafer, wherein part of the metal layer is deposited over the protective layer. Semiconductor devices are formed while preventing metal silicide formation on the wafer bevel. | 11-08-2012 |
| 20130040451 | METHOD FOR PERMANENT CONNECTION OF TWO METAL SURFACES - A process for the production of a permanent, electrically conductive connection between a first metal surface of a first substrate and a second metal surface of a second substrate, wherein a permanent, electrically conductive connection is produced, at least primarily, by substitution diffusion between metal ions and/or metal atoms of the two metal surfaces. | 02-14-2013 |
| 20130095649 | Chemical Bath Replenishment - Ions depleted from a chemical bath by a reaction such as plating are continually replenished by production and moving of ions through selectively permeable membranes while isolating potential contaminant ions from the chemical bath. | 04-18-2013 |
| 20130130490 | COMBINATORIAL APPROACH FOR SCREENING OF ALD FILM STACKS - In some embodiments of the present invention, methods of using one or more small spot showerhead apparatus to deposit materials using CVD, PECVD, ALD, or PEALD on small spots in a site isolated, combinatorial manner are described. The small spot showerheads may be configured within a larger combinatorial showerhead to allow multi-layer film stacks to be deposited in a combinatorial manner. | 05-23-2013 |
| 20130230980 | PHOTORESIST STRUCTURES HAVING RESISTANCE TO PEELING - A method of patterning a semiconductor device including dividing a layout into more than one pattern. The method further includes depositing a film stack on a semiconductor substrate, depositing a hard mask on the film stack, and depositing a first photoresist on the hard mask. The method further includes patterning the first photoresist using a first pattern of the more than one pattern. The method further includes etching the hard mask to transfer a design of the first pattern of the more than one pattern to the hard mask. The method further includes depositing a second photoresist over the etched hard mask and patterning the second photoresist using a second pattern of the more than one pattern. The method further includes etching portions of the film stack exposed by a combination of the etched hard mask and the second photoresist. | 09-05-2013 |
| 20140004696 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE | 01-02-2014 |
| 20140170847 | METHOD OF FORMING CRACK FREE GAP FILL - Techniques disclosed herein may achieve crack free filling of structures. A flowable film may substantially fill gaps in a structure and extend over a base in an open area adjacent to the structure. The top surface of the flowable film in the open area may slope down and may be lower than top surfaces of the structure. A capping layer having compressive stress may be formed over the flowable film. The bottom surface of the capping layer in the open area adjacent to the structure is lower than the top surfaces of the lines and may be formed on the downward slope of the flowable film. The flowable film is cured after forming the capping layer, which increases tensile stress of the flowable film. The compressive stress of the capping layer counteracts the tensile stress of the flowable film, which may prevent a crack from forming in the base. | 06-19-2014 |
| 20140220771 | WORM MEMORY DEVICE AND PROCESS OF MANUFACTURING THE SAME - A process of manufacturing a Write-Once-Read-Many-times memory, at least includes the following steps: (A) providing a substrate as a lower electrode; (B) depositing a first oxide layer on the substrate; (C) depositing at least one or more silicon/germanium (Si/Ge) layers on the first oxide layer; (D) depositing a second oxide layer on the at least one or more Si/Ge layers; (E) carrying out a rapid thermal annealing to form SiGe nanocrystals embedded in the first dioxide layer and the second oxide layer; and (F) depositing a conductive layer on the second oxide layer as an upper electrode. The SiGe nanocrystals embedded in the Al | 08-07-2014 |
| 20140220772 | Doping Control of Metal Nitride Films - Described are methods for controlling the doping of metal nitride films such as TaN, TiN and MnN. The temperature during deposition of the metal nitride film may be controlled to provide a film density that permits a desired amount of doping. Dopants may include Ru, Cu, Co, Mn, Mo, Al, Mg, Cr, Nb, Ta, Ti and V. The metal nitride film may optionally be exposed to plasma treatment after doping. | 08-07-2014 |
| 20140342544 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor wafer is subjected to a protection film formation step process as a process before evaluation of electrical characteristics. In this process, after an insulating film serving as a protection film is formed, a photolithography process and an etching process are performed so as to form a protection film having a plurality of openings exposing an emitter electrode. Then, electrical characteristics are evaluated by bringing a contact probe in contact with the exposed emitter electrode through each opening. | 11-20-2014 |
| 20150044862 | PHASE CHANGING ON-CHIP THERMAL HEAT SINK - A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip. | 02-12-2015 |
| 20150099355 | PLATING APPARATUS, PLATING METHOD, AND STORAGE MEDIUM - A plating apparatus | 04-09-2015 |
| 20150380288 | Substrate Processing Apparatus, Method of Manufacturing Semiconductor Device and Non-Transitory Computer-Readable Recording Medium - Provided is a substrate processing apparatus including a substrate container transfer device configured to transfer a substrate container accommodating a substrate and purge an inside of the substrate container; a purge gas supply unit installed at the substrate container transfer device and configured to supply a purge gas into the substrate container; a substrate container standby unit configured to accommodate the substrate container; a contact preventing unit installed at the substrate container standby unit and configured to prevent a contact between the purge gas supply unit and the substrate container standby unit when the substrate container is transferred to the substrate container standby unit by the substrate container transfer device; and a control unit configured to control the substrate container transfer device and the purge gas supply unit. | 12-31-2015 |
