Entries |
Document | Title | Date |
20080200023 | METHOD OF FABRICATING MICRO CONNECTORS - A wafer is provided, and a first surface of the wafer is etched to form a plurality of through holes. A first surface conductive layer is formed on the first surface, and an internal conductive layer is formed to fill up each through hole. A first insulating layer is formed on the first surface conductive layer. A thinning process is performed to thin a second surface of the wafer so as to expose the internal conductive layer in the through holes. A second surface conductive layer is formed on the second surface, and the second surface conductive layer is electrically connected to the first surface conductive layer via the internal conductive layer. | 08-21-2008 |
20080233734 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a first insulating film over a semiconductor substrate, forming a trench in the first insulating film, forming a metal interconnect in the trench, exposing the surface of the metal interconnect to a silicon-containing gas, performing a plasma treatment of the surface of the metal interconnect after exposing to the silicon-containing gas, and forming a second insulating film over the metal interconnect. | 09-25-2008 |
20080293237 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE BY USING DUAL DAMASCENE PROCESS AND METHOD FOR MANUFACTURING ARTICLE HAVING COMMUNICATING HOLE - A method for manufacturing a semiconductor device is provided, in which the lengths of a wiring trench and a via hole in a depth direction are easily controlled. A component having a first insulating film is prepared on a substrate, and a layer is disposed on the above-described first insulating film. A mold having a pattern is imprinted on the above-described layer so as to form a second insulating film having a wiring trench and a first via, the pattern corresponding to the wiring trench and the first via. Thereafter, the above-described first insulating film is etched by using the above-described second insulating film as a mask so as to form a second via, which is connected to the first via, in the first insulating film. | 11-27-2008 |
20080318408 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Disclosed is a method of manufacturing a semiconductor device which includes: providing an insulating film formed above a semiconductor substrate with a processed portion; supplying a surface of the processed portion of the insulating film with a primary reactant from a reaction of a raw material including at least a Si-containing compound; and subjecting the primary reactant to dehydration condensation to form a silicon oxide film on the surface of the processed portion. | 12-25-2008 |
20090004841 | Forming vias using sacrificial material - In one embodiment, the present invention includes a method for forming a sacrificial material layer, patterning it to obtain a first patterned sacrificial material layer, embedding the first patterned sacrificial material layer into a dielectric material, treating the first patterned sacrificial material layer to remove it to thus provide a patterned dielectric layer having a plurality of openings in which vias may be formed. Other embodiments are described and claimed. | 01-01-2009 |
20090004842 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The present invention relates to a method of fabricating a semiconductor device. According to the method, a first insulating layer having a contact hole formed therein is formed over a semiconductor substrate. A second insulating layer is gap filled within the contact hole. A third insulating layer having a trench formed therein is formed over the semiconductor substrate including the contact hole. The second insulating layer gap filled within the contact hole is removed. A contact plug and a bit line are formed within the contact hole and the trench. | 01-01-2009 |
20090011590 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device in which a plurality of conductive lines having a fine pitch and a uniform thickness can be formed is provided. The method includes forming a plurality of first conductive patterns in a insulation layer as closed curves, forming a plurality of mask patterns on the insulation layer, the mask patterns exposing end portions of each of the first conductive patterns, and forming a plurality of second conductive patterns in the insulation layer as lines by removing the end portions of each of the first conductive patterns. | 01-08-2009 |
20090011591 | Film substrate, fabrication method thereof, and image display substrate - In a film substrate (FB) including a film base material ( | 01-08-2009 |
20090023283 | INTERCONNECTION PROCESS - An interconnection process is described. A substrate having a conductive region formed therein is provided. A dielectric layer is formed on the substrate. A patterned metal hard mask layer having a trench opening is formed on the dielectric layer. A dielectric hard mask layer is formed conformally on the patterned metal hard mask layer and filled in the trench opening. A photoresist pattern is defined to remove a portion of the dielectric hard mask layer and a portion of the dielectric layer to form a first opening in the dielectric layer. The photoresist pattern is removed. A first etching process is performed using the patterned metal hard mask layer as a mask to form a trench and a second opening extending downward from the first opening in the dielectric layer. The second opening exposes the conductive region. A conductive layer is formed in the trench and the second opening. | 01-22-2009 |
20090023284 | Integrated Wafer Processing System for Integration of Patternable Dielectric Materials - The present disclosure relates to an integrated wafer processing apparatus for fabricating semiconductor chips. This integrated wafer processing system combines the lithography patterning steps and irradiation curing steps of the patternable dielectric into one system. The patternable low-k material of the present disclosure also functions as a photoresist, i.e. is a photo-patternable low-k dielectric material. | 01-22-2009 |
20090023285 | METHOD OF FORMING CONTACT OF SEMICONDUCTOR DEVICE - The present invention relates to a method of forming a contact of a semiconductor device. According to a method of forming a contact of a semiconductor device in accordance with an aspect of the present invention, first and second insulating layers are sequentially formed over a semiconductor substrate. A contact hole is formed by sequentially etching the first and second insulating layers. An aperture portion of the contact hole is widened by etching the second insulating layer. A conductive material is gap-filled over an entire surface including the contact hole, thus forming a contact. | 01-22-2009 |
20090023286 | DIELECTRIC INTERCONNECT STRUCTURES AND METHODS FOR FORMING THE SAME - Dielectric interconnect structures and methods for forming the same are provided. Specifically, the present invention provides a dielectric interconnect structure having a noble metal layer (e.g., Ru, Ir, Rh, Pt, RuTa, and alloys of Ru, Ir, Rh, Pt, and RuTa) that is formed directly on a modified dielectric surface. In a typical embodiment, the modified dielectric surface is created by treating an exposed dielectric layer of the interconnect structure with a gaseous ion plasma (e.g., Ar, He, Ne, Xe, N | 01-22-2009 |
20090023287 | INTERCONNECTION PROCESS - An interconnection process is described. A substrate having a conductive region formed therein is provided. A dielectric layer is formed on the substrate. A patterned metal hard mask layer having a trench opening is formed on the dielectric layer. A dielectric hard mask layer is formed conformally on the patterned metal hard mask layer and filled in the trench opening. A photoresist pattern is defined to remove a portion of the dielectric hard mask layer and a portion of the dielectric layer to form a first opening in the dielectric layer. The photoresist pattern is removed. A first etching process is performed using the patterned metal hard mask layer as a mask to form a trench and a second opening extending downward from the first opening in the dielectric layer. The second opening exposes the conductive region. A conductive layer is formed in the trench and the second opening. | 01-22-2009 |
20090035930 | METHOD OF FORMING A WIRE STRUCTURE - In a method of forming a wire structure, first active regions and second active regions are formed on a substrate. Each of the first active regions has a first sidewall of a positive slope and a second sidewall opposed to the first sidewall. The second active regions are arranged along a first direction. An isolation layer is between the first active regions and the second active regions. A first mask is formed on the first active regions, the second active regions and the isolation layer. The first mask has an opening exposing the first sidewall and extending along the first direction. The first active regions, the second active regions and the isolation layer are etched using the first mask to form a groove extending along the first direction and to form a fence having a height substantially higher than a bottom face of the groove. A wire is formed to fill the groove. A contact is formed on the wire. The contact is disposed toward the second active regions from the fence. | 02-05-2009 |
20090035931 | METHOD FOR FORMING VIAS IN A SUBSTRATE - The present invention relates to a method for forming vias in a substrate, comprising the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a photo resist layer on the first surface of the substrate; (c) forming a pattern on the photo resist layer; (d) forming a groove and a pillar in the substrate according to the pattern, wherein the groove surrounds the pillar; (e) forming a polymer in the groove of the substrate; (f) removing the pillar of the substrate to form an accommodating space; (g) forming a conductive metal in the accommodating space; and (h) removing part of the second surface of the substrate to expose the conductive metal and the polymer. As a result, thicker polymer can be formed in the groove, and the thickness of the polymer in the groove is uniform. | 02-05-2009 |
20090035932 | METHOD FOR FORMING VIAS IN A SUBSTRATE - The present invention relates to a method for forming vias in a substrate, including the following steps: (a) providing a substrate having a first surface and a second surface; (b) forming a groove on the substrate; (c) filling the groove with a conductive metal; (d) removing part of the substrate which surrounds the conductive metal, wherein the conductive metal is maintained so as to form an accommodating space between the conductive metal and the substrate; (e) forming an insulating material in the accommodating space; and (f) removing part of the second surface of the substrate to expose the conductive metal and the insulating material. In this way, thicker insulating material can be formed in the accommodating space, and the thickness of the insulating material in the accommodating space is even. | 02-05-2009 |
20090035933 | DENDRITE GROWTH CONTROL CIRCUIT - A circuit is provided which prevents dendrite formation on interconnects during semiconductor device processing due to a dendrite-forming current. The circuit includes a switch located in at least one of the dendrite-forming current paths. The switch is configured to be open or in the “off” state during processing, and is configured to be closed or in the “on” state after processing to allow proper functioning of the semiconductor device. The switch may include an nFET or pFET, depending on the environment in which it is used to control or prevent dendrite formation. The switch may be configured to change to the “closed” state when an input signal is provided during operation of the fabricated semiconductor device. | 02-05-2009 |
20090061615 | METHOD FOR FORMING CONTACT IN SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes providing a substrate, forming an insulation layer over the substrate, forming a photoresist pattern for a contact hole over the insulation layer, wherein the photoresist pattern includes an opening having a critical dimension (CD) greater than a desired contact CD, forming a contact hole by selectively etching the insulation layer using the photoresist pattern, and forming a spacer on a sidewall of the contact hole until a CD of the contact hole whose sidewall is covered by the spacer is reduced to a desired contact CD. | 03-05-2009 |
20090068831 | 3D IC METHOD AND DEVICE - A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface. Alternatively, first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect first and second contact structures and provide electrical access to interconnected first and second contact structure to a surface. Also, a device may be formed in a first substrate, the device being disposed in a device region of the first substrate and having a first contact structure. A via may be etched, or etched and filled, through the device region and into the first substrate before bonding and the first substrate thinned to expose the via, or filled via after bonding. | 03-12-2009 |
20090075470 | Method for Manufacturing Interconnect Structures Incorporating Air-Gap Spacers - Methods for manufacturing air-gap (e.g., side wall air-gap) containing metal/insulator interconnect structures for Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging comprise forming the air-gap spacers by deviating from a conventional dual-damascene etch process in order to avoid damage to the dielectric, and instead utilize intentional and controlled chemical damage of the Si, C, O, H containing dielectric by appropriate strip/ash etch chemistries after the trench etch and/or after via etch. The damaged dielectric layer is left in place after etch and the stack is taken through metallization and chemical mechanical planarization (CMP) processes. Subsequent to this, selective removal of the oxide-like damaged layer takes place by exposure to appropriate chemistries such as dilute HF, leaving behind air-gap spacers. Pinch-off cap deposition ensures integration of the air-gap for narrow air-gaps or perforated caps for wide air-gaps. | 03-19-2009 |
20090081862 | AIR GAP STRUCTURE DESIGN FOR ADVANCED INTEGRATED CIRCUIT TECHNOLOGY - A method for forming air gaps between interconnect structures in semiconductor devices provides a sacrificial layer formed over a dielectric and within openings formed therein. The sacrificial layer is a blanket layer that is converted to a material that is consumable in an etchant composition that the dielectric material and a subsequently formed interconnect material are resistant to. After the interconnect material is deposited a planarized surface including portions of the dielectric material, vertical sections of the converted material and portions of the interconnect material is produced. The etchant composition then removes the converted material thereby forming voids. A capping layer is formed over the structure resulting in air gaps. A sidewall protection layer may be optionally formed between the interconnect structure and the sacrificial material. In some embodiments an ARC layer may be formed over the dielectric and form part of the planar surface. | 03-26-2009 |
20090087978 | INTERCONNECT MANUFACTURING PROCESS - An interconnect process is provided. A substrate is provided. A plurality of gate structures is disposed on the substrate, and doped regions are disposed in the substrate and respectively located between two adjacent gate structure. A liner is conformally formed above the substrate. A dielectric layer is formed above the substrate. A contact opening is formed in the dielectric layer between two neighboring gate structures to expose the liner on the doped region and on a portion of the top surface and a portion of the sidewall of each of the gate structures. A polymer material is deposited on the liner on the portion of the top surface of each of the gate structures and on the doped region. The liner on the doped regions is removed. A conductive layer is filled in the contact opening, which is free of electrical connection to the gate structures. | 04-02-2009 |
20090093112 | METHODS AND APPARATUS OF CREATING AIRGAP IN DIELECTRIC LAYERS FOR THE REDUCTION OF RC DELAY - A method and apparatus for generating air gaps in a dielectric material of an interconnect structure. One embodiment provides a method for forming a semiconductor structure comprising depositing a first dielectric layer on a substrate, forming trenches in the first dielectric layer, filling the trenches with a conductive material, planarizing the conductive material to expose the first dielectric layer, depositing a dielectric barrier film on the conductive material and exposed first dielectric layer, depositing a hard mask layer over the dielectric barrier film, forming a pattern in the dielectric barrier film and the hard mask layer to expose selected regions of the substrate, oxidizing at least a portion of the first dielectric layer in the selected region of the substrate, removing oxidized portion of the first dielectric layer to form reversed trenches around the conductive material, and forming air gaps in the reversed trenches while depositing a second dielectric material in the reversed trenches. | 04-09-2009 |
20090093113 | Electrochemical etching of through silicon vias - A process is disclosed to form through silicon vias in a silicon wafer. The method comprises, forming a dielectric layer on a silicon wafer, forming a masking layer using photolithography, etching the dielectric layer, and electrochemically etching a through silicon via in the silicon wafer. | 04-09-2009 |
20090098725 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device, the method includes forming a metal line over a substrate, the metal line having a stacked structure of a conductive layer and a barrier layer, forming an inter-metal dielectric layer over the barrier layer, etching the inter-metal dielectric layer by using a carbon-rich CF-based gas through a target opening the barrier layer, and forming a contact hole by overetching the barrier layer to a given depth by using a gas containing a smaller amount of carbon than in the etching of the inter-metal dielectric layer. | 04-16-2009 |
20090137111 | METHOD OF FABRICATING METAL INTERCONNECTION AND METHOD OF FABRICATING IMAGE SENSOR USING THE SAME - A method of fabricating a metal interconnection and a method of fabricating image sensor using the same are provided. The method of fabricating a metal interconnection including forming a interlayer dielectric layer on a substrate, forming an interconnection formation region in the interlayer dielectric layer, performing an ultraviolet (UV) treatment on the substrate after the interconnection formation region is formed and forming a metal interconnection in the interconnection formation region. | 05-28-2009 |
20090149017 | METHOD OF CLEANING SEMICONDUCTOR SUBSTRATE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SUBSTRATE PROCESSING APPARATUS FOR USE IN THE SAME - A semiconductor substrate processing apparatus is provided with a cleaning process chamber containing a semiconductor substrate for performing a cleaning process on the semiconductor substrate. Connected to the cleaning process chamber is a cleaning liquid feeding pipe for supplying a cleaning liquid to the semiconductor substrate. A gas dissolving unit is provided in the midpoint of the cleaning liquid feeding pipe for dissolving a prescribed gas in ultrapure water. An inert gas or a reducing gas is dissolved as a prescribed gas in ultrapure water. A control unit is provided having a function of supplying the cleaning liquid with the prescribed gas dissolved therein to the semiconductor substrate subjected to the cleaning process before performing a dry process. Therefore, the surface of the semiconductor substrate is free from stains. Moreover, a metal interconnection does not elude. | 06-11-2009 |
20090155994 | FORMING THIN FILM TRANSISTORS USING ABLATIVE FILMS WITH PRE-PATTERNED CONDUCTORS - An ablative film comprising a substrate; at least one ablative layer that is removable by exposure to radiation; one or more deposited conductors; and an active layer including a semiconductor material surrounded at least partially by a dielectric. | 06-18-2009 |
20090155995 | Self-aligned contact formation utilizing sacrificial polysilicon - In general, in one aspect, a method includes forming a spacer layer over a substrate having patterned stacks formed therein and trenches between the patterned stacks. A sacrificial polysilicon layer is deposited over the substrate to fill the trenches. A patterning layer is deposited over the substrate and patterned to define contact regions over at least a portion of the trenches. The sacrificial polysilicon layer is etched using the patterned patterning layer to form open regions. | 06-18-2009 |
20090170305 | METHOD FOR IMPROVING ELECTROMIGRATION LIFETIME FOR CU INTERCONNECT SYSTEMS - A method for forming a single damascene and/or dual damascene interconnect structure, comprising: performing front end processing, depositing copper, annealing the copper, performing CMP planarization, performing a post copper CMP clean process, performing a BTA rinse, performing IPA drying process, performing doping during thermal ramp up and performing remaining back end processing. | 07-02-2009 |
20090170306 | PROCESS FOR FILLING RECESSED FEATURES IN A DIELECTRIC SUBSTRATE - A process for filling recessed features of a dielectric substrate for a semiconductor device, comprises the steps (a) providing a dielectric substrate having a recessed feature in a surface thereof, wherein the smallest dimension (width) across said feature is less than ≦200 nm, a conductive layer being present on at least a portion of said surface, (b) filling said recessed feature with a conductive material, and (c) prior to filling said recessed feature with said conductive material, treating said surface with an accelerator. | 07-02-2009 |
20090186476 | STRUCTURE AND METHOD FOR IMPROVED SRAM INTERCONNECT - A method of forming an improved static random access memory (SRAM) interconnect structure is provided. The method includes forming a sidewall spacer around a periphery of a patterned poly-silicon layer formed over a silicon layer of a semiconductor substrate; removing the patterned poly-silicon layer for exposing a portion of a cap layer; etching the exposed portion of the cap layer for revealing a portion of the silicon layer; etching the potion of the silicon layer, in which a portion of said silicon layer connects at least a portion of pull-down device of said SRAM to at least a portion of pull-up device of said SRAM; forming a gate oxide; and forming a gate conductor over the gate oxide. An interconnect structure is also provided. | 07-23-2009 |
20090186477 | METHOD OF FORMING METAL WIRING OF NONVOLATILE MEMORY DEVICE - A method of forming metal wirings of a nonvolatile memory device include forming a first insulating layer over a semiconductor substrate including a first junction area and a second junction area, forming first and second contact holes through which the first and second junction areas are respectively exposed in the first insulating layer, forming first and second contact plugs within the first and second contact holes, etching a part of the second contact plug, thus forming a recess, forming a second insulating layer to fill the recess, forming a third insulating layer over the semiconductor substrate including the first and second insulating layers, forming a first trench through which the first contact plug is exposed a second trench through which the second contact plug is exposed by etching the third insulating layer, and forming first and second metal wirings within the first and second trenches, respectively. | 07-23-2009 |
20090233437 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURED THEREBY - A method of manufacturing a semiconductor device and a semiconductor device manufactured thereby are provided. The method includes forming a molding layer on a substrate, forming support patterns spaced apart from each other on the molding layer, forming storage node electrodes penetrating the molding layer on sidewalls of the support patterns and wherein the storage node electrodes are supported by the support patterns. The method further includes removing the molding layer, forming a dielectric layer on the storage node electrodes, and forming a plate electrode on the dielectric layer. | 09-17-2009 |
20090239372 | Seed Layers for Electroplated Interconnects - One embodiment of the present invention is a method for depositing two or more seed layers for electroplating metallic interconnects over a substrate, the substrate having a patterned insulating layer which includes at least one opening and a field surrounding the at least one opening, the at least one opening having top corners, sidewalls, and bottom, the field and the at least one opening being ready for depositing one or more seed layers, and the method includes: (a) depositing a continuous seed layer over the sidewalls and bottom of the at least one opening using a first set of deposition parameters; and (b) depositing a second seed layer over the continuous seed layer using a second set of deposition parameters, wherein (i) the second set of deposition parameters includes at least one deposition parameter which is different from any of the parameters in the first set of deposition parameters, or the second set of deposition parameters includes at least one deposition parameter whose value is different in the two sets of deposition parameters, (ii) the continuous and second seed layers being sufficiently thick over the field to enable uniform electroplating across the substrate, and (iii) after depositing the seed layers, there is sufficient room for electroplating inside the at least one opening. | 09-24-2009 |
20090239373 | CHEMICAL MECHANICAL POLISHING METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A chemical mechanical polishing method comprises polishing an organic film using a slurry including polymer particles having a surface functional group and a water-soluble polymer. | 09-24-2009 |
20090258487 | Method for Improving the Reliability of Low-k Dielectric Materials - A method for forming an integrated circuit structure includes providing a semiconductor substrate; forming a low-k dielectric layer over the semiconductor substrate; generating hydrogen radicals using a remote plasma method; performing a first hydrogen radical treatment to the low-k dielectric layer using the hydrogen radicals; forming an opening in the low-k dielectric layer; filling the opening with a conductive material; and performing a planarization to remove excess conductive material on the low-k dielectric layer. | 10-15-2009 |
20090269920 | METHOD OF FORMING INTERCONNECTION LINE AND METHOD OF MANUFACTURING THIN FILM TRANSISTOR SUBSTRATE - A method of forming an interconnection line and a method of manufacturing a thin film transistor substrate are provided in accordance with one or more embodiments of the present invention. The method of forming an interconnection line in accordance with one or more embodiments of the present invention includes preparing a substrate, forming a lower organic layer and an upper organic layer on the substrate in lamination, forming trenches in parts of the upper organic layer and the lower organic layer, forming a lower interconnection layer in the trenches formed in parts of the lower organic layer, removing the upper organic layer, and filling the trenches formed in parts of the lower organic layer with an upper interconnection layer. | 10-29-2009 |
20090275193 | METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light. | 11-05-2009 |
20090280636 | METHODS OF FABRICATING INTERCONNECT STRUCTURES CONTAINING VARIOUS CAPPING MATERIALS FOR ELECTRICAL FUSE AND OTHER RELATED APPLICATIONS - Methods are provided for fabricating interconnect structures containing various capping materials for electrical fuses and other related applications. The method includes forming a first interconnect structure having a first interfacial structure and forming a second interconnect structure adjacent to the first structure. The second interconnect structure is formed with a second interfacial structure different from the first interfacial structure of the first interconnect structure. | 11-12-2009 |
20090280637 | Method of manufacturing semiconductor device including ultra low dielectric constant layer - Provided is a method of manufacturing a semiconductor device. The method employs multi-step removal on a plurality of different porogens included in a low dielectric layer both before and after metal lines are formed, thereby facilitating formation of an ultra low dielectric constant layer which is used as an insulation layer between metal lines of a semiconductor device. The method may include forming an interlayer dielectric layer on a substrate, forming a plurality of porogens in the interlayer dielectric layer, removing a portion of the plurality of porogens in the interlayer dielectric layer to form a plurality of first pores in the interlayer dielectric layer, forming a wiring pattern where the plurality of first pores are formed, and removing the remaining porogens of the plurality of porogens to form a plurality of second pores in the interlayer dielectric layer. | 11-12-2009 |
20090286391 | SEMICONDUCTOR DEVICE FABRICATION METHOD - According to one aspect of the invention, there is provided a qsemiconductor device fabrication method having: | 11-19-2009 |
20090298279 | METHOD FOR REDUCING METAL IRREGULARITIES IN ADVANCED METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES - In a manufacturing sequence for forming metallization levels of semiconductor devices, out-gassing of volatile components after an etch process may be initiated immediately after the etch process, thereby reducing the probability of creating contaminants in other substrates and transport carriers during transport activities. Consequently, the defect rate of deposition-related irregularities in the metallization level may be reduced. | 12-03-2009 |
20090305495 | SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING THE SAME - A semiconductor device may include plugs disposed in a zigzag pattern, interconnections electrically connected to the plugs and a protection pattern which is interposed between the plugs and the interconnections to selectively expose the plugs. The interconnections may include a connection portion which is in contact with plugs selectively exposed by the protection pattern. A method of manufacturing a semiconductor device includes, after forming a molding pattern and a mask pattern, selectively etching a protection layer using the mask pattern to form a protection pattern exposing a plug. | 12-10-2009 |
20090305496 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A post-CMP cleaning process of a copper layer is to be performed as follows. An alkaline aqueous solution, a polycarboxylic acid, BTA, and an alkaline aqueous solution are sequentially brought into contact with a primary surface of a silicon substrate over which the copper layer is provided. | 12-10-2009 |
20090317970 | METHOD FOR FORMING AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE - A method for forming an on-chip high frequency electro-static discharge device on an integrated circuit is described. In one embodiment of the method, a capped first dielectric layer with more than one electrode formed therein is provided. A second dielectric layer is deposited over the capped first dielectric layer. A first hard mask dielectric layer is deposited over the second dielectric layer. A cavity trench is formed through the first hard mask dielectric layer and the second dielectric layer to the first dielectric layer, wherein the cavity trench is formed in the first dielectric layer between two adjacent electrodes. At least one via is formed through the second dielectric layer about the cavity trench. A metal trench is formed around each of the at least one via. A release opening is formed over the cavity trench. A third dielectric layer is deposited over the second dielectric layer, wherein the third dielectric layer hermetically seals the release opening to provide electro-static discharge protection. | 12-24-2009 |
20090317971 | RESTORING LOW DIELECTRIC CONSTANT FILM PROPERTIES - A method for restoring the dielectric constant of a low dielectric constant film is described. A porous dielectric layer having a plurality of pores is formed on a substrate. The plurality of pores is then filled with an additive to provide a plugged porous dielectric layer. Finally, the additive is removed from the plurality of pores. | 12-24-2009 |
20090325376 | Semiconductor Device and Manufacturing Method Thereof - An island-like interlayer insulating film is formed selectively in a region where a source interconnection and a gate interconnection intersect. For example, by use of ink jet method, a solution containing an insulating material is dropped on a region where the gate interconnection and the source interconnection intersect or a region where a holding capacitor is formed, that enable to reduce a photolithography process and to reduce the number of masks that are used in a TFT | 12-31-2009 |
20100022082 | Method for making a nanotube-based electrical connection between two facing surfaces - Facing surfaces made from semiconductor material are formed and then transformed into a porous semiconductor. The porous semiconductor is then transformed into a porous metallic material by silicidation. The porous metallic material then acts as catalyst for growth of the carbon nanotubes which electrically connect the facing surfaces made from porous metallic material. | 01-28-2010 |
20100022083 | CARBON NANOTUBE INTERCONNECT STRUCTURES - A method including forming an interconnect of single-walled carbon nanotubes on a sacrificial substrate; transferring the interconnect from the sacrificial substrate to a circuit substrate; and coupling the interconnect to a contact point on the circuit substrate. A method including forming a nanotube bundle on a circuit substrate between a first contact point and a second contact point, the nanotube defining a lumen therethrough; filling a portion of a length of the lumen of the nanotube bundle with an electrically conductive material; and coupling the electrically conductive material to the second contact point. A system including a computing device comprising a microprocessor, the microprocessor coupled to a printed circuit board, the microprocessor including a substrate having a plurality of circuit devices with electrical connections made to the plurality of circuit devices through interconnect structures including carbon nanotube bundles. | 01-28-2010 |
20100041227 | METHODS FOR INCORPORATING HIGH DIELECTRIC MATERIALS FOR ENHANCED SRAM OPERATION AND STRUCTURES PRODUCED THEREBY - Methods for fabricating a hybrid interconnect structure that possesses a higher interconnect capacitance in one set of regions than in other regions on the same microelectronic chip. Several methods to fabricate such a structure are provided. Circuit implementations of such hybrid interconnect structures are described that enable increased static noise margin and reduce the leakage in SRAM cells and common power supply voltages for SRAM and logic in such a chip. Methods that enable combining these circuit benefits with higher interconnect performance speed and superior mechanical robustness in such chips are also taught. | 02-18-2010 |
20100068879 | CONTACT FOR MEMORY CELL - A contact for memory cells and integrated circuits having a conductive layer supported by the sidewall of a dielectric mesa, memory cells incorporating such a contact, and methods of forming such structures. | 03-18-2010 |
20100081270 | Method and Apparatus for Strapping Two Polysilicon Lines in a Semiconductor Integrated Circuit Device - A method and apparatus for partially strapping two polysilicon lines, each having a first end and second end, uses a metal line having a plurality of spaced apart metal segments with each metal segment partially strapping a different portion of a polysilicon line. The metal segments are arranged from the first end to the second end with the signals propagating from the second end to the first end. Where two metal segments are used, the segments have lengths of | 04-01-2010 |
20100093168 | AIR GAP INTERCONNECTS USING CARBON-BASED FILMS - A method of forming an interconnect structure comprising: forming a sacrificial inter-metal dielectric (IMD) layer over a substrate, wherein the sacrificial IMD layer comprising a carbon-based film, such as amorphous carbon, advanced patterning films, porous carbon, or any combination thereof; forming a plurality of metal interconnect lines within the sacrificial IMD layer; removing the sacrificial IMD layer, with an oxygen based reactive process; and depositing a non-conformal dielectric layer to form air gaps between the plurality of metal interconnect lines. The metal interconnect lines may comprise copper, aluminum, tantalum, tungsten, titanium, tantalum nitride, titanium nitride, tungsten nitride, or any combination thereof. Carbon-based films and patterned photoresist layers may be simultaneously removed with the same reactive process. Highly reactive hydrogen radicals processes may be used to remove the carbon-based film and simultaneously pre-clean the metal interconnect lines prior to the deposition of a conformal metal barrier liner. | 04-15-2010 |
20100120241 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a semiconductor device including an integrated circuit having a plurality of semiconductor elements which are formed on a semiconductor substrate and electrically connected through a line, the method including: forming a conducting path to be connected to the semiconductor elements in a similar manner as the line is to be connected thereto; etching the semiconductor elements in a state where the semiconductor elements are electrically connected via the conducting path; and forming the line to be connected to the semiconductor elements in a similar manner as the conducting path is connected thereto. | 05-13-2010 |
20100144137 | METHOD OF INTERCONNECTING CHIPS USING CAPILLARY MOTION - A method of interconnecting semiconductor devices by using capillary motion, thereby simplifying fabricating operations, reducing fabricating costs, and simultaneously filling of through-silicon-vias (TSVs) and interconnecting semiconductor devices. The method includes preparing a first semiconductor device in which first TSVs are formed, positioning solder balls respectively on the first TSVs, performing a back-lap operation on the first semiconductor device, positioning a second semiconductor device, in which second TSVs are formed, above the first semiconductor device on which the solder balls are positioned, and performing a reflow operation such that the solder balls fill the first and second TSVs due to capillary motion. | 06-10-2010 |
20100173490 | HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION PROCESS - A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition. | 07-08-2010 |
20100197132 | Barrier-Metal-Free Copper Damascene Technology Using Atomic Hydrogen Enhanced Reflow - A method for forming conductive contacts and interconnects in a semiconductor structure, and the resulting conductive components are provided. In particular, the method is used to fabricate single or dual damascene copper contacts and interconnects in integrated circuits such as memory devices and microprocessor. | 08-05-2010 |
20100203722 | Semiconductor Device Having a Second Level of Metallization Formed over a First Level with Minimal Damage to the First Level and Method - A method for processing a semiconductor structure includes the steps of capping a top surface of the semiconductor structure that defines the metallization layer with a thin stop layer, forming a dielectric layer over the thin stop layer, wherein the dielectric layer defines at least one area where the thin stop layer is exposed, and removing the exposed thin stop layer to expose a top surface of the metallization layer using etchant gases substantially free from oxygen, so that the metallization layer is substantially free of damage. | 08-12-2010 |
20100233875 | CONTACT FORMATION - The present disclosure includes various method of contact embodiments. One such method embodiment includes creating a trench in an insulator stack material of a particular thickness and having a portion of the trench positioned between two of a number of gates. This method includes depositing a filler material in the trench and etching the filler material to a particular depth that is less than the particular thickness of the insulator stack material. This method also includes depositing a spacer material to at least one side surface of the trench to the particular depth of the filler material and depositing a conductive material into the trench over the filler material. | 09-16-2010 |
20100248471 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - Provided is a method for fabricating a semiconductor device, including forming an interconnect structure including first and second interconnects and an insulating material between the first and second interconnects, forming a first mask layer and a second mask layer having a plurality of micropores sequentially on the interconnect structure, coalescing the plurality of micropores in the second mask layer with each other and forming a plurality of first microholes in the second mask layer, forming a plurality of second microholes in the first mask layer using the plurality of first microholes, and removing the insulating material using the first mask layer with the plurality of second microholes as an etch mask so as to form an air-gap between the first and second interconnects. | 09-30-2010 |
20100304560 | SEMICONDUCTOR PROCESSING METHODS - The invention includes methods of forming electrically conductive material between line constructions associated with a peripheral region or a pitch region of a semiconductor substrate. The electrically conductive material can be incorporated into an electrically-grounded shield, and/or can be configured to create a magnetic field bias. Also, the conductive material can have electrically isolated segments that are utilized as electrical jumpers for connecting circuit elements. The invention also includes semiconductor constructions comprising the electrically conductive material between line constructions associated with one or both of the pitch region and the peripheral region. | 12-02-2010 |
20100323514 | RESTORATION METHOD USING METAL FOR BETTER CD CONTROLLABILITY AND CU FILING - Methods of making interconnect structures are provided. In one aspect of the innovation, when forming a trench or via in a dielectric layer, the sidewall surface of another via and/or trench is covered with a metal oxide layer. The metal oxide layer can prevent and/or mitigate surface erosion of the sidewall surface. As a result, the methods can improve the controllability of critical dimensions of the via and trench. | 12-23-2010 |
20100330799 | SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCING THE SAME - Improved control over formation of low k air gaps in interlayer insulating films is achieved by plasma pretreatment of the region of the insulating film to be removed. The intended air gap region is exposed through a mask while the film region to be preserved is shielded by the mask. The intended air gap region is then exposed to a plasma so as to render it more susceptible to removal in a subsequent treatment. One or more Cu interconnects are embedded in both regions of the insulator film. The insulator film in the intended air gap region is then selectively removed to form air gaps adjacent a Cu interconnect in that region. | 12-30-2010 |
20110008956 | SELF-ASSEMBLY PATTERN FOR SEMICONDUCTOR INTEGRATED CIRCUIT - A method of fabricating a semiconductor device is provided which includes providing a substrate. A material layer is formed over the substrate. A polymer layer is formed over the material layer. A nano-sized feature is self-assembled using a portion of the polymer layer. The substrate is patterned using the nano-sized feature. | 01-13-2011 |
20110014786 | METHOD, SYSTEM, AND PROGRAM PRODUCT FOR ROUTING AN INTEGRATED CIRCUIT TO BE MANUFACTURED BY DOUBLED PATTERNING - Disclosed are a method, apparatus, and program product for routing an electronic design using double patenting that is correct by construction. The layout that has been routed will by construction be designed to allow successful manufacturing with double patenting, since the router will not allow a routing configuration in the layout that cannot be successfully manufactured with double patterning. | 01-20-2011 |
20110034023 | SILICON CARBIDE FILM FOR INTEGRATED CIRCUIT FABRICATION - A silicon carbide (SiC) film for use in backend processing of integrated circuit manufacturing, is generated by including hydrogen in the reaction gas mixture. This SiC containing film is suitable for integration into etch stop layers, dielectric cap layers and hardmask layers in interconnects of integrated circuits. | 02-10-2011 |
20110034024 | METHOD AND ALGORITHM FOR RANDOM HALF PITCHED INTERCONNECT LAYOUT WITH CONSTANT SPACING - An embodiment of a system and method produces a random half pitched interconnect layout. A first normal-pitch mask and a second normal-pitch mask are created from a metallization layout having random metal shapes. The lines and spaces of the first mask are printed at normal pitch and then the lines are shrunk to half pitch on mask material. First spacers are used to generate a half pitch dimension along the outside of the lines of the first mask. The mask material outside of the first spacer pattern is partially removed. The spacers are removed and the process is repeated with the second mask. The mask material remains at the locations of first set of spacers and/or the second set of spacers to create a half pitch interconnect mask with constant spaces. | 02-10-2011 |
20110076845 | Method Of Forming An Interconnect Of A Semiconductor Device - A method for fabricating an integrated circuit device is provided. In one embodiment, the method includes providing a substrate. A first photolithography process is performed to define a first pattern on the substrate. The first pattern includes a first trench segment. A second photolithography process is performed which defines a second pattern on the substrate. The second pattern includes a second trench segment. The second trench segment includes an overlap area with the first trench segment. The embodiment of the method further includes etching the substrate according the first and second patterns; the etching includes forming a via hole defined by the overlap area. The first trench segment, second trench segment, and via hole may be used to form a dual damascene interconnect structure. | 03-31-2011 |
20110086506 | METHOD FOR FABRICATING DAMASCENE INTERCONNECT STRUCTURE HAVING AIR GAPS BETWEEN METAL LINES - An exemplary method for fabricating a damascene interconnect structure includes the following. First, providing a substrate. Second, depositing a multilayer dielectric film on the substrate. Third, forming a patterned photoresist on the multilayer dielectric film. Fourth, etching the multilayer dielectric film to form a plurality of trenches, a portion of each of the trenches having an enlarged width at each of sidewalls thereof. Fifth, filling the trenches with conductive metal to form conductive lines such that air is trapped in extremities of the enlarged width portions of the trenches. | 04-14-2011 |
20110097894 | Method of Forming a Topside Contact to a Backside Terminal of a Semiconductor Device - A process for forming a vertically conducting semiconductor device includes providing a semiconductor substrate having a topside surface and a backside surface. The semiconductor substrate serves as a terminal of the vertically conducting device for biasing the vertically conducting device during operation. The process also includes forming an epitaxial layer extending over the topside surface of the semiconductor substrate but terminating prior to reaching an edge of the semiconductor substrate so as to form a recessed region along a periphery of the semiconductor substrate. The method also includes forming an interconnect layer extending into the recessed region but terminating prior to reaching an edge of the semiconductor substrate. The interconnect layer electrically contacts the topside surface of the semiconductor substrate in the recessed region to thereby provide a topside contact to the semiconductor substrate. | 04-28-2011 |
20110111588 | WIRING FORMING METHOD - Size reduction and high integration of each of the laminated substrates are achieved, while forming an excellent wiring which electrically connects the substrates to each other. A conductive ink, i.e., an ink, containing a conductive material is used, and in a state where a voltage is applied between a print head and a substrate unit, an ink droplet of the conductive ink is discharged from the print head, while relatively shifting the substrate unit and the print head substantially parallel to at least the upper surface of the substrate. Thus, a conductive layer which electrically connects electrodes to each other between the substrates is formed. | 05-12-2011 |
20110111589 | BARRIER-METAL-FREE COPPER CAMASCENCE TECHNOLOGY USING ATOMIC HYDROGEN ENHANCED REFLOW - A method for forming conductive contacts and interconnects in a semiconductor structure, and the resulting conductive components are provided. In particular, the method is used to fabricate single or dual damascene copper contacts and interconnects in integrated circuits such as memory devices and microprocessor. | 05-12-2011 |
20110136337 | Method for Manufacturing Semiconductor Device - A method for manufacturing a semiconductor device. The method includes forming an energy cured resin layer on a semiconductor substrate having an electrode pad and a passivation film; fusing the resin layer so that fusion of a surface section is progressed more than of a central section by a first energy supply processing; forming a resin boss by curing and shrinking the resin layer by a second energy supply processing; and forming an electrical conducting layer which is electrically connected to the electrode pad and passes over the resin boss. | 06-09-2011 |
20110151658 | Methods of Forming a Semiconductor Device Having a Contact Structure - A method of forming a semiconductor device having a contact structure includes forming an insulating layer on a semiconductor substrate, and selectively implanting impurity ions into a predetermined region of the insulating layer to generate lattice defects in the predetermined region of the insulating layer. A thermal treatment, such as quenching the insulating layer at a temperature change rate of at least −20° C./minute, is performed on the insulating layer having the lattice defects to accelerate generation of the lattice defects in the predetermined region such that a conductive region results from the generated lattice defects to provide current paths in the predetermined region. | 06-23-2011 |
20110159683 | METHOD OF FORMING A HIGH DENSITY STRUCTURE - The invention relates to a method of forming a high density structure comprising the steps of providing a substrate ( | 06-30-2011 |
20110217838 | METHOD FOR FORMING INTERCONNECT STRUCTURE HAVING AIRGAP - A method for forming an interconnect structure with airgaps, includes: providing a structure having a trench formed on a substrate; depositing a spacer oxide layer on sidewalls of the trench as sidewall spacers by plasma enhanced atomic layer deposition; filling the trench having the sidewall spacers with copper; removing the sidewall spacers to form an airgap structure; and encapsulating the airgap structure, wherein airgaps are formed between the filled copper and the sidewalls of the trench. | 09-08-2011 |
20110217839 | Interconnect arrangement and associated production methods - An interconnect arrangement and fabrication method are described. The interconnect arrangement includes an electrically conductive mount substrate, a dielectric layer formed on the mount substrate, and an electrically conductive interconnect formed on the dielectric layer. At least a portion of the dielectric layer under the interconnect contains a cavity. To fabricate the interconnect arrangement, a sacrificial layer is formed on the mount substrate and the interconnect layer is formed on the sacrificial layer. The interconnect layer and the sacrificial layer are structured to produce a structured interconnect on the structured sacrificial layer. A porous dielectric layer is formed on a surface of the mount substrate and of the structured interconnect as well as the sacrificial layer. The sacrificial layer is then removed to form the cavity under the interconnect. | 09-08-2011 |
20110223759 | Low-k Cu Barriers in Damascene Interconnect Structures - In the formation of an interconnect structure, a metal feature is formed in a dielectric layer. An etch stop layer (ESL) is formed over the metal feature and the dielectric layer using a precursor and a carbon-source gas including carbon as precursors. The carbon-source gas is free from carbon dioxide (CO | 09-15-2011 |
20110230045 | METHOD OF MANUFACTURNING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device capable of improving a margin of a fabrication process of the semiconductor device, suppressing defect occurrence, and reducing a minimum design rule of a fine pattern is provided. The method of manufacturing a semiconductor device includes forming an input/output (I/O) pad and a metal interconnection, each of the I/O pad and the interconnection including a plurality of line patterns, the plurality of line patterns having the same line widths as each other and being separated by the same distance. | 09-22-2011 |
20110275213 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a plurality of first interconnection layers which are provided in an insulating layer and formed in a pattern having a width and space smaller than a resolution limit of an exposure technique, and a second interconnection layer which is provided between the first interconnection layers in the insulating layer and has a width larger than that of a first interconnection layer. A space between the second interconnection layer and each of first interconnection layers adjacent to both sides of the second interconnection layer equals the space between the first interconnection layers. | 11-10-2011 |
20110281431 | METHOD OF PATTERNING THIN METAL FILMS - A Cu interconnect is formed with improved directionality and smoothness. Embodiments include wet etching Cu while applying a pulsing electric current. An embodiment includes forming a Cu layer, and patterning the Cu layer by exposing it to a wet etching solution which includes a passivating surface active agent while simultaneously applying an electric current. The etching solution may be a mild acid. A UV light may be applied simultaneously with the electric current. The electric current may be pulsed with a cycle frequency between 50 kHz and 500 kHz. | 11-17-2011 |
20110294288 | METHOD OF FABRICATING METAL INTERCONNECTION AND METHOD OF FABRICATING IMAGE SENSOR USING THE SAME - A method of fabricating a metal interconnection and a method of fabricating image sensor using the same are provided. The method of fabricating a metal interconnection including forming a interlayer dielectric layer on a substrate, forming an interconnection formation region in the interlayer dielectric layer, performing an ultraviolet (UV) treatment on the substrate after the interconnection formation region is formed and forming a metal interconnection in the interconnection formation region. | 12-01-2011 |
20110306199 | METHOD FOR MANUFACTURING NONVOLATILE MEMORY DEVICE - According to one embodiment, a method is disclosed for manufacturing a nonvolatile memory device. The nonvolatile memory device includes a memory cell connected to a first interconnect and a second interconnect. The method can include forming a first electrode film on the first interconnect. The method can include forming a layer including a plurality of carbon nanotubes dispersed inside an insulator on the first electrode film. At least one carbon nanotube of the plurality of carbon nanotubes is exposed from a surface of the insulator. The method can include forming a second electrode film on the layer. In addition, the method can include forming a second interconnect on the second electrode film. | 12-15-2011 |
20110306200 | METHODS FOR FORMING INTERCONNECT STRUCTURES - Methods for forming interconnect structures are provided herein. In some embodiments, a method for forming an interconnect on a substrate may include depositing a material atop an upper surface of the substrate and atop one or more surfaces of a feature disposed in the substrate by a first deposition process that deposits the material at a faster rate on the upper surface than on a bottom surface of the feature; depositing the material atop the upper surface of the substrate and atop one or more surfaces of the feature by a second deposition process that deposits the material at a greater rate on the bottom surface of the feature than on the upper surface of the substrate; and heating the deposited material to draw the deposited material towards the bottom surface of the feature to at least partially fill the feature with the deposited material. | 12-15-2011 |
20120021600 | METHOD OF FABRICATING FILM CIRCUIT SUBSTRATE AND METHOD OF FABRICATING CHIP PACKAGE INCLUDING THE SAME - A method of fabricating a film circuit substrate and a method of fabricating a chip package. The method of fabricating a film circuit substrate can include providing a base film including a chip packaging area to package a chip and a separation area to separate the two chip packaging areas from each other, the separation area including a cut area and an uncut area; forming a reserve interconnection pattern having a first height on the base film; and forming an interconnection pattern having a second height that is lower than the first height on the out area by selectively etching the reserve interconnection pattern of the cut area. | 01-26-2012 |
20120028457 | Metal Layer End-Cut Flow - A method of patterning a metal layer is disclosed. The method includes providing a substrate and forming a material layer over the substrate. The method includes forming a second material layer over the first material layer. The method includes performing a first patterning process to the second material layer to form a trench in the second material layer. The first patterning process defines a width size of the trench, the width size being measured in a first direction. The method includes performing a second patterning process to the trench to transform the trench. The second patterning process defines a length size of the transformed trench. The length size is measured in a second direction different from the first direction. The method also includes filling the transformed trench with a conductive material. | 02-02-2012 |
20120184097 | Reduced Number of Masks for IC Device with Stacked Contact Levels - A three-dimensional stacked IC device has a stack of contact levels at an interconnect region. According to some examples of the present invention, it only requires a set of N etch masks to create up to and including 2N levels of interconnect contact regions at the stack of contact levels. According to some examples, 2 | 07-19-2012 |
20120190187 | PAD BONDING EMPLOYING A SELF-ALIGNED PLATED LINER FOR ADHESION ENHANCEMENT - Two substrates are brought together and placed in a plating bath. In one embodiment, a conductive material is plated in microscopic cavities present at the interface between a first metal pad and a second metal pad to form at least one interfacial plated metal liner portion that adheres to a surface of the first metal pad and a surface of the second metal pad. In another embodiment, at least one metal pad is recessed relative to a dielectric surface before being brought together. The two substrates are placed in a plating bath and a conductive material is plated in the cavity between the first metal pad and the second metal pad to form a contiguous plated metal liner layer that adheres to a surface of the first metal pad and a surface of the second metal pad. | 07-26-2012 |
20120252204 | PATTERNABLE LOW-K DIELECTRIC INTERCONNECT STRUCTURE WITH A GRADED CAP LAYER AND METHOD OF FABRICATION - An interconnect structure is provided that includes at least one patterned and cured low-k material located on a surface of a patterned graded cap layer. The at least one cured and patterned low-k material and the patterned graded cap layer each have conductively filled regions embedded therein. The patterned and cured low-k material is a cured product of a functionalized polymer, copolymer, or a blend including at least two of any combination of polymers and/or copolymers having one or more acid-sensitive imageable groups, and the graded cap layer includes a lower region that functions as a barrier region and an upper region that has antireflective properties of a permanent antireflective coating. | 10-04-2012 |
20120264287 | METHOD FOR FORMING AN INTERCONNECT STRUCTURE - A method for forming an interconnect structure includes providing a semiconductor substrate having a barrier layer, a low dielectric constant (Low K) inter-dielectric layer and a cap dielectric layer sequentially formed thereon; etching the cap dielectric layer and the Low K inter-dielectric layer sequentially until the barrier layer is exposed and a groove is formed; removing the cap dielectric layer until the Low K inter-dielectric layer is exposed; and doping a carbon element into the Low K inter-dielectric layer. The advantages of the method includes a decrease of the dielectric constant of the Low K inter-dielectric layer, thus, reduces the resistive-capacitive (RC) delay of interconnect layers of a semiconductor device and improve its operating speed and performance. | 10-18-2012 |
20120276734 | METHOD OF MANUFACTURING AN OPTO-ELECTRIC DEVICE - A method of manufacturing an opto-electric device is disclosed, comprising the steps of providing a substrate ( | 11-01-2012 |
20120329266 | LAYOUT METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A plurality of gate electrode patterns to be laid out in parallel are alternately set as first patterns to be formed in a first exposure step of double patterning and as second patterns to be formed in a second exposure step. Subsequently, a circuit that includes transistor pairs each formed by connecting one of the first patterns and one of the second patterns in parallel is laid out. This reduces the risk of variations in characteristics of transistors caused by double patterning. | 12-27-2012 |
20130012016 | ENHANCING METAL/LOW-K INTERCONNECT RELIABILITY USING A PROTECTION LAYER - A protection layer is coated or otherwise formed over the interconnect structure. The interconnect structure includes a metal line (such as top and bottom metal layers connected by a metal via) and a low-K material. The protection layer includes a vertically aligned dielectric or other material dispersed with carbon nanotubes. The protection layer could include one or multiple layers of carbon nanotubes, and the carbon nanotubes could have any suitable dispersion, alignment, and pattern in each layer of the protection layer. Among other things, the carbon nanotubes help to reduce or prevent damage to the interconnect structure, such as by reducing or preventing the collapse of the low-K material or delamination between the metal line and the low-K material. | 01-10-2013 |
20130065389 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a first interconnection and a second interconnection above a semiconductor substrate, forming a first sidewall insulating film on a side wall of the first interconnection, and a second sidewall insulating film on a side wall of the second interconnection, forming a conductive film above the semiconductor substrate with the first interconnection, the first sidewall insulating film, the second interconnection and the second sidewall insulating film formed on, and selectively removing the conductive film above the first interconnection and the second interconnection to form in a region between the first interconnection and the second interconnection a third interconnection formed of the conductive film and spaced from the first interconnection and the second interconnection by the first sidewall insulating film and the second sidewall insulating film. | 03-14-2013 |
20130095650 | System And Method For Constructing Waffle Transistors - Waffle transistors are used within an integrated circuit when a transistor must carry an amount of current greater than the amount of current carried by a typical transistor in the integrated circuit. In a waffle transistor a set of source areas and drain areas are arranged in a checkerboard pattern. The source areas must all be connected together and the drain areas must all be connected together. To efficiently connect the source (or drain) areas together, a serpentine metal interconnect pattern is used. The serpentine pattern reduces the amount of metal required outside of the array. The serpentine pattern may be improved with offset contacts in the source and drain areas that cause the serpentine metal interconnects to be straighter. | 04-18-2013 |
20130164931 | Metal Structure for Memory Device - A semiconductor device is provided that includes a substrate, a static random access memory (SRAM) unit cell formed in the substrate, a first metal layer formed over the substrate, the first metal layer providing local interconnection to the SRAM unit cell, a second metal layer formed over the first metal layer, the second metal layer including: a bit line and a complementary bit line each having a first thickness and a Vcc line disposed between the bit line and the complementary bit line, and a third metal layer formed over the second metal layer, the third metal layer including a word line having a second thickness greater than the first thickness. | 06-27-2013 |
20130210223 | METHODS OF FORMING INTEGRATED CIRCUIT DEVICES USING MODIFIED RECTANGULAR MASK PATTERNS TO INCREASE RELIABILITY OF CONTACTS TO ELECTRICALLY CONDUCTIVE LINES - Methods of forming integrated circuit devices include forming first and second electrically conductive lines at side-by-side locations on an integrated circuit substrate. Steps are performed to selectively etch each of the first and second electrically conductive lines into a respective pair of interconnects having facing ends that are separated from each other. This selective etching step is performed using a photolithography mask having a modified-rectangular mask pattern thereon, which is configured to define a shape of the facing ends of each of the pair of interconnects. | 08-15-2013 |
20130237050 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method of manufacturing a semiconductor device, includes forming first layer on first and second regions in substrate, first layer having first width in first region and having larger dimension than first width in second region, forming first sidewall on first layer, forming second layer covering first sidewall in the second region and forming third layer having second width smaller than first width on the side face of first sidewall having second width after removing first layer, forming second and third sidewalls having second width so that second and third sidewalls is adjacent to first sidewall across third layer by second width in first region and across second and third layers by second interval larger than second width in the second region. | 09-12-2013 |
20130273732 | METHOD OF AND APPARATUS FOR ACTIVE ENERGY ASSIST BAKING - An Active Energy Assist (AEA) baking chamber includes an AEA light source assembly and a heater pedestal. The AEA baking chamber further includes a controller for controlling a power input to the AEA light source assembly and a power input to the heater pedestal. A method of forming interconnects on a substrate includes etching a substrate and wet cleaning the etched substrate. The method further includes active energy assist (AEA) baking the substrate after the wet-cleaning. The AEA baking includes placing the substrate on a heater pedestal in an AEA chamber, exposing the substrate to light having a wavelength equal to or greater than 400 nm, wherein said light is emitted by a light source and controlling the light source and the heater pedestal using a controller. | 10-17-2013 |
20130280905 | SOFTWARE AND METHOD FOR VIA SPACING IN A SEMICONDUCTOR DEVICE - A computer-readable software product is provided for executing a method of determining the location of a plurality of power rail vias in a semiconductor device. The semiconductor device includes an active region and a power rail. Locations of a first via and a second via are assigned along the power rail. The spacing between the location of the first via and the location of the second via is a minimum spacing allowable. The spacing between the location of the second via and the locations of structures in the active region which may electrically interfere with the second via is determined. The location of the second via is changed in response to the spacing between the location of the second via and the location of one of the structures in the active region being less than a predetermined distance. | 10-24-2013 |
20130295763 | LOW TEMPERATURE THIN WAFER BACKSIDE VACUUM PROCESS WITH BACKGRINDING TAPE - Vacuum processing, such as a backside metallization (BSM) deposition, is performed on a taped wafer after a gas escape path is formed between a base film of the tape and the wafer frontside surface following backgrind. Venting provided by the gas escape path reduces formation of bubbles under the tape. The gas escape path may be provided, for example, by a selective pre-curing of tape adhesive, to breach an edge seal and place the wafer frontside surface internal to the edge seal in fluid communication with an environment external to the edge seal. With the thinned wafer supported by the pre-cured tape, BSM is then deposited while the wafer and tape are cooled, for example, via a cooled electrostatic chuck. | 11-07-2013 |
20130316527 | Multi-Chip-Scale Package - Some exemplary embodiments of a multi-chip semiconductor package utilizing a semiconductor substrate and related method for making such a semiconductor package have been disclosed. One exemplary embodiment comprises a first semiconductor device including, on a surface thereof, a first patterned dielectric layer, a conductive redistribution layer, a second patterned dielectric layer, and a second semiconductor device. The conductive redistribution layer connects to a first and a second patterned conductive attach material for connecting the first and second semiconductor devices to provide coplanar electrical connections for mounting on a printed circuit board. In one embodiment, the first semiconductor device is a diode having anode and cathode contacts on an upper surface thereof, and the second semiconductor device is an IGBT. | 11-28-2013 |
20140187035 | METHOD OF ETCHING A POROUS DIELECTRIC MATERIAL - The invention relates to a method of etching a layer of porous dielectric material, characterized in that the etching is performed in a plasma formed from at least one silicon-based gas mixed with oxygen (O | 07-03-2014 |
20140193972 | Buried Hard Mask for Embedded Semiconductor Device Patterning - Methods and apparatus for manufacturing semiconductor devices, and such semiconductor devices, are described. According to various aspects of the disclosure, a semiconductor device can be manufactured by forming a core region of the semiconductor device and forming a periphery region of the semiconductor device. A first polysilicon region can then be formed over the core and periphery regions of the semiconductor device. A first mask is formed on the first poly silicon layer and a second polysilicon layer is disposed such that the second polysilicon layer covers the first mask. A second mask can then be formed on the second polysilicon layer. After forming the second mask, portions of the first and second polysilicon layers that are uncovered by either the first or second masks are removed. | 07-10-2014 |
20140248765 | SEMICONDUCTOR MEMORY DEVICE HAVING DUMMY CONDUCTIVE PATTERNS ON INTERCONNECTION AND FABRICATION METHOD THEREOF - A semiconductor memory device having a cell pattern formed on an interconnection and capable of reducing an interconnection resistance and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate in which a cell area, a core area, and a peripheral area are defined and a bottom structure is formed, a conductive line formed on an entire structure of the semiconductor substrate, a memory cell pattern formed on the conductive line in the cell area, and a dummy conductive pattern formed on any one of the conductive line in the core area and the peripheral area. | 09-04-2014 |
20140248766 | THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - Provided are a three-dimensional semiconductor device and a method of fabricating the same. The three-dimensional semiconductor device may include a mold structure for providing gap regions and an interconnection structure including a plurality of interconnection patterns disposed in the gap regions. The mold structure may include interlayer molds defining upper surfaces and lower surfaces of the interconnection patterns and sidewall molds defining sidewalls of the interconnection patterns below the interlayer molds. | 09-04-2014 |
20140273431 | LASER RESIST REMOVAL FOR INTEGRATED CIRCUIT (IC) PACKAGING - Embodiments of the present disclosure are directed to laser removal of resist material from integrated circuit (IC) packaging components, as well as package assemblies and systems incorporating such material and removal methods. A resist layer may be applied to one or more components of a package assembly. The resist layer may be subsequently removed by applying laser radiation and a flow of fluid to the resist layer. The laser radiation may cause cracking, delamination, and/or polymer chain scission, and the flow of fluid may enhance mechanical separation of the resist material from the package assembly components. | 09-18-2014 |
20140287577 | METHODS FOR PRODUCING INTERCONNECTS IN SEMICONDUCTOR DEVICES - A method for producing interconnects on a workpiece includes obtaining a workpiece substrate having a feature, depositing a conductive layer in the feature, to partially or fully fill the feature, depositing a copper fill to completely fill the feature if the feature is partially filled by the conductive layer, applying a copper overburden, thermally treating the workpiece, and removing the overburden to expose the substrate and the metalized feature. | 09-25-2014 |
20140287578 | Electroplating Methods for Fabricating Integrated Circuit Devices and Devices Fabricated Thereby - Provided are methods of fabricating a semiconductor device and semiconductor devices fabricated thereby. In the methods, dummy recess regions may be formed between cell recess regions and a peripheral circuit region. Due to the presence of the dummy recess regions, it may be possible to reduce a concentration gradient of a suppressor contained in a plating solution near the dummy pattern region, to make the concentration of the suppressor more uniform in the cell pattern region, and to supply an electric current more effectively to the cell pattern region. As a result, a plating layer can be more uniformly formed in the cell pattern region, without void formation therein. | 09-25-2014 |
20140315380 | TRENCH PATTERNING WITH BLOCK FIRST SIDEWALL IMAGE TRANSFER - A method including forming a tetra-layer hardmask above a substrate, the tetra-layer hardmask including a second hardmask layer above a first hardmask layer; removing a portion of the second hardmask layer of the tetra-layer hardmask within a pattern region of a structure comprising the substrate and the tetra-layer hardmask; forming a set of sidewall spacers above the tetra-layer hardmask to define a device pattern; and transferring a portion of the device pattern into the substrate and within the pattern region of the structure. | 10-23-2014 |
20140315381 | INTERCONNECT FABRICATION AT AN INTEGRATED SEMICONDUCTOR PROCESSING STATION - A stand-alone processing station of a semiconductor manufacturing system may be configured to fabricate interconnects on a semiconductor wafer. The stand-alone processing station may include a chemical mechanical polishing (CMP) module and an electro-chemical deposition (ECD) module. The CMP module may be configured to receive a semiconductor wafer from another processing station and selectively remove a first top layer from the received semiconductor wafer. The ECD module may be configured to receive a semiconductor wafer from the CMP module and fill interconnect features with metal. The CMP module may also be configured to receive a semiconductor wafer from the ECD module and selectively remove excess metal and a second top layer from the semiconductor wafer. Methods of forming an interconnect on a semiconductor wafer are also provided, as are other aspects. | 10-23-2014 |
20140335688 | MASK ASSEMBLY AND THIN FILM DEPOSITION METHOD USING THE SAME - A mask assembly and a thin film deposition method using the same are provided. The mask assembly includes a mask frame including first to fourth sides. The first to fourth sides form a rectangle. Inner sides of the rectangle define a window. The mask frame has a plurality of substrate seating portions provided to project toward the window from at least two corners. The two corners face each other in a diagonal direction. The mask assembly includes four corners positioned where the first to fourth sides of the mask assembly meet each other. A mask includes a plurality of openings for deposition. The plurality of openings are arranged to correspond to the window. | 11-13-2014 |
20140342548 | Integrated Circuit Devices Including Interconnections Insulated by Air Gaps and Methods of Fabricating the Same - Semiconductor devices and methods of fabricating the same are provided. The semiconductor device may include interconnections extending in a first direction on a substrate and spaced apart from each other in a second direction perpendicular to the first direction, barrier dielectric patterns disposed on top surfaces of the interconnections, respectively, and an upper interlayer dielectric layer disposed on the interconnection. Respective air gaps are disposed between adjacent ones of the interconnections. | 11-20-2014 |
20150024587 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device is provided. An etch-target layer is formed on a substrate. A photoresist layer is formed on the etch-target layer. A first exposure process is performed using a first photo mask to form a plurality of first-irradiated patterns in the photoresist layer. The first photo mask includes a plurality of first transmission regions. Each first transmission region has different optical transmittance. A second exposure process is performed using a second photo mask to form a plurality of second-irradiated patterns in the photoresist layer. The second photo mask includes a plurality of second transmission regions. Each second transmission region has different optical transmittance. A photoresist pattern is formed from the photoresist layer by removing the plurality of first-irradiated and second-irradiated patterns from the photoresist layer. A lower structure is formed from the etch-target layer by etching the etch-target layer using the photoresist pattern. | 01-22-2015 |
20150031201 | TRENCH PATTERNING WITH BLOCK FIRST SIDEWALL IMAGE TRANSFER - A method including forming a tetra-layer hardmask above a substrate, the tetra-layer hardmask including a second hardmask layer above a first hardmask layer; removing a portion of the second hardmask layer of the tetra-layer hardmask within a pattern region of a structure comprising the substrate and the tetra-layer hardmask; forming a set of sidewall spacers above the tetra-layer hardmask to define a device pattern; and transferring a portion of the device pattern into the substrate and within the pattern region of the structure. | 01-29-2015 |
20150044865 | METHODS OF MAKING INTEGRATED CIRCUITS INCLUDING AIR GAPS AROUND INTERCONNECT STRUCTURES - A method of making an integrated circuit includes forming an interconnect structure in an opening in a dielectric layer. The method further includes forming an air gap between the dielectric layer and the interconnect structure, where a first liner layer along a bottom portion of a sidewall of the opening of the dielectric layer is under the air gap, and a top portion of the first liner layer is below a lowest portion of the air gap. | 02-12-2015 |
20150050804 | METHODS FOR MANUFACTURING GRATING SHEET AND LCD PANEL - Methods for manufacturing the grating sheet and a liquid crystal display panel are provided. The grating sheet comprises a plurality of primary color gratings in parallel, each of which comprises a red R sub-grating, a green G sub-grating and a blue B sub-grating in parallel, and each sub-grating comprises an opening area and a reflective region disposed around the opening area and corresponds to a pixel unit on a sub-array substrate. The methods for manufacturing the grating sheet and a liquid crystal display panel may be applicable to a system with a liquid crystal display. | 02-19-2015 |
20150079783 | Methods of Forming Printable Integrated Circuit Devices and Devices Formed Thereby - Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. A step is performed to selectively etch through the semiconductor active layer and the sacrificial layer in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. A step can be performed to selectively etch through the capping layer and the first portion of the semiconductor active layer to thereby expose the sacrificial layer. The sacrificial layer may be selectively removed from between the first portion of the semiconductor active layer and the handling substrate to thereby define a suspended integrated circuit chip encapsulated by the capping layer. | 03-19-2015 |
20150093891 | METHOD OF ENABLING SEAMLESS COBALT GAP-FILL - Methods for depositing a metal layer in a feature definition of a semiconductor device are provided. In one implementation, a method for depositing a metal layer for forming a semiconductor device is provided. The method comprises performing a cyclic metal deposition process to deposit a metal layer on a substrate and annealing the metal layer disposed on the substrate. The cyclic metal deposition process comprises exposing the substrate to a deposition precursor gas mixture to deposit a portion of the metal layer on the substrate, exposing the portion of the metal layer to either a plasma treatment process or hydrogen annealing process and repeating the exposing the substrate to a deposition precursor gas mixture and exposing the portion of the metal layer to either a plasma treatment process or hydrogen annealing process until a predetermined thickness of the metal layer is achieved. | 04-02-2015 |
20150111376 | Processes and structures for IC fabrication - The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process provides multiple interconnect wires in the form of a ribbon between the bond pads, and then subsequently separates the ribbon into multiple individual interconnect wires. | 04-23-2015 |
20150132942 | METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES HAVING BURIED CONTACTS AND RELATED SEMICONDUCTOR DEVICES - Provided is a method of manufacturing a semiconductor device. The method includes: forming bit line structures spaced apart from each other by first groove disposed in first direction, extending in first direction, and spaced apart from each other in second direction perpendicular to first direction, on substrate in which word line is buried; forming multilayer spacer on both sidewalls of bit line structure; forming sacrificial layer to fill first groove; forming second grooves spaced apart from each other in first direction and second direction, by patterning sacrificial layer; etching outermost spacer of multilayer spacer located in second groove; forming first supplementary spacer in second groove; forming insulating layer to fill second groove; and forming third grooves spaced apart from each other in first direction and second direction, on both sides of first supplementary spacer, by removing sacrificial layer and insulating layer. | 05-14-2015 |
20150132943 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a semiconductor device. The method includes forming isolated contact filling portions and an etch control portion, the isolated contact filling portions filling contact holes defined in a support layer and are spaced apart from each other in a first direction and a second direction perpendicular to the first direction and the etch control layer surrounding the isolated contact filling portions, forming an interconnection layer on the isolated contact filling portions and the etch control portion, and forming interconnection patterns by photo-etching the interconnection layer, the isolated contact patterns, and the etch control portion, the interconnection patterns being relatively narrow in the first direction and relatively wide in the second direction. | 05-14-2015 |
20150140803 | METHODS OF FORMING SEMICONDUCTOR STRUCTURES - Methods of forming semiconductor structures that include bodies of a semiconductor material disposed between rails of a dielectric material are disclosed. Such methods may include filling a plurality of trenches in a substrate with a dielectric material and removing portions of the substrate between the dielectric material to form a plurality of openings. In some embodiments, portions of the substrate may be undercut to form a continuous void underlying the bodies and the continuous void may be filled with a conductive material. In other embodiments, portions of the substrate exposed within the openings may be converted to a silicide material to form a conductive material under the bodies. For example, the conductive material may be used as a conductive line to electrically interconnect memory device components. Semiconductor structures and devices formed by such methods are also disclosed. | 05-21-2015 |
20150303102 | SEMICONDUCTOR WAFER WITH NONSTICK SEAL REGION - A semiconductor wafer includes a nonstick region. During integrated circuit fabrication processes, the wafer may be inserted into an electrodeposition (e.g. plating, etc.) tool. The tool may contact the nonstick region to e.g. prevent leaks, prevent plating upon a shorting layer of the wafer, etc. When the wafer is removed the nonstick region has a propensity to not transfer to the tool, improving tool availability and reducing wafer scraps. The nonstick region may contain a nonstick seal formed from a liquid photoresist based material, an organic dielectric, etc. | 10-22-2015 |
20150325603 | ARRAY SUBSTRATE, METHOD FOR FABRICATING THE SAME AND DISPLAY DEVICE - An array substrate, a method for fabricating the same and a display device are disclosed. The array substrate comprises a plurality of gate lines and a plurality of data lines which intersect each other to define a plurality of pixel regions, each of the pixel regions comprises a thin film transistor and further comprises: a base substrate; more than one protrusion disposed apart from each other on the base substrate; a first electrode layer comprising at least one first electrode strip disposed in a gap between adjacent protrusions; a second electrode layer comprising at least one second electrode strip disposed on the protrusions. | 11-12-2015 |
20150332958 | Sublithographic Kelvin Structure Patterned With DSA - In one aspect, a DSA-based method for forming a Kelvin-testable structure includes the following steps. A guide pattern is formed on a substrate which defines i) multiple pad regions of the Kelvin-testable structure and ii) a region interconnecting two of the pad regions on the substrate. A self-assembly material is deposited onto the substrate and is annealed at a temperature/duration sufficient to cause it to undergo self-assembly to form a self-assembled pattern on the substrate, wherein the self-assembly is directed by the guide pattern such that the self-assembled material in the region interconnecting the two pad regions forms multiple straight lines. A pattern of the self-assembled material is transferred to the substrate forming multiple lines in the substrate, wherein the pattern of the self-assembled material is configured such that only a given one of the lines is a continuous line between the two pad regions on the substrate. | 11-19-2015 |
20150332960 | CONDUCTIVE LINES IN CIRCUITS - In a method, conductive lines used in a circuit are formed. Signal traces of a plurality of signal traces are grouped to a first group of first signal traces or a second group of second signal traces. A first mask is used to form a first conductive line for a first signal trace of the first group. A second mask is used to form a second conductive line for a second signal trace of the second group. The first traces each have a first width. The second traces each have a second width different from the first width. The grouping is based on at least one of following conditions: a current flowing through a signal trace of the signal traces of the plurality of signal traces, a length of the signal trace, a resistivity of the signal trace, or a resistivity-capacitive constant of the signal trace. | 11-19-2015 |
20150348795 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - In a method of manufacturing a semiconductor device, which uses a triple patterning process, a porous layer covering sidewalls and an upper surface of a polymer-containing pattern is formed on a layer to be etched. A decomposition gas is supplied to the polymer-containing pattern through the porous layer, and a portion of the polymer-containing pattern is decomposed to form a reduced polymer-containing pattern and form a void between the reduced polymer-containing pattern and the porous layer. A portion of the porous layer is removed to form a porous spacer pattern spaced apart from the reduced polymer-containing pattern. The layer to be etched is etched by using the reduced polymer-containing pattern and the porous spacer pattern as an etch mask. | 12-03-2015 |
20150371890 | METHOD FOR FABRICATING AND MANUFACTURING MICRO- and NANO-FABRICATED DEVICES AND SYSTEMS SECURELY - A method is disclosed for manufacturing integrated circuits, microelectronics, micro-electro-mechanical systems (MEMS), nano-electro-mechanical systems (NEMS), photonic, and any micro- and nano-fabricated devices and systems designs that allow these designs to be kept secure. The manufacturing of the devices in the substrates is performed in a traditional manner at a foundry that can be located anywhere in the world., The manufacturing at this foundry is stopped just before the fabrication of the first layer of electrical interconnects. At this stage, the semiconductor substrates with the devices, minus electrical interconnects, are sent back to the design organization (or their designated trusted foundry) to perform the fabrication of the electrical interconnects to complete the entire manufacturing process. Since the electrical interconnection wiring diagram is the critical component of the design, this de-coupling of the manufacturing allows the designs of the devices and systems to be kept secure and confidential. | 12-24-2015 |
20150380300 | Self-Aligned Double Spacer Patterning Process - Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a first hard mask layer over a semiconductor device layer, the first hard mask layer comprising a metal-containing material, forming a second hard mask layer over the first hard mask layer, and forming a first set of metal-containing spacers over the second hard mask layer. The method further includes patterning the second hard mask layer using the first set of metal-containing spacers as a mask, forming a second set of metal-containing spacers on sidewalls of the patterned second hard mask layer, and patterning the first hard mask layer using the second set of metal-containing spacers as a mask. | 12-31-2015 |
20150380308 | MASKING METHOD FOR SEMICONDUCTOR DEVICES WITH HIGH SURFACE TOPOGRAPHY - The method comprises the steps of providing a semiconductor body or substrate ( | 12-31-2015 |
20150380415 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device includes a bit line disposed over a semiconductor substrate, a supporting film being perpendicular to the bit line, a first storage node contact disposed at a lower part of a region disposed between the bit line and the supporting film, and a second storage node contact having a line shape, disposed over the first storage node contact and the bit line, isolated by the supporting film, and patterned in a diagonal direction across the bit line. | 12-31-2015 |
20160013097 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME | 01-14-2016 |
20160027686 | METHOD FOR MANUFACTURING INTERCONNECT STRUCTURES INCORPORATING AIR GAP SPACERS - A dual damascene article of manufacture comprises a trench containing a conductive metal column where the trench and the conductive metal column extend down into and are contiguous with a via. The trench and the conductive metal column and the via have a common axis. These articles comprise interconnect structures incorporating air-gap spacers containing metal/insulator structures for Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging. The trench in this regard comprises a sidewall air-gap immediately adjacent the side walls of the trench and the conductive metal column, the sidewall air-gap extending down to the via to a depth below a line fixed by the bottom of the trench, and continues downward in the via for a distance of from about 1 Angstrom below the line to the full depth of the via. In another aspect, the article of manufacture comprises a capped dual damascene structure. | 01-28-2016 |
20160042111 | LAYOUT METHOD OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING SEMICONDUCTOR DEVICE - A layout method for use in fabricating a semiconductor device includes creating a contact layout including cell contact layouts and peripheral contact layouts using a computer, and creating an interconnection layout including cell interconnection layouts and peripheral interconnection layouts using the computer. The interconnection layout includes a plurality of line layouts and bride layouts. The line layouts include cell interconnection layouts and peripheral line layouts. The peripheral line layouts include a first peripheral line layout and a second peripheral line layout adjacent to each other, and the peripheral contact layouts include a misaligned contact layout interposed between the first and second peripheral line layouts. The bridge layout connects the first and second peripheral line layouts and overlaps the misaligned contact layout. In the method, the second peripheral line layout is divided along its length. | 02-11-2016 |
20160042995 | INTERCONNECT STRUCTURES FOR INTEGRATED CIRCUITS AND THEIR FORMATION - An embodiment of an interconnect structure for an integrated circuit may include a first conductor coupled to circuitry, a second conductor, a dielectric between the first and second conductors, and a conductive underpass under and coupled to the first and second conductors and passing under the dielectric or a conductive overpass over and coupled to the first and second conductors and passing over the dielectric. The second conductor would be floating but for its coupling to the conductive underpass or the conductive overpass. In other embodiments, another dielectric might be included that would electrically isolate the second conductor but for its coupling to the conductive underpass or the conductive overpass. | 02-11-2016 |
20160056070 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Both enhancement of embeddability of a wiring groove and suppression of the generation of a coupling failure between a wiring and a coupling member are simultaneously achieved. In a cross-section perpendicular to a direction passing through the contact and a direction in which the second wiring extends, the center of the contact is more close to a first side surface of the second wiring than the center of the second wiring. In addition, when a region where the first side surface of the second wiring overlaps the contact in the direction in which the second wiring extends, is set to be an overlapping region, at least the lower part of the overlapping region has an inclination steeper than that of other portions of the side surface of the second wiring. | 02-25-2016 |
20160056075 | PRECUT METAL LINES - Embodiments of the present invention provide a method for cuts of sacrificial metal lines in a back end of line structure. Sacrificial Mx+1 lines are formed above metal Mx lines. A line cut lithography stack is deposited and patterned over the sacrificial Mx+1 lines and a cut cavity is formed. The cut cavity is filled with dielectric material. A selective etch process removes the sacrificial Mx+1 lines, preserving the dielectric that fills in the cut cavity. Precut metal lines are then formed by depositing metal where the sacrificial Mx+1 lines were removed. Thus embodiments of the present invention provide precut metal lines, and do not require metal cutting. By avoiding the need for metal cutting, the risks associated with metal cutting are avoided. | 02-25-2016 |
20160071762 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - Provided are a cleaning composition for removing an organic material remaining on an organic layer and a method of forming a semiconductor device using the composition. The cleaning composition includes 0.01-5 wt %. hydroxide based on a total weight of the cleaning composition and deionized water. | 03-10-2016 |
20160079249 | PITCH-HALVING INTEGRATED CIRCUIT PROCESS - A pitch-halving IC process is described. Parallel base line patterns are formed over a substrate, each being connected with a hammerhead pattern at a first or second side of the base line patterns, wherein the hammerhead patterns are arranged at the first side and the second side alternately, and the hammerhead patterns at the first or second side are arranged in a staggered manner. The above patterns are trimmed. A spacer is formed on the sidewalls of each base line pattern and the corresponding hammerhead pattern, including a pair of derivative line patterns, a loop pattern around the hammerhead pattern, and a turning pattern at the other end of the base line pattern. The base line patterns and the hammerhead patterns are removed. A portion of each loop pattern and at least a portion of each turning pattern are removed to disconnect each pair of derivative line patterns. | 03-17-2016 |
20160095208 | DEVICES AND METHODS TO REDUCE STRESS IN AN ELECTRONIC DEVICE - A device includes a stress relief region between at least two stress domains of a substrate (e.g., of a semiconductor die or other integrated circuit). The stress relief region includes a conductive structure electrically coupling circuitries of the stress domains between which the conductive structure is disposed. | 03-31-2016 |
20160099174 | METHOD OF FORMING AN INTERCONNECT STRUCTURE FOR A SEMICONDUCTOR DEVICE - Methods of semiconductor device fabrication are provided including those that provide a substrate having a plurality of trenches disposed in a dielectric layer formed above the substrate. A via pattern including a plurality of openings may be defined above the substrate. A spacer material layer is formed on a sidewall at least one trench. Via holes can be etched in the dielectric layer using the via pattern and spacer material layer as a masking element. | 04-07-2016 |
20160104636 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - Manufacturing stability of a semiconductor device is improved. A method of manufacturing a semiconductor device includes the steps of: forming an etching stopper film over a first interlayer insulating film; forming an inorganic insulating film over the etching stopper film; forming a resist film over the inorganic insulating film; selectively etching the etching stopper film and the inorganic insulating film by using the resist film as a mask to form a first opening in the etching stopper film and to form a second opening in the inorganic insulating film; removing the resist film by O | 04-14-2016 |
20160126094 | LATTICE MATCHED ASPECT RATIO TRAPPING TO REDUCE DEFECTS IN III-V LAYER DIRECTLY GROWN ON SILICON - A structure having application to electronic devices includes a III-V layer having high crystal quality and a low defect density on a lattice mismatched substrate. Trenches are formed in a layer of III-V semiconductor material grown on a substrate having a different lattice constant. Dielectric material is deposited within the trenches, forming dielectric regions. A portion of the layer of III-V material is removed, leaving new trenches defined by the dielectric regions. A new layer of III-V semiconductor material having reduced defect density is grown on the remaining portion of the originally deposited III-V semiconductor layer and within the trenches defined by the dielectric regions. | 05-05-2016 |
20160133495 | MULTI-LAYER LASER DEBONDING STRUCTURE WITH TUNABLE ABSORPTION - The absorption properties of both an adhesive layer and an ablation layer are employed to facilitate debonding of a device wafer and a glass handler without damaging the device wafer. The penetration depths of the adhesive and ablation layers are selected such that no more than a negligible amount of the ablation fluence reaches the surface of the device wafer. | 05-12-2016 |
20160133513 | METAL OXYSILICATE DIFFUSION BARRIERS FOR DAMASCENE METALLIZATION WITH LOW RC DELAYS AND METHODS FOR FORMING THE SAME - A method is disclosed to form a metal-oxysilicate diffusion barrier for a damascene metallization. A trench is formed in an Inter Layer Dielectric (ILD) material. An oxysilicate formation-enhancement layer comprising silicon, carbon, oxygen, a constituent component of the ILD, or a combination thereof, is formed in the trench. A barrier seed layer is formed on the oxysilicate formation-enhancement layer comprising an elemental metal selected from a first group of elemental metals in combination with an elemental metal selected from a second group of elemental metals. An elemental metal in the second group is immiscible in copper or an alloy thereof, has a diffusion constant greater than a self-diffusion of copper or an alloy thereof; does not reducing silicon-oxygen bonds during oxysilicate formation; and promotes adhesion of copper or an alloy of copper to the metal-oxysilicate barrier diffusion layer. The structure is then annealed to form a metal-oxysilicate diffusion barrier. | 05-12-2016 |
20160163584 | SELF-ALIGNED DOUBLE PATTERNING PROCESS FOR TWO DIMENSIONAL PATTERNS - One method includes forming a mandrel element above a hard mask layer, forming first and second spacers on the mandrel element, removing the mandrel element, a first opening being defined between the first and second spacers and exposing a portion of the hard mask layer and having a longitudinal axis extending in a first direction, forming a block mask covering a middle portion of the first opening, the block mask having a longitudinal axis extending in a second direction different than the first direction, etching the hard mask layer in the presence of the block mask and the first and second spacers to define aligned first and second line segment openings in the hard mask layer extending in the first direction, etching recesses in a dielectric layer disposed beneath the hard mask layer based on the first and second line segment openings, and filling the recesses with a conductive material. | 06-09-2016 |
20160163592 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In a method for manufacturing a semiconductor, a Through Silicon Via (TSV) template wafer and production wafers form a sandwich structure, in which the TSV template wafer has TSV structures uniformly distributed therein, for providing electrical connection between the production wafers to form 3D interconnection. The TSV template wafer is obtained by thinning a semiconductor wafer, which facilitates reducing the difficulty in etching and filling. Connection parts are provided on the TSV template wafer, for convenience of interconnection between the overlying and underlying production wafers, which facilitates reducing the difficulty in alignment and improving the convenience of design of electrical connection for 3D devices. | 06-09-2016 |
20160181144 | METHOD FOR MANUFACTURING INTERCONNECT STRUCTURES INCORPORATING AIR GAP SPACERS | 06-23-2016 |
20160190004 | METHODS FOR FABRICATING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICES FABRICATED BY THE SAME - The inventive concepts provide methods for fabricating a semiconductor device and semiconductor devices fabricated by the same. According to the method, conductive lines having a fine pitch smaller than the minimum pitch realized by an exposure process may be formed using two or three photolithography processes and two spacer formation processes. In addition, node separation regions of the conductive lines may be easily formed without a misalignment problem. | 06-30-2016 |
20160190016 | ELONGATED CONTACTS USING LITHO-FREEZE-LITHO-ETCH PROCESS - A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which connect to two active areas and/or MOS gates and directly connect to a first level interconnect, using a litho-freeze-litho-etch process for a contact etch mask. A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which connect to two active areas and/or MOS gates and directly connect to a first level interconnect, using a litho-freeze-litho-etch process for a first level interconnect trench etch mask. A process of forming the integrated circuit using a litho-freeze-litho-etch process for a contact etch mask and a litho-freeze-litho-etch process for a first level interconnect trench etch mask. | 06-30-2016 |
20160197002 | INTERCONNECT STRUCTURES INCORPORATING AIR-GAP SPACERS | 07-07-2016 |
20160204029 | LAMINATE AND CORE SHELL FORMATION OF SILICIDE NANOWIRE | 07-14-2016 |
20160254194 | Layout Architecture for Performance Improvement | 09-01-2016 |
20160379864 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. Metal patterns are formed on a first dielectric layer. A modifiable layer is formed to cover the metal patterns and the first dielectric layer. A modification process is performed to modify a part of the modifiable layer on top sides of the metal patterns, thereby top masks being formed. A removing process is performed to remove a part of the modifiable layer on sidewalls of the metal patterns but preserve the top masks. A dielectric layer having voids under the top masks and between the metal patterns is formed. Moreover, the present invention also provides a semiconductor structure formed by said semiconductor process. | 12-29-2016 |
20160379880 | LOW RESISTANCE METAL CONTACTS TO INTERCONNECTS - A semiconductor device and a method of fabricating a contact to interface with an interconnect in a semiconductor device are described. The device includes a dielectric layer formed on a semiconductor layer, and a contact fabricated in a via formed within the dielectric layer. An interconnect formed above the contact interfaces with an exposed surface of the contact opposite a surface closest to the semiconductor layer. The contact includes a contact material in a first portion of the contact and an interface metal in a second portion of the contact. | 12-29-2016 |
20180025936 | LITHOGRAPHIC PATTERNING TO FORM FINE PITCH FEATURES | 01-25-2018 |