| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438620000 | Forming contacts of differing depths into semiconductor substrate | 8 |
| 20090087979 | DUAL DAMASCENE WITH AMORPHOUS CARBON FOR 3D DEEP VIA/TRENCH APPLICATION - A method for fabricating a 3-D monolithic memory device in which a via and trench are etched using an amorphous carbon hard mask. The via extends in multiple levels of the device as a multi-level vertical interconnect. The trench extends laterally, such as to provide a word line or bit line for memory cells, or to provide other routing paths. A dual damascene process can be used in which the via is formed first and the trench is formed second, or the trench is formed first and the via is formed second. The technique is particularly suitable for deep via applications, such as for via depths of greater than 1 μm. A dielectric antireflective coating, optionally with a bottom antireflective coating, can be used to etch an amorphous carbon layer to provide the amorphous carbon hard mask. | 04-02-2009 |
| 20120171859 | CREATION OF VIAS AND TRENCHES WITH DIFFERENT DEPTHS - Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided. | 07-05-2012 |
| 20130210224 | METHOD AND APPARATUS FOR DIVIDING THIN FILM DEVICE INTO SEPARATE CELLS - A method and apparatus for dividing a thin film device having a first layer which is a lower electrode layer, a second layer which is an active layer and a third layer which is an upper electrode layer, the layers each being continuous over the device, into separate cells each having a width W, which are electrically interconnected in series by interconnect structures. The dividing of the cells and the formation of the interconnect structures between adjacent cells are carried out by a process head which is arranged to operate on more than one interconnect structure at a time in a sequence of passes to and fro over the device, the process head performing the following steps: a) making a first cut through the first, second and third layers; b) making a second cut through the second and third layers, the second cut being adjacent to the first cut; c) making a third cut through the third layer the third cut being adjacent to the second cut and on the opposite side of the second cut to the first cut; d) using a first ink jet print head to deposit a non-conducting material into the first cut; and e) using a second ink jet print head to apply conducting material to bridge the non-conducting material in the first cut and either fully or partially fill the second cut such to form an electrical connection between the first layer and the third layer, wherein step (a) precedes step (d), step (d) precedes step (e) and step (b) precedes step (e), (otherwise the steps may be carried out in any order in the single pass of the process head across the device). The thin film device may be a solar panel, a lighting panel or a battery. | 08-15-2013 |
| 20140148004 | METHOD OF FORMING CONTACT HOLES - A method of forming contact holes includes: forming a first conductive layer and a second conductive layer; forming an insulating layer on the first conductive layer and the second conductive layer; forming a photoresist pattern which exposes first and second etch surfaces of a top surface of the insulating layer; performing a first etching process on the insulating layer at a first etching rate; and performing a second etching process on the insulating layer at a second etching rate which is higher than the first etching rate, after a top surface of the first conductive layer is exposed through the insulating layer. The first etch surface is on the first conductive layer, the second etch surface is on the second conductive layer, and a distance between the second etch surface and the second conductive layer is greater than a distance between the first etch surface and the first conductive layer. | 05-29-2014 |
| 20140193973 | METHOD FOR FORMING INTERLAYER CONNECTORS TO A STACK OF CONDUCTIVE LAYERS - A method forms interlayer connectors extending to conductive layers of a stack of W conductive layers interleaved with dielectric layers. The stack is etched to expose landing areas at W−1 conductive layers using a set of M etch masks. For each etch mask m, m going from 0 to M−1, there is a first etching step, at least one mask trimming step, and a subsequent etching step following each trimming step. The etch mask may cover N | 07-10-2014 |
| 20140349476 | MANUFACTURING METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE - The present invention provides a manufacturing method of a semiconductor device, at least containing the following steps: first, a substrate is provided, wherein a first dielectric layer is formed on the substrate, at least one metal gate is formed in the first dielectric layer and at least one source drain region (S/D region) is disposed on two sides of the metal gate, at least one first trench is then formed in the first dielectric layer, exposing parts of the S/D region. The manufacturing method for forming the first trench further includes performing a first photolithography process through a first photomask and performing a second photolithography process through a second photomask, and at least one second trench is formed in the first dielectric layer, exposing parts of the metal gate, and finally, a conductive layer is filled in each first trench and each second trench. | 11-27-2014 |
| 20150140804 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device and a method for manufacturing the same are disclosed. The semiconductor device includes adjacent storage node contact plugs having different heights, and lower-electrode bowing profiles having different heights, such that a spatial margin between the lower electrodes is assured and a bridge fail is prevented, resulting in improved device operation characteristics. The semiconductor device includes a first storage node contact plug and a second storage node contact plug formed over a semiconductor substrate, wherein the second storage node contact plug is arranged at a height different from that of the first storage node contact plug, and a lower electrode formed over the first storage node contact plug and the second storage node contact plug. | 05-21-2015 |
| 20150364359 | Non-Hierarchical Metal Layers for Integrated Circuits - An integrated circuit structure includes a semiconductor substrate, and a first metal layer over the semiconductor substrate. The first metal layer has a first minimum pitch. A second metal layer is over the first metal layer. The second metal layer has a second minimum pitch smaller than the first minimum pitch. | 12-17-2015 |
