| Entries |
| Document | Title | Date |
|---|
| 20080220607 | SIGNAL ROUTING ON REDISTRIBUTION LAYER - A method of routing signals within a semiconductor memory device includes providing a semiconductor wafer having a top surface with a center portion, an edge portion and wafer bond pads at the center portion. A redistribution layer is provided on the top surface of the semiconductor wafer. The method includes redistributing signals from the wafer bond pads to redistribution edge pads utilizing the redistribution layer, and routing signals from the semiconductor wafer up to the redistribution layer and routing these signals back down to the semiconductor wafer. | 09-11-2008 |
| 20080248643 | SOLDER CONNECTOR STRUCTURE AND METHOD - Disclosed are embodiments of a far back end of the line solder connector and a method of forming the connector that eliminates the use aluminum, protects the integrity of the ball limiting metallurgy (BLM) layers and promotes adhesion of the BLM layers by incorporating a thin conformal conductive liner into the solder connector structure. This conductive liner coats the top of the via filling in any divots in order to create a uniform surface for BLM deposition and to, thereby, protect the integrity of the BLM layers. The liner further coats the dielectric sidewalls of the well in which the BLM layers are formed in order to enhance adhesion of the BLM layers to the well. | 10-09-2008 |
| 20080254610 | Semiconductor device and process for manufacturing the same - The present invention relates to a semiconductor device in which electrodes formed on a semiconductor chip and electrodes formed on a wiring board are electrically connected via projecting elastic electrodes, and further relates to a mounting method of reducing a pressure applied to electrodes formed on a substrate or underlying wirings when a semiconductor chip and a wiring board are bonded. | 10-16-2008 |
| 20080268632 | LED epiwafer pad manufacturing process & new construction thereof - A pad manufacturing process applied in LED epiwafer and a new construction thereof comprising of a means to increase interfacial bonding strength being provided first to the surface of the epiwafer; followed with a metal deposition means provided to the surface of the epiwafer by having the surface processed with plasma to improve adhesion between pad and epiwafer; and plating conditions being controlled to obtain finer and more uniform grains to correct the problem of pad surface roughness in order to improve the bonding strength between pad and bonding wire. Furthermore, a new construction of epiwafer and a pad is comprised of an epiwafer containing a substrate, an epitaxial layer, and a first metal layer covering the top of the epitaxial layer; an adhesion layer covering the top of the first metal layer; and a pad covering the top of the adhesion layer in sequence. | 10-30-2008 |
| 20080274608 | STRUCTURE AND METHOD FOR ENHANCING RESISTANCE TO FRACTURE OF BONDING PADS - The present invention provides bond pads structures between semiconductor integrated circuits and the chip package with enhanced resistance to fracture and improved reliability. Mismatch in the coefficient of temperature expansion (CTE) among the materials used in bond structures induces stress and shear on them that may result in fractures within the back end dielectric stacks and cause reliability problems of the packaging. By placing multiple metal pads which are connected to the bond pad through multiple metal via, the adhesion between the bond pads and the back end dielectric stacks is enhanced. | 11-06-2008 |
| 20080286958 | Semiconductor Substrate Having Enhanced Adhesion And Method For Manufacturing The Same - A semiconductor substrate for having enhanced adhesion to semiconductor device and its manufacturing method are provided. The wire circuit layout on the surface of the semiconductor substrate is of a specialized design and surface treatment for enhanced adhesion between the packaged adhered material and the substrate surface (the bonding pad in particular). In the manufacturing method of the semiconductor substrate, the processing by the passivation treatment or the roughening treatment of the whole or a part of the bonding pad on the substrate, such as the brown-oxide treatment or the black-oxide treatment, etc, and the use of an enlarged contact area act to enhance adhesion to the semiconductor device during the packaging of the semiconductor device. | 11-20-2008 |
| 20080293232 | Standoff Height Improvement for Bumping Technology Using Solder Resist - A system to support a die includes a substrate. A solder resist is disposed over the substrate. A first solder bump is disposed in the solder resist to provide electrical connectivity through the solder resist to the substrate. A second solder bump is formed over the solder resist to correspond with a peripheral edge or a corner of the die. The second solder bump provides standoff height physical support to the die. | 11-27-2008 |
| 20080293233 | POST LAST WIRING LEVEL INDUCTOR USING PATTERNED PLATE PROCESS - A method of a semiconductor device. A substrate is provided. At least one metal wiring level is within the substrate. An insulative layer is deposited on a surface of the substrate. An inductor is formed within the insulative layer using a patterned plate process. A wire bond pad is formed within the insulative layer, wherein at least a portion of the wire bond pad is substantially co-planar with the inductor. | 11-27-2008 |
| 20080305624 | Bonding Structure With Buffer Layer And Method Of Forming The Same - A bonding structure with a buffer layer, and a method of forming the same are provided. The bonding structure comprises a first substrate with metal pads thereon, a protection layer covered on the surface of the substrate, a first adhesive metal layer formed on the metal pads, a buffer layer coated on the protection layer and the metal pads, a first metal layer covered on the buffer layer, and a second substrate with electrodes and a bonding layer thereon. The first metal layer, the electrodes and the bonding layer are bonded to form the bonding structure. Direct bonding can be performed through surface activation or heat pressure. The method uses fewer steps and is more reliable. The temperature required for bonding the structure is lower. The bonding density between the contacted surfaces is increased to a fine pitch. The quality at the bonding points is increased because fewer contaminations between the contacted surfaces are generated. | 12-11-2008 |
| 20090023281 | SOLDER BUMP FORMING METHOD - A solder bump forming method of carrying out a reflow treatment over a conductive ball mounted on a plurality of pads, thereby forming a solder bump, includes a metal film forming step of forming a metal film capable of chemically reacting to a tackifying compound on the pads, an organic sticking layer forming step of causing a solution containing the tackifying compound to chemically react to the metal film, thereby forming an organic sticking layer on the metal film, and a conductive ball mounting step of supplying the conductive ball on the pads having the organic sticking layer formed thereon, thereby mounting the conductive ball on the pads through the metal film. | 01-22-2009 |
| 20090029542 | METHODS AND SYSTEMS FOR LASER ASSISTED WIREBONDING - The invention provides methods and systems for laser assisted wirebonding. One or more conditioning laser pulses are used to prepare a bonding surface for wirebonding by removing impurities such as residues from manufacturing processes, oxides, or irregularities on the bonding surface. Subsequently, a free air ball is brought into contact with the conditioned bonding surface to form a weld. | 01-29-2009 |
| 20090093109 | Method for producing a semiconductor device using a solder alloy - In producing a semiconductor device, a solder alloy is prepared to contain antimony in a range of from 3 to 5 wt %, a trace amount of germanium, and a balance of tin. An insulative substrate having conductor patterns on both surfaces thereof is prepared, and a heat sink plate is mounted on a back surface of the insulative substrate by a soldering process using the solder alloy at a temperature ranging from 310 C.° to 320 C.° in a hydrogen reducing furnace. A semiconductor chip is mounted on a front surface of the insulative substrate. | 04-09-2009 |
| 20090111258 | Method for Manufacturing a Semiconductor Device - A manufacturing method of a semiconductor device wherein a metal pad is etched to form a trench in which a central part is concave in form, or to form a trench in the shape of a cylinder or a parallelepiped on the edge part of a metal pad. Accordingly, the contact area between a polymide isoindro quirazorindione (PIQ) or similar curable layer and the metal pad is increased and the bondability is improved. Accordingly, the technology of improving the characteristic of device by preventing the problem that the metal pad is excessively opened in a subsequent curing process and the layer of a lower portion of the metal pad is attacked is disclosed. | 04-30-2009 |
| 20090124072 | SEMICONDUCTOR DEVICE HAVING THROUGH ELECTRODE AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a substrate, and a through electrode passing through the substrate. The semiconductor device has a pad region and a through electrode region. A pad covers the pad region, extends into the through electrode region, and delimits an opening in the through electrode region. A through electrode extends through the semiconductor substrate below the hole in the pad in the through region. | 05-14-2009 |
| 20090124073 | SEMICONDUCTOR DEVICE WITH BONDING PAD - A method for forming a semiconductor device with a bonding pad is disclosed. A first substrate having a device area and a bonding area is provided, wherein the first substrate has an upper surface and a bottom surface. Semiconductor elements are formed on the upper surface of the first substrate in the device area. A first inter-metal dielectric layer is formed on the upper surface of the substrate in the bonding area. A lowermost metal pattern is formed in the first inter-metal dielectric layer, wherein the lowermost metal pattern serves as the bonding pad. An opening through the first substrate is formed to expose the lowermost metal pattern. | 05-14-2009 |
| 20090163019 | FORMING ROBUST SOLDER INTERCONNECT STRUCTURES BY REDUCING EFFECTS OF SEED LAYER UNDERETCHING - A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening of a first diameter, and a solder material is formed over the barrier layer using a second patterned opening of a second diameter. The second patterned opening is configured such that the second diameter is larger than the first diameter. | 06-25-2009 |
| 20090176362 | METHODS OF FORMING INTERCONNECTS IN A SEMICONDUCTOR STRUCTURE - A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed. | 07-09-2009 |
| 20090181532 | INTEGRATION SCHEME FOR EXTENSION OF VIA OPENING DEPTH - An interconnect structure having an incomplete via opening is processed to deepen a via opening and to expose a metal line. In case the interconnect structure comprises a metal pad or a blanket metal layer, the metal pad or the metal layer is removed selective to an underlying dielectric layer to expose the incomplete via opening. Another dielectric layer is formed within the incomplete via opening to compensated for differences in the total dielectric thickness above the metal line relative to an optimal dielectric stack. A photoresist is applied thereupon and patterned. An anisotropic etch process for formation of a normal via opening may be employed with no or minimal modification to form a proper via opening and to expose the metal line. A metal pad is formed upon the metal line so that electrical contact is provided between the metal pad and the metal line. | 07-16-2009 |
| 20090215257 | SEMICONDUCTOR DEVICES HAVING A TRENCH IN A SIDE PORTION OF A CONDUCTING LINE PATTERN AND METHODS OF FORMING THE SAME - A semiconductor device having a trench in the side portion of a conducting line pattern and methods of forming the same. The semiconductor device provides a way of preventing an electrical short between the conducting line pattern and a landing pad adjacent to the conducting line pattern. There are disposed two conducting line patterns on a semiconductor substrate. Each of the conducting line patterns includes a conducting line and a conducting line capping layer pattern stacked thereon. Each of the conducting line patterns has a trench between the conducting line capping layer pattern and the conducting line. Conducting line spacers are formed between the conducting line patterns. One conducting line spacer covers a portion of a sidewall of one of the conducting line patterns, and the remaining conducting line spacer covers an entire sidewall of the remaining conducting line pattern. A landing pad is disposed between the conducting line patterns. | 08-27-2009 |
| 20090258485 | Semiconductor Processing Methods - Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the growth of the conductive contact regions over the front side. In some embodiments, plasma-enhanced atomic layer deposition may be utilized to for the deposition, and may be conducted at a temperature suitable to anneal passivation materials so that such annealing occurs simultaneously with the plasma-enhanced atomic layer deposition. | 10-15-2009 |
| 20100015792 | Bonding Metallurgy for Three-Dimensional Interconnect - A method provides a first substrate with a conductive pad and disposes layers of Cu, TaN, and AlCu, respectively, forming a conductive stack on the conductive pad. The AlCu layer of the first substrate is bonded to a through substrate via (TSV) structure of a second substrate, wherein a conductive path is formed from the conductive pad of the first substrate to the TSV structure of the second substrate. | 01-21-2010 |
| 20100015793 | CONTACT SURROUNDED BY PASSIVATION AND POLYMIDE AND METHOD THEREFOR - A semiconductor device has contact between the last interconnect layer and the bond pad that includes a barrier metal between the bond pad and the last interconnect layer. Both a passivation layer and a polyimide layer separate the last interconnect layer and the bond pad. The passivation layer is patterned to form a first opening to contact the last interconnect layer. The polyimide layer is also patterned to leave a second opening that is inside and thus smaller than the first opening through the passivation. The barrier layer is then deposited in contact with the last interconnect layer and bounded by the polyimide layer. The bond pad is then formed in contact with the barrier, and a wire bond is then made to the bond pad. | 01-21-2010 |
| 20100081269 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING ELECTRODE FOR EXTERNAL CONNECTION - A method for manufacturing semiconductor device which includes forming a first metal film over an electrode pad disposed on a substrate, forming a second metal film on the first metal film, forming a first oxide film on a surface of the first metal film and a second oxide film on a surface of the second metal film by oxidizing the surfaces of the first metal film and the second metal film, removing the first oxide film, and melting the second metal film after removing the first oxide film. | 04-01-2010 |
| 20100130000 | Method of manufacturing semiconductor device - When a bump electrode is formed on an opening formed in a semiconductor substrate, the invention prevents a void that is caused by gas trapped in the opening. A method of manufacturing a semiconductor device of the invention includes forming a first wiring on a main surface of a semiconductor substrate, forming an opening in the semiconductor substrate from the back surface to the main surface so as to expose the back surface of the first wiring, forming a second wiring connected to the back surface of the first wiring and extending from inside the opening onto the back surface of the semiconductor substrate, forming a solder layer connected to part of the second wiring on the bottom of the opening and extending from inside the opening onto the back surface of the semiconductor substrate, and forming a bump electrode on the opening by reflowing the solder layer. | 05-27-2010 |
| 20100159690 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE THAT USES BOTH A NORMAL PHOTOMASK AND A PHASE SHIFT MASK FOR DEFINING INTERCONNECT PATTERNS - According to one embodiment of the present invention, a method of manufacturing a semiconductor device includes below steps. | 06-24-2010 |
| 20100184285 | METHOD TO PREVENT CORROSION OF BOND PAD STRUCTURE - There is provided a method of fabrication an integrated circuit comprising providing a substrate with a bond pad formed thereover, the bond pad having a top surface for the formation of bonding connections. A passivation layer is provided over the bond pad followed by an overlying masking layer. The passivation layer is subsequently etched in accordance with the masking layer to form a patterned passivation layer with an opening that exposes a portion of the top surface of the bond pad. After etching the passivation layer, the mask layer is removed by a plasma resist strip followed by a wet solvent clean that removes etch residue from the passivation layer etch. Finally, a bond pad protective layer is grown over the surface of the bond pad. The bond pad may be composed of aluminum and the bond pad protective layer may be aluminum oxide. | 07-22-2010 |
| 20100240211 | SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND PHASE SHIFT MASK - A method of manufacturing a semiconductor device including an integrated circuit part in which an integrated circuit is formed and a main wall part including metal films surrounding said integrated circuit part, includes the step of selectively forming a sub-wall part including metal films between the integrated circuit part and the main wall part, in parallel to formation of the integrated circuit part and the main wall part. A sub-wall part which is in an “L” shape is provided between each corner of the main wall part and the integrated circuit part of the resulting semiconductor device. | 09-23-2010 |
| 20100248469 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and method of fabricating the same reduce the likelihood of the occurrence of electrical defects. The device includes a first interlayer insulating film on a semiconductor substrate; a contact pad spacer on the first interlayer insulating film; and a contact pad in the first interlayer insulating film and the contact pad spacer. The cross-sectional area of an upper portion of the contact pad in the contact pad spacer in a direction horizontal to the substrate is equal to or less than a cross-sectional area of an intermediate portion at an interface between the contact pad spacer and the first interlayer insulating film in a direction horizontal to the substrate. | 09-30-2010 |
| 20100261344 | ACTIVE AREA BONDING COMPATIBLE HIGH CURRENT STRUCTURES - A method of forming a semiconductor structure is provided. One method comprises forming a device region between a substrate and a bond pad. Patterning a conductor between the bond pad and the device region with gaps. Filling the gaps with insulation material that is harder than the conductor to form pillars of relatively hard material that extend through the conductor and forming an insulation layer of the insulation material between the conductor and the bond pad. | 10-14-2010 |
| 20100279501 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - After a plurality of pads ( | 11-04-2010 |
| 20100304559 | METHOD OF PRODUCTION OF A CONTACT STRUCTURE - A probe card having a plurality of silicon finger contactors contacting pads provided on a tested semiconductor wafer and a probe board mounting the plurality of silicon finger contactors on its surface, wherein each silicon finger contactor has a base part on which a step difference is formed, a support part with a rear end side provided at the base part and with a front end side sticking out from the base part, and a conductive part formed on the surface of the support part, each silicon finger contactor mounted on the probe board so that an angle part of the step difference formed on the base part contacts the surface of the probe board. | 12-02-2010 |
| 20100330796 | Manufacturing method of semiconductor device - The manufacturing method includes: forming a seed film on a semiconductor chip; forming a photoresist having an opening above an electrode of the semiconductor chip on the seed film; forming a first Au bump on the seed film in the opening by electrolytic plating with a current density of 1.5 A/dm | 12-30-2010 |
| 20100330797 | FABRICATION METHOD FOR CIRCUIT SUBSTRATE HAVING POST-FED DIE SIDE POWER SUPPLY CONNECTIONS - A circuit substrate uses post-fed top side power supply connections to provide improved routing flexibility and lower power supply voltage drop/power loss. Plated-through holes are used near the outside edges of the substrate to provide power supply connections to the top metal layers of the substrate adjacent to the die, which act as power supply planes. Pins are inserted through the plated-through holes to further lower the resistance of the power supply path(s). The bottom ends of the pins may extend past the bottom of the substrate to provide solderable interconnects for the power supply connections, or the bottom ends of the pins may be soldered to “jog” circuit patterns on a bottom metal layer of the substrate which connect the pins to one or more power supply terminals of an integrated circuit package including the substrate. | 12-30-2010 |
| 20110014784 | SEMICONDUCTOR PROCESS - A semiconductor process is provided. First, a substrate having a dielectric layer formed thereon is provided. Thereafter, an interconnection structure including copper is formed in the dielectric layer. Afterwards, a metal layer is formed on the dielectric layer. The metal layer is then patterned to form a pad. An annealing process is performed, wherein the gas source for the annealing process includes hydrogen in a concentration of 50% to 90%. | 01-20-2011 |
| 20110027983 | Method for Manufacturing a Semiconductor Device - A manufacturing method of a semiconductor device wherein a metal pad is etched to form a trench in which a central part is concave in form, or to form a trench in the shape of a cylinder or a parallelepiped on the edge part of a metal pad. Accordingly, the contact area between a polymide isoindro quirazorindione (PIQ) or similar curable layer and the metal pad is increased and the bondability is improved. Accordingly, the technology of improving the characteristic of device by preventing the problem that the metal pad is excessively opened in a subsequent curing process and the layer of a lower portion of the metal pad is attacked is disclosed. | 02-03-2011 |
| 20110092064 | Preventing UBM Oxidation in Bump Formation Processes - A method of forming an integrated circuit structure includes forming a copper-containing seed layer on a wafer, and performing a descum step on an exposed surface of the copper-containing seed layer. The descum step is performed using a process gas including fluorine and oxygen. A reduction/purge step is then performed on the exposed surface of the copper-containing seed layer using a nitrogen-containing gas. A copper-containing layer is plated on the copper-containing seed layer. | 04-21-2011 |
| 20110097891 | Method of Manufacturing the Semiconductor Device - A method of manufacturing semiconductor device includes preparing a substrate having a first surface and a second surface opposite to the first surface. A first insulation layer is formed on the second surface. A sacrificial layer is formed on the first insulation layer. An opening is formed to penetrate through the substrate and extend from the first surface to a portion of the sacrificial layer. A second insulation layer is formed on an inner wall of the opening. A plug is formed to fill the opening. The sacrificial layer is removed to expose a lower portion of the plug through the second surface. | 04-28-2011 |
| 20110097892 | Sprocket Opening Alignment Process and Apparatus for Multilayer Solder Decal - A process for aligning at least two layers in an abutting relationship with each other comprises forming a plurality of sprocket openings in each of the layers for receiving a sprocket of diminishing diameters as the sprocket extends outwardly from a base, with the center axes of the sprocket openings in each layer being substantially alignable with one another, the diameter of the sprocket openings in an abutting layer for first receiving the sprocket being greater than the diameter of the sprocket openings in an abutted layer. This is followed by forming a plurality of reservoir openings in each of at least two of the layers and positioning the sprocket openings in the layers to correspond with one another and the reservoir openings in the layers to correspond with one another so that substantial alignment of the center axes of the corresponding sprocket openings in the layers effects substantial alignment of the center axes of the corresponding reservoir openings in the layers. Engaging the sprocket openings with the sprocket by inserting the end of the sprocket having the smallest diameter into the sprocket openings having the largest diameter in the layers and continuing through to the sprocket opening having the smallest diameter in the layers effects substantial alignment of the center axes of the corresponding sprocket openings and substantial alignment of the center axes of the corresponding reservoir openings in the layers. The invention also comprises apparatus for performing this process. | 04-28-2011 |
| 20110097893 | Integrated Circuit Having Stress Tuning Layer and Methods of Manufacturing Same - Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 μm, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component. | 04-28-2011 |
| 20110104886 | MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE - A manufacturing method includes forming a semi-cured insulation layer made of a photosensitive material on a supporting body; forming an opening part in the insulation layer by a photolithography method, the opening part being configured to expose the supporting body; arranging a semiconductor chip on the insulation layer so that a position of an electrode of the semiconductor chip is consistent with a position of the opening part, and curing the insulation layer; forming sealing resin on a surface of the insulation layer at the semiconductor chip side, the sealing resin being configured to seal the semiconductor chip; removing the supporting body; and providing a wiring layer on a surface of the insulation layer opposite to the semiconductor chip side, the wiring layer being electrically connected to the electrode exposed in the opening part, so that a wiring structural body including the insulation layer and the wiring layer is formed. | 05-05-2011 |
| 20110129993 | Semiconductor device and inspection method therefor - A method of fabricating a semiconductor device, including forming a circuit block in a peripheral edge portion of a semiconductor chip, forming a circuit block pad on the circuit block to provide an electrical interface for the circuit block, and forming a bonding pad laterally offset from the circuit block and the circuit block pad, the bonding pad being electrically connected to the circuit block pad and providing a bonding wire pad for the circuit block. | 06-02-2011 |
| 20110136334 | METHOD OF FORMING AT LEAST ONE BONDING STRUCTURE - A method of forming at least one bonding structure may be provided. A ball may be formed on the front end of a wire outside a capillary. The capillary may be moved downwardly to form a preliminary compressed ball on a first pad using the ball. The capillary may be moved upwardly to form a neck portion on the preliminary compressed ball using the preliminary compressed ball and the wire. The capillary may be moved obliquely and downwardly to form a compressed ball. The capillary may extend the wire from the compressed ball to a second pad. | 06-09-2011 |
| 20110136335 | Semiconductor Device with Improved Contacts - A device with a solder joint made of a copper contact pad ( | 06-09-2011 |
| 20110165772 | CARRIER SOLVENT COMPOSITIONS, COATINGS COMPOSITIONS, AND METHODS TO PRODUCE THICK POLYMER COATINGS - Compositions and methods useful for the coating of polymeric materials onto substrates, for example, electronic device substrates such as semiconductor wafers, are provided. These compositions and methods are particularly suitable manipulating thickness of a polymeric coating in a single coating event. Such methods to control photoresist thickness are used to facilitate the layering of electronic circuitry in a three-dimensional fashion. Furthermore, the compositions of the present invention may be effectively used to deposit thick films of polymeric material in a uniform manner onto inorganic substrates which provides a significant benefit over conventional systems. | 07-07-2011 |
| 20110189848 | METHOD TO FORM SOLDER DEPOSITS ON SUBSTRATES - Described is a method of forming a solder deposit on a substrate comprising the following steps i) provide a substrate including a surface bearing electrical circuitry that includes at least one contact area, ii) form a solder mask layer that is placed on the substrate surface and patterned to expose the at least one contact area, iii) contact the entire substrate area including the solder mask layer and the at least one contact area with a solution suitable to provide a conductive layer on the substrate surface, iv) electroplate a solder deposit layer containing a tin or tin alloy onto the conductive layer and v) etch away an amount of the solder deposit layer containing tin or tin alloy sufficient to remove the solder deposit layer from the solder mask layer area leaving a solder material layer on the at least one contact area. | 08-04-2011 |
| 20110217837 | CONNECTING PAD PRODUCING METHOD - A connecting pad producing method has a first process of projecting an insulating member in a surface of a base material such that a region where a connecting pad is formed is surrounded, a second process of forming a conductive layer in the surface of the base material such that the insulating member is coated with the conductive layer, and a third process of removing the conductive layer with which the insulating member is coated, exposing the insulating member over a whole periphery from the conductive layer, and forming the connecting pad including the conductive layer in a region surrounded by the insulating member. | 09-08-2011 |
| 20110237064 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip having a wire and a passivation film formed on the outermost surface with an opening partially exposing the wire. A resin layer is stacked on the semiconductor chip and provided with a through-hole in a position opposed to a portion of the wire facing the opening. A pad is formed on a peripheral portion of the through-hole in the resin layer and in the through-hole so that an external connection terminal is arranged on the surface thereof. The peripheral portion of the resin layer is formed more thickly than the remaining portion of the resin layer other than the peripheral portion. | 09-29-2011 |
| 20110281430 | WAFER LEVEL PACKAGE AND METHOD OF MANUFACTURING THE SAME - A method of manufacturing a wafer level package can include: forming an indentation, by etching one side of a semiconductor chip, on one side of which a chip pad is formed; forming a rewiring pattern, which is electrically connected with the chip pad and which includes a post pad having a corrugated shape in correspondence with the indentation, by selectively adding a conductive material on one side of the semiconductor chip; forming a sacrificial layer on one side of the semiconductor chip such that a window is formed in the sacrificial layer that completely or partially uncovers the post pad; forming a conductive post on the post pad, by filling the window with a conductive material; and removing the sacrificial layer. This method can be used to produce a wafer level package having a post structure that provides greater strength against lateral shear stresses. | 11-17-2011 |
| 20110318917 | METHODS OF FORMING THROUGH-SILICON VIA STRUCTURES INCLUDING CONDUCTIVE PROTECTIVE LAYERS - Through-Silicon-Via (TSV) structures can be provided by forming a conductive via through a substrate extending from an upper surface of the substrate to a backside surface of the substrate, that is opposite the upper surface, and having a conductive protective layer comprising Ni and/or Co formed at a bottom of the conductive via. A polymer insulating layer can be formed on the backside surface that is separate from the substrate and in contact with the conductive protective layer. | 12-29-2011 |
| 20120021598 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device having a GaN-based semiconductor layer on a first surface of a substrate made of SiC, a pad being provided on the GaN-based layer, includes: forming a first via hole in the substrate by etching, with fluorine based gas, from a second surface of the substrate opposite to the first surface, the etching being carried out with the GaN-based layer being used as an etch stopper; and forming a second via hole in the GaN-based semiconductor layer, with chlorine based gas, from a bottom surface of the first via hole, the etching being carried out with the pad being used as an etching stopper, the chlorine based gas being an etchant different from the fluorine based gas. | 01-26-2012 |
| 20120021599 | Methods for Avoiding Parasitic Capacitance in an Integrated Circuit Package - An integrated circuit package substrate includes a first and an additional electrically conductive layer separated from each other by an electrically insulating layer, a contact pad formed in the first electrically conductive layer for making a direct connection between the integrated circuit package substrate and a printed circuit board, and a cutout formed in the additional electrically conductive layer wherein the cutout encloses an area that completely surrounds the contact pad for avoiding parasitic capacitance between the additional electrically conductive layer and the printed circuit board. | 01-26-2012 |
| 20120058635 | METHOD FOR MANUFACTURING SEMICONDUCTOR OPTICAL DEVICE - A method for manufacturing includes the steps of forming a BCB resin region on a semiconductor optical device; processing a surface of the BCB resin region with inductively coupled plasma produced with a high-frequency power supply for supplying ICP power and a high-frequency power supply for supplying bias power, thus forming a silicon oxide film on the surface of the BCB resin region and roughening the surface of the BCB resin region with projections and recesses; and forming an electrode pad on the surface of the BCB resin region in direct contact with the silicon oxide film. The surface roughness of the BCB resin region and the thickness of the silicon oxide film on the surface of the BCB resin region are controlled by adjusting the bias power and the ICP power. | 03-08-2012 |
| 20120064711 | COPPER BONDING COMPATIBLE BOND PAD STRUCTURE AND METHOD - A copper bonding compatible bond pad structure and associated method is disclosed. The device bond pad structure includes a buffering structure formed of regions of interconnect metal and regions of non-conductive passivation material, the buffering structure providing buffering of underlying layers and structures of the device. | 03-15-2012 |
| 20120094480 | Stacked Coplanar Waveguides Having Signal and Ground Lines Extending Through Plural Layers - An integrated circuit structure includes a semiconductor substrate; an interconnect structure over the semiconductor substrate; a first dielectric layer over the semiconductor substrate and in the interconnect structure; a second dielectric layer in the interconnect structure and over the first dielectric layer; and a wave-guide. The wave-guide includes a first portion in the first dielectric layer and a second portion in the second dielectric layer. The first portion adjoins the second portion. | 04-19-2012 |
| 20120100711 | SINGLE CHIP SEMICONDUCTOR COATING STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a single chip semiconductor coating structure includes following steps. Step | 04-26-2012 |
| 20120122311 | METAL LAYER FORMATION METHOD FOR DIODE CHIPS/WAFERS - An electroless plated metal layer formation method for forming a metal layer on a diode chip/wafer for wire bonding is disclosed to include the step of forming a metal base material on a diode chip/wafer adapted for inducing a reduction system to cause a catalytic reaction at location(s) where the desired metal layer is to be formed, and the step of employing an electroless plating process to form a metal layer on the diode chip/wafer that surrounds the metal base material. An isolation layer may be formed on the metal base layer and opening(s) may be formed on the isolation layer before deposition of the metal layer. | 05-17-2012 |
| 20120142183 | ALUMINUM ENHANCED PALLADIUM CMP PROCESS - A process of forming an integrated circuit using a palladium CMP operation in which 25 to 125 ppm aluminum is added to the CMP slurry, allowing a palladium removal rate of at least 80 nanometers per minute at a polish pad pressure less than 9 psi and a surface speed between 1.9 and 2.2 meters per second. The palladium CMP operation may be applied to form a palladium bond pad cap after which an external bond element is formed on the palladium bond pad cap. Alternatively, the palladium CMP operation may be applied to form a palladium interconnect conductor in a first dielectric layer. | 06-07-2012 |
| 20120171858 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, wherein a first substrate where first electrode pads are formed and a second substrate where second electrode pads are formed are stacked and the first electrode pads and the corresponding second electrode pads are electrically connected thereby forming the semiconductor device is disclosed. The method includes steps of performing a first hydrophilic treatment with respect to the first electrode pads; supplying liquid to a surface where the first electrode pads are formed in the first substrate; and placing the second substrate on the first substrate to which the liquid is supplied so that the surface where the first electrode pads are formed opposes a surface where the second electrode pads are formed, thereby aligning the first electrode pads and the second electrode pads by the liquid that gathers in the first electrode pads that have been subject to the first hydrophilic treatment. | 07-05-2012 |
| 20120220117 | POLYMER AND SOLDER PILLARS FOR CONNECTING CHIP AND CARRIER - A method of connecting chips to chip carriers, ceramic packages, etc. (package substrates) forms smaller than usual first solder balls and polymer pillars on the surface of a semiconductor chip and applies adhesive to the distal ends of the polymer pillars. The method also forms second solder balls, which are similar in size to the first solder balls, on the corresponding surface of the package substrate to which the chip will be attached. Then, the method positions the surface of the semiconductor chip next to the corresponding surface of the package substrate. The adhesive bonds the distal ends of the polymer pillars to the corresponding surface of the package substrate. The method heats the first solder balls and the second solder balls to join the first solder balls and the second solder balls into solder pillars. | 08-30-2012 |
| 20120309186 | CONDUCTIVE STRUCTURE FOR A SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR FORMING THE SAME - A conductive structure for a semiconductor integrated circuit and method for forming the conductive structure are provided. The semiconductor integrated circuit has a pad and a passivation layer partially covering the pad to define a first opening portion having a first lateral size. The conductive structure electrically connects to the pad via the first opening portion. The conductive structure comprises a support layer defining a second opening portion. A conductor is formed in the second opening portion to serve as a bump having a planar top surface. | 12-06-2012 |
| 20120329263 | METHOD OF FORMING A BOND PAD DESIGN FOR IMPROVED ROUTING AND REDUCED PACKAGE STRESS - A method for the fabrication of a semiconductor chip, comprises forming one or more semiconductor devices on a substrate; forming a passivation layer on the substrate; forming a plurality of bond pads on the passivation layer; and forming a plurality of under-bump metallurgy (UBM) layers on respective ones of the plurality of bond pads, wherein at least one of the bond pads has an elongated shape having an elongated portion and a contracted portion, the elongated portion oriented substantially along a stress direction radiating from a center of the chip to the periphery thereof. | 12-27-2012 |
| 20130034955 | SEMICONDUCTOR DEVICE - A technique for expanding an effective area in which a semiconductor structure required for a semiconductor device to function is desired. With the semiconductor device | 02-07-2013 |
| 20130040452 | Methods of Forming Semiconductor Devices Having Narrow Conductive Line Patterns - Semiconductor devices and methods of forming semiconductor devices are provided in which a plurality of patterns are simultaneously formed to have different widths and the pattern densities of some regions are increased using double patterning. The semiconductor device includes a plurality of conductive lines each including a first line portion and a second line portion, where the first line portion extends on a substrate in a first direction, the second line portion extends from one end of the first line portion in a second direction, and the first direction is different from the second direction; a plurality of contact pads each of which is connected with a respective conductive line of the plurality of conductive lines via the second line portion of the corresponding conductive line; and a plurality of dummy conductive lines each including a first dummy portion extending from a respective contact pad of the plurality of contact pads, in parallel with the corresponding second line portion in the second direction. | 02-14-2013 |
| 20130072011 | METHOD OF REPAIRING PROBE PADS - A method that includes forming a first level of active circuitry on a substrate, forming a first probe pad electrically connected to the first level of active circuitry where the first probe pad having a first surface, contacting the first probe pad with a probe tip that displaces a portion of the first probe pad above the first surface, and performing a chemical mechanical polish on the first probe pad to planarize the portion of the first probe pad above the first surface. The method also includes forming a second level of active circuitry overlying the first probe pad, forming a second probe pad electrically connected to the second level of active circuitry, contacting the second probe pad with a probe tip that displaces a portion of the probe pad, and chemically mechanically polishing the second probe pad to remove the portion displaced. | 03-21-2013 |
| 20130130492 | SYSTEM AND METHOD FOR IMPROVING SOLDER JOINT RELIABILITY IN AN INTEGRATED CIRCUIT PACKAGE - Solder joint reliability in an integrated circuit package is improved. Each terminal of a quad, flat, non-leaded integrated circuit package is formed having portions that define a solder slot in the bottom surface of the terminal. An external surface of the die pad of the integrated circuit package is also formed having portions that define a plurality of solder slots on the periphery of the die pad. When solder is applied to the die pad and to the terminals, the solder that fills the solder slots increases the solder joint reliability of the integrated circuit package. | 05-23-2013 |
| 20130130493 | CONNECTING PAD PRODUCING METHOD - A connecting pad producing method has a first process of projecting an insulating member in a surface of a base material such that a region where a connecting pad is formed is surrounded, a second process of forming a conductive layer in the surface of the base material such that the insulating member is coated with the conductive layer, and a third process of removing the conductive layer with which the insulating member is coated, exposing the insulating member over a whole periphery from the conductive layer, and forming the connecting pad including the conductive layer in a region surrounded by the insulating member. The conductive layer with which the insulating member is coated is removed so as not to reach the conductive layer surface in a region adjacent to the insulating member in the third process. | 05-23-2013 |
| 20130137259 | Process for Making Contact with and Housing Integrated Circuits - A process for producing electrical contact connections for a component integrated in a substrate material is provided, the substrate material having a first surface region, and at least one terminal contact being arranged at least partially in the first surface region for each component, which is distinguished in particular by application of a covering to the first surface region and production of at least one contact passage which, in the substrate material, runs transversely with respect to the first surface region, in which process, in order to form at least one contact location in a second surface region which is to be provided, at least one electrical contact connection from the contact location to at least one of the terminal contacts is produced via the respective contact passages. | 05-30-2013 |
| 20130143399 | Method for Forming a Reliable Solderable Contact - A silver-containing solderable contact on a semiconductor die has its outer edge spaced from the confronting edge of an epoxy passivation layer so that, after soldering, silver ions are not present and are not therefor free to migrate under the epoxy layer to form dendrites. | 06-06-2013 |
| 20130149855 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - To provide: a technique capable of suppressing a titanium nitride film that is exposed at the side surface of an opening from turning into a titanium oxide film even when water permeates the opening over a pad from outside a semiconductor device and thus improving the reliability of the semiconductor device; and a technique capable of suppressing a crack from occurring in a surface protective film of a pad and improving the reliability of a semiconductor device. An opening is formed so that the diameter of the opening is smaller than the diameter of another opening and the opening is included in the other opening. Due to this, it is possible to cover the side surface of an antireflection film that is exposed at the side surface of the other opening with a surface protective film in which the opening is formed. As a result of this, it is possible to form a pad without exposing the side surface of the antireflection film. | 06-13-2013 |
| 20130157454 | SELF-ALIGNED WET ETCHING PROCESS - A self-aligned wet etching process comprises the steps of: etching a substrate having an etch protection layer on a surface thereof to form a plurality of trenches spaced from each other; and sequentially forming an insulating layer, an etch stop layer and a primary insulator in each trench, wherein the primary insulator is filled inside an accommodation space surrounded by the etch stop layer. During the wet etching process, the etch stop layer protects the primary insulator from being etched, whereby is achieved anisotropic wet etching. Further, the present invention expands the contact areas for electrically connecting with external circuits and exempts the electric contactors formed on the contact areas from short circuit caused by excessively etching the primary insulators. | 06-20-2013 |
| 20130210222 | SEMICONDUCTOR DEVICES HAVING CONDUCTIVE VIA STRUCTURES AND METHODS FOR FABRICATING THE SAME - In one embodiment, the method includes forming a conductive via structure in a base layer. The base layer has a first surface and a second surface, and the second surface is opposite the first surface. The method further includes removing the second surface of the base layer to expose the conductive via structure such that the conductive via structure protrudes from the second surface, and forming a first lower insulating layer over the second surface such that an end surface of the conductive via structure remains exposed by the first lower insulating layer. | 08-15-2013 |
| 20130217223 | Methods of Stripping Resist After Metal Deposition - In accordance with an embodiment of the present invention, a method of forming a semiconductor device includes forming a seed layer over a dielectric layer and a patterned resist layer over the seed layer. Next, metal lines are formed on regions of the seed layer not covered by the patterned resist layer. The patterned resist layer is removed using a plasma process, which involves using an oxidizing species and a reducing species in the plasma. The reducing species substantially prevents the oxidation of the metal lines and the seed layer during the plasma process. | 08-22-2013 |
| 20130260551 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME - In a semiconductor device, an organic insulation pattern is disposed between first and second rerouting patterns. The organic insulation pattern may absorb the physical stress that occurs when the first and second rerouting patterns expand under heat. Since the organic insulation pattern is disposed between the first and second rerouting patterns, insulating properties can be increased relative to a semiconductor device in which a semiconductor pattern is disposed between rerouting patterns. Also, since a seed layer pattern is disposed between the first and second rerouting patterns and the organic insulation pattern and between the substrate and the organic insulation pattern, the adhesive strength of the first and second rerouting patterns is enhanced. This also reduces any issues with delamination. Also, the seed layer pattern prevents the metal that forms the rerouting pattern from being diffused to the organic insulation pattern. Therefore, a semiconductor device with enhanced reliability may be implemented. | 10-03-2013 |
| 20130267087 | LAYOUT AND PAD FLOOR PLAN OF POWER TRANSISTOR FOR GOOD PERFORMANCE OF SPU AND STOG - A power transistor for use in an audio application is laid out to minimize hot spots. Hot spots are created by non-uniform power dissipation or overly concentrated current densities. The source and drain pads are disposed relative to each other to facilitate uniform power dissipation. Interleaving metal fingers and upper metal layers are connected directly to lower metal layers in the absence of vias to improve current density distribution. This layout improves some fail detection tests by 17%. | 10-10-2013 |
| 20130309860 | SEMICONDUCTOR WAFER PLATING BUS AND METHOD FOR FORMING - A semiconductor wafer includes a die, an edge seal, a bond pad, a plating bus, and trace. The die is adjacent to a saw street. The edge seal is along a perimeter of the die and includes a conductive layer formed in a last interconnect layer of the die. The bond pad is formed as part of metal deposition layer above the last interconnect layer or part of the last interconnect layer. The plating bus is within the saw street. The trace is connected to the bond pad and to the plating bus (1) over the edge seal, insulated from the edge seal, and formed in the metal deposition layer or (2) through the edge seal and insulated from the edge seal. | 11-21-2013 |
| 20130330921 | Plating Process and Structure - A system and method for plating a contact connected to a test pad is provided. An embodiment comprises inserting a blocking material into vias between the contact and the test pad. In another embodiment a blocking structure may be inserted between the contact and the test pad. In yet another embodiment a blocking layer may be inserted into a contact stack. Once the blocking material, the blocking structure, or the blocking layer have been formed, the contact may be plated, with the blocking material, the blocking structure, or the blocking layer reducing or preventing degradation of the test pad due to galvanic effects. | 12-12-2013 |
| 20140051243 | PACKAGE FOR SEMICONDUCTOR DEVICE INCLUDING GUIDE RINGS AND MANUFACTURING METHOD OF THE SAME - An example embodiment relates to a semiconductor package. The semiconductor package includes a first substrate including a first pad, a second substrate upwardly spaced apart from the first substrate and including a second pad opposite to the first pad. At least one electrode is coupled between the first pad and the second pad. The semiconductor package includes a guide ring formed at a periphery of the electrode between the first substrate and the second substrate. | 02-20-2014 |
| 20140113444 | ACTIVE AREA BONDING COMPATIBLE HIGH CURRENT STRUCTURES - A semiconductor structure comprises a top metal layer, a bond pad formed on the top metal layer, a conductor formed below the top metal layer, and an insulation layer separating the conductor from the top metal layer. The top metal layer includes a sub-layer of relatively stiff material compared to the remaining portion of the top metal layer. The sub-layer of relatively stiff material is configured to distribute stresses over the insulation layer to reduce cracking in the insulation layer. | 04-24-2014 |
| 20140170848 | Method of Forming Substrate - A method of forming a substrate is provided, which includes steps of providing a metal plate having a first surface and a second surface; forming a plurality of recesses on the first surface of the metal plate by using laser cutting technique; filling the plurality of recesses with an insulating material; removing a part of the metal plate in a direction of from the second surface to the first surface, so that two ends of the insulating material are exposed, and a substrate body is formed by a conductor portion formed by the remaining part of the metal plate and an insulating portion formed by the insulating material; and forming a circuit layer on a first surface of the substrate body and a circuit layer on a second surface of the substrate body is provided. Thus, the two circuit layers are electrically connected by the conductor portion that also provides a heat dissipation path and are separated by the insulating portion. | 06-19-2014 |
| 20140170849 | PACKAGE SYSTEMS AND MANUFACTURING METHODS THEREOF - A method of forming a package system includes providing a first substrate having a metallic pad and at least one metallic guard ring. The method further includes bonding the metallic pad of the first substrate with a semiconductor pad of a second substrate, wherein the at least one metallic guard ring is configured to at least partially interact with the semiconductor pad to form at least a first portion of an electrical bonding material between the first and second substrates. | 06-19-2014 |
| 20140193970 | ISOLATED WIRE STRUCTURES WITH REDUCED STRESS, METHODS OF MANUFACTURING AND DESIGN STRUCTURES - An integrated circuit (IC) including a set of isolated wire structures disposed within a layer of the IC, methods of manufacturing the same and design structures are disclosed. The method includes forming adjacent wiring structures on a same level, with a space therebetween. The method further includes forming a capping layer over the adjacent wiring structures on the same level, including on a surface of a material between the adjacent wiring structures. The method further includes forming a photosensitive material over the capping layer. The method further includes forming an opening in the photosensitive material between the adjacent wiring structures to expose the capping layer. The method further includes removing the exposed capping layer. | 07-10-2014 |
| 20140193971 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The semiconductor device includes: a semiconductor substrate; an insulating film provided on a surface of the semiconductor substrate; a porous metal film provided on the insulating film; a protective film provided on the porous metal film, and having an opening portion for defining a pad region; and a wire wire-bonded to the porous metal film in the pad region. The stress generated by the impact of wire-bonding is mostly absorbed in the porous metal film owing to the distortion of the porous metal film, preventing generation of cracks in the insulating film. | 07-10-2014 |
| 20140199830 | CHIP PACKAGE AND METHOD FOR FORMING THE SAME - According to an embodiment of the invention, a chip package is provided. The chip package includes: a substrate having an upper surface and a lower surface; a plurality of conducting pads located under the lower surface of the substrate; a dielectric layer located between the conducting pads; a trench extending from the upper surface towards the lower surface of the substrate; a hole extending from a bottom of the trench towards the lower surface of the substrate, wherein a sidewall of the hole is substantially perpendicular to the lower surface of the substrate, and the sidewall or a bottom of the hole exposes a portion of the conducting pads; and a conducting layer located in the hole and electrically connected to at least one of the conducting pads. | 07-17-2014 |
| 20140206184 | INTERPOSER HAVING MOLDED LOW CTE DIELECTRIC - A method for making an interconnection component is disclosed, including forming a plurality of metal posts extending away from a reference surface. Each post is formed having a pair of opposed end surface and an edge surface extending therebetween. A dielectric layer is formed contacting the edge surfaces and filling spaces between adjacent ones of the posts. The dielectric layer has first and second opposed surfaces adjacent the first and second end surfaces. The dielectric layer has a coefficient of thermal expansion of less than 8 ppm/° C. The interconnection component is completed such that it has no interconnects between the first and second end surfaces of the posts that extend in a lateral direction. First and second pluralities of wettable contacts are adjacent the first and second opposed surfaces. The wettable contacts are usable to bond the interconnection component to a microelectronic element or a circuit panel. | 07-24-2014 |
| 20140308809 | BUNDLED MEMORY AND MANUFACTURE METHOD FOR A BUNDLED MEMORY WITH AN EXTERNAL INPUT/OUTPUT BUS - A bundled memory includes a substrate, a first memory die, a second memory die, a scribe line, and an electrical connection. The first memory die has a first input/output bus, and the second memory die has a second input/output bus, where the first memory die and the second memory die are formed over the substrate. The scribe line is formed between the first memory die and the second memory die. The electrical connection is formed over the scribe line for electrically connecting to the first input/output bus and the second input/output bus, where the electrical connection is electrically connected to an external input/output bus, where a size of the external input/output bus of the bundled memory is larger than or equal to a size of the first input/output bus and a size of the second input/output bus. | 10-16-2014 |
| 20140322908 | METHOD OF MAKING BOND PAD - A method of making a bonding pad for a semiconductor device which includes forming a first region over a buffer layer, where the first region includes aluminum and having a first average grain size. The method further includes forming a second region over the first region, where the second region includes aluminum, and where the second region has a second average grain size different from the first average grain size. Additionally, the method includes forming a first passivation layer surrounding the first region and the second region. Furthermore, the method includes forming a second passivation layer partially covering the second region, where the first region and the second region extend along a top surface of the first passivation layer. | 10-30-2014 |
| 20140349475 | MOISTURE BARRIER FOR A WIRE BOND - An electronic device comprising a bond pad on a substrate and a wire bonded to the bond pad. The device further comprises an intermetallic compound interface located between the bond pad and the wire and a silicon nitride or silicon carbonyl layer covering the intermetallic compound interface | 11-27-2014 |
| 20150044863 | SYSTEMS AND METHODS TO FABRICATE A RADIO FREQUENCY INTEGRATED CIRCUIT - To reduce radio frequency (RF) losses during operation of a radio frequency integrated circuit (RFIC) module, the RFIC module is fabricated such that at least one of an edge of the wirebond pad on the copper trace and a sidewall of the copper trace is free from high-resistivity plating material. The unplated portion provides a path for the RF current to flow around the high-resistivity material, which reduces the RF signal loss associated with the high resistivity plating material. | 02-12-2015 |
| 20150347663 | Adjusting Sizes of Connectors of Package Components - A device includes a plurality of connectors on a top surface of a package component. The plurality of connectors includes a first connector having a first lateral dimension, and a second connector having a second lateral dimension. The second lateral dimension is greater than the first lateral dimension. The first and the second lateral dimensions are measured in directions parallel to a major surface of the package component. | 12-03-2015 |
| 20150357296 | HYBRID BONDING MECHANISMS FOR SEMICONDUCTOR WAFERS - A method of forming a hybrid bonding structure includes depositing an etch stop layer over surface of a substrate, wherein the substrate comprises a conductive structure, and the etch stop layer contacts the conductive structure. The method further includes depositing a dielectric material over the etch stop layer. The method further includes depositing a first diffusion barrier layer over the dielectric material. The method further includes forming an opening extending through the etch stop layer, the dielectric material and the diffusion barrier layer. The method further includes lining the opening with a second diffusion barrier layer. The method further includes depositing a conductive pad on the second diffusion barrier layer in the opening, wherein a surface of the first diffusion barrier layer is aligned with a surface of the conductive pad. | 12-10-2015 |
| 20160020183 | METHOD OF MAKING BOND PAD - A method of making a bonding pad for a semiconductor device includes depositing a first region of the bonding pad on a top metal of the semiconductor device at a first temperature, wherein the first region comprises aluminum, and an entirety of a material of the first region of the bonding pad is different from a material of the top metal. The method further includes depositing a second region of the bonding pad on the first region at a second temperature, wherein the first temperature is different from the second temperature, and the second region is a metallic region. | 01-21-2016 |
| 20160133482 | System and Method for an Improved Interconnect Structure - Presented herein are an interconnect structure and method for forming the same. The interconnect structure comprises a contact pad disposed over a substrate and a connector disposed over the substrate and spaced apart from the contact pad. A passivation layer is disposed over the contact pad and over connector, the passivation layer having a contact pad opening, a connector opening, and a mounting pad opening. A post passivation layer comprising a trace and a mounting pad is disposed over the passivation layer. The trace may be disposed in the contact pad opening and contacting the mounting pad, and further disposed in the connector opening and contacting the connector. The mounting pad may be disposed in the mounting pad opening and contacting the opening. The mounting pad may be separated from the trace by a trace gap, which may optionally be at least 10 μm. | 05-12-2016 |
| 20160148893 | WAFER LEVEL PACKAGING USING A CATALYTIC ADHESIVE - Wafer level packaging includes a first layer of a catalytic adhesive on a wafer surface. The catalytic adhesive includes catalytic particles that will reduce electroless copper (Cu) from Cu | 05-26-2016 |
| 20160254238 | Packaging Devices and Methods of Manufacture Thereof | 09-01-2016 |
