| Entries |
| Document | Title | Date |
|---|
| 20080213992 | SEMICONDUCTOR PACKAGE HAVING ENHANCED HEAT DISSIPATION AND METHOD OF FABRICATING THE SAME - A semiconductor package comprising a semiconductor chip and a first heat spreader adhered to the upper surface of the semiconductor chip is provided. The first heat spreader comprises a flat metal plate and a plurality of metal balls adhered to the flat metal plate. A method of fabricating the semiconductor chip package is also provided. | 09-04-2008 |
| 20080261390 | METHOD FOR FORMING BUMPS ON UNDER BUMP METALLURGY - A method for forming metal bumps is provided. A bonding pad is first formed on the active surface of a chip and then a passivation layer is formed on the active surface of the chip and exposes the bonding pad. An under bump metallurgy is formed on the active surface of the chip to overlay the bonding pad. A layer of patterned photoresist is formed on the under bump metallurgy and exposes the portion of the under bump metallurgy on the bonding pad. A layer of copper is plated on the exposed portion of the under bump metallurgy and then a layer of solder is printed on the copper layer. Afterward the solder is reflowed to form a spherical metal bump. Finally, the photoresist layer is removed and the exposed portion of the under bump metallurgy is etched out. | 10-23-2008 |
| 20080293234 | Semiconductor device and manufacturing method of the same - A semiconductor device includes a plurality of electrode layers provided at designated positions of a semiconductor substrate, an organic insulation film formed on the semiconductor substrate by selectively exposing designated areas of the electrode layers, and projection electrodes for outside connection, the projection electrodes being formed on the designated areas of the electrode layers. Thickness of the organic insulation film situated in the vicinity of the periphery of the projection electrodes is greater than thickness of the organic insulation film situated between the projection electrodes. | 11-27-2008 |
| 20090023282 | CONDUCTIVE BALL MOUNTING METHOD AND APPARATUS - There is provided a method of mounting conductive balls on pads on a substrate. The method includes: (a) placing the substrate having the pads coated with an adhesive over a container for containing the conductive balls therein and whose top surface is open such that the pads faces the top surface of the container; and (b) throwing up the conductive balls in the container by moving the container up and down at a given stroke, thereby allowing the conductive balls to adhere to the adhesive coated on the pads. Step (b) is repeatedly performed. | 01-22-2009 |
| 20090035929 | Method of manufacturing semiconductor device - A method of manufacturing a semiconductor device includes: (a) forming an insulating layer having a contact hole on a semiconductor section in which an element is formed; (b) forming an electrode pad on the insulating layer so that a depression or a protrusion remains at a position at which the electrode pad overlaps the contact section; (c) forming a passivation film to have an opening on a first section of the electrode pad and to be positioned on a second section of the electrode pad; (d) forming a barrier layer on the electrode pad; and (e) forming a bump to be larger than the opening in the passivation film and to be partially positioned on the passivation film. The contact section is connected with the second section at a position within a range in which the contact section overlaps the bump while avoiding the first section of the electrode pad. | 02-05-2009 |
| 20090042382 | Device packages - Low volume production of electronic devices having ball attachments, e.g. solder ball arrays, is advantageously achieved using a specific method. In particular a stencil having holes in, for example, the ball grid array pattern is formed by laser ablation of the holes in materials such as paper and polymers. The stencil holes are aligned with corresponding pads on the electronic device. Balls such as solder balls are introduced into the holes and heated to induce adhesion of the balls to the corresponding pads. | 02-12-2009 |
| 20090075469 | THERMO-COMPRESSION BONDED ELECTRICAL INTERCONNECT STRUCTURE AND METHOD - An electrical structure and method for forming electrical interconnects. The method includes positioning a sacrificial carrier substrate such that a first surface of a non-solder metallic core structure within the sacrificial carrier substrate is in contact with a first electrically conductive pad. The first surface is thermo-compression bonded to the first electrically conductive pad. The sacrificial carrier substrate is removed from the non-solder metallic core structure. A solder structure is formed on a second electrically conductive pad. The first substrate comprising the non-solder metallic core structure is positioned such that a second surface of the non-solder metallic core structure is in contact with the solder structure. The solder structure is heated to a temperature sufficient to cause the solder structure to melt and form an electrical and mechanical connection between the second surface of the non-solder metallic core structure and the second electrically conductive pad. | 03-19-2009 |
| 20090081861 | MANUFACTURING METHOD OF SOLDER BALL DISPOSING SURFACE STRUCTURE OF PACKAGE SUBSTRATE - A manufacturing method of a solder ball disposing surface structure on a core board including: providing a core board with a first metal layer and an opposing metal bump-equipped second metal layer; forming resists on the first and second metal layers respectively; forming third, fourth and fifth openings in the resists; removing the first and second metal layers in the third and fourth openings to form first and second circuit layers and metal pads respectively; removing the metal bumps in the fifth openings to form metal flanges; removing the resists; forming first and second insulative protection layers on the first and second circuit layers and metal pads respectively; forming first and second openings in the first and second insulative protection layers to expose the first circuit layer as electrical connecting pads and expose the metal flanges respectively. Accordingly, increased contact surface area for mounting conductive elements prevents detachment thereof. | 03-26-2009 |
| 20090093110 | BGA package having half-etched bonding pad and cut plating line and method of fabricating same - A ball grid array (BGA) package having a half-etched bonding pad and a cut plating line and a method of fabricating the same. In the BGA package, the plating line is cut to form a predetermined uneven bonding pad using half-etching, thereby increasing the contact area between the bonding pad and a solder ball. The BGA package includes a first external layer having a first circuit pattern and a wire bonding pad pattern wherein a chip is connected to a wire bonding pad using wire bonding. A second external layer includes a second circuit pattern, a cut plating line pattern, and a half-etched uneven solder ball pad pattern. In the second external layer, another chip is mounted on a solder ball pad. An insulating layer having a through hole interposed between the first and second external layers and electrically connects the first and second external layers therethrough. | 04-09-2009 |
| 20090104766 | Method of Forming Micro Metal Bump - The present invention provides a method of forming a micro metal bump, which is capable of stably and industrially forming a micro metal bump, by a gas deposition process, at a prescribed position of a metal part formed on one side surface of a substrate. The method comprises the steps of: forming a straight hole ( | 04-23-2009 |
| 20090111259 | METHODS FOR FORMING CONNECTIVE ELEMENTS ON INTEGRATED CIRCUITS FOR PACKAGING APPLICATIONS - Methods for forming connective elements on integrated circuits for packaging applications are provided herein. In some embodiments, a method of forming connective elements on an integrated circuit for flipchip packaging may include providing a resist layer on the integrated circuit; forming a plurality of holes through the resist layer; filling the plurality of holes with conductive material; and stripping at least a portion of the resist layer using a stripping solution containing acetic anhydride and ozone to expose the connective elements. | 04-30-2009 |
| 20090117729 | Electrostatic Discharge (ESD) Protection Structure - A semiconductor device has a substrate with a plurality of active devices formed thereon. A contact pad is formed on the substrate. A solder bump is formed on the contact pad. An electrostatic discharge (ESD) bump electrode is formed on the contact pad. The ESD bump electrode has a tip. The ESD bump electrode is made with gold. A chip carrier substrate has a contact pad metallurgically connected to the solder bump. The chip carrier substrate also has a ground plate. The ground plate is a low impedance ground point. The tip of the ESD bump electrode is separated from the ground plate by a distance according to ESD sensitivity of the active devices. The distance is determined by a ratio of a discharging threshold voltage for ESD sensitivity of the active device to be protected to an atmosphere discharging voltage. | 05-07-2009 |
| 20090117730 | MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED DEVICE - Manufacture of semiconductor products such as LCD driver requires a bump plating step for forming a gold bump electrode having a size of from about 15 to 20 μm. This bump plating step is performed by electroplating with a predetermined plating solution, but projections intermittently appear on the bump electrode during a mass production process. In the invention, abnormal growth of projections over the gold bump electrode is prevented by adding, prior to the gold bump plating step, a step of circulating and stirring a plating solution while erecting a plating cup and efficiently dissolving/discharging a precipitate. This step is performed for each wafer to be treated. | 05-07-2009 |
| 20090124074 | WAFER LEVEL SENSING PACKAGE AND MANUFACTURING PROCESS THEREOF - A wafer level sensing package and manufacturing process thereof are described. The process includes providing a wafer having sensing chips, in which each sensing chip has a sensing area and pads; forming a stress release layer on a wafer surface; cladding a photoresist layer on the stress release layer; patterning the photoresist layer to expose the pads and a portion of the stress release layer, without exposing opening areas of the sensing areas; forming a conductive metal layer of re-distributed pads on the portion of the stress release layer exposed by the photoresist layer; removing the photoresist layer; forming a re-cladding photoresist layer on the stress release layer and the conductive metal layer; forming holes in the re-cladding photoresist layer above the re-distributed pad area; and forming conductive bumps in the holes to electrically connect to the conductive metal layer. | 05-14-2009 |
| 20090130838 | METHOD OF FORMING CONDUCTIVE BUMPS - A method of forming a conductive bump of the present invention, includes the steps of, preparing a substrate including a connection pad and a protection insulating layer, in which an opening portion is provided on the connection pad, on a surface layer side, arranging a first conductive ball, at least an outer surface portion of which is made of solder, on the connection pad in the opening portion of the protection insulating layer, filling a solder layer in the opening portion by applying a reflow heating to the first conductive ball, arranging a second conductive ball on the solder layer, and obtaining a conductive bump which protrudes from an upper surface of the protection insulating layer, by joining the solder layer and the second conductive ball by a reflow heating. | 05-21-2009 |
| 20090130839 | MANUFACTURING METHOD OF REDISTRIBUTION CIRCUIT STRUCTURE - A method of manufacturing a redistribution circuit structure is provided. First, a substrate is provided. The substrate has a plurality of pads and a passivation layer. The passivation layer has a plurality of first openings exposing a portion of each of the pads, respectively. A first patterned photoresist layer is formed on the passivation layer. The first patterned photoresist layer has a plurality of second openings exposing a portion of each of the pads. A plurality of first bumps is formed in the second openings, respectively. An under ball metal (UBM) material layer is formed over the substrate to cover the first patterned photoresist layer and the first bumps. A plurality of conductive lines is formed on the UBM material layer. The UBM material layer is patterned to form a plurality of UBM layers using the conductive lines as a mask. | 05-21-2009 |
| 20090149014 | METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE | 06-11-2009 |
| 20090149015 | MANUFACTURING METHOD OF CONTACT STRUCTURE - A manufacturing method of a contact structure includes first providing a substrate on which a contact pad has already been formed. Afterwards, a polymer bump is formed on the contact pad. Next, a conductive layer is formed on the polymer bump. The conductive layer covers the polymer bump and extends to the outside of the polymer bump. The portion of the conductive layer extending to the outside of the polymer bump serves as a test pad. | 06-11-2009 |
| 20090155993 | TERMINAL PAD STRUCTURES AND METHODS OF FABRICATING SAME - Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process. | 06-18-2009 |
| 20090176363 | Etching composition for an under-bump metallurgy layer and method of forming a bump structure using the same - In an etching composition for an under-bump metallurgy (UBM) layer and a method of forming a bump structure, the etching composition includes about 40% by weight to about 90% by weight of hydrogen peroxide (H | 07-09-2009 |
| 20090191701 | MICROELECTRONIC DEVICES AND METHODS FOR FORMING INTERCONNECTS IN MICROELECTRONIC DEVICES - Microelectronic devices, methods for packaging microelectronic devices, and methods for forming interconnects in microelectronic devices are disclosed herein. In one embodiment, a method comprises providing a microelectronic substrate having a front side and a backside. The substrate has a microelectronic die including an integrated circuit and a terminal operatively coupled to the integrated circuit. The method also includes forming a passage at least partially through the substrate and having an opening at the front side and/or backside of the substrate. The method further includes sealing the opening with a conductive cap that closes one end of the passage while another end of the passage remains open. The method then includes filling the passage with a conductive material. | 07-30-2009 |
| 20090253259 | Solder ball attachment jig and method for manufacturing semiconductor device using the same - Disclosed are a solder attachment jig and a method of manufacturing a semiconductor device using the same. The solder ball attachment jig, which arranges a solder ball to be aligned with a conductive post of a semiconductor wafer, can include a body and a receiving hole, which is formed on the body to hold the solder ball. Internal walls of the receiving hole that face each other are symmetrically inclined. Using the solder ball attachment jig in accordance with an embodiment of the present invention, the alignment of the solder ball can be improved while reducing the cost and simplifying the processes. | 10-08-2009 |
| 20090258486 | SEMICONDUCTOR DEVICE FABRICATION METHOD - A method of forming a semiconductor device including a semiconductor substrate with circuit elements and electrode pads formed on one surface. This surface is covered by a dielectric layer with openings above the electrode pads. A metal layer is deposited on the dielectric layer and patterned to form a conductive pattern with traces leading to the electrode pads. A protective layer having openings exposing part of the conductive pattern is formed. Each opening is covered by an electrode such as a solder bump, which is electrically connected through the conductive pattern to one of the electrode pads. The method enables the thickness of the protective layer, which may function as a package of the semiconductor device, to be reduced. The protective layer may be formed from a photosensitive material, simplifying the formation of the openings for the electrodes. | 10-15-2009 |
| 20090275192 | MOLDED DIELECTRIC LAYER IN PRINT-PATTERNED ELECTRONIC CIRCUITS - A method forms a first active electronic layer, prints an array of pillars on the first active electronic layer, dispenses a curable polymer over the array of pillars, molds the curable polymer by contacting the curable polymer with a mold structure to displace the curable polymer from upper surfaces of the pillars, cures the curable polymer to produce a hardened polymer, and removes the array of pillars to leave an array of holes in the hardened polymer. Another method provides a substrate having selected areas, prints an array of pillars on the substrate, dispenses a curable polymer over the array of pillars, molds the curable polymer by contacting the array of pillars with a mold structure to displace the curable polymer from upper surfaces of the pillars, cures the curable polymer to produce a hardened polymer, and removes the array of pillars to leave an array of holes in the hardened polymer corresponding to the selected areas. Another method forms a first active electronic layer on a substrate, prints an array of conductive pillars on the active electronic layer on a substrate, dispenses a curable polymer on the array of conductive pillars, molds the curable polymer by contacting the array of pillars with a mold structure to displace the curable polymer from the upper surfaces of the conductive pillars, curing the curable polymer to produce a hardened polymer, and forms a second active electronic layer on the hardened polymer such that the second active electronic layer is in electrical connection with the first active electronic layer through the conductive pillars. | 11-05-2009 |
| 20090286390 | METHOD OF PACKAGING A SEMICONDUCTOR DEVICE AND A PREFABRICATED CONNECTOR - A method of packaging a first device having a first major surface and a second major surface includes forming a first layer over a second major surface of the first device and around sides of the first device and leaving the first major surface of the first device exposed, wherein the first layer is selected from the group consisting of an encapsulant and a polymer; forming a first dielectric layer over the first major surface of the first device, forming a via in the first dielectric layer, forming a seed layer within the via and over a portion of the first dielectric layer, physically coupling a connector to the seed layer, and plating a conductive material over the seed layer to form a first interconnect in the first via and over a portion of the first dielectric layer. | 11-19-2009 |
| 20090298277 | Maskless Process for Solder Bumps Production - Methods of producing a solder bump are presented. Preferred methods lack a requirement for photoresist processing or masking a target substrate. Contemplated methods include forming a well around one or more bond pads on a wafer where the walls of the well are formed by a passivation layer material. Contact material can comprise a solder paste or an under bump metallization layer, which can be placed within the wells as a contact bed for solder balls. A priori prepared solder balls, in solid form or in molten form, can deposited on the contact material to produce the solder bump. | 12-03-2009 |
| 20090305494 | Bump structure for a semiconductor device and method of manufacture - A semiconductor device employing the bump structure includes a plurality of bump structures arrayed along a substrate in a first direction. Each bump structure has a width in the first direction greater than a pitch gap between successively arrayed bump structures, and at least one bump structure has a sidewall facing in the first direction that is non-conductive. | 12-10-2009 |
| 20090317969 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND METHOD AND STRUCTURE FOR IMPLEMENTING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming an electrode; forming a projection projecting with respect to the electrode by melting a resin; and providing a conductive layer electrically connected to the electrode. The conductive layer is extended to an upper surface of the projection. Therefore, productivity of the semiconductor is improved. | 12-24-2009 |
| 20090325375 | REDUCING LEAKAGE IN DIELECTRIC MATERIALS INCLUDING METAL REGIONS INCLUDING A METAL CAP LAYER IN SEMICONDUCTOR DEVICES - By introducing an additional heat treatment prior to and/or after contacting a sensitive dielectric material with wet chemical agents, such as an electrolyte solution, enhanced performance with respect to leakage currents or dielectric strength may be accomplished during the fabrication of advanced semiconductor devices. For example, metal cap layers for metal lines may be provided on the basis of electroless deposition techniques, wherein the additional heat treatment(s) may provide the required electrical performance. | 12-31-2009 |
| 20100015794 | PACKAGING CONDUCTIVE STRUCTURE AND METHOD FOR FORMING THE SAME - A packaging conductive structure for a semiconductor substrate and a method for forming the structure are provided. The dielectric layer of the packaging conductive structure partially overlays the metallic layer of the semiconductor substrate and has a receiving space. The lifting layer and conductive layer are formed in the receiving space, wherein the conductive layer extends for connection to a bump. The lifting layer is partially connected to the dielectric layer. As a result, the conductive layer can be stably deposited on the edge of the dielectric layer for enhancing the reliability of the packaging conductive structure. | 01-21-2010 |
| 20100015795 | SEMICONDUCTOR DEVICE HAVING PROJECTING ELECTRODE FORMED BY ELECTROLYTIC PLATING, AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a semiconductor substrate, and a plurality of wiring lines provided on one side of the semiconductor substrate, each of the wiring lines having a connection pad portion. An overcoat film is provided on the wiring lines and the one side of the semiconductor substrate. The overcoat film has a plurality of openings in parts corresponding to the connection pad portions of the wiring lines. A plurality of foundation metal layers are respectively provided on inner surfaces of the openings of the overcoat film and electrically connected to the pat portions of the wiring lines. A plurality of projecting electrodes are respectively provided on the foundation metal layers in the openings of the overcoat film. | 01-21-2010 |
| 20100029074 | Maskless Process for Solder Bump Production - Methods of producing a solder bump are presented. Preferred methods lack a requirement for masking a target substrate. Contemplated methods include forming a well around one or more bond pads on a wafer where the walls of the well are formed by a covering layer material, possibly comprising photoresist or passivation material. The well can be filled with a contact material. Contact material can comprise a solder paste or an under bump metallization layer, which can be placed within the wells as a contact bed for solder balls. A priori prepared solder balls, in solid form or in molten form, can deposited on the contact material to produce the solder bump. | 02-04-2010 |
| 20100055895 | Electrically conductive structure on a semiconductor substrate formed from printing - Provided are methods for forming an electrically conductive structure of a desired three-dimensional shape on a substantially planar surface of a substrate, e.g., a semiconductor wafer. Typically, the particulate matter is deposited in a layer-by-layer manner and adhered to selected regions on the substrate surface. The particulate matter may be deposited to produce a mold for forming the structure and/or to produce the structure itself. A three-dimensional printer with associated electronic data may be used without the need of a lithographic mask or reticle. | 03-04-2010 |
| 20100062597 | Interconnection for flip-chip using lead-free solders and having improved reaction barrier layers - An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components. | 03-11-2010 |
| 20100075493 | METHOD OF FORMING ELECTRODE CONNECTING PORTION - A manufacturing method for an electrode connecting portion includes covering an electrode forming surface with a solder sheet, rolling a heating roller on the solder sheet that covers the electrode forming surface, and removing the solder sheet after the heating roller has passed over the solder sheet. | 03-25-2010 |
| 20100144136 | SEMICONDUCTOR DEVICE WITH SOLDER BALLS HAVING HIGH RELIABILITY - A semiconductor device includes a substrate, a metal layer, an alloy layer and a Sn—Ag—Cu-based solder ball. The metal layer is configured to be formed on the substrate. The alloy layer is configured to be formed on the metal layer. The Sn—Ag—Cu-based solder ball is configured to be placed on the alloy layer. The alloy layer includes Ni and Zn as essential elements. | 06-10-2010 |
| 20100151670 | Methods Of Adding Pads And One Or More Interconnect Layers To The Passivated Topside Of A Wafer Including Connections To At Least A Portion Of The Integrated Circuit Pads Thereon - A pattern of conductive ink is disposed on the topside of the unsingulated integrated circuits of a wafer, and, typically after wafer probing, the pattern of conductive ink is removed. The conductive ink pattern provides an electrical pathway between bond pads on an integrated circuit and large contact pads disposed on the topside of the integrated circuit. Each of the large contact pads is much greater in area than the corresponding bond pads, and are spaced apart so that the pitch of the large contact pads is much greater than that of the bond pads. In one aspect of the present invention, the conductive ink includes a mixture of conductive particles and wafer bonding thermoset plastic. In another aspect of the present invention, the conductive ink is heated and disposed on a wafer by an ink jet printing system. | 06-17-2010 |
| 20100159691 | PHOTOSENSITIVE RESIN COMPOSITION AND LAMINATE - Disclosed is a photosensitive resin composition showing excellent contrast performance after exposure to light. Also disclosed is a photosensitive resin laminate using the composition. The photosensitive resin composition comprises (a) 20 to 90% by mass of a binder having a carboxyl group, (b) 5 to 75% by mass of an addition-polymerizable monomer having at least one ethylenically unsaturated terminal group, (c) 0.01 to 30% by mass of a photopolymerization initiator, and (d) 0.01 to 10% by mass of a leuco dye, wherein a specific binder is contained as the binder (a) and a specific monomer is contained as the addition-polymerizable monomer (b). | 06-24-2010 |
| 20100159692 | ATTACHMENT USING MAGNETIC PARTICLE BASED SOLDER COMPOSITES - Electronic devices and methods for fabricating electronic devices are described. One method includes providing a first body with a plurality of composite bumps thereon, the composite bumps comprising a solder and magnetic particles. The method also includes applying a magnetic field to the magnetic particles to generate sufficient heat to melt the solder and form molten bump regions containing the magnetic particles therein. The method also includes coupling a second body to the first body through the molten bump regions, and cooling the molten bump regions to form solidified composite bumps coupling the second body to the first body. Other embodiments are described and claimed. | 06-24-2010 |
| 20100178761 | Stacked Integrated Chips and Methods of Fabrication Thereof - Structure and methods of forming stacked semiconductor chips are described. In one embodiment, a method of forming a semiconductor chip includes forming an opening for a through substrate via from a top surface of a first substrate. The sidewalls of the opening are lined with an insulating liner and the opened filled with a conductive fill material. The first substrate is etched from an opposite bottom surface to form a protrusion, the protrusion being covered with the insulating liner. A resist layer is deposited around the protrusion to expose a portion of the insulating liner. The exposed insulating liner is etched to form a sidewall spacer along the protrusion. | 07-15-2010 |
| 20100203720 | SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME FOR DECREASING NUMBER OF PROCESSES - A semiconductor package and a method for manufacturing the same. The semiconductor package includes a semiconductor chip having bonding pads; a first insulation layer pattern; redistribution line patterns; a second insulation layer pattern; and conductive balls. The first insulation layer pattern having first openings exposing the bonding pads. The redistribution line patterns are located on the first insulation layer pattern and are electrically connected with the bonding pads. The second insulation layer pattern covering the redistribution line patterns and having second openings having first open areas which expose portions of the redistribution line patterns and having second open areas which extend from the first open areas along the semiconductor chip. The conductive balls are electrically connected with the portions of the redistribution line patterns which are exposed through the first open areas of the second insulation layer pattern. | 08-12-2010 |
| 20100203721 | MULTI-COMPONENT INTEGRATED CIRCUIT CONTACTS - An integrated circuit connection is describe that includes a first, securing member and a second, connection member. The first member, in an embodiment, is a spike that has a portion of its body fixed in a layer of an integrated circuit structure and extends outwardly from the integrated circuit structure. The second material is adapted to form a mechanical connection to a further electrical device. The second material (e.g., solder), is held by the first member to the integrated circuit structure. The first member increases the strength of the connection and assists in controlling the collapse of second member to form the mechanical connection to another circuit. The connection is formed by coating the integrated circuit structure with a patterned resist and etching the layer beneath the resist. A first member material (e.g., metal) is deposited. The resist is removed. The collapsible material is fixed to the first member. | 08-12-2010 |
| 20100216302 | Lead-free tin alloy electroplating compositions and methods - Disclosed are electrolyte compositions for depositing a tin alloy on a substrate. The electrolyte compositions include tin ions, ions of one or more alloying metals, a flavone compound and a dihydroxy bis-sulfide. The electrolyte compositions are free of lead and cyanide. Also disclosed are methods of depositing a tin alloy on a substrate and methods of forming an interconnect bump on a semiconductor device. | 08-26-2010 |
| 20100221908 | Manufacturing method of semiconductor device - Disclosed is a method of manufacturing a semiconductor device that does not have a defect, such as wire breakage, due to an uplifted portion created at a rewiring pattern in a multilayer wire structure. Before a wiring layer is formed on an insulation layer, the insulation layer is exposed via a mask. The mask has a weak exposure part and a strong exposure part. The mask is positioned such that the weak exposure part corresponds to an arrangement position of a wire line of an underlying wiring layer, and such that the strong exposure part corresponds to an arrangement position of a via part of the underlying wiring layer. The underlying wiring layer is a layer immediately below the insulation layer. | 09-02-2010 |
| 20100221909 | METHOD FOR MAKING AN ELECTRIC INTERCONNECTION BETWEEN TWO CONDUCTING LAYERS - This method for making an electric interconnection between two conducting layers separated by at least one insulation or semi-conducting layer, comprises forming a stud extending at least between the lower conducting layer and the upper conducting layer, wherein the nature and/or the shape of said stud impart non-wettability properties relative to the material used for the separating layer. | 09-02-2010 |
| 20100221910 | METHOD OF PRODUCING SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor substrate having an internal circuit; an electrode pad electrically connected to the internal circuit; an insulating film having a through hole exposing the electrode pad; and a re-distribution wiring pattern formed on the insulating film and electrically connected to the electrode pad. The semiconductor device further includes a recess groove formed in the insulating film around and adjacent to the re-distribution wiring pattern. | 09-02-2010 |
| 20100330798 | Formation of TSV Backside Interconnects by Modifying Carrier Wafers - An integrated circuit structure includes a semiconductor wafer, which includes a first notch extending from an edge of the semiconductor wafer into the semiconductor wafer. A carrier wafer is mounted onto the semiconductor wafer. The carrier wafer has a second notch overlapping at least a portion of the first notch. A side of the carrier wafer facing the semiconductor wafer forms a sharp angle with an edge of the carrier wafer. The carrier wafer has a resistivity lower than about 1×10 | 12-30-2010 |
| 20110014785 | Method for manufacturing semiconductor device, and semiconductor manufacturing apparatus used in said method - This method includes an electrode pad forming process for forming an electrode pad on a substrate, a solder bump forming process for forming a solder bump on the electrode pad, at least part of the surface of the solder bump being covered with a flux, and an oxygen exposure process for supplying an oxygen gas having reactive properties, such as an ozone (O | 01-20-2011 |
| 20110027984 | PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A CONDUCTIVE STUD OVER A BONDING PAD REGION - An electronic device can include an interconnect level including a bonding pad region. An insulating layer can overlie the interconnect level and include an opening over the bonding pad region. In one embodiment, a conductive stud can lie within the opening and can be substantially encapsulated. In another embodiment, the electronic device can include a barrier layer lying along a side and a bottom of the opening and a conductive stud lying within the opening. The conductive stud can substantially fill the opening. A majority of the conductive stud can lie within the opening. In still another embodiment, a process for forming an electronic device can include forming a conductive stud within the opening wherein from a top view, the conductive stud lies substantially completely within the opening. The process can also include forming a second barrier layer overlying the conductive stud. | 02-03-2011 |
| 20110034022 | SEMICONDUCTOR PACKAGE AND FABRICATION METHOD - A semiconductor package and a fabrication method thereof are disclosed, whereby an environmental problem is solved by using external connection terminals or semiconductor element-mounting terminals containing a smaller amount of lead, while at the same time achieving a fine pitch of the terminals. The semiconductor package includes a board ( | 02-10-2011 |
| 20110059606 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND MASK - A photosensitive resin film is formed on a protective insulating film. Next, a plurality of bump cores is formed on the protective insulating film along a first straight line by exposing and developing the photosensitive resin film. Next, a plurality of bumps, and a plurality of interconnects that connects each of the plurality of bumps to any of the electrode pads are formed by selectively forming conductive films on a plurality of bump cores, a plurality of electrode pads, and the protective insulating film. In the step of forming a plurality of bump cores, a region bordering on the interconnect on the lateral faces of the bump core is formed to have a gentler slope than that of a region intersecting the first straight line, by exposing the photosensitive resin film only one time using a multi-gradation mask. | 03-10-2011 |
| 20110092065 | SEMICONDUCTOR DEVICE SUITABLE FOR A STACKED STRUCTURE - A semiconductor device is provided that forms a three-dimensional semiconductor device having semiconductor devices stacked on one another. In this semiconductor device, a hole is formed in a silicon semiconductor substrate that has an integrated circuit unit and an electrode pad formed on a principal surface on the outer side. The hole is formed by etching, with the electrode pad serving as an etching stopper layer. An embedded electrode is formed in the hole. This embedded electrode serves to electrically lead the electrode pad to the principal surface on the bottom side of the silicon semiconductor substrate. | 04-21-2011 |
| 20110117736 | MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - When relatively hard Au bump electrodes are mass-produced by electrolytic plating while ensuring usually required properties such as a non-glossy property and shape-flatness, combination of conditions, such as low liquid temperature, high current density, and low concentration of added Tl (thallium) that is an adjuvant, will be selected by itself. However, in such conditions, there is a problem that it is difficult to maintain the Tl concentration in a plating solution and, when the Tl concentration is reduced, defective appearance of the Au bump electrodes is generated by anomalous deposition. Conventionally, there has been no means to directly monitor minute Tl concentration and the Tl concentration has been controlled by analyzing the plating solution periodically. However, this cannot prevent generation of a lot of defective products. | 05-19-2011 |
| 20110129994 | Method of manufacturing a dual face package - A method of manufacturing a dual face package, including: preparing an upper substrate composed of an insulating layer including a post via-hole; forming a filled electrode in a semiconductor substrate, the filled electrode being connected to a die pad; applying an adhesive layer on one side of the semiconductor substrate including the filled electrode, and attaching the upper substrate to the semiconductor substrate; cutting another side of the semiconductor substrate in a thickness direction, thus making the filled electrode into a through-electrode; and forming a post electrode in the post via-hole, forming an upper redistribution layer connected to the post electrode of the semiconductor substrate, and forming a lower redistribution layer connected to the through-electrode on the other side of the semiconductor substrate. | 06-02-2011 |
| 20110136336 | METHODS OF FORMING CONDUCTIVE VIAS - Methods of forming a conductive via may include forming a blind via hole partially through a substrate, forming an aluminum film on surfaces of the substrate, removing a first portion of the aluminum film from some surfaces, selectively depositing conductive material onto a second portion of the aluminum film, and exposing the blind via hole through a back side of the substrate. Methods of fabricating a conductive via may include forming at least one via hole through at least one unplated bond pad, forming a first adhesive over at least one surface of the at least one via hole, forming a dielectric over the first adhesive, forming a base layer over the dielectric and the at least one unplated bond pad, and plating nickel onto the base layer. | 06-09-2011 |
| 20110195567 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device comprises: immersing a semiconductor substrates in a Pd activating solution containing Pd ions and adhering a Pd catalyst to a surface of the semiconductor substrate; and immersing the semiconductor substrate, to which the Pd catalyst is adhered, in a Pd electroless plating solution and forming an electroless-plated Pd film on the semiconductor substrate. | 08-11-2011 |
| 20110195568 | SEMICONDUCTOR STRUCTURE, METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE AND SEMICONDUCTOR PACKAGE - A semiconductor structure, a method for manufacturing a semiconductor structure and a semiconductor package are provided. The method for manufacturing a semiconductor structure includes the following steps. Firstly, a silicon substrate is provided. Next, a part of the silicon substrate is removed to form a ring hole and a silicon pillar surrounded by the silicon pillar. Then, a photosensitive material is disposed in the ring hole, wherein the photosensitive material is insulating. After that, the silicon pillar is removed, such that the ring hole forms a through hole and the photosensitive material covers a lateral wall of the through hole. Lastly, the conductive material is disposed in the through hole, wherein the outer surface of the conductive material is surrounded by the photosensitive material. | 08-11-2011 |
| 20110201194 | Direct IMS (Injection Molded Solder) Without a Mask for Forming Solder Bumps on Substrates - An assembly is obtained; it includes a substrate; a plurality of wet-able pads formed on a surface of the substrate; and a solder resist layer deposited on the surface of the substrate and having an outer surface. At least the solder resist layer is formed with recessed regions defining volumes adjacent the wet-able pads. Molten solder is directly injected into the volumes adjacent the wet-able pads, such that the volumes adjacent the wet-able pads are filled with solder. The solder is allowed to solidify. It forms a plurality of solder structures adhered to the wet-able pads. The substrate and the solder are re-heated after the solidification, to re-flow the solder into generally spherical balls extending above the outer surface of the solder resist layer. The volumes adjacent the wet-able pads are configured and dimensioned to receive sufficient solder in the injecting step such that the generally spherical balls extend above the outer surface of the solder resist layer as a result of the re-heating step. In an alternative approach, solder injection and solidification are carried out in a nitrogen environment or a forming gas environment, and the reflow step may be omitted. | 08-18-2011 |
| 20110201195 | FLIP CHIP MOUNTING METHOD AND BUMP FORMING METHOD - The invention involves mounting a solder resin composition ( | 08-18-2011 |
| 20110212614 | MICROELECTRONIC WORKPIECES AND METHOD FOR MANUFACTURING MICROELECTRONIC DEVICES USING SUCH WORKPIECES - Microelectronic workpieces and methods for manufacturing microelectronic devices using such workpieces are disclosed. In one embodiment, a microelectronic assembly comprises a support member having a first side and a projection extending away from the first side. The assembly also includes a plurality of conductive traces at the first side of the support member. Some of the conductive traces include bond sites carried by the projection and having an outer surface at a first distance from the first side of the support member. The assembly further includes a protective coating deposited over the first side of the support member and at least a portion of the conductive traces. The protective coating has a major outer surface at a second distance from the first side of the support member. The second distance is approximately the same as the first distance such that the outer surface of the protective coating is generally co-planar with the outer surface of the bond sites carried by the projection. In several embodiments, a microelectronic die can be coupled to the corresponding bond sites carried by the projection in a flip-chip configuration. | 09-01-2011 |
| 20110230043 | TAPE RESIDUE-FREE BUMP AREA AFTER WAFER BACK GRINDING - Organic-adhesive tapes are often used to secure and protect the bumps during wafer processing after bump formation. While residual organic-adhesive tape may remain on the wafer after tape de-lamination, applying a bump template layer on the bumps before laminating the tape allows any residue to be removed afterwards and results in a residue-free wafer. | 09-22-2011 |
| 20110230044 | CONTACT STRUCTURE HAVING A COMPLIANT BUMP AND A TESTING AREA AND MANUFACTURING METHOD FOR THE SAME - A contact structure having both a compliant bump and a testing area and a manufacturing method for the same is introduced. The compliant bump is formed on a conductive contact of the silicon wafer or a printed circuit board. The core of the bump is made of polymeric material, and coated with a conductive material. In particular, the compliant bump is disposed on the one side of the conductive contact structure that includes both the bump and the testing area, wherein the testing area allows the area to be functionality tested, so as to prevent damage of the coated conductive material over the compliant bump during a probe testing. | 09-22-2011 |
| 20110269306 | SOLDER BUMP, ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING THE ELECTRONIC COMPONENT - An electronic component includes a plurality of first electrode pads arranged on a first substrate, a plurality of second electrode pads arranged at positions corresponding to the first electrode pads on a second substrate and a plurality of solder bumps which join together the first electrode pads and the second electrode pads. Here, the first substrate is located over the second substrate so that the first electrode pads and the second electrode pads are at positions which are shifted from opposite positions where the first electrode pads opposite to the second electrode pads, and at least a part of the solder bumps are solidified into hourglass-shaped. | 11-03-2011 |
| 20110300705 | MANUFACTURING METHOD OF BUMP STRUCTURE WITH ANNULAR SUPPORT - A manufacturing method of a bump structure with an annular support includes the following steps. A substrate including pads and a passivation layer is provided. The passivation has first openings exposing a portion of the pads. An UBM material layer is formed to cover the passivation layer and the pads. A patterned photoresist layer, having second openings respectively exposing the UBM material layer over the pads, is formed on the UBM material layer. A diameter of each second opening located on a lower surface of the patterned photoresist layer is less than that located on an upper surface of the patterned photoresist layer. Bumps are formed in the second openings. A portion of the patterned photoresist layer is removed to form an annular support at a periphery of each bump. The UBM material layer is patterned using the annular supports and the bumps as masks to form UBM layers. | 12-08-2011 |
| 20120009775 | SEMICONDUCTOR PACKAGE WITH A REDUCED VOLUME AND THICKNESS AND CAPABLE OF HIGH SPEED OPERATION AND METHOD FOR FABRICATING THE SAME - A semiconductor package includes a semiconductor chip provided with a bonding pad disposed over a surface thereof; a through electrode passing from the surface to a second surface opposing the first surface and connected electrically with the bonding pad; and a redistribution disposed at the second surface and connected electrically with the through electrode. An embodiment of the present invention is capable of significantly reducing the thickness and volume of the semiconductor package. It is also capable of high speed operation since the path of the signal inputted and/or outputted from the semiconductor package is is shortened. It is capable of stacking easily at least two semiconductor packages having a wafer level, and it is capable of significantly reducing parasitic capacitance. | 01-12-2012 |
| 20120009776 | SEMICONDUCTOR SUBSTRATES WITH UNITARY VIAS AND VIA TERMINALS, AND ASSOCIATED SYSTEMS AND METHODS - Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative method in accordance with a particular embodiment includes forming a blind via in a semiconductor substrate, applying a protective layer to a sidewall surface of the via, and forming a terminal opening by selectively removing substrate material from an end surface of the via, while protecting from removal substrate material against which the protective coating is applied. The method can further include disposing a conductive material in both the via and the terminal opening to form an electrically conductive terminal that is unitary with conductive material in the via. Substrate material adjacent to the terminal can then be removed to expose the terminal, which can then be connected to a conductive structure external to the substrate. | 01-12-2012 |
| 20120058636 | COMPOSITION FOR REMOVING A PHOTORESIST AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE COMPOSITION - Provided are a composition for removing a photoresist and a method of manufacturing a semiconductor device using the composition. The composition includes about 60-90 wt % of dimethyl sulfoxide, about 10-30 wt % of a polar organic solvent, about 0.5-1.5 wt % of hydroxy alkyl ammonium and about 1-10 wt % of an amine containing no hydroxyl group. | 03-08-2012 |
| 20120083113 | CREATION OF LEAD-FREE SOLDER JOINT WITH INTERMETALLICS - A method of coupling an integrated circuit to a substrate includes providing the substrate, forming a contact pad in the substrate, contacting the contact pad with a solder ball, and repeatedly exposing the solder ball to a thermal process to cause intermetallics based on a metal in the contact pad to be formed in the thermal ball. | 04-05-2012 |
| 20120129333 | METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE MANUFACTURED USING THE SAME - Provided are a method for manufacturing a semiconductor package and a semiconductor package manufactured using the method. The method includes providing a substrate having a first region and a second region having a higher step difference than the first region, i.e., having a difference in height, forming a mask pattern having a first opening exposing a portion of the first region and a second opening exposing a portion of the second region on the substrate, forming first and second bump material films filling the first and second openings, respectively, and forming the first and second bumps by performing a reflow process on the first and second bump material films, wherein the first opening has a lower portion having the same width with the second opening and a top portion having a width greater than the second opening. | 05-24-2012 |
| 20120129334 | SEMICONDUCTOR PACKAGES AND METHODS OF MANUFACTURING THE SAME - Provided are semiconductor packages and methods of manufacturing the semiconductor package. The semiconductor packages may include a substrate including a chip pad, a redistributed line which is electrically connected to the chip pad and includes an opening. The semiconductor packages may also include an external terminal connection portion, and an external terminal connection pad which is disposed at an opening and electrically connected to the redistributed line. The present general inventive concept can solve the problem where an ingredient of gold included in a redistributed line may be prevented from being diffused into an adjacent bump pad to form a void or an undesired intermetallic compound. In a chip on chip structure, a plurality of bumps of a lower chip are connected to an upper chip to improve reliability, diversity and functionality of the chip on chip structure. | 05-24-2012 |
| 20120142184 | MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE - A manufacturing method of a semiconductor structure includes providing a substrate having an upper surface and a bottom surface. First openings are formed in the substrate. An oxidization process is performed to oxidize the substrate having the first openings therein to form an oxide-containing material layer, and the oxide-containing material layer has second openings therein. A conductive material is filled into the second openings to form conductive plugs. A first device layer is formed a first surface of the oxide-containing material layer, and is partially or fully electrically connected to the conductive plugs. A second device layer is formed on a second surface of the oxide-containing material layer, and is partially or fully electrically connected to the conductive plugs. | 06-07-2012 |
| 20120164825 | SEMICONDUCTOR PACKAGE WITH A METAL POST AND MANUFACTURING METHOD THEREOF - Disclosed are a semiconductor package and a manufacturing method thereof. The semiconductor package can include a semiconductor substrate, having one surface on which a conductive pad is formed; an insulating layer, being formed on one surface of the semiconductor substrate; a metal post, penetrating through the conductive pad, the semiconductor substrate, and the insulating layer; and an outer-layer circuit, being electrically connected to the metal post. With the present invention, it can become unnecessary to form an additional via for electrically connecting both surfaces of the semiconductor substrate, thereby simplifying the manufacturing process, reducing the manufacturing cost, and improving the coupling reliability. | 06-28-2012 |
| 20120178251 | METHOD OF FORMING METAL PILLAR - The disclosure relates to fabrication of to a metal pillar. An exemplary method of fabricating a semiconductor device comprises the steps of providing a substrate having a contact pad; forming a passivation layer extending over the substrate having an opening over the contact pad; forming a metal pillar over the contact pad and a portion of the passivation layer; forming a solder layer over the metal pillar; and causing sidewalls of the metal pillar to react with an organic compound to form a self-assembled monolayer or self-assembled multi-layers of the organic compound on the sidewalls of the metal pillar. | 07-12-2012 |
| 20120214302 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A method of fabricating a semiconductor device is provided. The method may include preparing a substrate having a first surface and a second surface, forming a via hole exposing at least a portion of the substrate from the first surface of the substrate, forming a first insulating film on an inner wall of the via hole, forming a conductive connection part filling an inside of the via hole including the first insulating film, polishing the second surface of the substrate until the conductive connection part is exposed, and selectively forming a second insulating film on the second surface of the substrate using an electrografting method to expose the conductive connection part. | 08-23-2012 |
| 20120231621 | Manufacturing Method Of A Semiconductor Load Board - A manufacturing method of a semiconductor load board is disclosed. The manufacturing method includes a first conductive layer forming step, a first patterning step, a dielectric layer forming step, a drilling step, a second conductive layer forming step, a second patterning step or a two-times patterning step, and a solder connecting step. In a second patterning step or a two-times patterning step, a solder pads is formed in the opening of the dielectric layer, wherein each solder pad has a height higher than the height of the dielectric, and the width of each solder pad is equal to or smaller than the maximum width of the opening, such that wider intervals are provided in the same area and the problems of short circuit failure and electrical interference can be reduced. | 09-13-2012 |
| 20120252203 | CONTROLLED ELECTROPLATED SOLDER BUMPS - The uniformity of the composition of plated solder bumps from one batch of wafers to another is improved by controlling the rotational speed of the wafers based on the particular solder bump pattern. Embodiments include sequentially horizontal fountain electroplating a pattern of solder bumps, e.g., SnAg solder bumps, on a plurality batches of wafers and controlling the rotational speed of each batch of wafers during electroplating based on a calibration plot of the concentration of a solder bump component, e.g., Ag, as a function of rotational speed for each solder bump pattern, such that the uniformity of the Ag concentration in the patterns of solder bumps is greater than 95%, e.g., greater than 98%. Embodiments further include electroplating in the same plater sequential batches of wafers having both different patterns and different solder bump compositions at the same high throughput. | 10-04-2012 |
| 20120270388 | ROUTING LAYER FOR MITIGATING STRESS IN A SEMICONDUCTOR DIE - A routing layer for a semiconductor die is disclosed. The routing layer includes pads for attaching solder bumps; bond-pads bonded to bump-pads of a die having an integrated circuit, and traces interconnecting bond-pads to pads. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces at least partially surrounding some pads so as to absorb stress from solder bumps attached to the pads. Parts of the traces that surround pads protect parts of the underlying dielectric material proximate the solder bumps, from the stress. | 10-25-2012 |
| 20120276733 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In order to provide a semiconductor device that includes a conductive layer on one surface of a semiconductor substrate with an insulating layer therebetween, a bump on the other surface of the semiconductor substrate, and a through-electrode through the semiconductor substrate connecting the conductive layer with the bump, a through-hole is formed from the other surface of the semiconductor substrate to be connected to the conductive layer, a seed metal film is formed on the through-hole and the other surface, a photoresist is formed thereon, a mask layer is formed by processing the photoresist with a pattern larger than the through-hole, a plated film is grown by electrolytic plating so as to integrally form the through-electrode and a part of the bump. | 11-01-2012 |
| 20120282767 | METHOD FOR PRODUCING A TWO-SIDED FAN-OUT WAFER LEVEL PACKAGE WITH ELECTRICALLY CONDUCTIVE INTERCONNECTS, AND A CORRESPONDING SEMICONDUCTOR PACKAGE - A semiconductor packaging process includes drilling apertures in a reconstituted wafer, then filling the apertures with conductive paste by wiping a quantity of the paste across a back surface of the wafer so that paste is forced into the apertures. The paste is cured to form conductive posts. The wafer is thinned, and redistribution layers are formed on front and back surfaces of the wafer, with the posts acting as interconnections between the redistribution layers. In an alternative process, blind apertures are drilled. A dry film resist is applied to the front surface of the wafer, and patterned to expose the apertures. Conductive paste is applied from the front. To prevent paste from trapping air pockets in the apertures, the wiping process is performed under vacuum. After curing the paste, the wafer is thinned to expose the cured paste in the apertures, and redistribution layers are formed. | 11-08-2012 |
| 20120289042 | Arrangement for solder bump formation on wafers - An apparatus and a process for the manufacture of a solder-bump adhered wafer substrate for use in the semiconductor industry, comprising one or more of the following steps including: arranging a first compressive member and a second compressive member in an opposed, compressibly displaceable, spaced-apart relationship, with a pattern plate disposed therebetween with the pattern plate having a plurality of aligned through-holes arranged thereon; filling the through-holes with a molten solder; compressing the solder and the pattern plate between the first and second opposed compressive members to compact the solder therein and cleans the pattern plate of excess solder; chilling the pattern plate to solidify the molten solder in the through-holes; and removing the pattern plate from the spaced-apart compressive members to produce a wafer with solder bumps thereon. | 11-15-2012 |
| 20120309187 | Conformal Coining of Solder Joints in Electronic Packages - Thermal deformation of a substrate and the substrate's warp at room temperature are used to determine the expected profile of the substrate at reflow. A contact surface profile of a coining pressure plate is selected based on the expected substrate profile. A solder surface is shaped on the substrate or a die to be joined to the substrate by the coining pressure plate, thereby facilitating the chip-joining process. | 12-06-2012 |
| 20120322255 | Metal Bump Formation - A system and method for forming metal bumps is provided. An embodiment comprises attaching conductive material to a carrier medium and then contacting the conductive material to conductive regions of a substrate. Portions of the conductive material are then bonded to the conductive regions using a bonding process to form conductive caps on the conductive regions, and residual conductive material and the carrier medium are removed. A reflow process is used to reflow the conductive caps into conductive bumps. | 12-20-2012 |
| 20130034956 | CLEANING RESIDUAL MOLDING COMPOUND ON SOLDER BUMPS - A method of forming wafer-level chip scale packaging solder bumps on a wafer substrate involves cleaning the surface of the solder bumps using a laser to remove any residual molding compound from the surface of the solder bumps after the solder bumps are reflowed and a liquid molding compound is applied and cured. | 02-07-2013 |
| 20130040453 | Through Silicon Via Layout - A system and method for forming under bump metallization layers that reduces the overall footprint of UBMs, through silicon vias, and trace lines is disclosed. A preferred embodiment comprises forming an under bump metallization layer over a plurality of through silicon vias, whereas the UBM is connected to only a portion of the total number of through silicon vias over which it is located. The trace lines connected to the through silicon vias may additionally be formed beneath the UBM to save even more space on the surface of the die. | 02-14-2013 |
| 20130065388 | SUBSTRATE STRUCTURE WITH COMPLIANT BUMP AND MANUFACTURING METHOD THEREOF - A substrate structure with compliant bump comprises a substrate, a plurality of bumps, and a metallic layer, wherein the substrate comprises a surface, a trace layer, and a protective layer. The trace layer comprises a plurality of conductive pads, and each of the conductive pads comprises an upper surface. The protective layer comprises a plurality of openings. The bumps are formed on the surface, and each of the bumps comprises a top surface, an inner surface and an outer surface and defines a first body and a second body. The first body is located on the surface. The second body is located on top of the first body. The metallic layer is formed on the top surface, the inner surface, and the upper surface. | 03-14-2013 |
| 20130072012 | Method For Forming Package Substrate With Ultra-Thin Seed Layer - A method for forming a package substrate with a seed layer is provided, which includes a step of etching away the metal foil laminated on the substrate, so that the substrate has a rough surface, and a step of forming an ultra-thin seed layer on the rough surface of the substrate, wherein the ultra-thin seed layer is formed along the rough surface of the substrate, and thereby the ultra-thin seed layer has a rough surface. Consequently, the adhesion between the metal bumps or circuits formed on the ultra-thin rough seed layer and the substrate can be increased. Furthermore, because the seed layer is ultra thin, the metal bumps or the circuit lines formed on the package substrate can be made finer in line widths and line pitches, and the good yield of the package substrate with fine circuit lines can be increased. | 03-21-2013 |
| 20130089977 | METHOD FOR FORMING HIGH DENSITY PATTERNS - In one or more embodiments, a method is provided for forming an integrated circuit with a pattern of isolated features having a final density of isolated features that is greater than a starting density of isolated features in an integrated circuit by a multiple of two or more. The method can include forming a pattern of pillars having a density X, and forming a pattern of holes amongst the pillars, the holes having a density at least X. The pillars can be selectively removed to form a pattern of holes having a density at least 2X. In some embodiments, plugs can be formed in the pattern of holes, such as by epitaxial deposition on the substrate, in order to provide a pattern of pillars having a density 2X. In other embodiments, the pattern of holes can be transferred to the substrate by etching. | 04-11-2013 |
| 20130109169 | METHODS OF MANUFACTURING STRESS BUFFER STRUCTURES IN A MOUNTING STRUCTURE OF A SEMICONDUCTOR DEVICE | 05-02-2013 |
| 20130122700 | Multi-Die Stacking Using Bumps with Different Sizes - A device includes a first die having a first side and a second side opposite to first side, the first side includes a first region and a second region, and a first metal bump of a first horizontal size formed on the first region of the first side of the first die. A second die is bonded to the first metal bump at the first side of the first die. A dielectric layer is formed over the first side of the first die and includes a first portion directly over the second die, a second portion covering the second die. A second metal bump of a second horizontal size greater than the first horizontal size is formed on the second region of the first side of the first die. An electrical component is bonded to the first side of the first die through the second metal bump. | 05-16-2013 |
| 20130130494 | EMBEDDED SEMICONDUCTOR DEVICE SUBSTRATE AND PRODUCTION METHOD THEREOF - An embedded semiconductor device substrate having a semiconductor device integrated therein is formed by disposing a semiconductor device in an opening provided on an insulating resin, and sandwiching the semiconductor device and the insulating resin with a front surface wiring layer and a rear surface wiring layer and performing heat pressing. Connection between bumps of the semiconductor device and the front surface wiring layer is made with a connection wiring pattern. The connection wiring pattern is formed by patterning a resist film by direct exposure thereof with a light beam, and then performing etching. Thereby, it becomes possible to absorb a mounting error of a semiconductor device to a printed wiring board and a positional error of electrodes between semiconductor devices accompanying the tendency of reduction of the pitch of a semiconductor device, and to perform electric connection with a wiring pattern securely. | 05-23-2013 |
| 20130149856 | Interface Structure for Copper-Copper Peeling Integrity - An integrated circuit device is disclosed. An exemplary integrated circuit device includes a first copper layer, a second copper layer, and an interface between the first and second copper layers. The interface includes a flat zone interface region and an intergrowth interface region, wherein the flat zone interface region is less than or equal to 50% of the interface. | 06-13-2013 |
| 20130149857 | SOLDER INTERCONNECT BY ADDITION OF COPPER - A method of forming an electronic device provides an electronic device substrate having a solder bump pad located thereover. A nickel-containing layer is located over the solder bump pad. A copper-containing layer is formed on the nickel-containing layer prior to subjecting the electronic device to a reflow process. | 06-13-2013 |
| 20130157455 | Electrical Contact Alignment Posts - An electronic apparatus and method of fabrication of the apparatus, the apparatus including a first electronic device having an interconnection surface with a first plurality of interconnection pads extending from the surface by a first distance and a second plurality of alignment posts extending from the surface by a second distance greater than the first distance, and a second electrical device having an interconnection surface with a first plurality of electrical interconnection pads, each pad arranged to contact a corresponding first electronic device interconnection surface pad upon assembly of the first electronic device interconnection surface upon the second electronic device interconnection surface, the second electronic device interconnection surface including a third plurality of alignment posts, each located to be adjacent to at least one of the first electronic device alignment posts upon assembly. | 06-20-2013 |
| 20130171816 | APPARATUS AND METHOD FOR PLACING SOLDER BALLS - A system and process for forming a ball grid array on a substrate includes defining a plurality of openings in a resist layer on the substrate, and forming a plurality of openings in the resist layer, each positioned over a contact pad of the substrate. Flux is then deposited in the openings, and solder balls are positioned in each opening with the flux. Solder bumps are formed by reflowing the solder balls in the respective openings. The resist layer is then removed, leaving an array of solder bumps on the substrate. The flux can be deposited by depositing a layer of flux, then removing the flux, except a portion that remains in each opening. Solder balls can be positioned by moving a ball feeder across the resist layer and dropping a solder ball each time an aperture in the ball feeder aligns with an opening in the resist layer. | 07-04-2013 |
| 20130183823 | BUMPING PROCESS - A bumping process includes providing a silicon substrate, forming a titanium-containing metal layer on the silicon substrate, wherein the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas, forming a photoresist layer on the titanium-containing metal layer, patterning the photoresist layer to form a plurality of opening slots corresponded to the first areas of the titanium-containing metal layer, forming a plurality of copper bumps at the opening slots, proceeding a heat procedure, forming a plurality of bump isolation layers on the copper bumps, forming a plurality of connective layers on the bump isolation layers, removing the photoresist layer, removing the second areas and enabling each the first areas to form an under bump metallurgy layer. | 07-18-2013 |
| 20130196498 | BUMPING PROCESS AND STRUCTURE THEREOF - A bumping process includes providing a silicon substrate; forming a titanium-containing metal layer on silicon substrate, the titanium-containing metal layer comprises a plurality of first areas and a plurality of second areas; forming a first photoresist layer on titanium-containing metal layer; patterning the first photoresist layer to form a plurality of first opening slots; forming a plurality of copper bumps within first opening slots, said copper bump comprises a first top surface and a first ring surface; removing the first photoresist layer; forming a second photoresist layer on titanium-containing metal layer; patterning the second photoresist layer to form a plurality of second opening slots; forming a plurality of bump isolation layers at spaces, the first top surfaces and the first ring surfaces; forming a plurality of connective layers on bump isolation layers; removing the second photoresist layer, removing the second areas to form an under bump metallurgy layer. | 08-01-2013 |
| 20130224946 | Passivated Copper Chip Pads - A structure and method of forming passivated copper chip pads is described. In various embodiments, the invention describes a substrate that includes active circuitry and metal levels disposed above the substrate. A passivation layer is disposed above a last level of the metal levels. A conductive liner is disposed in the sidewalls of an opening disposed in the passivation layer, wherein the conductive liner is also disposed over an exposed surface of the last level of the metal levels. | 08-29-2013 |
| 20130237049 | METHOD OF FABRICATING A PACKAGE SUBSTRATE - A method of fabricating a package substrate including preparing a substrate having at least one conductive pad, forming an insulating layer having an opening to expose the conductive pad on the substrate, forming a separation barrier layer on the conductive pad inside the opening to be higher than the upper surface of the insulating layer along the side walls thereof, forming a post terminal on the separation barrier layer, and forming a solder bump on the post terminal. | 09-12-2013 |
| 20130244417 | Template Wafer Fabrication Process for Small Pitch Flip-Chip Interconnect Hybridization - A template wafer fabrication process is disclosed for high density indium bumping of microchips by using an innovative template wafer upon which the bumps are initially fabricated. Once fabricated, these bumps are transferred to the microchip, after which can be hybridized to another microchip. Such a template wafer is reusable, and thus provides an economical way to fabricate indium bumps. Reusability also eliminates nonuniformities in bump shape and size in serial processing of separate microchips, which is not the case for other indium bump fabrication processes. Such a fabrication process provides a way to form relatively tall indium bumps and accomplishes this without the standard thick photoresist liftoff process. The described process can be suitable for bump pitches under 10 microns, and is only limited by the resolution of the photolithography equipment used. | 09-19-2013 |
| 20130252414 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR AFFIXING A POST TO A SUBSTRATE PAD - A system, method, and computer program product are provided for affixing a post to a substrate pad. In use, a post is affixed to each of one or more pads of a substrate, where each post receives a ball of a package during an assembly process. | 09-26-2013 |
| 20130273730 | METHOD TO REALIZE FLUX FREE INDIUM BUMPING - A method to realize flux free indium bumping process includes several steps including substrate metallization, contact holes opening, underbump metallization (UBM) layer thickening, indium bump preparation and Ag layer coating. The method can be used in the occasion for some special application, e.g., the packaging of the photoelectric chip (with optical lens), MEMS and biological detection chip, where the usage of flux is prohibited. | 10-17-2013 |
| 20130273731 | FAN-OUT CHIP SCALE PACKAGE - A chip scale package has a semiconductor die having an array of die bond pads arranged with a bond pad density per unit area, embedded in a molded die support body having a surface supporting an array of conducting contacts, each of the contacts connected by an electrical lead to a corresponding one of the die bond pads. | 10-17-2013 |
| 20130280904 | METHOD FOR CHIP PACKAGING - Provided is a method for chip packaging, including the steps of: providing a semi-packaged wafer which has a cutting trail and a metal bonding pad of the chip; forming a first protective layer on the cutting trail; forming on the metal bonding pad a sub-ball metal electrode; forming a solder ball on the sub-ball metal electrode; dicing the wafer along the cutting trail. The first protective layer according to the present invention can prevent the metal in the cutting trail from being separated by electroplating, and protect the lateral sides of a discrete chip after cutting. The process flow thereof is simple, and enhances the efficiency of the packaging as well as its yield. | 10-24-2013 |
| 20130288473 | Electrical Connection Structure - A structure comprises a top metal connector formed underneath a bond pad. The bond pad is enclosed by a first passivation layer and a second passivation layer. A polymer layer is further formed on the second passivation layer. The dimension of an opening in the first passivation layer is less than the dimension of the top metal connector. The dimension of the top metal connector is less than the dimensions of an opening in the second passivation layer and an opening in the polymer layer. | 10-31-2013 |
| 20130330922 | Semiconductor Constructions and Assemblies and Electronic Systems - The invention includes semiconductor assemblies having two or more dies. An exemplary assembly has circuitry associated with a first die front side electrically connected to circuitry associated with a second die front side. The front side of the second die is adjacent a back side of the first die, and a through wafer interconnect extends through the first die. The through wafer interconnect includes a conductive liner within a via extending through the first die. The conductive liner narrows the via, and the narrowed via is filled with insulative material. The invention also includes methods of forming semiconductor assemblies having two or more dies; and includes electronic systems containing assemblies with two or more dies. | 12-12-2013 |
| 20130344693 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP. | 12-26-2013 |
| 20140038405 | Packaging Structures and Methods with a Metal Pillar - A package component is free from active devices therein. The package component includes a substrate, a through-via in the substrate, a top dielectric layer over the substrate, and a metal pillar having a top surface over a top surface of the top dielectric layer. The metal pillar is electrically coupled to the through-via. A diffusion barrier is over the top surface of the metal pillar. A solder cap is disposed over the diffusion barrier. | 02-06-2014 |
| 20140038406 | METHOD FOR FABRICATING A THROUGH WIRE INTERCONNECT (TWI) ON A SEMICONDUCTOR SUBSTRATE HAVING A BONDED CONNECTION AND AN ENCAPSULATING POLYMER LAYER - A method for fabricating a through wire interconnect for a semiconductor substrate having a substrate contact includes the steps of: forming a via through the semiconductor substrate from a first side to a second side thereof; placing a wire in the via having a first end with a bonded connection to the substrate contact and a second end proximate to the second side; forming a first contact on the wire proximate to the first side; forming a second contact on the second end of the wire; and forming a polymer layer on the first side at least partially encapsulating the wire while leaving the first contact exposed. | 02-06-2014 |
| 20140045326 | METHOD OF MAKING A SEMICONDUCTOR DEVICE HAVING A POST-PASSIVATION INTERCONNECT STRUCTURE - A method of making a semiconductor device includes forming a passivation layer overlying a semiconductor substrate, the semiconductor substrate having a first region and a second region, wherein the first region is a conductive pad and the second region is adjacent to the first region. The method further includes forming a first protective layer overlying the passivation layer and forming an interconnect layer overlying the first protective layer. The method further includes forming a plurality of slots in the second region and forming a second protective layer overlying the interconnect layer, wherein the second protective layer fills each slot of the plurality of slots. The method further includes exposing a portion of the interconnect layer through the second protective layer; forming a barrier layer on the exposed portion of the interconnect layer; and forming a solder bump on the barrier layer. | 02-13-2014 |
| 20140051244 | METHOD OF FORMING AN INTEGRATED CIRCUIT DEVICE - A method of forming an integrated circuit device includes forming an under-bump metallurgy (UBM) layer overlying a semiconductor substrate. Next, a first photoresist film is formed on the UBM layer where the first photoresist film has a first photosensitivity and a first thickness. Additionally, the method includes forming a second photoresist film on the first photoresist film. Next, the method includes performing an exposure process on the second photoresist film and the first photoresist film. The method further includes removing an exposed portion of the second photoresist film to form a first opening. The method further also includes removing an exposed portion of the first photoresist film to expose a portion of the UBM layer. Furthermore, the method includes forming a copper layer in the first opening. The method also includes removing the second photoresist film and the first photoresist film where the copper layer forms a copper post. | 02-20-2014 |
| 20140057429 | Method of Forming a Step Pattern Structure - A method of forming a multi-floor step pattern structure includes forming a stacked structure having alternating insulating interlayers and sacrificial layers on a substrate. A first photoresist pattern is formed on the stacked structure. A first preliminary step pattern structure is formed by etching portions of the stacked structure using the first photoresist pattern as an etching mask. A passivation layer pattern is formed on upper surfaces of the first photoresist pattern and the first preliminary step pattern structure. A second photoresist pattern is formed by removing a side wall portion of the first photoresist pattern exposed by the passivation layer pattern. A second preliminary step pattern structure is formed by etching exposed insulating interlayers and underlying sacrificial layers using the second photoresist pattern as an etching mask. The above steps may be repeated on the second preliminary step pattern structure to form the multi-floor step pattern structure. | 02-27-2014 |
| 20140057430 | SEMICONDUCTOR DEVICE, FABRICATING METHOD THEREOF AND SEMICONDUCTOR PACKAGE INCLUDING THE SEMICONDUCTOR DEVICE - In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector. | 02-27-2014 |
| 20140073127 | SEMICONDUCTOR DEVICE AND INFORMATION PROCESSING SYSTEM INCLUDING THE SAME - A method of forming a semiconductor device includes forming first and second bumps on a semiconductor substrate, forming first and second penetration electrodes penetrating the semiconductor substrate, forming a first conductive structure making a first electrical path between the first bump and the first penetration electrode, and forming a second conductive structure making a second electrical path between the second bump and the second penetration electrode, the second conductive structure being smaller in resistance value than the first conductive structure. | 03-13-2014 |
| 20140087553 | Fabricating a Wafer Level Semiconductor Package Having a Pre-formed Dielectric Layer - There are disclosed herein various implementations of improved wafer level semiconductor packages. One exemplary implementation comprises forming a post-fabrication redistribution layer (post-Fab RDL) between first and second dielectric layers affixed over a surface of a wafer, and forming a window for receiving an electrical contact body in the second dielectric layer, the window exposing the post-Fab RDL. At least one of the first and second dielectric layers is a pre-formed dielectric layer, which may be affixed over the surface of the wafer using a lamination process. In one implementation, the window is formed using a direct laser ablation process. | 03-27-2014 |
| 20140087554 | METHODS FOR FORMING ARRAYS OF SMALL, CLOSELY SPACED FEATURES - Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed patterns of crossing elongate features with pillars at the intersections. Spacers are simultaneously applied to sidewalls of both sets of crossing lines to produce a pitch-doubled grid pattern. The pillars facilitate rows of spacers bridging columns of spacers. | 03-27-2014 |
| 20140106560 | DEBOND INTERCONNECT STRUCTURES - The present subject matter relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming an interconnect that has a portion thereof which becomes debonded from the microelectronic device during cooling after attachment to an external device. The debonded portion allows the interconnect to flex and absorb stress. | 04-17-2014 |
| 20140113445 | AL BOND PAD CLEAN METHOD - Embodiments of the present disclosure provide a method for controlling moisture from substrate being processed. Particularly, embodiments of the present disclosure provide methods for removing moisture from polymer materials adjacent bond pad areas. One embodiment of the present includes providing a moisture sensitive precursor and forming a compound from a reaction between the moisture to be controlled and the moisture sensitive precursor. | 04-24-2014 |
| 20140113446 | Semiconductor Device and Method of Confining Conductive Bump Material with Solder Mask Patch - A semiconductor device has a semiconductor die having a plurality of die bump pad and substrate having a plurality of conductive trace with an interconnect site. A solder mask patch is formed interstitially between the die bump pads or interconnect sites. A conductive bump material is deposited on the interconnect sites or die bump pads. The semiconductor die is mounted to the substrate so that the conductive bump material is disposed between the die bump pads and interconnect sites. The conductive bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the semiconductor die and substrate. The solder mask patch confines the conductive bump material within the die bump pad or interconnect site. The interconnect structure can include a fusible portion and non-fusible portion. An encapsulant is deposited between the semiconductor die and substrate. | 04-24-2014 |
| 20140162449 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - Semiconductor devices, and methods of fabricating a semiconductor device, include forming a via hole through a first surface of a substrate, the via hole being spaced apart from a second surface facing the first surface, forming a first conductive pattern in the via hole, forming an insulating pad layer on the first surface of the substrate, the insulating pad having an opening exposing the first conductive pattern, performing a thermal treatment on the first conductive pattern to form a protrusion protruding from a top surface of the first conductive pattern toward the opening, and then, forming a second conductive pattern in the opening. | 06-12-2014 |
| 20140170850 | UBM Structures for Wafer Level Chip Scale Packaging - A wafer level chip scale semiconductor device comprises a semiconductor die, a first under bump metal structure and a second under bump metal structure. The first under bump metal structure having a first enclosure is formed on a corner region or an edge region of the semiconductor die. A second under bump metal structure having a second enclosure is formed on an inner region of the semiconductor die. The first enclosure is greater than the second enclosure. | 06-19-2014 |
| 20140206185 | BALL PLACEMENT IN A PHOTO-PATTERNED TEMPLATE FOR FINE PITCH INTERCONNECT - A photo-patternable polymer film is deposited on a substrate, wherein the substrate includes metal pads. Ultraviolet light is transmitted through a photomask on the deposited photopatternable polymer film to generate cavities in Depositing a film on a substrate, wherein the substrate includes metal pads the deposited polymer film and expose the metal pads. The substrate is developed and rinsed, and then flux is applied on the surface of the substrate. Balls are placed in the generated cavities. A reflow process is performed to form bumps and remove flux, subsequent to the placing of the balls in the generated cavities. Plasma cleaning is performed to remove the photo-patternable film. | 07-24-2014 |
| 20140220774 | METHOD OF FORMING EXTERNAL TERMINALS OF A PACKAGE AND APPARATUS FOR PERFORMING THE SAME - A method of forming external terminals of a package is provided in which a package substrate may be fixed, an edge portion of the package substrate may be supported to prevent the edge portion of the package substrate from being upwardly bent, a mask having openings may be arranged on the package substrate, and the external terminals may be supplied to the package substrate through the openings of the mask. The supporting portion may downwardly press the edge portion of the package substrate so that the edge portion of the package substrate may not be upwardly bent. As a result, the external terminals on the package substrate may have a uniform thickness. | 08-07-2014 |
| 20140242791 | METHOD OF FORMING BUMP STRUCTURE - A method of forming a bump structure includes forming a metallization layer on a top metal layer by electroless plating process, forming a polymer layer over the metallization layer; forming an opening on the polymer layer to expose the metallization layer, and forming a solder bump over the exposed metallization layer to make electrical contact with the top metal layer. | 08-28-2014 |
| 20140256126 | Electrical Connectors and Methods for Forming the Same - A method includes coating a photo resist over an Under-Bump Metallurgy (UBM) layer and exposing the photo resist. In the step of exposing, a light amount reaching a bottom of the photo resist is less than about 5 percent of a light amount reaching a top surface of the photo resist. The method further includes developing the photo resist to form an opening in the photo resist. A portion of the UBM layer is exposed through the opening. The opening has a bottom lateral dimension greater than a top lateral dimension. An electrical connector is formed in the opening, wherein the electrical connector is non-reflowable. | 09-11-2014 |
| 20140273430 | INTEGRATED CLUSTER TO ENABLE NEXT GENERATION INTERCONNECT - Embodiments of the present invention generally relate to methods for forming a metal structure and passivation layers. In one embodiment, metal columns are formed on a substrate. The metal columns are doped with manganese, aluminum, zirconium, or hafnium. A dielectric material is deposited over and between the metal columns and then cured to form a passivation layer on vertical surfaces of the metal columns. | 09-18-2014 |
| 20140322909 | Wafer Backside Interconnect Structure Connected to TSVs - An integrated circuit structure includes a semiconductor substrate having a front surface and a back surface; a conductive via passing through the semiconductor substrate; and a metal feature on the back surface of the semiconductor substrate. The metal feature includes a metal pad overlying and contacting the conductive via, and a metal line over the conductive via. The metal line includes a dual damascene structure. The integrated circuit structure further includes a bump overlying the metal line. | 10-30-2014 |
| 20140329381 | TSV Backside Reveal Structure and Exposing Process - A TSV exposing process is provided, including: performing a mechanical grinding process on the substrate back surface of a substrate with a TSV conductive column, a liner between the substrate and the TSV conductive column; performing a first and a second chemical mechanical polishing process on the grinded substrate back surface; then performing an etching on the substrate back surface, and making the TSV backside reveal more than 10 μm. | 11-06-2014 |
| 20140342545 | Techniques for Fabricating Fine-Pitch Micro-Bumps - Techniques for fabricating fine-pitch micro-bumps are disclosed. According to one embodiment, a fabrication process may comprise the following steps: depositing a dielectric layer on a wafer; forming a pattern of through holes in the dielectric layer; depositing a seed metal layer on top of the dielectric layer and inside the through holes; depositing a layer of UBM metal on top of the seed metal layer (including inside the holes), and further filling the holes with a low melting point metal; performing chemical mechanical polishing (CMP) to remove conductive material(s) outside the holes and/or on the surface of the dielectric layer, such that the metal stacks of adjacent holes are insulated by the dielectric material between them; and etching the dielectric material surrounding the holes to cause the tip of the metal stacks to extend slightly higher than the surrounding dielectric surface, thereby forming fine-pitch micro-bumps. | 11-20-2014 |
| 20140357074 | SEMICONDUCTOR APPARATUS AND METHOD OF FABRICATING THE SAME - In a semiconductor apparatus, a plurality of semiconductor chips including through-silicon vias are stacked in a vertical direction, wherein the through-silicon via formed in each semiconductor chip protrudes beyond heights of each semiconductor chip. | 12-04-2014 |
| 20140357075 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor chip and a metal layer electrically coupled to the semiconductor chip. The semiconductor device includes an array of solder balls coupled to the metal layer and a front side protect material directly contacting the metal layer and laterally surrounding a portion of at least a plurality of solder balls. The front side protect material is configured to become fluid during solder reflow. | 12-04-2014 |
| 20140377946 | Bonded Structures for Package and Substrate - The embodiments described provide elongated bonded structures near edges of packaged structures free of solder wetting on sides of copper posts substantially facing the center of the packaged structures. Solder wetting occurs on other sides of copper posts of these bonded structures. The elongated bonded structures are arranged in different arrangements and reduce the chance of shorting between neighboring bonded structures. In addition, the elongated bonded structures improve the reliability performance. | 12-25-2014 |
| 20150044864 | COMPENSATING FOR WARPAGE OF A FLIP CHIP PACKAGE BY VARYING HEIGHTS OF A REDISTRIBUTION LAYER ON AN INTEGRATED CIRCUIT CHIP - Structures and methods of making a flip chip package that employ polyimide pads of varying heights at a radial distance from a center of an integrated circuit (IC) chip for a flip chip package. The polyimide pads may be formed under electrical connectors, which connect the IC chip to a chip carrier of the flip chip package, so that electrical connectors formed on polyimide pads of greater height are disposed at a greater radial distance from the center of the IC chip, while electrical connectors formed on polyimide pads of a lesser height are disposed more proximately to the center of the IC chip. Electrical connectors of a greater relative height to the IC chip's surface may compensate for a gap, produced by heat-induced warpage during the making of the flip chip package, that separates the electrical connectors on the IC chip from flip chip attaches on the chip carrier. | 02-12-2015 |
| 20150072515 | LASER ABLATION METHOD AND RECIPE FOR SACRIFICIAL MATERIAL PATTERNING AND REMOVAL - A method including introducing a passivation material over contact pads on a surface of an integrated circuit substrate; patterning a sacrificial material on the passivation material to define openings in the sacrificial material to the contact pads; introducing solder to the contact pads; and after introducing the solder, removing the sacrificial material with the proviso that, where the sacrificial material is a photosensitive material, removing comprises using temporally coherent electromagnetic radiation. A method including introducing a passivation material over contact pads; exposing the contact pads; patterning a photosensitive material on the passivation material; introducing solder to the contact pads; and after introducing the solder, removing the photosensitive material using temporally coherent electromagnetic radiation. A method including introducing a passivation material over contact pads; exposing the contact pads; patterning a non-photosensitive material on the passivation material; introducing solder to the contact pads; and after introducing the solder, removing the non-photosensitive material. | 03-12-2015 |
| 20150072516 | METHOD FOR REMOVING ELECTROPLATED METAL FACETS AND REUSING A BARRIER LAYER WITHOUT CHEMICAL MECHANICAL POLISHING - A method for avoiding using CMP for eliminating electroplated copper facets and reusing barrier layer in the back end of line (“BEOL”) manufacturing processes. Electropolishing is employed to remove the deposited surface metal, stopping at the barrier layer to form a smooth surface that may be utilized in subsequent steps. The method is suitable for the electropolishing of metal surfaces after formation of filled vias for through-silicon via processes employing metals such as copper, tungsten, aluminum, or alloys thereof. The remaining barrier layer may be reused to fabricate the redistribution layer. | 03-12-2015 |
| 20150099357 | METHOD OF FABRICATING WAFER-LEVEL CHIP PACKAGE - A method of fabricating a wafer-level chip package is provided. First, a wafer with two adjacent chips is provided, the wafer having an upper surface and a lower surface, and one side of each chip includes a conducting pad on the lower surface. A recess and an isolation layer extend from the upper surface to the lower surface, which the recess exposes the conducting pad. A part of the isolation layer is disposed in the recess with an opening to expose the conducting pad. A conductive layer is formed on the isolation layer and the conductive pad, and a photo-resist layer is spray coated on the conductive layer. The photo-resist layer is exposed and developed to expose the conductive layer, and the conductive layer is etched to form a redistribution layer. After stripping the photo-resist layer, a solder layer is formed on the isolation layer and the redistribution layer. | 04-09-2015 |
| 20150118840 | Alignment Marks in Substrate Having Through-Substrate Via (TSV) - A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate. | 04-30-2015 |
| 20150140801 | PATTERNED PHOTORESIST TO ATTACH A CARRIER WAFER TO A SILICON DEVICE WAFER - Patterned photoresist is used to attach a carrier wafer to a silicon device wafer. In one example, a silicon wafer is patterned for contact bumps by applying a photoresist over a surface of the wafer and removing the photoresist in locations at which the contact bumps are to be formed. The contact bumps are formed in the locations at which the photoresist is removed. A temporary carrier is attached to the photoresist over the wafer. The back side of the wafer opposite the contact bumps is processed while handling the wafer using the temporary carrier. The temporary carrier is removed. The photoresist on the front side of the wafer with the contact bumps is removed after removing the temporary carrier. | 05-21-2015 |
| 20150140802 | SEMICONDUCTOR DEVICE AND PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE - A semiconductor device includes: a substrate in which a product region and scribe regions are defined; a 1st insulation film formed above the substrate; a metal film in the 1st insulation film, disposed within the scribe regions in such a manner as to surround the product region; a 2nd insulation film formed on the 1st insulation film and the metal film; a 1st groove disposed more inside than the metal film in such a manner as to surround the product region, and reaching from a top surface of the 2nd insulation film to a position deeper than a top surface of the metal film; and a 2nd groove disposed more outside than the metal film in such a manner as to surround the metal film, and reaching from the top surface of the 2nd insulation film to a position deeper than the top surface of the metal film. | 05-21-2015 |
| 20150348922 | METHOD OF FORMING A SEMICONDUCTOR COMPONENT COMPRISING A SECOND PASSIVATION LAYER HAVING A FIRST OPENING EXPOSING A BOND PAD AND A PLURALITY OF SECOND OPENINGS EXPOSING A TOP SURFACE OF AN UNDERLYING FIRST PASSIVATION LAYER - A conductive feature on a semiconductor component is disclosed. A first passivation layer is formed over a substrate. A bond pad is formed over the first passivation layer. A second passivation layer overlies the first passivation layer and the bond pad. The second passivation layer has a first opening overlying the bond pad and a plurality of second openings exposing a top surface of the first passivation layer. A buffer layer overlies the second passivation layer and fills the plurality of second openings. The buffer layer has a third opening overlapping the first opening and together exposes a portion the bond pad. The combined first opening and third opening has sidewalls. An under bump metallurgy (UBM) layer overlies the sidewalls of the combined first opening and third opening, and contacts the exposed portion of the bond pad. A conductive feature overlies the UBM layer. | 12-03-2015 |
| 20160042993 | ETCHING LIQUID, ETCHING METHOD, AND METHOD OF MANUFACTURING SOLDER BUMP - An etching liquid which can selectively remove only a copper layer in an etching process of a multilayer structure including a cobalt layer and the copper layer is disclosed. The etching liquid is an etching liquid for etching the copper layer in the multilayer structure including the copper layer and the cobalt layer. This etching liquid includes at least one acid selected from a group consisting of citric acid, oxalic acid, malic acid, and malonic acid, and hydrogen peroxide, the etching liquid having pH in a range of 4.3 to 5.5. | 02-11-2016 |
| 20160049331 | INTEGRATED CLUSTER TO ENABLE NEXT GENERATION INTERCONNECT - Embodiments of the present invention generally relate to methods for forming a metal structure and passivation layers. In one embodiment, metal columns are formed on a substrate. The metal columns are doped with manganese, aluminum, zirconium, or hafnium. A dielectric material is deposited over and between the metal columns and then cured to form a passivation layer on vertical surfaces of the metal columns. | 02-18-2016 |
| 20160064343 | MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICES - A manufacturing method for semiconductor devices includes the steps of forming an Ni/Au film that includes an Ni film and an Au film formed over the Ni film over a wiring that is coupled to each of a plurality of electrode pads formed over a principal surface of a semiconductor wafer and arranges each of the electrode pads at a different position, grinding a back surface of the semiconductor wafer, performing reduction treatment on a surface of the Ni/Au film, and forming a solder bump over the Ni/Au film. In the reduction treatment, respective processes of flux application, reflow soldering and cleaning are performed and the solder bump is bonded to the Ni/Au film after the reduction treatment has been completed. Thereby, bonding reliability in flip chip bonding of a semiconductor device is improved. | 03-03-2016 |
| 20160093581 | SEMICONDUCTOR DEVICE WITH A THROUGH ELECTRODE - A semiconductor device includes a through electrode penetrating a substrate such that a first end portion of the through electrode protrudes from a first surface of the substrate, a passivation layer covering the first surface of the substrate and a sidewall of the first end portion of the through electrode, a bump having a lower portion penetrating the passivation layer and coupled to the first end portion of the through electrode, and a lower metal layer disposed between the bump and the first end portion of the through electrode. The lower metal layer extends onto a sidewall of the bump and has a concave shape. | 03-31-2016 |
| 20160118358 | DIRECT INJECTION MOLDED SOLDER PROCESS FOR FORMING SOLDER BUMPS ON WAFERS - Solder bumps are provided on round wafers through the use of injection molded solder. Copper pillars or ball limiting metallurgy are formed over I/O pads within the channels of a patterned mask layer. Solder is injected over the pillars or BLM, filling the channels. Molten solder can be injected in cavities formed in round wafers without leakage using a carrier assembly that accommodates wafers that have been previously subjected to mask layer deposition and patterning. One such carrier assembly includes an elastomeric body portion having a round recess, the walls of the recess forming a tight seal with the round wafer. Other carrier assemblies employ adhesives applied around the peripheral edges of the wafers to ensure sealing between the carrier assemblies and wafers. | 04-28-2016 |
| 20160126203 | SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME - A technique which improves the reliability in coupling between a bump electrode of a semiconductor chip and wiring of a mounting substrate, more particularly a technique which guarantees the flatness of a bump electrode even when wiring lies in a top wiring layer under the bump electrode, thereby improving the reliability in coupling between the bump electrode and the wiring formed on a glass substrate. Wiring, comprised of a power line or signal line, and a dummy pattern are formed in a top wiring layer beneath a non-overlap region of a bump electrode. The dummy pattern is located to fill the space between wirings to reduce irregularities caused by the wirings and space in the top wiring layer. A surface protection film formed to cover the top wiring layer is flattened by CMP. | 05-05-2016 |
| 20160133484 | Method of Manufacturing Semiconductor Device - Provided is a semiconductor device with improved reliability that achieves the reduction in size. A semiconductor wafer is provided that has a first insulating member with an opening that exposes from which an upper surface of an electrode pad. Subsequently, after forming a second insulating member over a main surface of the semiconductor wafer, another opening is formed to expose the upper surface of the electrode pad. Then, a probe needle is brought into contact with the electrode pad, to write data in a memory circuit at the main surface of the semiconductor wafer. After covering the upper surface of the electrode pad with a conductive cover film, a relocation wiring is formed. In the Y direction, the width of the relocation wiring positioned directly above the electrode pad is equal to or smaller than the width of the opening formed in the first insulating member. | 05-12-2016 |
| 20160133596 | DEBOND INTERCONNECT STRUCTURES - The present subject matter relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to forming an interconnect that has a portion thereof which becomes debonded from the microelectronic device during cooling after attachment to an external device. The debonded portion allows the interconnect to flex and absorb stress. | 05-12-2016 |
| 20160141260 | PRE-PACKAGE AND METHODS OF MANUFACTURING SEMICONDUCTOR PACKAGE AND ELECTRONIC DEVICE USING THE SAME - Methods of fabricating semiconductor packages are provided. One of the methods includes forming a protection layer including metal on a first surface of a substrate to cover a semiconductor device disposed on the first surface of the substrate, attaching a support substrate to the protection layer by using an adhesive member, processing a second surface of the substrate opposite to the protection layer to remove a part of the substrate, and detaching the support substrate from the substrate. | 05-19-2016 |
| 20160181217 | FORMATION OF SOLDER AND COPPER INTERCONNECT STRUCTURES AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS | 06-23-2016 |
| 20160204001 | METAL ETCHANT COMPOSITIONS AND METHODS OF FABRICATING A SEMICONDUCTOR DEVICE USING THE SAME | 07-14-2016 |
