| Entries |
| Document | Title | Date |
|---|
| 20080268641 | Method for forming dual damascene pattern - A method for forming a dual damascene pattern includes preparing a multi-functional hard mask composition including a silicon resin as a base resin; forming a deposition. structure including a self-arrangement contact insulation film, a first dielectric film, an etching barrier film, and a second dielectric film over a hardwiring layer; etching the deposition structure to expose the hardwiring layer, thereby forming a via hole; forming the multi-functional hard mask composition on the second dielectric film and in the via hole to form a multi-functional hard mask film; and etching the resulting structure to expose a part of the first dielectric film, thereby forming a trench having a width wider than that of the via hole; and removing the multi-functional hard mask film. | 10-30-2008 |
| 20090011593 | METHOD OF DEPOSITING AMORPHOUS FILM ON CAPACITOR ASSEMBLY - A capacitor assembly includes a semiconductor substrate having an interlayer insulation film on a first main surface of the semiconductor substrate, and a conductive barrier layer formed on the interlayer insulation film. The capacitor assembly also includes a contact plug electrically connected to the conductive barrier layer through the interlayer insulation film, and a lower electrode formed on the barrier layer. The capacitor assembly also includes a capacitor insulation film formed on the lower electrode, and an upper electrode formed on the capacitor insulation film. The capacitor insulation film is made from a ferroelectric material. The barrier layer is an amorphous film which includes titanium and aluminum. | 01-08-2009 |
| 20090011594 | Methods of Trench and Contact Formation in Memory Cells - Methods of contact formation and memory arrays formed using such methods, which methods include providing a substrate having a contacting area; forming a plurality of line-shape structures extending in a first direction; forming a hard mask spacer beside the line-shape structure; forming an insulating material layer above the hard mask spacer; forming a contiguous trench in the insulating material layer extending in a second direction different from the first direction and exposing the contacting area; and forming a conductive line in the trench to contact the contacting area. | 01-08-2009 |
| 20090017621 | Manufacturing method for semiconductor device and manufacturing device of semiconductor device - The semiconductor manufacturing method includes the step (ST. | 01-15-2009 |
| 20090017622 | CHEMICAL TREATMENT METHOD - A chemical treatment apparatus and a method for performing a chemical treatment of a wafer, etc., by supplying a chemical via a cell. The apparatus includes a cylindrical inner cell and a cylindrical outer cell with open ends disposed at an outer circumference of the inner cell. The outer cell is axially movable to vary the width of a slit formed between a bottom end of the outer cell and a top surface of the substrate-holding means by the axial movement, thereby adjusting the discharge rate of the chemical and varying the pressure of the chemical. | 01-15-2009 |
| 20090035940 | COPPER METALLIZATION OF THROUGH SILICON VIA - A method for metallizing a through silicon via feature in a semiconductor integrated circuit device substrate comprising immersing the semiconductor integrated circuit device substrate into an electrolytic copper deposition composition comprising a source of copper ions, an organic sulfonic acid or inorganic acid, or one or more organic compounds selected from among polarizers and/or depolarizers, and chloride ions. | 02-05-2009 |
| 20090047782 | METHOD FOR MANUFACTURING A DEVICE HAVING A HIGH ASPECT RATIO VIA - Method for manufacturing a device having a conductive via includes the following steps. A dielectric material layer including a through hole is formed on a substrate. A seed metallic layer is formed on the dielectric material layer and in the through hole. A metallic layer is formed on the seed metallic layer, and is filled in the through hole. The metallic layer located over the seed metallic layer and outside the through hole is etched by a spin etching process, whereby the metallic layer located in the through hole is formed to a lower portion. An upper portion is formed on the lower portion, and a metallic trace is formed on the seed metallic layer, wherein the upper and lower portions is formed to a conductive via, and the conductive via and the metallic trace expose a part of the seed metallic layer. The exposed seed metallic layer is etched. | 02-19-2009 |
| 20090061627 | METHOD FOR PRODUCING A METAL BACKSIDE CONTACT OF A SEMICONDUCTOR COMPONENT, IN PARTICULAR, A SOLAR CELL - The present invention relates to a method for manufacturing a backside contact of a semiconductor component, in particular, of a solar cell, comprising a metallic layer on the backside of a substrate in a vacuum treatment chamber, and the use of a vacuum treatment system for performing said method. Through this method and its use, in particular silicon based solar cells, can be provided with a back contact in a simple manner in a continuous process sequence, wherein the process sequence can be provided particularly efficient and economical, since no handling systems for rotating the substrate are required, and in particular silk screening steps can be dispensed with. | 03-05-2009 |
| 20090061628 | Laser trimming problem suppressing semiconductor device manufacturing apparatus and method - A semiconductor device manufacturing apparatus includes a substrate holding section that holds a semiconductor wafer substrate, a discharge mechanism that discharges liquid drops of metal paste from a discharge nozzle toward a surface of the semiconductor wafer substrate, and a driving mechanism that moves at least one of the substrate holding section and the discharge nozzle. A control section is provided to control the discharge and driving mechanisms so as to adhere the metal paste to the surface. The semiconductor wafer substrate includes a terminal unit formed from two or more electrically separated terminals connected to a device circuit and an insulation layer having an opening in a formation position of the terminal unit. Further, the control section controls the discharge and driving mechanisms to selectively coat the opening of the semiconductor wafer substrate with the metal paste overlying the terminal unit to be electrically connected. | 03-05-2009 |
| 20090124078 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH THROUGH HOLE - A semiconductor device with improved reliability and its manufacturing method is offered. The semiconductor device of this invention includes a pad electrode formed on a semiconductor substrate through a first insulation layer, and a via hole formed in the semiconductor substrate and extending from a back surface of the semiconductor substrate to the pad electrode, wherein the via hole includes a first opening of which a diameter in a portion close to the pad electrode is larger than a diameter in a portion close to the back surface of the semiconductor substrate, and a second opening formed in the first insulation layer and continuing from the first opening, of which a diameter in a portion close to the pad electrode is smaller than a diameter in a portion close to the front surface of the semiconductor substrate. | 05-14-2009 |
| 20090130847 | METHOD OF FABRICATING METAL PATTERN WITHOUT DAMAGING INSULATION LAYER - Provided is a method of fabricating a metal pattern so that an insulation layer between a wafer and the metal pattern can be prevented from being damaged in a planarization procedure when the metal pattern having a trench structure is fabricated on the wafer. The method includes operations of forming a first insulation layer on a surface of the wafer; selectively etching the surface of the wafer and the first insulation layer so as to form a plurality of trenches; forming a second insulation layer on a bottom and side walls of the plurality of trenches by using a thermal oxidation method; filling a metal inside the plurality of trenches; and performing planarization by removing the metal deposited outside the plurality of trenches. | 05-21-2009 |
| 20090137118 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Initially, an interconnection | 05-28-2009 |
| 20090233440 | Seed Layers for Metallic Interconnects - One embodiment of the present invention is a method for depositing two or more PVD seed layers for electroplating metallic interconnects over a substrate, the substrate including a patterned insulating layer which includes at least one opening surrounded by a field, the at least one opening having top corners, sidewalls, and bottom, the field and the at least one opening being ready for depositing one or more seed layers, and the method includes: (a) depositing by a PVD technique, in a PVD chamber, a continuous PVD seed layer over the sidewalls and bottom of the at least one opening, using a first set of deposition parameters; and (b) depositing by a PVD technique, in a PVD chamber, another PVD seed layer over the substrate, using a second set of deposition parameters, wherein (i) the second set of deposition parameters includes at least one deposition parameter which is different from any of the parameters in the first set of deposition parameters, or the second set of deposition parameters includes at least one deposition parameter whose value is different in the two sets of deposition parameters, (ii) at least one of the PVD seed layers includes a material selected from a group consisting of Cu, Ag, or alloys including one or more of these metals, (iii) the PVD seed layers have no substantial overhangs sealing or pinching-off the top corners of the at least one opening, (iv) the combined thickness of the seed layers over the field is sufficient to enable uniform electroplating across the substrate, and (v) the combined seed layers inside the at least one opening leave sufficient room for electroplating inside the at least one opening. | 09-17-2009 |
| 20090253262 | ELECTROLESS PLATING SYSTEM - An electroless plating system includes a plating solution, and controlling reducing agents in the plating solution for deposition over outlier features smaller than about five hundred nanometers and isolated by about one thousand nanometers. | 10-08-2009 |
| 20090258491 | Method of inhibiting background plating - Methods of inhibiting background plating on semiconductor substrates using oxidizing agents are disclosed. | 10-15-2009 |
| 20090269925 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A process for producing a semiconductor device, comprising the wiring region forming step of forming a wiring region on a semiconductor substrate; the copper wiring layer forming step of forming a copper wiring layer on the formed wiring region by electrolytic plating technique, wherein the copper wiring layer is formed by passing a current of application pattern determined from the relationship between application pattern of current passed at electrolytic plating and impurity content characteristic in the formed copper wiring layer so that the impurity content in the formed copper wiring layer becomes desired one; and the wiring forming step of polishing the formed copper wiring layer into a wiring. | 10-29-2009 |
| 20090325379 | METHODS FOR FABRICATING FINE LINE/SPACE (FLS) ROUTING IN HIGH DENSITY INTERCONNECT (HDI) SUBSTRATES - A method for fabricating fine line and space routing described. The method includes providing a substrate having a dielectric layer and a seed layer disposed thereon. An anti-reflective coating layer and a photo-resist layer are then formed above the seed layer. The photo-resist layer and the anti-reflective coating layer are patterned to form a patterned photo-resist layer and a patterned anti-reflective coating layer, to expose a first portion of the seed layer, and to leave covered a second portion of the seed layer. A metal layer is then formed on the first portion of the seed layer, between features of the patterned photo-resist layer and the patterned anti-reflective coating layer. The patterned photo-resist layer and the patterned anti-reflective coating layer are subsequently removed. Then, the second portion of the seed layer is removed to provide a series of metal lines above the dielectric layer. | 12-31-2009 |
| 20090325380 | METHOD FOR FORMING ELECTRODE ON SEMICONDUCTOR WAFER - In accordance with an embodiment of the present invention, there is provided a method for forming an electrode of a semiconductor wafer. The method includes a masking step of applying a mask having apertures formed in areas corresponding to an electrode area of each device, on the back surface of a semiconductor substrate, and an electrode forming step of depositing, by sputtering, gold on the back surface of the semiconductor substrate for which the masking step has been carried out to thereby form the electrode in the electrode area of each device, on the back surface of the semiconductor substrate. The method further includes a mask separating step of separating the mask applied on the back surface of the semiconductor substrate for which the electrode forming step has been carried out, and a gold collecting step of collecting gold deposited on the mask separated in the mask separating step. | 12-31-2009 |
| 20100029078 | METHOD OF FORMING SEMICONDUCTOR DEVICES CONTAINING METAL CAP LAYERS - Embodiments of methods for improving electrical leakage performance and minimizing electromigration in semiconductor devices containing metal cap layers are generally described herein. According to one embodiment, a method of forming a semiconductor device includes planarizing a top surface of a workpiece to form a substantially planar surface with conductive paths and dielectric regions, forming metal cap layers on the conductive paths, and exposing the top surface of the workpiece to a dopant source from a gas cluster ion beam (GCIB) to form doped metal cap layers on the conductive paths and doped dielectric layers on the dielectric regions. According to some embodiments the metal cap layers and the doped metal cap layers contain a noble metal selected from Pt, Au, Ru, Rh, Ir, and Pd. | 02-04-2010 |
| 20100068882 | Semiconductor Device and Method for Manufacturing the Same - The present method for manufacturing a semiconductor device comprises the steps of forming an aluminum wiring layer on a substrate; sequentially forming a hard mask, a polysilicon layer, and a bottom anti-reflective coating over the aluminum wiring layer; etching the polysilicon layer using a photoresist pattern formed over the bottom anti-reflective coating as mask; etching the hard mask to a predetermined thickness; and etching the hard mask to expose the aluminum wiring layer. The method for manufacturing a semiconductor device according to the present invention may prevent byproducts and polymer residue from when patterning the hard mask. As a result, the presently disclosed methods may avoid the need for a conventional cleaning process prior to etching the aluminum wiring layer to form aluminum lines. | 03-18-2010 |
| 20100124821 | METHODS FOR FORMING A CONDUCTIVE MATERIAL, METHODS FOR SELECTIVELY FORMING A CONDUCTIVE MATERIAL, METHODS FOR FORMING PLATINUM, AND METHODS FOR FORMING CONDUCTIVE STRUCTURES - Methods of selectively forming a conductive material and methods of forming metal conductive structures are disclosed. An organic material may be patterned to expose regions of an underlying material. The underlying material may be exposed to a precursor gas, such as a platinum precursor gas, that reacts with the underlying material without reacting with the remaining portions of the organic material located over the underlying material. The precursor gas may be used in an atomic layer deposition process, during which the precursor gas may selectively react with the underlying material to form a conductive structure, but not react with the organic material. The conductive structures may be used, for example, as a mask for patterning during various stages of semiconductor device fabrication. | 05-20-2010 |
| 20100144142 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES - A method of manufacturing a semiconductor device, forms connection pads electrically connected to integrated circuit portion formed in a semiconductor substrate, lays an insulating film and a protective film one over another, forms sub-lines electrically connected to the connection pads on the protective film, forms a coating film covering the sub-lines and the protective film, sticks a dry film onto the coating film, forms external connection electrodes externally connectable and electrically connected to the sub-lines, and removes the dry film and forms a sealing layer covering the coating film and side surfaces of the external connection electrodes. | 06-10-2010 |
| 20100159696 | MICROLENS MASK OF IMAGE SENSOR AND METHOD FOR FORMING MICROLENS USING THE SAME - Provided are a microlens mask of an image sensor and a method for forming a microlens using the same. In the method, an insulating layer is formed on a semiconductor substrate comprising a photodiode and a transistor. A passivation layer is formed on the insulating layer. A color filter layer is formed on the insulating layer vertically corresponding to the photodiode through the passivation layer. A microlens photoresist layer is formed over an entire surface of the semiconductor substrate. A microlens mask is formed on the microlens photoresist corresponding to the color filter layer. A one-time exposure process is performed at a light intensity of about 450/0 to about 550/0 dose/focus. The microlens photoresist layer is patterned to form a patterned microlens photoresist layer by removing the photoresist subjected to the exposure process. The patterned microlens photoresist layer is reflowed to form the microlens. | 06-24-2010 |
| 20100167537 | PARTITIONING FEATURES OF A SINGLE IC LAYER ONTO MULTIPLE PHOTOLITHOGRAPHIC MASKS - One embodiment relates to a computer method of providing an electronic mask set for an integrated circuit (IC) layer. In the method, a first electronic mask is generated for the IC layer. The first electronic mask includes a first series of longitudinal segments from the IC layer, where the first series has fewer than all of the longitudinal segments in the IC layer. A second electronic mask is also generated for the IC layer. The second electronic mask includes a second series of longitudinal segments from the IC layer, where the second series has fewer than all of the longitudinal segments in the IC layer and differs from the first series. The first and second masks are generated so a coupling segment extends traverse to the first direction and couples one longitudinal segment on the IC layer to another longitudinal segment on the IC layer. | 07-01-2010 |
| 20100184288 | Method of forming pattern structure - A method of forming a pattern structure includes forming a thin film pattern on a substrate, the thin film pattern including depression portions with first bottom widths, forming a protection layer on the thin film pattern by implanting ions into the thin film pattern, and etching a lower portion of the thin film pattern selectively using the protection layer as a mask to increase the first bottom widths of the depression portions into second bottom widths. | 07-22-2010 |
| 20100210108 | RADIATION-ASSISTED SELECTIVE DEPOSITION OF METAL-CONTAINING CAP LAYERS - A method for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices to improve electromigration and stress migration in bulk Cu metal. In one embodiment, the method includes providing a patterned substrate containing Cu metal surfaces and dielectric layer surfaces, exposing the patterned substrate to a process gas comprising a metal-containing precursor, and irradiating the patterned substrate with electromagnetic radiation, where selective metal-containing cap layer formation on the Cu metal surfaces is facilitated by the electromagnetic radiation. In some embodiments, the method further includes pre-treating the patterned substrate with additional electromagnetic radiation and optionally a cleaning gas prior to forming the metal-containing cap layer. | 08-19-2010 |
| 20100291768 | Method for Fabricating a Semiconductor Device - An exposure mask for recess gate includes a transparent substrate and a recess gate pattern. The recess gate pattern is disposed over the transparent substrate. The recess gate pattern includes a first portion having a first line width and a second portion having a second line width smaller than the first line width. In the second portion, elements of the recess gate pattern are separated. | 11-18-2010 |
| 20100304566 | ESTABLISHING A HYDROPHOBIC SURFACE OF SENSITIVE LOW-K DIELECTRICS OF MICROSTRUCTURE DEVICES BY IN SITU PLASMA TREATMENT - Silicon oxide based low-k dielectric materials may receive superior hydrophobic surface characteristics on the basis of a plasma treatment using hydrogen and carbon containing radicals. For this purpose, the surface of the low-k dielectric material may be exposed to these radicals, at least in one in situ process in combination with another reactive plasma ambient, for instance used for patterning the low-k dielectric material. Consequently, superior surface characteristics may be established or re-established without significantly contributing to product cycle time. | 12-02-2010 |
| 20100311240 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device according to an embodiment, includes forming a wiring in a surface of a first insulating film on a semiconductor substrate, exposing the first insulating film in whose surface the wiring is formed to a plasma containing a rare gas so as to form a densified layer on the surface of the first insulating film, removing an oxide film formed on the wiring, after the densified layer is formed and forming a second insulating film on the wiring from which the oxide film is removed and on the densified layer, wherein the processes from the removal of the oxide film to the formation of the second insulating film are carried out without being atmospherically-exposed. | 12-09-2010 |
| 20100317191 | COPPER INTERCONNECTION FOR FLAT PANEL DISPLAY MANUFACTURING - A method of depositing a copper interconnection layer on a substrate for use in a flat panel display interconnection system, comprising the steps of: a) coating said substrate with a photoresist layer; b) patterning said photoresist layer to obtain a patterned photoresist substrate comprising at least one trench patterned into said photoresist layer; c) providing a first catalyzation layer onto the patterned photoresist substrate; d) providing an electroless plated layer of an insulation layer deposited onto said first catalyzation layer; e) removing the successively superimposed photoresist layer, catalyzation layer and insulation layer except in the at least one trench, to obtain a pattern of the first catalyzation layer with an insulation layer deposited thereon. | 12-16-2010 |
| 20100317192 | MASKING METHOD - The invention relates to a method for masking a semiconductor substrate comprising the following steps: providing a planar semiconductor substrate having a first side and a second side lying opposite thereto, applying a mask to at least one of the sides, an extrusion printing method being envisaged for applying the mask. | 12-16-2010 |
| 20100317193 | INTEGRATED CIRCUIT FABRICATION - A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width. | 12-16-2010 |
| 20100323520 | Method of Forming Patterns of Semiconductor Device - A method of forming patterns of a semiconductor device comprises forming a number of first insulating patterns that define sidewalls by patterning a first insulating layer formed over a semiconductor substrate, forming second insulating patterns, each second insulating pattern comprising a horizontal portion having two ends and being parallel to the semiconductor substrate and spaced protruding portions protruding from both ends of the horizontal portion parallel to the sidewalls of the first insulating patterns, forming third insulating patterns each filling a space between the protruding portions, removing the protruding portions to form trenches, and forming conductive patterns within the respective trenches. | 12-23-2010 |
| 20110021023 | Surface Treatment of Silicon - A method of forming a resist pattern on a silicon semiconductor substrate having an anti-reflective layer thereon is described. The method includes the steps of a) modifying surface energy of the anti-reflective surface with a chemical treatment composition, b) applying a UV etch resist to the treated anti-reflective surface, and c) exposing the anti-reflective surface to a wet chemical etchant composition to remove exposed areas of the anti-reflective surface. Thereafter, the substrate can be metallized to provide a conductor pattern. The method may be used to produce silicon solar cells. | 01-27-2011 |
| 20110034028 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING POROUS LOW DIELECTRIC CONSTANT LAYER FORMED FOR INSULATION BETWEEN METAL LINES - The present invention related to a method for manufacturing a semiconductor device. More particularly, this method describes how to manufacture a semiconductor device having a porous, low dielectric constant layer formed between metal lines, comprising an insulation layer enveloping fillers. | 02-10-2011 |
| 20110053374 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - There is provided a method for manufacturing a semiconductor device which is capable of stably forming a plated layer on a plating base layer while adhered chippings are reduced. The method includes forming an insulating film covering at least a base metal on a diffusion region of a semiconductor substrate, forming an organic coating film having an opening at least at a surface section of the base metal being to be exposed on the insulating film, pasting a surface protection tape on the semiconductor substrate to cover the insulating film and the organic coating film, polishing a back surface of the semiconductor substrate that opposes the base metal, removing the surface protection tape, etching the insulating film with the organic coating film used as a mask to expose the base metal and forming a conductive plated layer on the base metal. | 03-03-2011 |
| 20110053375 | METHOD FOR PROCESSING AMORPHOUS CARBON FILM, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD USING THE METHOD - A method for processing an amorphous carbon film which has been formed on a substrate and wet-cleaned after being dry-etched includes preparing the substrate having the wet-cleaned amorphous carbon film and modifying a surface of the amorphous carbon film, before forming an upper layer on the wet-cleaned amorphous carbon film. | 03-03-2011 |
| 20110076847 | LASER SYSTEM FOR PROCESSING SOLAR WAFERS IN A CARRIER - An apparatus and method for processing the solar cell substrates is provided. In one embodiment, a laser firing chamber for processing solar cell substrates placed in a carrier, comprising a laser module located at a side of the carrier, the laser module being adapted to generate and direct multiple laser beams over an entire surface of a plurality of solar cell substrates, and a transport adapted to convey the carrier through an outputting region of the laser beams. | 03-31-2011 |
| 20110081777 | Methods of forming a pattern and methods of fabricating a semiconductor device having a pattern - Methods of forming a pattern and methods of fabricating a semiconductor device having a pattern are provided, the methods include forming a self-assembly induction layer including a first region and a second region on a semiconductor substrate. A block copolymer layer is coated on the self-assembly induction layer. A first pattern, a second pattern and a third pattern are formed by phase separating the block copolymer. At least one of the first, second and third patterns may be removed to form a preliminary pattern. An etching process may be performed using the preliminary pattern as an etching mask. The first pattern contains the same material as that of the second pattern, and the third pattern contains a material different from that of the first pattern. | 04-07-2011 |
| 20110159688 | Selective Metal Deposition Over Dielectric Layers - Selective deposition of metal over dielectric layers in a manner that minimizes or eliminates keyhole formation is provided. According to one embodiment, a dielectric target layer is formed over a substrate layer, wherein the target layer may be configured to allow conformal metal deposition, and a dielectric second layer is formed over the target layer, wherein the second layer may be configured to allow bottom-up metal deposition. An opening may then be formed in the second layer and metal may be selectively deposited over the substrate layer. | 06-30-2011 |
| 20110159689 | PRINTING PLATE AND METHOD FOR FABRICATING THE SAME - A printing plate and method for fabricating the same is disclosed. A metal layer is first formed on a glass substrate. The metal layer is then patterned in a predetermined shape. The glass substrate is next etched to a predetermined depth using the patterned metal layer as a mask and the metal layer removed. If necessary, additional metal layers have the same or different patterns may be formed on the glass substrate and the glass substrate etched after each metal layer is formed thereon until a desired etching depth in the glass is achieved. | 06-30-2011 |
| 20110177689 | Methods for Forming Wiring and Manufacturing Thin Film Transistor and Droplet Discharging Method - It is required that a line width of a wiring is prevented from being wider to be miniaturized when the wiring or the like is formed by a dropping method typified by an ink-jetting method. The invention provides a method for narrowing (miniaturizing) a line width according to a method different from a conventional method. One feature of the invention is that a plasma treatment is performed before forming a wiring or the like by a dropping method typified by an ink-jetting method. As the result of the plasma treatment, a surface for forming a conductive film is modified to be liquid-repellent. Consequently, a wiring or the like formed by a dropping method can be miniaturized. | 07-21-2011 |
| 20110217842 | METHOD FOR FORMING SEMICONDUCTOR DEVICE - A method for manufacturing semiconductor device includes forming an interlayer dielectric layer including a contact plug defined therein to electrically couple a semiconductor substrate on which a cell region and a dummy region are defined. A sacrificial layer is formed over the interlayer dielectric layer. An etch stop pattern is formed over the sacrificial layer, the etch stop pattern being vertically aligned to the dummy region. A storage electrode region through the sacrificial layer is defined to expose a first storage electrode contact of the cell region, the second storage electrode contact of the dummy region remaining covered by the sacrificial layer. A conductive layer is deposited within the storage electrode region to form a storage electrode contacting the first storage electrode contact of the cell region. | 09-08-2011 |
| 20120009787 | METHOD FOR FORMING MASKING LAYER BY USING ION IMPLANTATION AND SEMICONDUCTOR DEVICE FABRICATED BY USING THE SAME - A method for forming a masking layer of a semiconductor device includes forming a plurality of pillar structures separated by a trench, forming a gap-fill material partially filling the trench and exposing an upper sidewall of each pillar structure, forming a masking layer that covers the pillar structures and the gap-fill material, performing an ion implantation to the masking layer to form an implanted portion covering upper portion of the gap-fill material and one side of the upper sidewalls of each pillar structure and a non-implanted portion covering the other side of the upper sidewalls of each pillar structure, forming a sacrificial layer over the masking layer, exposing the non-implanted portion of the masking layer, and selectively removing the exposed non-implanted portion. | 01-12-2012 |
| 20120064716 | FILM FORMING APPARATUS AND A BARRIER FILM PRODUCING METHOD - A film forming apparatus is used in a semiconductor manufacturing process and a method for producing a barrier film is used for a semiconductor. When a metallic gas and a reactive gas are alternatively flown, a back-flow preventing gas and an auxiliary gas are flown, the reactive gas and the auxiliary gas are moved with the flow of the back-flow preventing gas, and radicals are produced by being in contact with them to a catalytic material. Since the metallic material gas is not in contact with the catalytic material, the catalytic material is not degraded. A shower plate may be disposed between a radical producing chamber and a reaction chamber, so that the radicals are fed into the reaction chamber through holes. Thus, a barrier film having low resistance and excellent coverage is formed. | 03-15-2012 |
| 20120208365 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming an insulating film on a surface of a semiconductor layer, forming a resist on a surface of the insulating film, the resist having an opening, forming a hardened layer on an inner circumference of the resist by attaching a pattern shrinking agent to the resist, the pattern shrinking agent undergoing a cross-linking reaction with the resist, etching the insulating film using the resist and the hardened layer as masks, removing the hardened layer, and forming a metal layer on a surface of the semiconductor layer, on a surface of the insulating film, and on a surface of the resist. The method further includes removing the resist and the portion of the metal layer on the surface of the resist by lift-off. | 08-16-2012 |
| 20120252211 | METHOD FOR PATTERNING A LACQUER LAYER TO HOLD ELECTRICAL GRIDLINES - A method is provided for simultaneously forming functional light structures and grooves configured to hold electrical circuitry on a lacquer layer deposited on a base substrate, which is for use in an optoelectronic device. The method includes applying the lacquer layer on the base substrate and heating it beyond its glass transition temperature to soften it. Thereafter, a stamper is used to simultaneously replicate the grooves and the functional light structures onto the lacquer layer. The stamper has a mating surface, which has negative impressions of the grooves on its first portion and the functional light structures on its second portion. Thereafter, the lacquer layer is cooled and the electrical circuitry is formed in the grooves on the lacquer layer. | 10-04-2012 |
| 20120289045 | METHOD FOR MAKING HOLES USING A FLUID JET - The method for making a hole in a layer includes the provision of first and second adhesion areas on a surface of a support. The first area has dimensions corresponding to the dimensions of the hole. The method includes depositing a layer on the first and second adhesion areas. The material of the layer has an adhesion coefficient to the first area lower than the adhesion coefficient to the second area. The part of layer arranged above the first area is eliminated by a fluid jet. | 11-15-2012 |
| 20130040459 | SUBSTRATE WIRING METHOD AND SEMICONDUCTOR MANUFACTURING DEVICE - In a substrate wiring method, copper is embedded all the way to the lowest parts of a wiring pattern formed on a substrate. The method is used to wire a substrate in a processing chamber kept in a vacuum state, the substrate having a wiring pattern formed thereon. The method includes a preprocessing step in which the wiring pattern on the substrate is cleaned using a desired cleaning gas and an embedding step in which, after the preprocessing step, metal nanoparticles are embedded in the wiring pattern using a clustered metal gas. | 02-14-2013 |
| 20130224951 | TEMPLATE AND SUBSTRATE PROCESSING METHOD - A template for feeding a processing solution to predetermined positions of a substrate has multiple opening portions formed in positions on a front surface corresponding to the predetermined positions, flow channels penetrating from the opening portions to a back surface in a thickness direction for flowing a processing solution, first hydrophilic regions set to be hydrophilic around the opening portions on the front surface, and second hydrophilic regions set to be hydrophilic on inner surfaces of flow channels. The first hydrophilic regions are formed in positions corresponding to hydrophilic patterns set to be hydrophilic around the predetermined positions on a substrate surface. | 08-29-2013 |
| 20130280908 | METAL ASSISTED CHEMICAL ETCHING TO PRODUCE III-V SEMICONDUCTOR NANOSTRUCTURES - Methods of metal assisted chemical etching III-V semiconductors are provided. The methods can include providing an electrically conductive film pattern disposed on a semiconductor substrate comprising a III-V semiconductor. At least a portion of the III-V semiconductor immediately below the conductive film pattern may be selectively removed by immersing the electrically conductive film pattern and the semiconductor substrate into an etchant solution comprising an acid and an oxidizing agent having an oxidation potential less than an oxidation potential of hydrogen peroxide. Such methods can form high aspect ratio semiconductor nanostructures. | 10-24-2013 |
| 20130309866 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device according to an embodiment, includes forming a wiring in a surface of a first insulating film on a semiconductor substrate, exposing the first insulating film in whose surface the wiring is formed to a plasma containing a rare gas so as to form a densified layer on the surface of the first insulating film, removing an oxide film formed on the wiring, after the densified layer is formed and forming a second insulating film on the wiring from which the oxide film is removed and on the densified layer, wherein the processes from the removal of the oxide film to the formation of the second insulating film are carried out without being atmospherically-exposed. | 11-21-2013 |
| 20140017889 | METHOD FOR FORMING FINE PATTERN OF SEMICONDUCTOR DEVICE USING DOUBLE SPACER PATTERNING TECHNOLOGY - A method of forming a fine pattern of a semiconductor device using double SPT process, which is capable of implementing a line and space pattern having a uniform fine line width by applying a double SPT process including a negative SPT process, is provided. The method includes a first SPT process and a second SPT process and the second SPT process includes a Negative SPT process. | 01-16-2014 |
| 20140106564 | ADDITIVE CONDUCTOR REDISTRIBUTION LAYER (ACRL) - A first plate-able layer is selectively plated to form one or more redistribution paths. The connection points of an IC package are connected to the redistribution paths, and the IC package is over molded for stability. The first plate-able layer is then removed, leaving the one or more redistribution paths exposed. The redistribution paths allow one or more contact points of the IC package to be moved to a new location in order to facilitate integration of the IC package into a system. By plating the redistribution paths up from the first plate-able layer, fine geometries for repositioning the contact points of the IC package with minimal conductor thickness are achieved without the need for specialized manufacturing equipment. Accordingly, a redistribution layer is formed at a low cost while minimizing the impact of the layer on the operation of the IC device. | 04-17-2014 |
| 20140248771 | METHODS FOR FORMING A CONDUCTIVE MATERIAL AND METHODS FOR FORMING A CONDUCTIVE STRUCTURE - A method of forming a conductive material comprises forming at least one opening extending through an organic material and an insulative material underlying the organic material to expose at least a portion of a substrate and a conductive contact in the substrate. The method further comprises lining exposed surfaces of the insulative material, the conductive contact, and the at least a portion of the substrate in the at least one opening with a conductive material without forming the conductive material on the organic material. | 09-04-2014 |
| 20140273449 | MAGNETIC TRAP FOR CYLINDRICAL DIAMAGNETIC MATERIALS - A system for self-aligning diamagnetic materials includes first and second magnets contacting each other along a contact line and having a diametric magnetization perpendicular to the contact line and a diamagnetic rod positioned to levitate above the contact line of the first and second magnets. | 09-18-2014 |
| 20140273450 | MAGNETIC TRAP FOR CYLINDRICAL DIAMAGNETIC MATERIALS - A method of arranging a diamagnetic rod includes levitating a diamagnetic rod above a contact line at which a first magnet contacts a second magnet, the first magnet and the second magnet having diametric magnetization in a direction perpendicular to the contact line. | 09-18-2014 |
| 20150056806 | INTERCONNECT STRUCTURE WITH ENHANCED RELIABILITY - An improved interconnect structure including a dielectric layer having a conductive feature embedded therein, the conductive feature having a first top surface that is substantially coplanar with a second top surface of the dielectric layer; a metal cap layer located directly on the first top surface, wherein the metal cap layer does not substantially extend onto the second top surface; a first dielectric cap layer located directly on the second top surface, wherein the first dielectric cap layer does not substantially extend onto the first top surface and the first dielectric cap layer is thicker than the metal cap layer; and a second dielectric cap layer on the metal cap layer and the first dielectric cap layer. A method of forming the interconnect structure is also provided. | 02-26-2015 |
| 20150111380 | Self-aligned Double Patterning - A system and method for a semiconductor device are provided. An embodiment comprises a dielectric layer and masking layers over the dielectric layer. A thin spacer layer is used to form spacers alongside a pattern. A reverse image of the spacer pattern is formed and an enlargement process is used to slightly widen the pattern. The widened pattern is subsequently used to pattern an underlying layer. This process may be used to form a pattern in a dielectric layer, which openings may then be filled with a conductive material. | 04-23-2015 |
| 20150132951 | Surface Poisoning Using ALD For High Selectivity Deposition Of High Aspect Ratio Features - Methods of selectively depositing a feature onto a substrate surface while maintaining substantially straight sidewalls on the feature. A portion of the feature is grown and then covered with a protective film. The protective film is removed from the top of the feature, leaving some of the film on the sides of the feature and the process is repeated to grow a feature of desired thickness. | 05-14-2015 |
| 20150132952 | Air Gap Formation by Damascene Process - The present disclosure provides a method for forming a semiconductor device. The method includes forming first conductive layer structures in a first dielectric layer on a substrate; forming a patterned photoresist layer having portions that are each disposed over a respective one of the first conductive layer structures; forming an energy removable film (ERF) on the sidewalls of each of the portions; forming a second dielectric layer over the ERFs, the portions of the patterned photoresist layer, and the first dielectric layer; removing the portions to leave behind a plurality of openings; filling a conductive material in the openings, the conductive material defining second conductive layer structures; forming a ceiling layer over the second conductive layer structures, the ERFs, and the second dielectric layer; and applying energy to the ERFs to partially remove the ERFs on the sidewalls of the portions thereby forming air gaps. | 05-14-2015 |
| 20160027685 | METHODS FOR FABRICATING INTEGRATED CIRCUITS USING DIRECTED SELF-ASSEMBLY - Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a graphoepitaxy DSA directing confinement well using a sidewall of an etch layer that overlies a semiconductor substrate. The graphoepitaxy DSA directing confinement well is filled with a block copolymer. The block copolymer is phase separated into an etchable phase and an etch resistant phase. The etchable phase is etched while leaving the etch resistant phase substantially in place to define an etch mask with a nanopattern. The nanopattern is transferred to the etch layer. | 01-28-2016 |
| 20160104624 | Methods For Depositing Fluorine/Carbon-Free Conformal Tungsten - Provided are atomic layer deposition methods to deposit a tungsten film or tungsten-containing film using a tungsten-containing reactive gas comprising one or more of tungsten pentachloride, a compound with the empirical formula WCl | 04-14-2016 |
| 20160202610 | THINNER COMPOSITIONS AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME | 07-14-2016 |
