| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438677000 | Pretreatment of surface to enhance or retard deposition | 9 |
| 20090004857 | Method of manufacturing a semiconductor device using the self aligned contact (SAC) process flow for semiconductor devices with aluminum metal gates - In one embodiment, a method, comprises forming a diffusion layer on a semiconductor substrate, forming a selectively deposited metal or metal alloy on an aluminum gate structure by removing an aluminum oxide layer from the aluminum gate structure and depositing a zinc layer on the aluminum gate structure by a zincating process, and selectively depositing a sacrificial metal or metal alloy cap on the aluminum gate layer by displacing the zinc layer. This embodiment enables the SAC process flow on devices with Aluminum gates. | 01-01-2009 |
| 20100136788 | THERMAL METHODS FOR CLEANING POST-CMP WAFERS - Methods for cleaning semiconductor wafers following chemical mechanical polishing are provided. An exemplary method exposes a wafer to a thermal treatment in an oxidizing environment followed by a thermal treatment in a reducing environment. The thermal treatment in the oxidizing environment both removes residues and oxidizes exposed copper surfaces to form a cupric oxide layer. The thermal treatment in the reducing environment then reduces the cupric oxide to elemental copper. This leaves the exposed copper clean and in condition for further processing, such as electroless plating. | 06-03-2010 |
| 20100184289 | SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A photosensitive transparent resin film, provided selectively with a groove reaching a transparent substrate is formed on the transparent substrate, and a wiring portion is provided in the groove substantially in flush with the photosensitive transparent resin film. The wiring portion can be formed quickly while controlling the thickness easily by preprocessing the surface of the photosensitive transparent resin film or the bottom face of the groove before the wiring portion is set in the groove. | 07-22-2010 |
| 20110059609 | FABRICATION METHOD OF TWO-TERMINAL SEMICONDUCTOR COMPONENT USING TRENCH TECHNOLOGY - A method of fabricating a two-terminal semiconductor component using a trench technique is disclosed that includes forming a trench by etching an etching pattern formed on a substrate on which an active layer having impurities added is grown, forming a front metal layer on a front upper surface of the substrate by using an evaporation method or a sputtering method after removing the etching pattern, forming a metal plated layer on the front surface of the substrate on which the front metal layer is formed, polishing a lower surface of the substrate by using at least one of a mechanical polishing method and a chemical polishing method until the front metal layer is exposed, forming a rear metal layer on the polished substrate, and removing each component by using at least one of a dry etching method and a wet etching method. | 03-10-2011 |
| 20110244680 | SURFACE CLEANING AND SELECTIVE DEPOSITION OF METAL-CONTAINING CAP LAYERS FOR SEMICONDUCTOR DEVICES - A method is provided for integrating metal-containing cap layers into copper (Cu) metallization of semiconductor devices. In one embodiment, the method includes providing a planarized patterned substrate containing metal surfaces and dielectric layer surfaces with a residue formed thereon, removing the residue from the planarized patterned substrate, and depositing metal-containing cap layers selectively on the metal surfaces by exposing the dielectric layer surfaces and the metal surfaces to a deposition gas containing metal-containing precursor vapor. The removing includes treating the planarized patterned substrate containing the residue with a reactant gas containing a hydrophobic functional group, and exposing the treated planarized patterned substrate to a reducing gas. | 10-06-2011 |
| 20150044871 | METHOD FOR INCREASING ADHESION OF COPPER TO POLYMERIC SURFACES - Techniques disclosed herein a method and system for conditioning a polymeric layer on a substrate to enable adhesion of a metal layer to the polymeric layer. Techniques may include conditioning the polymeric layer with nitrogen-containing plasma to generate a nitride layer on the surface of the polymeric layer. In another embodiment, the conditioning may include depositing a CuN layer using a lower power copper sputtering process in a nitrogen rich environment. Following the condition process, a higher power copper deposition or sputtering process may be used to deposit copper onto the polymeric layer with good adhesion properties. | 02-12-2015 |
| 20150294908 | METHOD OF FABRICATING ULTRA SHORT GATE LENGTH THIN FILM TRANSISTORS USING OPTICAL LITHOGRAPHY - A method is provided for fabricating an ultra short gate length thin film transistor. A plurality of layers is deposited on a substrate including a refractory metal and a first and second photosensitive material. The second material is sensitive to longer wavelength optical radiation than the first material and the first material is not soluble in chemicals used to develop or strip the second material. A source contact pattern is defined in the second material to mask the first photosensitive material. The first material is processed to produce an undercut of the first material with respect to the second material. A metal layer is deposited at a normal incidence on the second material and an exposed portion of the refractory metal. The second material is removed. Exposed portions of the refractory metal corresponding to the undercut of the first material are removed to form a gap in the refractory metal. | 10-15-2015 |
| 20150325446 | SELECTIVE COBALT DEPOSITION ON COPPER SURFACES - Embodiments of the invention provide processes to selectively form a cobalt layer on a copper surface over exposed dielectric surfaces. In one embodiment, a method for capping a copper surface on a substrate is provided which includes positioning a substrate within a processing chamber, wherein the substrate contains a contaminated copper surface and a dielectric surface, exposing the contaminated copper surface to a reducing agent while forming a copper surface during a pre-treatment process, exposing the substrate to a cobalt precursor gas to selectively form a cobalt capping layer over the copper surface while leaving exposed the dielectric surface during a vapor deposition process, and depositing a dielectric barrier layer over the cobalt capping layer and the dielectric surface. In another embodiment, a deposition-treatment cycle includes performing the vapor deposition process and subsequently a post-treatment process, which deposition-treatment cycle may be repeated to form multiple cobalt capping layers. | 11-12-2015 |
| 20160042991 | MOLECULAR SELF-ASSEMBLY IN SUBSTRATE PROCESSING - Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to an organosilane, where the organosilane includes a hydrolysable group for facilitating attachment with the porous dielectric, and where the organosilane does not include an alkyl group; and forming a layer as a result of the exposing to seal the porous dielectric. In some embodiments, methods are presented where the organosilane includes: alkynyl groups, aryl groups, flouroalkyl groups, heteroarlyl groups, alcohol groups, thiol groups, amine groups, thiocarbamate groups, ester groups, ether groups, sulfide groups, and nitrile groups. In some embodiments, method further include: removing contamination from the porous dielectric and a conductive region of the substrate prior to the exposing; and removing contamination from the conductive region after the forming. | 02-11-2016 |
