Entries |
Document | Title | Date |
20080213999 | Compositions and methods for forming and depositing metal films on semiconductor substrates using supercritical solvents - Compositions and methods for depositing elemental metal M(0) films on semiconductor substrates are disclosed. One of the disclosed methods comprises: heating the semiconductor substrate to obtain a heated semiconductor substrate; exposing the heated semiconductor substrate to a composition containing a metal precursor, an excess amount of neutral labile ligands, and a supercritical solvent; exposing the metal precursor to a reducing agent and/or thermal energy at or near the heated semiconductor substrate; reducing the metal precursor to the elemental metal M(0) by using the reducing agent and/or the thermal energy; and depositing the elemental metal M( | 09-04-2008 |
20080242083 | Method for Manufacturing Memory Element - A first conductive layer is formed, a composition layer over the first conductive layer is formed by discharging a composition in which nanoparticles comprising a conductive material covered with an organic material are dispersed in a solvent, and the composition layer is dried. Subsequently, pretreatment is performed in which the organic material covering the nanoparticles, which are positioned on a surface of the composition layer, is decomposed, and then baking is performed. In this manner, a second conductive layer is formed by sintering nanoparticles which are positioned on a surface of the composition layer. A memory layer is formed between the first conductive layer and the second conductive layer using the nanoparticles covered with the organic materials to which the pretreatment is not performed. | 10-02-2008 |
20080268637 | Electrically conductive composition for via-holes - The present invention relates to an electrically conductive composition for filling via-holes formed in an electronic circuit substrate containing an electrically conductive metal and a vehicle, wherein the content of the electrically conductive metal is 57 vol % or more, and the composition is a plastic fluid for which fluidity increases when external pressure is applied to the composition. | 10-30-2008 |
20090004851 | SALICIDATION PROCESS USING ELECTROLESS PLATING TO DEPOSIT METAL AND INTRODUCE DOPANT IMPURITIES - A selective electroless plating operation provides for the selective deposition of a metal film only on exposed silicon surfaces of a semiconductor substrate and not on other surfaces such as dielectric surfaces. The plating solution includes metal ions and advantageously also includes dopant impurity ions. The pure metal or metal alloy film formed on the exposed silicon surfaces is then heat treated to form a metal silicide on the exposed silicon surfaces and to drive the dopant impurities to the interface formed between the exposed silicon surfaces and the metal silicide film. | 01-01-2009 |
20090017617 | METHOD FOR FORMATION OF HIGH QUALITY BACK CONTACT WITH SCREEN-PRINTED LOCAL BACK SURFACE FIELD - A thin silicon solar cell having a back dielectric passivation and rear contact with local back surface field is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness from 50 to 500 micrometers. A barrier layer and a dielectric layer are applied at least to the back surface of the silicon wafer to protect the silicon wafer from deformation when the rear contact is formed. At least one opening is made to the dielectric layer. An aluminum contact that provides a back surface field is formed in the opening and on the dielectric layer. The aluminum contact may be applied by screen printing an aluminum paste having from one to 12 atomic percent silicon and then applying a heat treatment at 750 degrees Celsius. | 01-15-2009 |
20090017618 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of forming a semiconductor device that includes heating a wafer on which an Al—Cu sputtering thin film is formed before patterning the Al—Cu sputtering thin film. The heating is performed at a temperature no less than a solid solution temperature of copper or at a temperature between 300° C. and 600° C. The process temperature in heating the process wafer is not higher than the flow temperature of aluminum or is the temperature at which a reflow process can be performed. | 01-15-2009 |
20090075476 | MANUFACTURING METHOD OF SUBSTRATE HAVING CONDUCTIVE LAYER AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The manufacturing method of a substrate having a conductive layer has the steps of: forming an inorganic insulating layer over a substrate; forming an organic resin layer with a desired shape over the inorganic insulating layer; forming a low wettability layer with respect to a composition containing conductive particles on a first exposed portion of the inorganic insulating layer; removing the organic resin layer; and coating a second exposed portion of the inorganic insulating layer with a composition containing conductive particles and baking, thereby forming a conductive layer. | 03-19-2009 |
20090098730 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes a lower wire, an interlayer insulating film formed on the lower wire and having a via hole exposing the upper surface of the lower wire, a diffusion barrier formed on the inner wall of the via hole, and an upper wire filling the via hole and directly contacting the lower wire, in which a dopant region containing a component of the diffusion barrier is formed in the lower wire in the extension direction of the via hole. | 04-16-2009 |
20090117736 | AMMONIA-BASED PLASMA TREATMENT FOR METAL FILL IN NARROW FEATURES - A method for fabricating a semiconductor device is described. A substrate is provided having a patterned dielectric layer disposed thereon. A trench is formed in the dielectric layer. The surfaces of the trench are treated with an ammonia-based plasma process. A metal layer is then formed in the trench. | 05-07-2009 |
20090149022 | METHOD FOR IMPROVING UNIFORMITY AND ADHESION OF LOW RESISTIVITY TUNGSTEN FILM - Methods of improving the uniformity and adhesion of low resistivity tungsten films are provided. Low resistivity tungsten films are formed by exposing the tungsten nucleation layer to a reducing agent in a series of pulses before depositing the tungsten bulk layer. According to various embodiments, the methods involve reducing agent pulses with different flow rates, different pulse times and different interval times. | 06-11-2009 |
20090170312 | METHOD FOR PRODUCING A MICROMECHANICAL AND/OR NANOMECHANICAL DEVICE WITH ANTI-BONDING STOPS - A method for producing a micromechanical and/or nanomechanical device comprising the steps of: | 07-02-2009 |
20090258490 | METHOD FOR FORMING CONDUCTIVE FILM - A method for forming a conductive film, includes: applying a dispersion liquid above a substrate, the dispersion liquid including a plurality of conductive fine-particles made of one conductive material selected from the group consisting of copper, nickel, and an alloy that includes copper or nickel as a main component; and forming the conductive film made from the conductive fine-particles, by heating the dispersion liquid that has been applied above the substrate in an atmosphere including formic acid, by baking the conductive fine-particles so that the conductive fine-particles are mutually fusion bonded. | 10-15-2009 |
20090280644 | Process for Producing Air Gaps in Microstructures, Especially of the Air Gap Interconnect Structure Type for Integrated Circuits - The invention relates to a process for producing at least one air gap in a microstructure, which comprises: | 11-12-2009 |
20090298283 | CONDUCTIVE COMPOSITIONS AND PROCESSES FOR USE IN THE MANUFACTURE OF SEMICONDUCTOR DEVICES - ORGANIC MEDIUM COMPONENTS - Embodiments of the invention relate to a silicon semiconductor device, and a conductive paste for use in the front side of a solar cell device. | 12-03-2009 |
20100041230 | METHODS FOR FORMING COPPER INTERCONNECTS FOR SEMICONDUCTOR DEVICES - Methods for forming copper interconnects for semiconductor devices are provided. In an exemplary embodiment, a method for forming a copper interconnect comprises depositing copper into a trench formed in a dielectric material overlying a semiconductor material. A force is applied to the semiconductor material and stress is induced within the copper deposited in the trench. Recrystallization and grain growth are effected within the copper and the stress is removed. | 02-18-2010 |
20100120245 | PLASMA AND THERMAL ANNEAL TREATMENT TO IMPROVE OXIDATION RESISTANCE OF METAL-CONTAINING FILMS - Method and apparatus are provided for treatment of a deposited material layer. In one embodiment, a method is provided for processing a substrate including depositing a metal-containing layer using an atomic layer deposition technique, exposing the metal-containing layer to a plasma treatment process at a temperature of less than about 200° C., and exposing the metal-containing layer to a thermal anneal process at a temperature of about 600° C. or greater. The plasma treatment process and/or the thermal anneal process may use a nitrating gas, which may form a passivating surface or layer with the metal-containing layer. | 05-13-2010 |
20100151676 | DENSIFICATION PROCESS FOR TITANIUM NITRIDE LAYER FOR SUBMICRON APPLICATIONS - Embodiments of the present invention provide methods of forming and densifying a titanium nitride barrier layer. The densification process is performed at a relatively low RF plasma power and high nitrogen to hydrogen ratio so as to provide a substantially titanium rich titanium nitride barrier layer. In one embodiment, a method for forming a titanium nitride barrier layer on a substrate includes depositing a titanium nitride layer on the substrate by a metal-organic chemical vapor deposition process, and performing a plasma treatment process on the deposited titanium nitride layer, wherein the plasma treatment process operates to densify the deposited titanium nitride layer, resulting in a densified titanium nitride layer, wherein the plasma treatment process further comprises supplying a plasma gas mixture containing a nitrogen gas to hydrogen gas ratio between about 20:1 and about 3:1, and applying less than about 500 Watts RF power to the plasma gas mixture. | 06-17-2010 |
20100159694 | METHOD FOR DEPOSITING THIN TUNGSTEN FILM WITH LOW RESISTIVITY AND ROBUST MICRO-ADHESION CHARACTERISTICS - Methods of forming low resistivity tungsten films with good uniformity and good adhesion to the underlying layer are provided. The methods involve forming a tungsten nucleation layer using a pulsed nucleation layer process at low temperature and then treating the deposited nucleation layer prior to depositing the bulk tungsten fill. The treatment operation lowers resistivity of the deposited tungsten film. In certain embodiments, the depositing the nucleation layer involves a boron-based chemistry in the absence of hydrogen. Also in certain embodiments, the treatment operations involve exposing the nucleation layer to alternating cycles of a reducing agent and a tungsten-containing precursor. The methods are useful for depositing films in high aspect ratio and/or narrow features. The films exhibit low resistivity at narrow line widths and excellent step coverage. | 06-24-2010 |
20100227475 | METHOD OF FORMING AN ELECTRONIC DEVICE USING A SEPARATION TECHNIQUE - A method of forming an electronic device can include forming a metallic layer by an electrochemical process over a side of a substrate that includes a semiconductor material. The method can also include introducing a separation-enhancing species into the substrate at a distance from the side, and separating a semiconductor layer and the metallic layer from the substrate, wherein the semiconductor layer is a portion of the substrate. In a particular embodiment, the separation-enhancing species can be incorporated into a metallic layer and moved into the substrate, and in particular embodiment, the separation-enhancing species can be implanted into the substrate. In still another embodiment, both the techniques can be used. In a further embodiment, a dual-sided process can be performed. | 09-09-2010 |
20100248474 | METHOD OF FORMING COATING-TYPE FILM - An aspect of the present invention, there is provided a method for providing a coating-type film, including, coating a solution including an organic metal compound on a surface of a substrate including a semiconductor substrate to form a coating film, heating the coating film to volatize a solvent in the coating film, and performing a treatment including at least one of a heat treatment, an ozone treatment and a moisture treatment to remove impurities from the coating film. | 09-30-2010 |
20110097898 | IMPROVED METHOD FOR DEGASSING CABLES - The present invention is a method for degassing an electrical cable having a crosslinked, semiconductive shield layer prepared from a composition made from or containing (i) a phase I material consisting essentially of a polar copolymer of ethylene and an unsaturated ester having 4 to 20 carbon atoms, (ii) a phase II material consisting essentially of a nonpolar, low density polyethylene, and (iii) a conducting filler material dispersed in the phase I material and/or the phase II material. The de-gassing temperature is greater than 70 degrees Celsius. | 04-28-2011 |
20110151665 | METHOD FOR NON-CONTACT MATERIALS DEPOSITION - Embodiments of the invention are directed to a method of printing lines. The method may include depositing material on a substrate from a plurality of nozzles to form a multi-layered line of a desired cross section area or a desired height by dispensing the material in at least two layers in a single scan. Each layer may be printed by different nozzles and the number of layers in the line is determined based on the desired cross section area or height. | 06-23-2011 |
20110269310 | SELECTIVE SILICIDE PROCESS - A method of self-aligned silicidation on structures having high aspect ratios involves depositing a metal oxide film using atomic layer deposition (ALD) and converting the metal oxide film to metal film in order to obtain uniform step coverage. The substrate is then annealed such that the metal in regions directly overlying the patterned and exposed silicon reacts with the silicon to form uniform metal silicide at the desired locations. | 11-03-2011 |
20110312179 | SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS - The present invention provides a substrate processing method and a substrate processing apparatus, which are capable of forming a high-k dielectric film with few trapping levels due to oxygen deficiencies and hot carriers by a sputtering method in one and the same vacuum vessel. The substrate processing method according to a first embodiment of the present invention includes: a first step of heating a to-be-processed substrate ( | 12-22-2011 |
20110318920 | LOW TEMPERATURE, LONG TERM ANNEALING OF NICKEL CONTACTS TO LOWER INTERFACIAL RESISTANCE - A method of annealing semiconductor devices to form substantially ohmic contact regions between a layer of wide band-gap semiconductor material and contact areas disposed thereon includes exposing the semiconductor devices to an annealing temperature less than approximately 900 degrees Celsius for an annealing duration of greater than approximately two hours. | 12-29-2011 |
20120009782 | APPARATUS AND METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT - The present invention relates to an apparatus for manufacturing an integrated circuit ( | 01-12-2012 |
20120034776 | DEVICE OF FILLING METAL IN THROUGH-VIA-HOLE OF SEMICONDUCTOR WAFER AND METHOD USING THE SAME - A device of filling metal in a through-via-hole formed in a semiconductor wafer and a method of filling metal in a through-via-hole using the same are disclosed. A device of filling metal in a through-via-hole formed in a semiconductor wafer includes a jig base comprising a jig configured to fix the wafer having the through-via-hole formed therein; a upper chamber 120 installed on the jig base; a lower chamber installed under the jig base; a heater installed in the upper chamber, the heater configured to apply heat to filling metal placed on the wafer to melt the filling metal; and a vacuum pump configured to generate pressure difference between the upper chamber and the lower chamber by the pressure of the lower chamber reduced by discharging air of the lower chamber 130 outside, only to fill the melted filling metal in the through-via-hole. | 02-09-2012 |
20120083118 | METHODS OF EVAPORATING METAL ONTO A SEMICONDUCTOR WAFER IN A TEST WAFER HOLDER - Apparatus and methods for evaporating metal onto semiconductor wafers are disclosed. One such apparatus can include an evaporation chamber that includes a wafer holder, such as a dome, and a test wafer holder that is separate and spaced apart from the wafer holder. In certain implementations, the test wafer can be coupled to a cross beam supporting at least one shaper. A metal can be evaporated onto production wafers positioned in the wafer holder while metal is evaporated on a test wafer positioned in a test wafer holder. In some instances, the production wafers can be GaAs wafers. The test wafer can be used to make a quality assessment about the production wafers. | 04-05-2012 |
20120100714 | Method of Fabricating a Landing Plug in a Semiconductor Device - A method of fabricating a landing plug in a semiconductor memory device, which in one embodiment includes forming a landing plug contact hole on a semiconductor substrate having an impurity region to expose the impurity region; forming a landing plug by filling the landing plug contact hole with a polysilicon layer, wherein the landing plug is divided into a first region, a second region, a third region, and a fourth region from a lower portion of the landing plug, and the first region is doped with a first doping concentration that is relatively lowest, the second region is doped with a second doping concentration that is higher than the first doping concentration, the third region is doped with a third doping concentration that is higher than the second doping concentration and the fourth region is not doped; and annealing the resulting product formed with the landing plug. | 04-26-2012 |
20120156873 | METHOD FOR RESTRICTING LATERAL ENCROACHMENT OF METAL SILICIDE INTO CHANNEL REGION - A method for restricting lateral encroachment of the metal silicide into the channel region, comprising: providing a semiconductor substrate, a gate stack being formed on the semiconductor substrate, a source region being formed in the semiconductor on one side of the gate stack, and a drain region being formed in the semiconductor substrate on the other side of the gate stack; forming a sacrificial spacer around the gate stack and on the semiconductor substrate; depositing a metal layer for covering the semiconductor substrate, the gate stack and the sacrificial spacer; performing a thermal treatment on the semiconductor substrate, thereby causing the metal layer to react with the sacrificial spacer and the semiconductor substrate in the source region and the drain region; removing the sacrificial spacer, reaction products of the sacrificial spacer and the metal layer, and a part of the metal layer which does not react with the sacrificial spacer. | 06-21-2012 |
20130078802 | HEAT TREATMENT METHOD FOR GROWING SILICIDE - Ions of silicon are implanted into source/drain regions in a semiconductor wafer to amorphize an ion implantation region in the semiconductor wafer. A nickel film is deposited on the amorphized ion implantation region. First irradiation from a flash lamp is performed on the semiconductor wafer with the nickel film deposited thereon to increase the temperature of a front surface of the semiconductor wafer from a preheating temperature to a target temperature for a time period in the range of 1 to 20 milliseconds. Subsequently, second irradiation from the flash lamp is performed to maintain the temperature of the front surface of the semiconductor wafer within a ±25° C. range around the target temperature for a time period in the range of 1 to 100 milliseconds. This causes nickel silicide to grow preferentially in a direction perpendicular to the semiconductor wafer. | 03-28-2013 |
20130089981 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - The invention provides a method of manufacturing a semiconductor device, capable of forming, on a silicon layer, a nickel mono-silicide layer having a low resistance value and a desirable flatness. The method includes depositing a platinum-containing nickel layer that covers the silicon layer formed on the substrate, and that has crystallinity lower in a portion thereof close to the silicon layer than in a portion remote from the silicon layer, and forming a nickel mono-silicide layer at the interface between the silicon layer and the platinum-containing nickel layer by heating the substrate. | 04-11-2013 |
20130149860 | Metal Silicide Nanowire Arrays for Anti-Reflective Electrodes in Photovoltaics - A method of fabricating single-crystalline metal silicide nanowires for anti-reflective electrodes for photovoltaics is provided that includes exposing a surface of a metal foil to oxygen or hydrogen at an elevated temperature, and growing metal silicide nanowires on the metal foil surface by flowing a silane gas mixture over the metal foil surface at the elevated temperature, where spontaneous growth of the metal silicide nanowires occur on the metal foil surface, where the metal silicide nanowires are post treated for use as an electrode in a photovoltaic cell or used directly as the electrode in the photovoltaic cell. | 06-13-2013 |
20130157459 | METHOD FOR FABRICATING INTERCONNECTING LINES INSIDE VIA HOLES OF SEMICONDUCTOR DEVICE - A method for fabricating interconnecting lines inside via holes of a semiconductor device comprises steps of providing a template having a receiving trench and a connection surface both on the same side of the template; filling an electric-conduction material into the receiving trench; connecting a substrate having at least one via hole with the connection surface to interconnect the via hole with the receiving trench; heating the electric-conduction material to a working temperature to liquefy a portion of the electric-conduction material and make it flows from the receiving trench into the via hole; and cooling the electric-conduction material to form an interconnecting line inside the via hole. The present invention fabricates interconnecting lines by a heat-forming method, which features simple steps and has advantages of shorter fabrication time, lower fabrication complexity, higher fabrication efficiency, higher yield and lower fabrication cost. | 06-20-2013 |
20130157460 | METHODS FOR ANNEALING A METAL CONTACT LAYER TO FORM A METAL SILICIDATION LAYER - Methods for annealing a contact metal layer for a metal silicidation process are provided in the present invention. In one embodiment, a method for annealing a contact metal layer for a silicidation process in a semiconductor device includes providing a substrate having a contact metal layer disposed thereon in a thermal annealing processing chamber, providing a heat energy to the contact metal layer in the thermal processing chamber, supplying a gas mixture including a nitrogen gas and a hydrogen gas while providing the heat energy to the contact layer in the thermal processing chamber, wherein the nitrogen gas and the hydrogen gas is supplied at a ratio between about 1:10 and about 1:1, and forming a metal silicide layer on the substrate. | 06-20-2013 |
20130189838 | SEMICONDUCTOR MANUFACTURING APPARATUS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a semiconductor manufacturing apparatus has a chamber, a microwave generator for generating a microwave, a waveguide for introducing the microwave into the chamber, a stage for mounting a semiconductor substrate, and a cover for covering an outer circumference portion of the stage exposed from the semiconductor substrate. In the semiconductor manufacturing apparatus, the stage is made of a material to be heated by the microwave, and the cover is made of a material through which the microwave penetrates. | 07-25-2013 |
20130260555 | METHOD OF ENABLING SEAMLESS COBALT GAP-FILL - Methods for depositing a contact metal layer in contact structures of a semiconductor device are provided. In one embodiment, a method for depositing a contact metal layer for forming a contact structure in a semiconductor device is provided. The method comprises performing a cyclic metal deposition process to deposit a contact metal layer on a substrate and annealing the contact metal layer disposed on the substrate. The cyclic metal deposition process comprises exposing the substrate to a deposition precursor gas mixture to deposit a portion of the contact metal layer on the substrate, exposing the portion of the contact metal layer to a plasma treatment process, and repeating the exposing the substrate to a deposition precursor gas mixture and exposing the portion of the contact metal layer to a plasma treatment process until a predetermined thickness of the contact metal layer is achieved. | 10-03-2013 |
20140051245 | DEVICE AND METHOD FOR KNIFE COATING AN INK BASED ON COPPER AND INDIUM - The device for knife coating a layer of ink based on copper and indium on a substrate includes a supply tank of an ink, said tank collaborating with a coating knife. In addition, the device includes means that allow the ink, the substrate and the coating knife to be kept at different and increasing respective temperatures. | 02-20-2014 |
20140073132 | Chip Comprising an Integrated Circuit, Fabrication Method and Method for Locally Rendering a Carbonic Layer Conductive - A method can be used for locally rendering a carbonic isolating layer conductive. In one embodiment, a laser beam is directed onto the carbonic isolating layer so as to convert amorphous carbon of the carbonic isolating layer into graphite-like carbon. In another embodiment, the carbonic layer is heated so as to form a conducting portion of the layer so that a lateral path through the conducting portion connects two circuit elements of the integrated circuit. | 03-13-2014 |
20140080302 | METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device including forming a first sacrificial layer on a substrate, the first sacrificial layer including a conductive material, forming a second sacrificial layer on the first sacrificial layer, the second sacrificial layer including an insulating material, patterning the second sacrificial layer and the first sacrificial layer to form an opening successively penetrating the second and first sacrificial layers, conformally forming a seed layer on the second and first sacrificial layers including the opening, and forming a conductive pattern filling the opening having the seed layer by a plating process. | 03-20-2014 |
20140148006 | LIQUID TREATMENT APPARATUS AND LIQUID TREATMENT METHOD - A liquid treatment apparatus of continuously performing a plating process on multiple substrates includes a temperature controlling container for accommodating a plating liquid; a temperature controller for controlling a temperature of the plating liquid in the temperature controlling container; a holding unit for holding the substrates one by one at a preset position; a nozzle having a supply hole through which the temperature-controlled plating liquid in the temperature controlling container is discharged to a processing surface of the substrate; a pushing unit for pushing the temperature-controlled plating liquid in the temperature controlling container toward the supply hole of the nozzle; and a supply control unit for controlling a timing when the plating liquid is pushed by the pushing unit. The temperature controller controls the temperature of the plating liquid in the temperature controlling container based on the timing when the plating liquid is pushed by the pushing unit. | 05-29-2014 |
20140256129 | SEMICONDUCTOR FILM DEPOSITION APPARATUS AND METHOD WITH IMPROVED HEATER COOLING EFFICIENCY - Provided is a physical vapor deposition apparatus with one or multiple deposition chambers for depositing films on substrates. The deposition chambers includes a heater and various cooling features to cool the chamber, the heater and the substrate. The sidewalls and top of the chamber are cooled by a cooling feature. The heater includes a cooling plate. A fitted heated cover is disposed between the heater and the substrate. A cooling pipe delivers a coolant throughout the cooling plate and extends in a high spatial density throughout the surface of the cooling plate. The cooling pipe occupies an area of about 14-20% of the area of the cooling plate and no location on the cooling plate surface is greater than about 15-20 mm from the cooling pipe. The cooling pipe cools the heater rapidly and enables deposition operations of long duration and using high power to be carried out. | 09-11-2014 |
20140287583 | ELECTRICALLY CONDUCTIVE PASTE FOR FRONT ELECTRODE OF SOLAR CELL AND PREPARATION METHOD THEREOF - The present invention provides an electrically conductive paste for a front electrode of a solar cell and a preparation method thereof. The electrically conductive paste is composed of a corrosion binder, a metallic powder and an organic carrier. The corrosion binder is one or more glass-free Pb—Te based crystalline compounds having a fixed melting temperature in a range of 440° C. to 760° C. During a sintering process of the electrically conductive paste for forming an electrode, the corrosion binder is converted into a liquid for easily corroding and penetrating an antireflective insulating layer on a front side of the solar cell, so that a good ohmic contact is formed. At the same time, the electrically conductive metallic powder is wetted, and the combination of the metallic powder is promoted. As a result, a high-conductivity front electrode of a crystalline silicon solar cell is formed. | 09-25-2014 |
20140295665 | METHOD FOR REMOVING NATIVE OXIDE AND ASSOCIATED RESIDUE FROM A SUBSTRATE - Native oxides and associated residue are removed from surfaces of a substrate by sequentially performing two plasma cleaning processes on the substrate in a single processing chamber. The first plasma cleaning process removes native oxide formed on a substrate surface by generating a cleaning plasma from a mixture of ammonia (NH | 10-02-2014 |
20140308811 | SEMICONDUCTOR INTEGRATED-CIRCUIT DEVICE AND METHOD OF PRODUCING THE SAME - A semiconductor integrated-circuit device using the copper wiring having increased electromigration resistance, low resistivity, and a line width of 70 nm or less, is provided. The present invention is characterized by the annealing treatment wherein a copper wiring having a line width of 70 nm or less is heated with a heating rate of 1K to 10K per second, and then the temperature is constantly maintained for a prescribed time duration. | 10-16-2014 |
20140370703 | TSV Front-top Interconnection Process - A TSV front-top interconnection process is provided. In an embodiment of the present invention, the stress concentration area of a TSV copper pillar is eliminated, which reduces the possibility of generating delamination or cracks between an insulating layer and the substrate due to stress. Meanwhile, the defect of the existing process that the TSV copper pillar may expose after an electroplating and annealing process is re-used to achieve the interconnection between the TSV copper pillar and the metal redistribution layer. | 12-18-2014 |
20150017802 | Double-etch nanowire process - In an aspect of this disclosure, a method is provided comprising the steps of: (a) providing a silicon-containing substrate, (b) depositing a first metal on the substrate, (c) etching the substrate produced by step (b) using a first etch, and (d) etching the substrate produced by step (c) using a second etch, wherein the second etch is more aggressive towards the deposited metal than the first etch, wherein the result of step (d) comprises silicon nanowires. The method may further comprise, for example, steps (b1) subjecting the first metal to a treatment which causes it to agglomerate and (b2) depositing a second metal. | 01-15-2015 |
20150111378 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS - [PROBLEMS TO BE SOLVED] | 04-23-2015 |
20150118843 | SHIELDING DESIGN FOR METAL GAP FILL - The present disclosure is directed to a physical vapor deposition system configured to heat a semiconductor substrate or wafer. In some embodiments the disclosed physical vapor deposition system comprises at least one heat source having one or more lamp modules for heating of the substrate. The lamp modules may be separated from the substrate by a shielding device. In some embodiments, the shielding device comprises a one-piece device or a two piece device. The disclosed physical vapor deposition system can heat the semiconductor substrate, reflowing a metal film deposited thereon without the necessity for separate chambers, thereby decreasing process time, requiring less thermal budget, and decreasing substrate damage. | 04-30-2015 |
20150147880 | CONTACT STRUCTURE AND FORMATION THEREOF - A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity. | 05-28-2015 |
20150311092 | METHOD FOR PROVIDING LATERAL THERMAL PROCESSING OF THIN FILMS ON LOW-TEMPERATURE SUBSTRATES - A method for thermally processing a minimally absorbing thin film in a selective manner is disclosed. Two closely spaced absorbing traces are patterned in thermal contact with the thin film. A pulsed radiant source is used to heat the two absorbing traces, and the thin film is thermally processed via conduction between the two absorbing traces. This method can be utilized to fabricate a thin film transistor (TFT) in which the thin film is a semiconductor and the absorbers are the source and the drain of the TFT. | 10-29-2015 |
20150348841 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device concerning the embodiment includes a semiconductor layer which has a first surface and a second surface which is opposite to the first surface, an interlayer which is provided on the first surface and which consists of only metal whose standard oxidation-reduction potential is not lower than 0 (zero) V in an ionization tendency, and an electrode provided on the interlayer. The semiconductor device further includes an electrical conductive layer which covers an inside of a hole which is formed in the semiconductor layer so as to reach the interlayer the interlayer from the second surface, and which is electrically connected to the electrode via the interlayer which is exposed to a bottom of the hole. | 12-03-2015 |
20160071766 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF - A semiconductor device includes a substrate having a top surface. A semiconductor circuit defines a circuit area on the top surface of the substrate. An interconnect is spaced apart from the circuit area and extends from the top surface into the substrate. The interconnect includes a sidewall formed of an electrically insulating material. An opening is provided in the sidewall. | 03-10-2016 |
20160093538 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a first metal containing a first conductivity-type impurity above a substrate provided with a first conductivity-type impurity region containing a first conductivity-type impurity and a second conductivity-type impurity region containing a second conductivity-type impurity; and forming a metal silicide containing the first metal by selectively causing, by thermal treatment, a reaction between the first metal and silicon contained in the substrate in the first conductivity-type impurity region. | 03-31-2016 |
20160104637 | METHOD FOR MANUFACTURING A CONTACT STRUCTURE USED TO ELECTRICALLY CONNECT A SEMICONDUCTOR DEVICE - A method for manufacturing contact structure includes the steps of: providing a substrate having the semiconductor device and an interlayer dielectric thereon, wherein the semiconductor device includes a gate structure and a source/drain region; forming a patterned mask layer with a stripe hole on the substrate, and concurrently forming a stripe-shaped mask layer on the substrate; forming a patterned photoresist layer with a plurality of slot holes on the substrate, wherein at least one of the slot holes is disposed right above the source/drain region; and forming a contact hole in the interlayer dielectric by using the patterned mask layer, the stripe-shaped mask layer and the patterned photoresist layer as an etch mask, and the source/drain region is exposed from the bottom of the contact hole when the step of forming the contact hole is completed. | 04-14-2016 |
20160118260 | METHODS FOR FORMING A METAL SILICIDE INTERCONNECTION NANOWIRE STRUCTURE - Methods and apparatus for forming a metal silicide as nanowires for back-end interconnection structures for semiconductor applications are provided. In one embodiment, the method includes forming a metal silicide layer on a substrate by a chemical vapor deposition process or a physical vapor deposition process, thermal treating the metal silicide layer in a processing chamber, applying a microwave power in the processing chamber while thermal treating the metal silicide layer; and maintaining a substrate temperature less than 400 degrees Celsius while thermal treating the metal silicide layer. In another embodiment, a method includes supplying a deposition gas mixture including at least a metal containing precursor and a reacting gas on a surface of a substrate, forming a plasma in the presence of the deposition gas mixture by exposure to microwave power, exposing the plasma to light radiation, and forming a metal silicide layer on the substrate from the deposition gas. | 04-28-2016 |
20160163551 | METHODS OF FORMING METAL SILICIDE REGIONS ON SEMICONDUCTOR DEVICES USING AN ORGANIC CHELATING MATERIAL DURING A METAL ETCH PROCESS - A method includes forming a refractory metal alloy layer above a silicon-containing material, performing a first heating process to form a metal silicide region in at least a portion of the silicon-containing material using the refractory metal alloy layer, and removing at least a first portion of an unreacted portion of the refractory metal alloy layer using a first solution comprising a solvent and an organic chelator. | 06-09-2016 |
20160204027 | DIRECT DEPOSITION OF NICKEL SILICIDE NANOWIRE | 07-14-2016 |