| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438661000 | Subsequent fusing conductive layer | 6 |
| 20080293243 | Prevention and Control of Intermetallic Alloy Inclusions - In using Ni(P) and Sn-rich solders in Pb free interconnections, the prevention and control of the formation of intermetallic compound inclusions, can be achieved through a reaction preventive or control layer that is positioned on top of an electroless Ni(P) metallization, such as by application of a thin layer of Sn on the Ni(P) or through the application of a thin layer of Cu on the Ni(P | 11-27-2008 |
| 20110143534 | METHOD FOR FORMING METALLIC MATERIALS COMPRISING SEMI-CONDUCTORS - The method for forming first and second metal-based materials comprises providing a substrate comprising an area made from a first semi-conductor material and an area made from a second semi-conductor material comprising germanium separated by a pattern made from dielectric material, depositing a metal layer and performing a first heat treatment in an atmosphere comprising a quantity of oxygen comprised between 0.01% and 5%. The metal layer reacts with the first semi-conductor material and the second semi-conductor material comprising germanium to respectively form the first metal-based material and the second metal-based material containing germanium. | 06-16-2011 |
| 20110143535 | PRODUCTION OF TSV INTERCONNECTION STRUCTURES MADE UP OF AN INSULATING CONTOUR AND A CONDUCTIVE ZONE SITUATED IN THE CONTOUR AND DISCONNECTED FROM THE CONTOUR - A method for producing an interconnection structure is disclosed. In one aspect, there is formation in a substrate of at least one trench forming a closed contour and at least one hole situated inside the closed contour, the trench and the hole being separated by a zone of the substrate. Furthermore, the trench is filled with a dielectric material and the hole is filled with a conducting material. | 06-16-2011 |
| 20130045595 | METHOD FOR PROCESSING METAL LAYER - The method for processing a metal layer including the following steps is illustrated. First, a semiconductor substrate is provided. Then, a metal layer is formed over the semiconductor substrate. Furthermore, a microwave energy is used to selectively heat the metal layer without affecting the underlying semiconductor substrate and other formed structures, in which the microwave energy has a predetermined frequency in accordance with a material of the metal layer, and the predetermined frequency ranges between 1 KHz to 1 MHz. | 02-21-2013 |
| 438662000 | Utilizing laser | 2 |
| 20110201199 | LASER ANNEALING FOR 3-D CHIP INTEGRATION - A laser annealing method for annealing a stacked semiconductor structure having at least two stacked layers is disclosed. A laser beam is focused on a lower layer of the stacked layers. The laser beam is then scanned to anneal features in the lower layer. The laser beam is then focused on an upper layer of the stacked layers, and the laser beam is scanned to anneal features in the upper layer. The laser has a wavelength of less than one micrometer. The beam size, depth of focus, energy dosage, and scan speed of the laser beam are programmable. Features in the lower layer are offset from features in the upper layer such that these features do not overlap along a plane parallel to a path of the laser beam. Each of the stacked layers includes active devices, such as transistors. Also, the first and second layers may be annealed simultaneously. | 08-18-2011 |
| 20160086849 | CONSTRAINED NANOSECOND LASER ANNEAL OF METAL INTERCONNECT STRUCTURES - In-situ melting and crystallization of sealed cooper wires can be performed by means of laser annealing for a duration of nanoseconds. The intensity of the laser irradiation is selected such that molten copper wets interconnect interfaces, thereby forming an interfacial bonding arrangement that increases specular scattering of electrons. Nanosecond-scale temperature quenching preserves the formed interfacial bonding. At the same time, the fast crystallization process of sealed copper interconnects results in large copper grains, typically larger than 80 nm in lateral dimensions, on average. A typical duration of the annealing process is from about 10's to about 100's of nanoseconds. There is no degradation to interlayer low-k dielectric material despite the high anneal temperature due to ultra short duration that prevents collective motion of atoms within the dielectric material. | 03-24-2016 |
