Entries |
Document | Title | Date |
20080293240 | MANUFACTURING METHOD OF A SILICON CARBIDE SEMICONDUCTOR DEVICE - A manufacturing method for a silicon carbide semiconductor device is disclosed. It includes an etching method in which an Al film and Ni film are laid on an SiC wafer in this order and wet-etched, whereby a two-layer etching mask is formed in which Ni film portions overhang Al film portions. Mesa grooves are formed by dry etching by using this etching mask. | 11-27-2008 |
20080293241 | CONTACT STRUCTURES OF WIRINGS AND METHODS FOR MANUFACTURING THE SAME, AND THIN FILM TRANSISTOR ARRAY PANELS INCLUDING THE SAME AND METHODS FOR MANUFACTURING THE SAME - First, a conductive material made of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed, and a semiconductor layer and an ohmic contact layer are sequentially formed. Next, a conductor layer including a lower layer of Cr and an upper layer of aluminum-based material is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad, respectively. Next, an amorphous silicon layer is deposited, an annealing process is executed to form inter-layer reaction layers on the drain electrode, the gate pa and the data pad, which are exposed through the contact holes. Then, the amorphous silicon layer is removed. Next, IZO is deposited and patterned to form a pixel electrode, a redundant gate pad and a redundant data pad respectively and electrically connected to the drain electrode, the gate pad and the data pad via the inter-layer reaction layers. | 11-27-2008 |
20080318418 | Process for Forming Continuous Copper Thin Films Via Vapor Deposition - A process for preparing a multi-layer substrate is described herein. In one embodiment, the process provides a multi-layer substrate comprising a first layer and a second layer where the process comprises the steps of providing the first layer comprising a barrier area and a copper area; and depositing the second layer comprising copper onto the first layer wherein the depositing provides the second layer comprising a first thickness ranging from about 20 Angstroms to about 2,000 Angstroms onto the barrier area and a second thickness ranging from about 0 Angstroms to about 1,000 Angstroms onto the copper area in the first layer wherein the first thickness is greater than the second thickness. | 12-25-2008 |
20090035936 | SEMICONDUCTOR DEVICE HAVING A GRAIN ORIENTATION LAYER - A manufacturing process of a semiconductor device includes generating a less random grain orientation distribution in metal features of a semiconductor device by employing a grain orientation layer. The less random grain orientation, e.g., a grain orientation distribution which has a higher percentage of grains that have a predetermined grain orientation, may lead to improved reliability of the metal features. The grain orientation layer may be deposited on the metal features wherein the desired grain structure of the metal features may be obtained by a subsequent annealing process, during which the metal feature is in contact with the grain orientation layer. | 02-05-2009 |
20090104768 | METHOD FOR FORMING METAL LINE IN SEMICONDUCTOR DEVICE - A method for forming a metal line in a semiconductor device may include forming a silicon (Si) monolayer as an etching prevention layer over an exposed portion of a lower metal layer and sidewalls of an upper metal layer, middle metal layer, and the entire surface of curved photoresist patterns. | 04-23-2009 |
20090137116 | ISOLATING CHIP-TO-CHIP CONTACT - An apparatus has two slabs of substrate material joined to each other, the two slabs including a pair of contacts joined to each other having a shape separating a first area from a second area. | 05-28-2009 |
20090163023 | Phase change memory and method of fabricating the same - A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern, the bottom surface of the hard mask pattern facing the upper electrode and being opposite the top surface of the hard mask pattern, and forming a capping layer to cover the top surface of the hard mask pattern and sidewalls of the hard mask pattern, phase change pattern, and upper electrode. | 06-25-2009 |
20090191704 | Formation of Through-Wafer Electrical Interconnections and Other Structures Using a Thin Dielectric Membrane - Providing through-wafer interconnections in a semiconductor wafer includes forming a sacrificial membrane in a pre-existing semiconductor wafer, depositing metallization over one side of the wafer so as to cover exposed portions of the sacrificial membrane facing the one side of the wafer, removing exposed portions of the sacrificial membrane facing the other side of the wafer, and depositing metallization over the other side of the wafer so as to contact the previously deposited metallization. Techniques also are disclosed for providing capacitive and other structures using thin metal membranes. | 07-30-2009 |
20090197404 | High yield and high throughput method for the manufacture of integrated circuit devices of improved integrity, performance and reliability - The present invention provides a method of forming a contact opening, such as a via hole, in which a sacrificial layer is deposited prior to exposing a conductor formed in a substrate at a bottom side of the opening to prevent damage and contamination to the materials constituting an integrated circuit device from happening. The exposing may or may not form a recess in the conductor. The present invention also provides a method of forming a contact opening having a recess in the conductor wherein a sacrificial layer is not deposited until the conductor is exposed, but deposited before a recess is formed in the conductor so that a major damage and contamination related to the recess formation can be prevented. By forming a trench feature over a contact opening formed by using the present invention, a dual damascene feature can be fabricated. By performing further damascene process steps over the various damascene interconnect features formed by using the present invention, various interconnect systems such as a single damascene planar via, a single damascene embedded via, and various dual damascene interconnect system having either a planar via or an embedded via can be fabricated. | 08-06-2009 |
20090258489 | Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same - A method of making a non-volatile memory device includes forming a first electrode, forming a steering element, forming at least one feature, forming a carbon resistivity switching material on at least one sidewall of the at least one feature such that the carbon resistivity switching material electrically contacts the steering element, and forming a second electrode. | 10-15-2009 |
20090269921 | Method for growing carbon nanotubes, and electronic device having structure of ohmic connection to carbon element cylindrical structure body and production method thereof - An electronic device having a structure of an ohmic connection to a carbon element cylindrical structure body, wherein a metal material is positioned inside the junction part of a carbon element cylindrical structure body joined to a connection objective and the carbon element cylindrical structure body and the connection objective are connected by an ohmic contact. Methods for producing such an electronic device are also disclosed. Further, a method for growing a carbon nanotube is disclosed. | 10-29-2009 |
20090269922 | Method of depositing a metal seed layer over recessed feature surfaces in a semiconductor substrate - We disclose a method of depositing a metal seed layer on a wafer substrate comprising a plurality of recessed device features. The method comprises depositing a first portion of the metal seed layer on the wafer via plasma deposition at a sufficient ratio of wafer substrate bias to DC source power that bottom coverage is achieved while resputtering of surfaces of the recessed device features is inhibited. The method also comprises depositing a second portion of the metal seed layer at a ration of substrate RF bias to DC source power such that resputtering is not inhibited. | 10-29-2009 |
20090275196 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | 11-05-2009 |
20090280639 | Atomic Layer Deposition Methods - An atomic layer deposition method includes providing a semiconductor substrate within a deposition chamber. A first metal halide-comprising precursor gas is flowed to the substrate within the chamber effective to form a first monolayer on the substrate. The first monolayer comprises metal and halogen of the metal halide. While flowing the first metal halide-comprising precursor gas to the substrate, H | 11-12-2009 |
20100009532 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MANUFACTURING APPARATUS THEREFOR - Provided is a manufacturing method for improving the reliability of a semiconductor device having a back electrode. After formation of semiconductor elements on the surface of a silicon substrate, the backside surface thereof, which is opposite to the element formation surface, is subjected to the following steps in a processing apparatus. After deposition of a first metal film over the backside surface of the silicon substrate in a first chamber, it is heat treated to form a metal silicide film. Then, a nickel film is deposited in a third chamber, followed by deposition of an antioxidant conductor film in a second chamber. Heat treatment for alloying the first metal film and the silicon substrate is performed at least prior to the deposition of the nickel film. The first chamber has therefore a mechanism for depositing the first metal film and a lamp heating mechanism. | 01-14-2010 |
20100029077 | Inhibiting background plating - Methods include selectively depositing a phase change resist having high light transmittance onto a dielectric to form a pattern, etching away portions of the dielectric not covered by the resist and depositing a metal seed layer on the etched portions of the dielectric. A metal layer is then deposited on the metal seed layer by light induced plating. | 02-04-2010 |
20100075495 | Method Of Selectively Plating Without Plating Lines - A method of selectively plating without plating lines is provided. The method employs a loading plate having a metalized temporary conductive layer. The loading plate and the temporary conductive layer are adapted for transmitting a plating current. A patterning photoresist layer is accorded for selectively and sequentially plating a separating metal layer, a plating protection layer, and a connection pad layer on to the temporary conductive layer. Then, the loading plate is further used for supplying current to form other circuit layers by a pressing lamination process. And when the plate process is completed or it is not need to plate, the loading plate and the temporary conductive layer can be removed, for further completing for example the solder mask process, and thus achieving the objective of plating without plating lines. | 03-25-2010 |
20100081273 | METHOD FOR FABRICATING CONDUCTIVE PATTERN - A method for fabricating a conductive pattern including following steps is provided. A first conductive layer is formed on a substrate. A patterned hard mask layer is formed on the first conductive layer. A portion of the first conductive layer is removed to expose a portion of the substrate by using the patterned hard mask layer as a mask. A dielectric layer covering the patterned hard mask layer is formed on the substrate. A portion of the dielectric layer is removed to expose the patterned hard mask layer. The patterned hard mask layer is removed to form an opening in the dielectric layer. A second conductive layer is formed in the opening. | 04-01-2010 |
20100130005 | METHOD OF FORMING CARBON NANOTUBE ON SEMICONDUCTOR SUBSTRATE, METHOD OF FORMING SEMICONDUCTOR METAL WIRE USING THE SAME, AND METHOD OF FABRICATING INDUCTOR USING THE SAME - A method of fabricating a semiconductor device by filling carbon nanotubes in a recess is disclosed. The method of fabricating the semiconductor device comprises patterning a mold on a substrate, coating carbon nanotubes on an entire surface of the recess and the mold formed by the patterning, filling the carbon nanotubes coated on the an entire surface of the mold in the recess, and removing the mold. | 05-27-2010 |
20100167529 | Method for Manufacturing Semiconductor Device - An embodiment of the present invention provides a method for manufacturing a semiconductor device. This method comprises: forming a seed film at least on an inner face of a recessed portion of a substrate; forming a protection film on the seed film, the protection film being made of a material that is more easily oxidized than a material forming the seed film; heat-treating the protection film; exposing at least part of the seed film by removing at least part of the heat-treated protection film; forming a plating film on the seed film through electrolytic plating to be buried in the recessed portion, by supplying current to the seed film that is at least partially exposed; and removing the plating film except for a portion buried in the recessed portion. | 07-01-2010 |
20100197134 | COAXIAL THROUGH CHIP CONNECTION - An integrated circuit chip includes devices formed by doping of a semiconductor on a substrate and at least one post-device formation through-chip via made up of an annulus of insulating material, an annulus of metallization bounding an outer surface of the annulus of insulating material and an annulus of electrically conductive material within the annulus of insulating material, the annulus of metallization and the annulus of electrically conductive material being electrically isolated from each another. | 08-05-2010 |
20100233876 | FILM FORMING APPARATUS, FILM FORMING METHOD, COMPUTER PROGRAM AND STORAGE MEDIUM - In a film forming method, a substrate is first loaded into a vacuum-evacuable processing chamber. At least a transition metal-containing source gas and a reduction gas are supplied into the processing chamber, and the substrate is heated. Then, a thin film is formed in a recess in the surface of the substrate by heat treatment. Accordingly, the surface recess of the substrate can be filled with a copper film. | 09-16-2010 |
20100240213 | Method of manufacturing a semiconductor device - A method of manufacturing a semiconductor device on a semiconductor substrate, includes the steps of forming a first metal film on a front surface of the semiconductor substrate; forming a second metal film on the surface of the first metal film; activating a surface of the second metal film to provide an activated surface; and forming a plated film on the activated surface by a wet plating method in a plating bath that includes a reducing agent that is oxidized during plating and that has a rate of oxidation, wherein the second metal film is a metal film mainly composed of a first substance that enhances the rate of oxidation of the reducing agent in the plating bath. Wet plating is preferably an electroless process. | 09-23-2010 |
20100323515 | Method for making semiconductor electrodes - Disclosed is a method for making semiconductor electrodes. In the method, there is provided a wafer. The wafer includes at least one conductive unit, a plurality of first connective units connected to the conductive unit, a plurality of first metal layers connected to the first connective units and a plurality of second connective units connected to the first metal layers. Photo-resist is provided on the first and second connective units. A second metal layer is provided on each of the first metal layers via using an electroplating device. The wafer is cut from the photo-resist, thus forming semiconductor electrodes. | 12-23-2010 |
20110008959 | METHOD OF ETCHING A SEMICONDUCTOR WAFER - A method for anisotropically plasma etching a semiconductor wafer is disclosed. The method comprises supporting a wafer in an environment operative to form a plasma, such as a plasma reactor, and providing an etching mixture to the environment. The etching mixture comprises at least one etch component, at least one passivation component, and at least one passivation material removal component. | 01-13-2011 |
20110014787 | Method of Forming Contacts for a Memory Device - The present invention is generally directed to a method of forming contacts for a memory device. In one illustrative embodiment, the method includes forming a layer of insulating material above an active area of a dual bit memory cell, forming a hard mask layer above the layer of insulating material, the hard mask layer having an original thickness, performing at least two partial etching processes on the hard mask layer to thereby define a patterned hard mask layer above the layer of insulating material, wherein each of the partial etching processes is designed to etch through less than the original thickness of the hard mask layer, the hard mask layer having openings formed therein that correspond to a digitline contact and a plurality of storage node contacts for the dual bit memory cell, and performing at least one etching process to form openings in the layer of insulating material for the digitline contact and the plurality of storage node contacts using the patterned hard mask layer as an etch mask. | 01-20-2011 |
20110027987 | Method and apparatus for manufacturing semiconductor device - A method for manufacturing a semiconductor device includes forming a laminated structure of a plurality of metal films on a semiconductor substrate using an electroless plating method. The forming of the metal films includes: performing an electroless plating process including a reduction reaction using a first plating tank; and performing an electroless plating process by only a substitution reaction using a second plating tank. The electroless plating process including the reduction reaction that is performed using the first plating tank is performed in a shading environment, and the electroless plating process performed by only the substitution reaction using the second plating tank is performed in a non-shading environment. | 02-03-2011 |
20110053369 | Methods of manufacturing a semiconductor memory device - Methods of forming a semiconductor include forming an insulation layer over a semiconductor substrate in which a first region and a second region are defined. A storage node contact (SNC) that passes through the insulation layer is formed and is electrically connected to the first region. A conductive layer that passes through the insulation layer is deposited and is electrically connected to the second region on the insulation layer and the SNC. A bit line is formed by removing an upper portion of the conductive layer, an upper portion of the insulation layer and an upper portion of the SNC until the SNC and the conductive layer are electrically separated from each other, wherein the bit line is a remaining part of the conductive layer. | 03-03-2011 |
20110104892 | ETCHING METHOD AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - The present invention discloses technique of etching selectively a layer containing siloxane. The present invention provides a semiconductor device with reduced operation deterioration due to etching failure. A method for manufacturing a semiconductor device comprises steps of forming a conductive layer electrically connecting to a transistor, an insulating layer covering the conductive layer, and a mask formed over the insulating layer; and etching the insulating layer with a processing gas including a hydrogen bromide gas. | 05-05-2011 |
20110151660 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF PROCESSING SUBSTRATE AND SUBSTRATE PROCESSING APPARATUS - A method of manufacturing a semiconductor device capable of minimally preventing the property deterioration caused by the oxidation of a metal film, and a substrate processing apparatus are provided. The method of manufacturing a semiconductor device includes: (a) loading a substrate into a processing container; (b) forming a metal film on the substrate using a chemical deposition method by supplying a processing gas into the processing container and exhausting the processing gas; (c) forming an aluminum nitride film on the metal film using the chemical deposition method by supplying an aluminum-containing source gas and a nitrogen-containing gas into the processing container and exhausting the aluminum-containing source gas and the nitrogen-containing gas; and (d) unloading the substrate from the processing container after forming the metal film and the aluminum nitride film, wherein the step (b) and the step (c) are continuously performed while maintaining an inside of the processing container to have an oxygen-free atmosphere. | 06-23-2011 |
20110183514 | STABLE ELECTROLESS FINE PITCH INTERCONNECT PLATING - A method and apparatus for plating facilitates the plating of a small contact feature of a wafer die while providing a relatively stable plating bath. The method utilizes a supplemental plating structure that is larger than a die contact that is to be plated. The supplemental plating structure may be located on the wafer, and is conductively connected to the die contact. Conductive connection between the die contact and the supplemental plating structure facilitates the plating of the die contact. The supplemental plating structure also can be used to probe test the die prior to singulation. | 07-28-2011 |
20110195570 | INTEGRATION OF BOTTOM-UP METAL FILM DEPOSITION - The described embodiments of methods of bottom-up metal deposition to fill interconnect and replacement gate structures enable gap-filling of fine features with high aspect ratios without voids and provide metal films with good film quality. In-situ pretreatment of metal film(s) deposited by gas cluster ion beam (GCIB) allows removal of surface impurities and surface oxide to improve adhesion between an underlying layer with the deposited metal film(s). Metal films deposited by photo-induced chemical vapor deposition (PI-CVD) using high energy of low-frequency light source(s) at relatively low temperature exhibit liquid-like nature, which allows the metal films to fill fine feature from bottom up. The post deposition annealing of metal film(s) deposited by PI-CVD densifies the metal film(s) and removes residual gaseous species from the metal film(s). For advanced manufacturing, such bottom-up metal deposition methods address the challenges of gap-filling of fine features with high aspect ratios. | 08-11-2011 |
20110212616 | METALLIZATION SYSTEM OF A SEMICONDUCTOR DEVICE COMPRISING ROUNDED INTERCONNECTS FORMED BY HARD MASK ROUNDING - In sophisticated metallization systems, vertical contacts and metal lines may be formed on the basis of a dual inlaid strategy, wherein an edge rounding or corner rounding may be applied to the trench hard mask prior to forming the via openings on the basis of a self-aligned via trench concept. Consequently, self-aligned interconnect structures may be obtained, while at the same time providing superior fill conditions during the deposition of barrier materials and conductive fill materials. | 09-01-2011 |
20110230046 | SEMICONDUCTOR DICE WITH BACKSIDE TRENCHES FILLED WITH ELASTIC MATERIAL FOR IMPROVED ATTACHMENT, PACKAGES USING THE SAME, AND METHODS OF MAKING THE SAME - Disclosed are semiconductor dice with backside trenches filled with elastic conductive material. The trenches reduce the on-state resistances of the devices incorporated on the dice. The elastic conductive material provides a conductive path to the backsides of the die with little induced stress on the semiconductor die caused by thermal cycling. Also disclosed are packages using the dice, and methods of making the dice. | 09-22-2011 |
20110237068 | METHOD FOR FORMING ELECTRIC VIAS - A method for forming through vias connecting the front surface to the rear surface of a semiconductor substrate, including the steps of: forming openings in the substrate, thermally oxidizing walls of the openings, filling the openings with a sacrificial material, forming electronic components in the substrate, etching the sacrificial material, filling the openings with a metal, and etching the rear surface of the substrate all the way to the bottom of the openings. | 09-29-2011 |
20110250750 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes: (a) forming an interlayer insulating film on a substrate; (b) forming an interconnect in the interlayer insulating film; (c) applying an organic solution to an upper surface of the interconnect and an upper surface of the interlayer insulating film; (d) after (c), applying a silylating solution to the upper surface of the interconnect and the upper surface of the interlayer insulating film; (e) after (d), heating the substrate; and (f) forming a first liner insulating film at least on the upper surface of the interconnect. | 10-13-2011 |
20110256712 | ETCHANT FOR ELECTRODE AND METHOD OF FABRICATING THIN FILM TRANSISTOR ARRAY PANEL USING THE SAME - The present invention relates to an etchant for etching metal wiring, and the metal wiring etchant according to the present invention includes hydrogen peroxide at about 5 wt % to about 15 wt %, an oxidant at about 0.5 wt % to about 5 wt %, a fluoride-based compound at about 0.1 wt % to about 1 wt %, a nitrate-based compound at about 0.5 wt % to about 5 wt %, and a boron-based compound at about 0.05 wt % to about 1 wt %. | 10-20-2011 |
20110256713 | POLYHEDRAL OLIGOMERIC SILSESQUIOXANE BASED IMPRINT MATERIALS AND IMPRINT PROCESS USING POLYHEDRAL OLIGOMERIC SILSESQUIOXANE BASED IMPRINT MATERIALS - A method of forming low dielectric contrast structures by imprinting a silsesquioxane based polymerizable composition. The imprinting composition including: one or more polyhedral silsesquioxane oligomers each having one or more polymerizable groups, wherein each of the one or more polymerizable group is bound to a different silicon atom of the one or more polyhedral silsesquioxane oligomers; and | 10-20-2011 |
20110256714 | SUBSTRATE STRUCTURE WITH DIE EMBEDDED INSIDE AND DUAL BUILD-UP LAYERS OVER BOTH SIDE SURFACES AND METHOD OF THE SAME - The present invention comprises a first substrate with a die formed on a die metal pad, a first and a second wiring circuits formed on the surfaces of the first substrate. A second substrate has a die opening window for receiving the die, a third wiring circuit is formed on top surface of the second substrate and a fourth wiring circuit on bottom surface of the second substrate. An adhesive material is filled into the gap between back side of the die and top surface of the first substrate and between the side wall of the die and the side wall of the die receiving through hole and the bottom side of the second substrate. During the formation, laser is introduced to cut the backside of the first substrate and an opening hole is formed in the first substrate to expose a part of the backside of the Au or Au/Ag metal layer of chip/die. | 10-20-2011 |
20110287628 | Activation Treatments in Plating Processes - A method of forming a device includes performing a first plating process to form a first metallic feature, and performing an activation treatment to a surface of the first metallic feature in an activation treatment solution, wherein the activation treatment solution includes a treatment agent in de-ionized (DI) water. After the step of performing the activation treatment, performing a second plating process to form a second metallic feature and contacting the surface of the first metallic feature. | 11-24-2011 |
20110287629 | SILICON FILM FORMATION METHOD AND SILICON FILM FORMATION APPARATUS - A silicon film formation method includes a first film formation operation, an etching operation, and a second film formation operation. In the first film formation operation, a first silicon film is formed to fill the groove of the object to be processed. In the etching operation, an opening of the groove is widened by etching the first silicon film formed in the first film formation operation. In the second film formation operation, a second silicon film is formed on the groove having the opening widened in the etching operation to fill the groove. Accordingly, a silicon film is formed on a groove of an object to be processed having the groove provided thereon. | 11-24-2011 |
20120009780 | WIRE BONDING ON REACTIVE METAL SURFACES OF A METALLIZATION OF A SEMICONDUCTOR DEVICE BY PROVIDING A PROTECTION LAYER - In semiconductor devices having a copper-based metallization system, bond pads for wire bonding may be formed directly on copper surfaces, which may be covered by an appropriately designed protection layer to avoid unpredictable copper corrosion during the wire bond process. A thickness of the protection layer may be selected such that bonding through the layer may be accomplished, while also ensuring a desired high degree of integrity of the copper surface. | 01-12-2012 |
20120034775 | Method for Forming a Patterned Thick Metallization atop a Power Semiconductor Chip - A method is disclosed for forming a patterned thick metallization atop a semiconductor chip wafer. The method includes fabricating a nearly complete semiconductor chip wafer ready for metallization; depositing a bottom metal layer of sub-thickness TK | 02-09-2012 |
20120045894 | Method for Manufacturing Display Device - When a mask layer is formed, a first liquid composition containing a mask-layer-forming material is applied on an outer side of a pattern that is desired to be formed (corresponding to a contour or an edge portion of a pattern) to form a first mask layer having a frame shape. A second liquid composition containing a mask-layer-forming material is applied so as to fill a space inside the first mask layer having a frame shape to form a second mask layer. The first mask layer and the second mask layer are formed to be in contact with each other, and the first mask layer is formed to surround the second mask layer. Therefore, the first mask layer and the second mask layer can be used as one continuous mask layer. | 02-23-2012 |
20120045895 | SEMICONDUCTOR PACKAGE HAVING THROUGH ELECTRODES THAT REDUCE LEAKAGE CURRENT AND METHOD FOR MANUFACTURING THE SAME - A stacked semiconductor package having through electrodes that exhibit a reduced leakage current and a method of making the same are presented. The stacked semiconductor package includes a semiconductor chip, through-holes, and a current leakage prevention layer. The semiconductor chip has opposing first and second surfaces. The through-holes pass entirely through the semiconductor chip and are exposed at the first and second surfaces. A polarized part is formed on at least one of the first and second surfaces of the semiconductor chip. The through-electrodes are disposed within the through-holes. The current leakage prevention layer covers the polarized part and exposes ends of the through-electrodes. | 02-23-2012 |
20120070979 | METHOD OF ELECTROLYTIC PLATING AND SEMICONDUCTOR DEVICE FABRICATION - The disclosure relates generally to semiconductor device fabrication, and more particularly to methods of electroplating used in semiconductor device fabrication. A method of electroplating includes: immersing an in-process substrate into an electrolytic plating solution to form a first metal layer on the in-process substrate; then performing a first chemical-mechanical polish to a liner on the in-process substrate followed by immersing the in-process substrate into the electrolytic plating solution to form a second metal layer on the first metal layer and the liner; and performing a second chemical-mechanical polish to the liner. | 03-22-2012 |
20120070980 | MULTI MATERIAL SECONDARY METALLIZATION SCHEME IN MEMS FABRICATION - Processes are provided herein for the fabrication of MEMS utilizing both a primary metal that is integrated into the final MEMS structure and two or more sacrificial secondary metals that provide structural support for the primary metal component during machining. A first secondary metal is thinly plated around the primary metal and over the entire surface of the substrate without using photolithography. A second secondary metal, is then thickly plated over the deposited first secondary metal without using photolithography. Additionally, techniques are disclosed to increase the deposition rate of the first secondary metal between primary metal features in order to prevent voiding and thus enhance structural support of the primary metal during machining. | 03-22-2012 |
20120115323 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A base conductive member is formed on a surface and in a hole section of a substrate, and a resist is formed on a part of the base conductive member in which a conductive layer is not to be formed. The conductive layer is formed on a part except for the part in which the resist has been formed, and a mask metal is formed on the conductive layer. Then, the resist is removed, and the base conductive member is etched using the mask metal as a mask to form the conductive layer into a predetermined shape. | 05-10-2012 |
20120129340 | ANTIFUSE STRUCTURE FOR IN LINE CIRCUIT MODIFICATION - An antifuse structure and methods of forming contacts within the antifuse structure. The antifuse structure includes a substrate having an overlying metal layer, a dielectric layer formed on an upper surface of the metal layer, and a contact formed of contact material within a contact via etched through the dielectric layer into the metal layer. The contact via includes a metal material at a bottom surface of the contact via and an untreated or partially treated metal precursor on top of the metal material. | 05-24-2012 |
20120178254 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING DIELECTRIC LAYER WITH IMPROVED ELECTRICAL CHARACTERISTICS - A semiconductor device having a dielectric layer with improved electrical characteristics and associated methods, the semiconductor device including a lower metal layer, a dielectric layer, and an upper metal layer sequentially disposed on a semiconductor substrate and an insertion layer disposed between the dielectric layer and at least one of the lower metal layer and the upper metal layer, wherein the dielectric layer includes a metal oxide film and the insertion layer includes a metallic material film. | 07-12-2012 |
20120208363 | METHODS OF DEPOSITING ALUMINIUM LAYERS - A method of depositing an aluminium film on a substrate includes placing the substrate on a support, depositing a first layer of aluminium onto the substrate with the substrate in an unclamped condition, clamping the substrate to the support and depositing a second layer of aluminium continuous with the first layer. The second layer is thicker than the first layer and the second layer is deposited at a substrate temperature of less than about 22° C. | 08-16-2012 |
20120231625 | METHOD OF FORMING WIRING OF A SEMICONDUCTOR DEVICE - A method of forming wiring of a semiconductor device includes: forming an insulating resin on a main surface of a substrate such that an opening portion defining a wiring pattern is provided in the insulating resin; forming a first wiring layer made of a first metal on a bottom surface and side surfaces of the opening portion surrounding and a surface of the insulating resin opposite to the main surface of the substrate, the first wiring layer having a bottom portion formed on the bottom surface of the opening portion and side portions formed on the side surfaces, the bottom portion having a thickness greater than a thickness of at least one of the side portions; and cutting the insulating resin and the first wiring layer such that the insulating resin and the first wiring layer are exposed. | 09-13-2012 |
20120258588 | SELF FORMING METAL FLUORIDE BARRIERS FOR FLUORINATED LOW-K DIELECTRICS - A device and method of forming fluoride metal barriers at an interface of a fluorinated low-K dielectric and Cu or Cu alloy interconnects is disclosed. The fluoride metal barriers may prevent interconnects from reacting with the fluorinated low-K dielectric. The method may include depositing a thin film of metal or metal alloy on the fluorinated low-K dielectric. The thin film may include a metal or metal alloying element that reacts with free fluorine and/or fluorine compounds from the fluorinated low-K dielectric to form fluoride metal barriers. | 10-11-2012 |
20120289044 | SEMICONDUCTOR SUBSTRATE, ELECTRODE FORMING METHOD, AND SOLAR CELL FABRICATING METHOD - A semiconductor substrate having an electrode formed thereon, the electrode including at least silver and glass frit, the electrode including: a multi-layered structure with a first electrode layer joined directly to the semiconductor substrate, and an upper electrode layer formed of at least one layer and disposed on the first electrode layer. The upper electrode layer is formed by firing a conductive paste having a total silver content of 75 wt % or more and 95 wt % or less, the content of silver particles having an average particle diameter of 4 μm or greater and 8 μm or smaller with respect to the total silver content in the upper electrode layer being higher than that in the first electrode layer. | 11-15-2012 |
20120295436 | FORMATION OF A ZINC PASSIVATION LAYER ON TITANIUM OR TITANIUM ALLOYS USED IN SEMICONDUCTOR PROCESSING - Embodiments of the current invention describe methods of processing a semiconductor substrate that include applying a zincating solution to the semiconductor substrate to form a zinc passivation layer on the titanium-containing layer, the zincating solution comprising a zinc salt, FeCl | 11-22-2012 |
20120315752 | METHOD OF FABRICATING NONVOLATILE MEMORY DEVICE - A method of fabricating a nonvolatile memory device includes providing an intermediate structure in which a floating gate and an isolation film are disposed adjacent to each other on a semiconductor substrate and a gate insulating film is disposed on the floating gate and the isolation film, forming a conductive film on the gate insulating film, and annealing the conductive film so that part of the conductive film on an upper portion of the floating gate flows down onto a lower portion of the floating gate and an upper portion of the isolation film. | 12-13-2012 |
20120322257 | METHOD OF FILLING A DEEP ETCH FEATURE - A method for anisotropically plasma etching a semiconductor wafer is disclosed. The method comprises supporting a wafer in an environment operative to form a plasma, such as a plasma reactor, and providing an etching mixture to the environment. The etching mixture comprises at least one etch component, at least one passivation component, and at least one passivation material removal component. | 12-20-2012 |
20130005139 | TECHNIQUES FOR MANUFACTURING PLANAR PATTERNED TRANSPARENT CONTACT AND/OR ELECTRONIC DEVICES INCLUDING SAME - Certain examples relate to improved methods for making patterned substantially transparent contact films, and contact films made by such methods. In certain cases, the contact films may be patterned and substantially planar. Thus, the contact films may be patterned without intentionally removing any material from the layers and/or film, such as may be required by photolithography. In certain example embodiments, an oxygen exchanging system comprising at least two layers may be deposited on a substrate, and the layers may be selectively exposed to heat and/or energy to facilitate the transfer of oxygen ions or atoms from the layer with a higher enthalpy of formation to a layer with a lower enthalpy of formation. In certain cases, the oxygen transfer may permit the conductivity of selective portions of the film to be changed. This advantageously may result in a planar contact film that is patterned with respect to conductivity and/or resistivity. | 01-03-2013 |
20130040454 | Annealing Copper Interconnects - A method for modifying the chemistry or microstructure of silicon-based technology via an annealing process is provided. The method includes depositing a reactive material layer within a selected proximity to an interconnect, igniting the reactive material layer, and annealing the interconnect via heat transferred from the ignited reactive material layer. The method can also be implemented in connection with a silicide/silicon interface as well as a zone of silicon-based technology. | 02-14-2013 |
20130072013 | Etching Method and Apparatus - An etching method comprises etching an oxide layer with a first dc bias of a plasma chamber, removing a photoresist layer with a second dc bias of the plasma chamber and etching through a liner film with a third dc bias of the plasma chamber. In order to reduce the copper deposition on the wall of the plasma chamber, the third dc bias is set to be less than the first and second dc bias. | 03-21-2013 |
20130115767 | Metal Alloy Cap Integration - A metal interconnect structure, which includes metal alloy capping layers, and a method of manufacturing the same. The originally deposited alloy capping layer element within the interconnect features will diffuse into and segregate onto top surface of the metal interconnect. The metal alloy capping material is deposited on a reflowed copper surface and is not physically in contact with sidewalls of the interconnect features. The metal alloy capping layer is also reflowed on the copper. Thus, there is a reduction in electrical resistivity impact from residual alloy elements in the interconnect structure. That is, there is a reduction, of alloy elements inside the features of the metal interconnect structure. The metal interconnect structure includes a dielectric layer with a recessed line, a liner material on sidewalls, a copper material, an alloy capping layer, and a dielectric cap. | 05-09-2013 |
20130164932 | METHODS OF FORMING WIRINGS IN ELECTRONIC DEVICES - A method of forming a wiring may include forming a first wire on a substrate; forming a material layer on the substrate, except on the first wire; forming a surface treatment film on the material layer; and forming a second wire on the first wire. The surface treatment film has physical properties opposite to the first wire. A method of forming a wiring may include forming a first wire on a substrate; forming a material layer on the substrate and the first wire; removing a portion of the material layer from the first wire; forming a surface treatment film on the material layer and the first wire; removing a portion of the surface treatment film from the first wire; and forming a second wire on the first wire. A thickness of the material layer on the substrate is greater than a thickness of the first wire on the substrate. | 06-27-2013 |
20130217226 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer. | 08-22-2013 |
20130288475 | METHOD FOR OBTAINING A PALLADIUM SURFACE FINISH FOR COPPER WIRE BONDING ON PRINTED CIRCUIT BOARDS AND IC-SUBSTRATES - The present invention relates to a method of bonding a copper wire to a substrate, particularly a printed circuit board and an IC-substrate, possessing a layer assembly comprising a copper bonding portion and a palladium or palladium alloy layer and a substrate having a copper wire bonded to aforementioned layer assembly. | 10-31-2013 |
20130344694 | PROBE-ON-SUBSTRATE - Probes are directly patterned on a test substrate, thereby eliminating a need for an interposer. Probe contact structures are formed as a two-level structure having a greater lateral dimension for a lower level portion than for an upper level portion. First cavities are formed in a masking layer applied to a test substrate, filling the cavities with a conductive material, and planarizing the top surfaces of the conductive material portions to form lower level portions. Another masking layer is applied over the lower level portions and patterned to define second cavities having a smaller lateral dimension that the lower level portions. The second cavities are filled with at least one conductive material to form upper level portions of the probe contact structures. The upper level portion of each probe contact structure can be employed to penetrate a surface oxide of solder balls. | 12-26-2013 |
20140011352 | METAL WIRE ETCHANT AND METHOD OF FORMING METAL WIRE USING THE SAME - A metal wire etchant including persulfate, a sulfonate, a fluorine compound, an azole-based compound, an organic acid, a nitrate, and a chlorine compound, and a method of making the same. | 01-09-2014 |
20140011353 | FILM DEPOSITION METHOD - A film deposition method is provided. A first metal compound film is deposited by performing a first cycle of exposing a substrate to a first source gas containing a first metal, and of exposing the substrate to a reaction gas reactive with the first source gas. Next, the first source gas is adsorbed on the first metal compound film by exposing the substrate having the first metal compound film deposited thereon to the first source gas. Then, a second metal compound film is deposited on the substrate by performing a second cycle of exposing the substrate having the first source gas adsorbed thereon to a second source gas containing a second metal, and of exposing the substrate to the reaction gas reactive with the second source gas. | 01-09-2014 |
20140073129 | SEMICONDUCTOR DEVICE INCLUDING BOTTOM SURFACE WIRING AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE - Disclosed herein is a semiconductor device including a semiconductor substrate, a wiring layer formed above the semiconductor substrate, a through-hole electrode extending from the bottom surface of the semiconductor substrate to the wiring layer, a bottom surface wiring provided, at the bottom surface of the semiconductor substrate such that the bottom surface wiring is connected to the through-hole electrode, and an external terminal connected to the bottom surface wiring. The bottom surface wiring has a greater film thickness than a film thickness of the through-hole electrode at least a portion of the bottom surface wiring including a connection part between the bottom surface wiring and the external terminal. | 03-13-2014 |
20140094030 | MANUFACTURING METHOD OF SEMICONDUCTOR APPARATUS - A first wiring part has an intermediate layer made of a material different from materials of a first insulator layer and a first conductor layer and located between the first insulator layer and the first conductor layer. In a step of forming a first hole, which penetrates through a first element part and the first insulator layer, from a side of a first semiconductor layer toward the first conductor layer, and forming a second hole, which penetrates through the first element part, the first wiring part, and a second insulator layer, from the side toward the second conductor layer, an etching condition of the first insulator layer when the first hole is formed is that an etching rate for the material of the first insulator layer under the etching condition is higher than an etching rate for the material of the intermediate layer under the etching condition. | 04-03-2014 |
20140120716 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method allows stably forming a plating layer at low cost on one main surface side of a substrate, while preventing unintended plating layer deposition on the other main surface side. Emitter and collector electrodes are respectively formed on the front and back surfaces of a semiconductor substrate. A first film is attached to the back surface. A notch portion of the substrate is filled with a resin member. A second film is attached to an outer peripheral portion of the substrate, straddling the substrate from the front surface to the back surface. The first and second films push out air remaining between the first and second films and the substrate. An electroless plating process is carried out while the first and second films are attached to the substrate, thereby sequentially forming a nickel plating layer and a gold plating layer on the front surface side. | 05-01-2014 |
20140134839 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH ELECTRODE SUPPORT PATTERNS - Methods include sequentially forming a first mold film, a first support film, a second mold film, and a second support film on a substrate, forming a contact hole through the second support film, the second mold film, the first support film and the first mold film, forming an electrode in the contact hole, and removing portions of the second support film, the second mold film and the first mold film to leave a portion of the first support film as a first support pattern surrounding the electrode and to leave a portion of the second support film as a second support pattern surrounding the electrode. | 05-15-2014 |
20140220776 | Multi-Direction Design for Bump Pad Structures - An integrated circuit structure includes a semiconductor chip having a first region and a second region; a dielectric layer formed on the first region and the second region of the semiconductor chip; a first elongated under-bump metallization (UBM) connector formed in the dielectric layer and on the first region of the semiconductor chip and having a first longer axis extending in a first direction; and a second elongated UBM connector formed in the dielectric layer on the second region of the semiconductor chip and having a second longer axis extending in a second direction. The first direction is different from the second direction. | 08-07-2014 |
20140302670 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - The number of masks and photolithography processes used in a manufacturing process of a semiconductor device are reduced. A first conductive film is formed over a substrate; a first insulating film is formed over the first conductive film; a semiconductor film is formed over the first insulating film; a semiconductor film including a channel region is formed by etching part of the semiconductor film; a second insulating film is formed over the semiconductor film; a mask is formed over the second insulating film; a first portion of the second insulating film that overlaps the semiconductor film and second portions of the first insulating film and the second insulating film that do not overlap the semiconductor film are removed with the use of the mask; the mask is removed; and a second conductive film electrically connected to the semiconductor film is formed over at least part of the second insulating film. | 10-09-2014 |
20140349480 | COBALT SELECTIVITY IMPROVEMENT IN SELECTIVE COBALT PROCESS SEQUENCE - Embodiments of the invention provide processes to selectively form a cobalt layer on a copper surface over exposed dielectric surfaces. Embodiments described herein control selectivity of deposition by preventing damage to the dielectric surface, repairing damage to the dielectric surface, such as damage which can occur during the cobalt deposition process, and controlling deposition parameters for the cobalt layer. | 11-27-2014 |
20140357076 | SEMICONDUCTOR DEVICE WITH AIR GAPS AND METHOD FOR FABRICATING THE SAME - A method for fabricating a semiconductor device includes forming a plurality of bit line structures over a substrate, forming contact holes between the bit line structures, forming sacrificial spacers on sidewalls of the contact holes, forming first plugs recessed inside the contact holes, forming air gaps by removing the sacrificial spacers, forming conductive capping layers capping the first plugs and the air gaps, and forming second plugs over the conductive capping layers. | 12-04-2014 |
20150056800 | Self-aligned interconnects formed using substractive techniques - A method of forming an interconnect structure for semiconductor or MEMS structures at a 10 nm Node (16 nm HPCD) down to 5 nm Node (7 nm HPCD), or lower, where the conductive contacts of the interconnect structure are fabricated using solely subtractive techniques applied to conformal layers of conductive materials. | 02-26-2015 |
20150111377 | MEMORY PROCESS - A memory process is described. A substrate is provided, having therein trenches and conductive lines buried in the trenches and having thereon an array area, wherein each of the conductive lines has an array portion in the array area. A contact area apart from the array area is defined on the substrate, wherein each of the conductive lines has a contact portion in the contact area. The substrate between the contact portions of the conductive lines is etched down to below the tops of the conductive layers to form gaps between the contact portions of the conductive lines. The gaps are then filled with an insulating layer. | 04-23-2015 |
20150126027 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes: forming an insulating film on a substrate where a first conductive film is formed; forming a recess in the insulating film such that the first conductive film is exposed in a portion of the recess; forming a metal oxide film to cover the insulating film and the first conductive film after forming a recess; performing a hydrogen radical treatment of irradiating the substrate with atomic hydrogen after forming a metal oxide film; and forming a second conductive film in the recess. | 05-07-2015 |
20150325476 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device of an embodiment includes: a substrate on which a semiconductor circuit is formed; an interlayer insulating film in which a contact hole is formed on the substrate; a catalyst metal film on a side wall of the contact hole; catalyst metal particles on a bottom of the contact hole; graphene on the catalyst metal film; and carbon nanotubes, which penetrates the contact hole, on the catalyst metal particles. | 11-12-2015 |
20150340276 | METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE - A method of filling a dielectric trench includes forming two adjacent conductors on a substrate, forming a dielectric layer over a surface of the conductors and the substrate, removing a portion of the dielectric layer, treating a top surface of the dielectric layer with phosphorous plasma, and repeating the forming the dielectric layer, the removing the portion of the dielectric layer, and the treating the top surface of the dielectric layer in a multi cycle fashion. A narrowest width of the dielectric trench between the two adjacent conductors is smaller than about 30 nm. | 11-26-2015 |
20160042958 | METHOD FOR FORMING BASE FILM OF GRAPHENE, GRAPHENE FORMING METHOD, AND APPARATUS FOR FORMING BASE FILM OF GRAPHENE - A method for forming a base film of a graphene includes: forming a metal film as a base film of a graphene on a substrate by chemical vapor deposition (CVD) of an organic metal compound using a hydrogen gas and an ammonia gas; heating the substrate to a temperature at which impurities included in the formed metal film are eliminated as a gas; and heating the substrate to a temperature at which crystal grains of metal are grown in the metal film, wherein the temperature of the substrate in the heating the substrate to a temperature at which crystal grains of metal are grown in the metal film is higher than the temperature of the substrate in the heating the substrate to a temperature at which impurities included in the formed metal film are eliminated as a gas. | 02-11-2016 |
20160056073 | Semiconductor Constructions; and Methods for Providing Electrically Conductive Material Within Openings - Some embodiments include methods for depositing copper-containing material utilizing physical vapor deposition of the copper-containing material while keeping a temperature of the deposited copper-containing material at greater than 100° C. Some embodiments include methods in which openings are lined with a metal-containing composition, copper-containing material is physical vapor deposited over the metal-containing composition while a temperature of the copper-containing material is no greater than about 0° C., and the copper-containing material is then annealed while the copper-containing material is at a temperature in a range of from about 180° C. to about 250° C. Some embodiments include methods in which openings are lined with a composition containing metal and nitrogen, and the lined openings are at least partially filled with copper-containing material. Some embodiments include semiconductor constructions having a metal nitride liner along sidewall peripheries of an opening, and having copper-containing material within the opening and directly against the metal nitride liner. | 02-25-2016 |
20160087074 | Metalization of a Field Effect Power Transistor - A metalization of a field effect power transistor having lateral semiconductor layers on an insulator substrate or an intrinsically conducting semiconductor substrate is described. The lateral semiconductor layers have different band gaps such that a two-dimensional electron gas can form in their semiconductor depletion layer. Upon application of a voltage between source electrode contact areas and drain electrode contact areas or source and drain, an electric current can flow through the lateral semiconductor depletion layer. Current intensity in a channel region between the source electrode contact areas and the drain electrode contact areas is controllable via gate electrode contact areas by means of a gate voltage. | 03-24-2016 |
20160126106 | SELECTIVE GROWTH METHOD AND SUBSTRATE PROCESSING APPARATUS - There is provided a selective growth method of selectively growing a thin film on exposed surfaces of an underlying insulation film and an underlying metal film, which includes: selectively growing a film whose thickness is decreased by combustion on the underlying metal film using metal of the underlying metal film as a catalyst; and selectively growing a silicon oxide film on the underlying insulation film while combusting the film whose thickness is decreased by combustion. | 05-05-2016 |
20160148811 | Method of Manufacturing Semiconductor Device and Substrate Processing Apparatus - A method of manufacturing a semiconductor device includes (a) providing a substrate and (b) forming a film including a first element, a second element and a third element in a same group as the second element on the substrate by performing a cycle a predetermined number of times, the cycle including: (b-1) supplying a halogen-based source gas including the first element to the substrate; (b-2) supplying a first reactive gas including the second element and reactive with the halogen-based source gas; and (b-3) supplying a second reactive gas including the third element without mixing the second reactive gas with the first reactive gas, wherein the second reactive gas is reactive with the halogen-based source gas and unreactive with the first reactive gas. | 05-26-2016 |
20160163477 | SWITCHES FOR USE IN MICROELECTROMECHANICAL AND OTHER SYSTEMS, AND PROCESSES FOR MAKING SAME - Embodiments of switches ( | 06-09-2016 |