Entries |
Document | Title | Date |
20100333056 | TEMPERATURE-CONTROLLED 3-DIMENSIONAL BUS PLACEMENT - Block placement within each device-containing layer is optimized under the constraint of a simultaneous optimization of interlayer connectivity between the device-containing layer and immediately adjacent device-containing layers. For each functional block within the device-containing layer, lateral heat flow is calculated to laterally adjacent functional blocks. If the lateral heat flow is less than a threshold value for a pair of adjacent functional blocks, placement of the functional blocks and/or interlayer interconnect structure array therebetween or modification of the interlayer interconnect structure array is performed. This routine is repeated for all adjacent pairs of functional blocks in each of the device-containing layers. Subsequently, block placement within each device-containing layer may be optimized under the constraint of a simultaneous optimization of interlayer connectivity across all device-containing layers. This method provides a design having sufficient lateral heat flow in each of the device-containing layers in a semiconductor chip. | 12-30-2010 |
20110072405 | Chip-Level ECO Shrink - In a method of forming an integrated circuit, a layout of a chip representation including a first intellectual property (IP) is provided. Cut lines that overlap, and extend out from, edges of the first IP, are generated. The cut lines divide the chip representation into a plurality of circuit regions. The plurality of circuit regions are shifted outward with relative to a position of the first IP to generate a space. The first IP is blown out into the space to generate a blown IP. A direct shrink is then performed. | 03-24-2011 |
20110078646 | SUPPORT APPARATUS AND DESIGN SUPPORT METHOD - A design support method executed by a computer includes: detecting a layout position of a first terminal in a cell as a first layout position from layout data including a cell of a macro which is arranged at a plurality of orientations, the first terminal being arranged at a first orientation; calculating a second layout position of a first terminal which is arranged at a second orientation which is different from the first orientation based on a variation from the first orientation to the second orientation and the first layout position; associating the second layout position with the first layout position and the layout data; and outputting an association result. | 03-31-2011 |
20110161907 | Practical Approach to Layout Migration - The present disclosure provides an integrated circuit design method in many different embodiments. An exemplary IC design method comprises providing an IC design layout of a circuit in a first technology node; migrating the IC design layout of the circuit to a second technology node; applying an electrical patterning (ePatterning) modification to the migrated IC design layout according to an electrical parameter of the circuit; and thereafter fabricating a mask according to the migrated IC design layout of the circuit in the second technology node. | 06-30-2011 |
20110161908 | GENERATING CAPACITANCE LOOK-UP TABLES FOR WIRING PATTERNS IN THE PRESENCE OF METAL FILLS - A computer system selects a signal conductor from an electronic circuit design layout and assigns a first potential to the selected signal conductor. Next, the computer system assigns a second potential to other signal conductors included in the electronic circuit design layout. The computer system then selects a metal fill from the electronic circuit design layout, which is void from carrying an electrical signal, and generates a zero charge equation for the selected metal fill. The zero charge equation establishes that a total charge residing on the selected metal fill is equal to zero. The computer system includes the zero charge equation in a system of equations, which includes grid point potential equations, and solves the system of equations. In turn, the computer system computes capacitance values for the signal conductors based upon the system of equation solutions, and simulates the electronic circuit design layout using the computed capacitance values. | 06-30-2011 |
20110191738 | DENSITY-BASED AREA RECOVERY IN ELECTRONIC DESIGN AUTOMATION - Some embodiments provide techniques and systems for improving the efficiency of area recovery in an electronic design automation (EDA) flow. During operation, the system determines a utilization of a region from a set of regions in a design floorplan. Next, the system performs area recovery (e.g., by using a processor) on the region based at least on the utilization. Specifically, the system can overlay the design floorplan with a grid, wherein the grid comprises a set of grid cells and uses the grid cells as the set of regions. The grid can be associated with a predetermined number of rows and a predetermined number of columns. The system can determine the utilization of the region by calculating the utilization as a cell area of the region divided by a placement area of the region. The utilization can be incrementally calculated during the creation and optimization of the design. | 08-04-2011 |
20110202896 | ADAPTIVE PATTERNING FOR PANELIZED PACKAGING - An adaptive patterning method and system for fabricating panel based package structures is described. Misalignment for individual device units in a panel or reticulated wafer may be adjusted for by measuring the position of each individual device unit and forming a unit-specific pattern over each of the respective device units. | 08-18-2011 |
20110209111 | AUTOMATED INTEGRATED CIRCUIT CLOCK INSERTION - A user device receives a request to perform an automatic clock insertion operation for an integrated circuit; retrieves location information regarding a group of components, of the integrated circuit, that use a clock signal; deploys a clock mesh based on the location information regarding the group of components; and inserts drop points into the clock mesh; deploys a particular buffer for a particular drop point; maps a component, of the group of components, to the particular buffer; generates a clock box for the particular buffer, where dimensions of the clock box are based on a location of the component; deploys an H-tree for the clock box, where dimensions of the H-tree are proportional to the clock box dimensions; connects the H-tree to the component; and displays or stores clock mesh information, information regarding the group of buffers, information regarding the H-tree, and the location information regarding the group of components. | 08-25-2011 |
20110239177 | METHOD AND SYSTEM FOR APPROXIMATE PLACEMENT IN ELECTRONIC DESIGNS - Disclosed are method, system, and computer program product for a method and system for a fast and stable placement/floorplanning method that gives consistent and good quality results. Various embodiments of the present invention provide a method and system for approximate placement of various standard cells, macro-blocks, and I/O pads for the design of integrated circuits by approximating the final shapes of the objects of interest by one or more probability distribution functions over the areas for the objects of interest with improved runtime and very good stability. These probability distributions are gradually localized to final shapes satisfying the placement constraints and optimizing an objective function. | 09-29-2011 |
20110252392 | STANDARD CELL LIBRARY AND SEMICONDUCTOR INTEGRATED CIRCUIT - A standard cell library is used in design of a semiconductor integrated circuit. A driving force sequence of cells for a single function is in the form of geometric progression with a geometric ratio of the “p | 10-13-2011 |
20110265055 | HANDLING TWO-DIMENSIONAL CONSTRAINTS IN INTEGRATED CIRCUIT LAYOUT - A computer-implemented method for handling a plurality of constraints in layout optimization for an integrated circuit (IC) layout is disclosed. In one embodiment, the method includes building a graph representing the plurality of constraints; marking two-dimensional constraints in the plurality of constraints; generating two-dimensional clusters including groups of the two-dimensional constraints; handling at least one of the two-dimensional clusters, the handling including finding a solution for the two-dimensional constraints in the at least one two-dimensional cluster; repeating the handling for any unprocessed two-dimensional clusters until all of the two-dimensional clusters are handled; and adopting the solution for each of the two-dimensional clusters to solve at least a portion of the plurality of constraints including the two-dimensional clusters. | 10-27-2011 |
20110265056 | Semiconductor integrated circuit, layout design method of semiconductor integrated circuit, and layout program product for same - A layout design method of a semiconductor integrated circuit includes providing a cell layout including a cell that includes a gate or a plurality of gates extending in a first direction, a plurality of diffusion layers, a first boundary of the cell in parallel with the gate or the plurality of gates, a second boundary of the cell being in an opposite side of the first boundary of the cell, a first distance, a second distance, A third distance, and a fourth distance, regenerating the cell layout to set the first distance and the second distance to a first value, or to set the third distance and the fourth distance to a second value, and generating a library data of the cell for a placement and routing tool, based on the cell layout. | 10-27-2011 |
20110289466 | Table-Based DFM for Accurate Post-Layout Analysis - Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data. | 11-24-2011 |
20110296363 | HIERACHICALLY-MODULAR NANOELECTRONIC DIFFERENTIAL AMPLIFIERS, OP AMPS, AND ASSOCIATED CURRENT SOURCES UTILIZING CARBON NANOTUBES, GRAPHENE NANORIBBONS, PRINTED ELECTRONICS, POLYMER SEMICONDUCTORS, OR OTHER RELATED MATERIALS - A method for implementing electronic circuit modules on elongated structures of semiconducting materials such as carbon nanotubes, graphene nanoribbons, elongated structures of semiconducting polymers or organic semiconductors, other related materials, and printed electronics strip structures is disclosed. The method provides that a plurality of modules can be implemented on distinct adjacent portions of the same elongated structure of semiconducting materials. In powering the modules, each circuit comprises a chain of electronic components arranged so that each end of the chain can function as a power supply terminal. Larger electronic circuit modules can be created from smaller module, and. such a modular hierarchy may be extended to an arbitrary number of levels. In a Computer Aided Design (CAD) applications for nanoelectronics and printed electronics, designs for hierarchies electronic circuit modules can be stored and retrieved from one or more a libraries of circuit designs. | 12-01-2011 |
20110302544 | POST-PLACEMENT CELL SHIFTING - A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that has high detailed routing costs. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell in a selected tile. The expander applies multiple techniques to reposition these cells at new locations to improve the detailed routability. The expander can place an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile, and repositions the selected cell within the bounding box to form a modified design to improve the detailed routability. The expander may also inflate and legalize those cells. | 12-08-2011 |
20110307854 | MANIPULATING PARAMETERIZED CELL DEVICES IN A CUSTOM LAYOUT DESIGN - A system, apparatus and computer-implemented method for manipulating a parameterized cell device into a custom layout design. The method begins by receiving at least one parameterized cell representing a physical circuit from, for example, a database or configuration file. The parameterized cell has a plurality of configurable attributes. The method continues by adjusting one of the configurable attributes of the parameterized cell according to a capability associated with the one attribute. The attributes may include one or more of a parameter mapping capability, a port mapping capability, an abutment capability, a directional extension capability, a channel width capability, and a boundary layer capability. The method then calculates a new configuration for the parameterized cell based upon the adjustment, and applies the new configuration for the parameterized cell to a layout of the represented physical circuit. | 12-15-2011 |
20110320997 | Delay-Cell Footprint-Compatible Buffers - A method for creating a design for an integrated circuit, by developing a set of delay cells where each of the cells in the set has a different delay time from the other cells in the set, and where each of the cells in the set has the same surface area, has the same pin-outs, has the same drive strength, and has the same input capacitance, where an originally-used cell in the set can be swapped out for a different replacement cell in the set without any impact on the design of the integrated circuit besides a change in delay time from the originally-used cell to the replacement cell. | 12-29-2011 |
20120005643 | System and Method for Placing Integrated Circuit Functional Blocks According to Dataflow Width - Macroblock placement for an integrated circuit register-transfer level design is enhanced by tagging blocks having a set of functions as usage element definitions that have a minimum input signal width, such as tags added to a netlist of the design. Tagged blocks aid preferred and regular placement of library cells that are morphed to adapt for reduced congestion and improved utilization. | 01-05-2012 |
20120017191 | COMPUTING DEVICE AND METHOD FOR CHECKING DISTANCES BETWEEN TRANSMISSION LINES AND ANTI-PADS ARRANGED ON PRINTED CIRCUIT BOARD - A computing device and a method involves selection of one or more transmission lines from a printed circuit board (PCB) layout file, reading a transmission line from the one or more selected transmission lines, and determining neighboring anti-pads of the read transmission line in the PCB layout file. The computing device and method further determine an actual distance between the read transmission line and a neighboring anti-pad. If the actual distance is less than a preset standard distance, the computing device and method determine that the read transmission line and the neighboring anti-pad do not satisfy design requirements, and highlight the read transmission line and the neighboring anti-pad, to prompt a user to amend design of the read transmission line and the neighboring anti-pad. | 01-19-2012 |
20120030640 | DESIGN SUPPORT APPARATUS, CONTROL METHOD, AND CONTROL PROGRAM - A design support apparatus that supports designing of a circuit and is connected to a display unit, the design support apparatus includes a storage unit that stores logical connection information of the circuit and cell information of a plurality of cells included in the circuit, a selection unit that selects target cell information of a cell to be placed out of the cell information stored in the storage unit, a placement unit that provisionally places the cell corresponding to the selected target cell information based on inputted positional information, a determination unit that determines whether a wiring mode is set, a wiring unit that provisionally arranges wiring connected to the provisionally placed cell when the determination unit determines that the wiring mode is set, and a finalization unit that finalizes a position of the wiring provisionally arranged based on finalization of a position of the cell provisionally placed. | 02-02-2012 |
20120042296 | Asymmetric Segmented Channel Transistors - Structures, layouts and methods of forming integrated circuits are described. In various embodiments, the current invention includes an asymmetric segmented transistor. The asymmetric segmented transistor includes a source region and a drain region disposed within an active region, a floating source/drain region disposed within the active region, a first channel region disposed in the active region between the source region and the floating source/drain region, the first channel having a first length and a first width. A second channel region is disposed in the active region between the drain region and the floating source/drain region, the second channel having a second length and a second width. A first gate dielectric overlies the first channel region and a second gate dielectric overlies the second channel region. A gate line overlies the first gate dielectric and the second gate dielectric. | 02-16-2012 |
20120102445 | IMPLEMENTING ENHANCED RLM CONNECTIVITY ON A HIERARCHICAL DESIGN WITH TOP LEVEL PIPELINE REGISTERS - A method, system, and computer program product are provided for implementing enhanced random logic macro (RLM) connectivity on a hierarchical design on an integrated circuit chip with top-level pipeline registers. Random logic macros (RLMs) to be connected are identified. Pipeline registers are identified; an input net is connected to an output net of the identified RLMs, removing the pipeline registers from the design. A chip floor plan results is displayed, providing direct RLM connectivity. | 04-26-2012 |
20120144360 | Scalable Meta-Data Objects - A method is disclosed for defining an integrated circuit. The method includes generating a digital data file that includes both electrical connection information and physical topology information for a number of circuit components. The method also includes operating a computer to execute a layout generation program. The layout generation program reads the electrical connection and physical topology information for each of the number of circuit components from the digital data file and automatically creates one or more layout structures necessary to form each of the number of circuit components in a semiconductor device fabrication process, such that the one or more layout structures comply with the physical topology information read from the digital data file. The computer is also operated to store the one or more layout structures necessary to form each of the number of circuit components in a digital format on a computer readable medium. | 06-07-2012 |
20120180016 | Standard Cell Architecture Using Double Poly Patterning for Multi VT Devices - An apparatus fabricated using a standard cell architecture including devices having different voltage thresholds may include a first set of polylines associated with a first channel length, where each polyline within the first set of polylines is separated by a substantially constant pitch. The apparatus may further include a second set of polylines associated with a second channel length and aligned with the first set of polylines, where each polyline within the second set of polylines is laterally separated by the substantially constant pitch. The apparatus may further include a first active region below the first set of polylines, and a second active region below the second set of polylines, where the first active region and the second active region are separated by a distance of less than 170 nm. | 07-12-2012 |
20120185816 | LAYOUT METHOD FOR SOFT-ERROR HARD ELECTRONICS, AND RADIATION HARDENED LOGIC CELL - This invention comprises a layout method to effectively protect logic circuits against soft errors (non-destructive errors) and circuit cells, with layout, which are protected against soft errors. In particular, the method protects against cases where multiple nodes in circuit are affected by a single event. These events lead to multiple errors in the circuit, and while several methods exist to deal with single node errors, multiple node errors are very hard to deal with using any currently existing protection methods. The method is particularly useful for CMOS based logic circuits in modern technologies (.ltoreq.90 nm), where the occurrence of multiple node pulses becomes high (due to the high integration level). It uses a unique layout configuration, which makes the circuits protected against single event generated soft-errors. | 07-19-2012 |
20120185817 | Enhanced Static Random Access Memory Stability Using Asymmetric Access Transistors and Design Structure for Same - A memory circuit includes a plurality of bit line structures (each including a true and a complementary bit line), a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations; and a plurality of cells located at the plurality of cell locations. Each of the cells includes a logical storage element, a first access transistor selectively coupling a given one of the true bit lines to the logical storage element, and a second access transistor selectively coupling a corresponding given one of the complementary bit lines to the logical storage element. One or both of the first and second access transistors are configured with asymmetric current characteristics to enable independent enhancement of READ and WRITE margins. Also included within the 6-T scope are one or more design structures embodied in a machine readable medium, comprising circuits as set forth herein. | 07-19-2012 |
20120192137 | PLACEMENT AND OPTIMIZATION OF PROCESS DUMMY CELLS - A method for laying out process dummy cells in relationship to inside memory cells of a memory array includes (a) calculating an initial process performance parameter for the memory array; (b) changing dummy cell layout configuration for a layer electrically connected to inside cells; (c) applying lithographic simulation and yield model for both the inside memory cells and the changed layout configuration process dummy cells; and (d) repeating steps (b) and (c) until yield is maximized. Checks may be performed to ensure that there is enough room to make the change and that there is no significant adverse effect to neighboring circuits. The process performance parameter may be yield or a process window for the inside memory cells. | 07-26-2012 |
20120204140 | Generating Capacitance Look-up Tables for Wiring Patterns in the Presence of Metal Fills - A computer system selects a signal conductor from an electronic circuit design layout and assigns a first potential to the selected signal conductor. Next, the computer system assigns a second potential to other signal conductors included in the electronic circuit design layout. The computer system then selects a metal fill from the electronic circuit design layout, which is void from carrying an electrical signal, and generates a zero charge equation for the selected metal fill. The zero charge equation establishes that a total charge residing on the selected metal fill is equal to zero. The computer system includes the zero charge equation in a system of equations, which includes grid point potential equations, and solves the system of equations. In turn, the computer system computes capacitance values for the signal conductors based upon the system of equation solutions, and simulates the electronic circuit design layout using the computed capacitance values. | 08-09-2012 |
20120240092 | METHOD AND DEVICE FOR REORDERING SCAN CHAINS CONSIDERING PLAN GROUPS - Provided in the present invention is a reconfiguration method and device for scan chains with the planned unit taken into consideration, wherein said reconfiguration method of the scan chains comprises a first phase reconfiguration and second phase reconfiguration. Said first phase reconfiguration first classifies a number of scan chains, wherein scan chains with the starting point and the ending point in the same planned unit are classified as a first aggregation of scan chains; scan chains with the starting point and the ending point not in the same planned unit are classified as a second aggregation of scan chains; and scan chains with both the starting point and the ending point at the same top level are classified as a third aggregation of scan chains. Then, in sequence the scan chains within said first aggregation of scan chains are reconfigured, then the scan chains within said second aggregation of scan chains are reconfigured, and finally the scan chains within said third aggregation of scan chains are reconfigured. Starting from a situation taken as a whole, the present invention of the reconfiguration method and device for scan chains takes into consideration the information of the positions of the starting and ending points of the scan chain, so that it can go through as few planned units as possible, thus reducing by a large margin ports on the planned units and the connection wires between planned units, and reducing the demand for resources and the difficulty in the subsequent design. | 09-20-2012 |
20120254817 | Cell Architecture for Increasing Transistor Size - A cell-based architecture for an integrated circuit that uses at least two categories of cells: cut-gate cells and breaker cells. Cut-gate cells have gates that extend from one boundary of the cell to an opposite boundary of the cell. Cut gate features are located along the boundaries of the cell to indicate locations for cutting the gates during fabrication. Instances of the cut-gate cells are arranged in abutting rows that result in the formation of continuous gate strips during the fabrication process, which are then cut into individual gates with a cut-gate mechanism. Breaker cells have gates that do not extend to the boundaries of the breaker cell. To prevent the continuous gate strips from exceeding design rule requirements, instances of breaker cells are placed at intervals between the rows of cut-gate cell instances to restrict the size of the gate strips. | 10-04-2012 |
20120272202 | Enhanced Modularity in Heterogeneous 3D Stacks - A method for generating and implementing a three-dimensional ( | 10-25-2012 |
20120290995 | CHANGING THE LOCATION OF A BUFFER BAY IN A NETLIST - In an embodiment, a buffer bay is represented with a moveable object that has a location within a unit in a netlist. The location of the moveable object that represents the buffer bay is changed to a new location in the netlist if changing the location improves placement within the unit. In an embodiment, a net weight of a net that connects the moveable object to an artificial pin is considered in determining whether to change the location to the new location. In an embodiment a bounding area that encompasses the location is considered in determining whether to change the location to the new location. | 11-15-2012 |
20120304142 | DESIGN SUPPORT DEVICE OF THREE-DIMENSIONAL INTEGRATED CIRCUIT AND METHOD THEREOF - To provide a design support device of a three-dimensional integrated circuit capable of, in the case where a placement position of a through-via changes in the design phase of a three-dimensional integrated circuit composed of a plurality of semiconductor chips in layers, avoiding change of respective placement positions of other parts as much as possible. A design support device | 11-29-2012 |
20130036396 | LAYOUT DESIGN APPARATUS AND LAYOUT DESIGN METHOD - A layout design apparatus includes: a memory unit to store design data of a hierarchical layout of a multilayer circuit including a macro; a channel count calculation unit to calculate a channel count of channels available to lead wiring from a terminal of the macro to a wiring layer based on the design data stored in the memory unit; and a path calculation unit to calculate a path for leading wiring from a terminal of the macro to the wiring layer in ascending order of the channel count. | 02-07-2013 |
20130042216 | Row Based Analog Standard Cell Layout Design and Methodology - A system and method of designing the physical layout of an SoC incorporating row-based placement of analog standard cells whose heights are constrained to a predetermined row height or integer multiple thereof. A library of analog standard cells may be utilized by an ECAD tool to map, place, and route analog and mixed signal circuits in a manner similar to how such ECAD tool may utilize a library of digital standard cells to map, place, and route digital circuits. Mapping, placing, and routing of digital, analog, and mixed signal circuits may proceed within a unified ECAD SoC physical design flow. Finally, a general type analog standard cell is taught to further increase the speed and efficiency of analog and mixed-signal SoC layout. | 02-14-2013 |
20130074026 | LAYOUT TECHNIQUE FOR STRESS MANAGEMENT CELLS - An integrated circuit device layout is created based on charge carrier mobility characteristics of the device's non-functional cells. The charge carrier mobility of the non-functional cells can alter behavioral characteristics such as the hold time, setup time, or leakage current of nearby functional logic cells. Accordingly, a layout tool creates the layout for the integrated circuit device by selecting and placing non-functional cells having different mobility so as to selectively alter the characteristics of nearby logic cells. | 03-21-2013 |
20130074027 | DESIGNING DEVICE FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND DESIGNING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT - A designing device for a semiconductor integrated circuit of an embodiment includes a low-order hierarchy wiring design portion configured to design a first wiring; and a high-order hierarchy wiring design portion configured to design a second wiring. The low-order hierarchy wiring design portion divides the first functional block into a plurality of small regions, calculates a number of wiring layers required for wiring in the functional block for each of the plurality of small regions and sets the number as the number of low-order hierarchy wiring layers, sets wiring layers in the number of the low-order hierarchy wiring layers from the wiring layer located on the lowermost part as a low-order hierarchy wiring region for each of the plurality of small regions, and places the first wiring in the low-order hierarchy wiring region. | 03-21-2013 |
20130086543 | MULTI-PATTERNING LITHOGRAPHY AWARE CELL PLACEMENT IN INTEGRATED CIRCUIT DESIGN - A method, system, and computer program product for multi-patterning lithography (MPL) aware cell placement in integrated circuit (IC) design are provided in the illustrative embodiments. A global phase of cell movement is performed. A local phase cell movement is performed, wherein the local phase includes moving a color instance of the cell from a plurality of color instances of the cell within a row of cell in the IC design, wherein the global phase and the local phase are each performed before a final placement is produced for the IC design. | 04-04-2013 |
20130125077 | METHOD FOR OPTIMISING CELL VARIANT SELECTION WITHIN A DESIGN PROCESS FOR AN INTEGRATED CIRCUIT DEVICE - A method is provided for optimising cell variant selection within a design process for an integrated circuit device. The method comprises performing cell placement and signal routing for an integrated circuit being designed using default cell layout information for cell variants of at least one cell type. The method further comprises performing cell variant optimisation comprising identifying at least one cell of the at least one cell type to be substituted and substituting a default cell variant of the at least one identified cell with an alternative variant of the at least one identified cell. The method further comprises, during cell optimisation, configuring a pin interconnect modification for mapping at least one pin location of the alternative variant of the at least one identified cell to at least one pin contact for the default cell layout. | 05-16-2013 |
20130159955 | DYNAMIC PIN ACCESS MAXIMIZATION FOR MULTI-PATTERNING LITHOGRAPHY - A method, system, and computer program product for improving pin access in a design of an integrated circuit (IC) for multi-patterning lithography (MPL) are provided in the illustrative embodiments. A cell is placed in the IC design, the cell including a pin shape configured to connect a pin of the cell to a semi-conductor component in the IC design, the cell including a coloring conflict due to the pin shape and an other shape in the cell each being colored using a first color for fabricating onto a wafer using MPL. A net is routed to the pin shape without resolving the coloring conflict, wherein the routing routes the net using a first segment of the pin shape. The pin shape is modified after routing to resolve the coloring conflict to result in a modified cell. | 06-20-2013 |
20130185690 | Automatically Modifying a Circuit Layout to Perform Electromagnetic Simulation - Automatically modifying a layout to perform circuit simulation. Initially, a first layout of the electronic system may be received or stored. A second layout of the electronic system may be automatically generated based on the first layout. The automatic generation may involve automatically simplifying the first layout using a set of rules for electromagnetic (EM) simulation. The second layout may then be used to perform EM simulation of the electronic system, e.g., to perform verification. | 07-18-2013 |
20130198712 | Canonical Signature Generation For Layout Design Data - Contour-related information for geometric elements in layout design data is obtained. Relevant portions of the contour-related information are provided to a canonical hash function, from which a canonical signature for the layout design data is generated. | 08-01-2013 |
20130212549 | CELL ROUTABILITY PRIORITIZATION - A layout of a standard cell is created by prioritizing routability characteristics of the standard cell layout. The routability characteristics are prioritized so that the characteristics that are more likely to enhance routing efficiency are emphasized in the cell layout. The prioritization of the routability characteristics can be indicated by a set of weights, with each weight in the set indicating the priority of a corresponding routability characteristic of the standard cell layout. The weights can be used to calculate a weighted sum of the routability characteristics of the standard cell, thereby providing a way to efficiently compare the routability of different standard cell layouts. | 08-15-2013 |
20130263076 | BANDED COMPUTATION ARCHITECTURES - A convolution of the kernel over a layout in a multi-core processor system includes identifying a sector, called a dynamic band, of the layout including a plurality of evaluation points. Layout data specifying the sector of the layout is loaded in shared memory, which is shared by a plurality of processor cores. A convolution operation of the kernel and the evaluation points in the sector is executed. The convolution operation includes iteratively loading parts of the basis data set, called a stride, into space available in shared memory given the size of the layout data specifying the sector. A plurality of threads is executed concurrently using the layout data for the sector and the currently loaded part of the basis data set. The iteration for the loading basis data set proceeds through the entire data set until the convolution operation is completed. | 10-03-2013 |
20130275937 | METHODOLOGIES FOR AUTOMATIC 3-D DEVICE STRUCTURE SYNTHESIS FROM CIRCUIT LAYOUTS FOR DEVICE SIMULATION - A method of automatically generating structure files employing a full structure generator automated program is provided. An annotated device layout file is generated from a design layout by annotating the codes for design shapes with additional text representing the functionality of a physical structure associated with each design shape. Functioning individual semiconductor devices are identified from the annotated device layout file, and a circuit area including multiple interconnected semiconductor devices are identified. A front-end-of-line (FEOL) device structure file and a back-end-of-line (BEOL) device structure file are generated from layer by layer analysis of the components of the annotated device layout within the circuit area. Finite element meshes (FEMs) are generated for the FEOL and BEOL structure files and merged to provide a structure file that can be employed for simulation of semiconductor devices therein. | 10-17-2013 |
20130339916 | TOPOLOGY DENSITY AWARE FLOW (TDAF) - A method for selecting and placing of an IP block in a SOC design based on a topology and/or a density of the SOC design is disclosed. Embodiments include: displaying a user interface; causing, at least in part, a presentation in the user interface of a topology and density view of a SOC design that includes an IP block; and modifying, prior to a tape-out of the SOC design, topology and/or density transition for the IP block in the SOC design based on the presentation. | 12-19-2013 |
20140007035 | Method and Apparatus to Perform Footprint-Based Optimization Simultaneously with Other Steps | 01-02-2014 |
20140033152 | METHOD OF DECOMPOSING LAYOUT OF SEMICONDUCTOR DEVICE - Embodiments relate to a method of decomposing a layout of a semiconductor device. The method may include generating a pattern layout including first patterns and second patterns, generating an interference map for the pattern layout, the interference map including optical interference information regarding the first and second patterns, and decomposing the pattern layout into a first decomposition pattern layout including the first patterns, and a second decomposition pattern layout including the second patterns, based on the interference map. In the interference map, an influence of constructive interference on the first patterns may be greater than an influence of constructive interference on the second patterns. | 01-30-2014 |
20140040847 | SYSTEM AND METHOD FOR GENERATING PHYSICAL DETERMINISTIC BOUNDARY INTERCONNECT FEATURES FOR DUAL PATTERNING TECHNOLOGIES - One aspect provides a system for generating a layout for dual patterning technologies. In one embodiment, the system includes: (1) a deterministic boundary interconnect feature generator configured to generate a deterministic boundary interconnect feature for a cell based on at least one dual patterning design rule; and (2) cell placement and interconnect routing tools associated with the deterministic boundary interconnect feature generator and configured to place the deterministic boundary interconnect feature. | 02-06-2014 |
20140053122 | METHOD FOR ADJUSTING A LAYOUT OF AN INTEGRATED CIRCUIT - A method for adjusting a layout of an integrated circuit includes a first layer, a second layer, a target metal line, and a first non-target metal line. The integrated circuit is configured for a focused ion beam (FIB) detection to the target metal line. The method includes the steps of: disposing the first non-target metal line on the first layer; disposing the target metal line on the second layer; and adjusting one of the target metal line and the first non-target metal line such that the target metal line can be detected by the FIB detection. | 02-20-2014 |
20140109032 | METHODS AND SYSTEMS FOR INTEGRATED CIRCUIT C4 BALL PLACEMENT - Methods and systems for improving the reliability of C4 solder ball contacts performed at the design stage to reduce the incidence of thermally-induced failures, including those due to electromigration and thermal cycling. | 04-17-2014 |
20140115553 | System and Method for Designing Cell Rows - A system and method for designing integrated circuits is disclosed. An embodiment comprises placing a standard cell with a first cell height into a cell row with a different height. The standard cell may have a height smaller than the cell row or else may have a height that is larger than the cell row. Vertical fillers and horizontal fillers are utilized to extend and connect the standard cell to adjacent cells without having to redesign the entire cell row. | 04-24-2014 |
20140137065 | ELECTRONIC DEVICE HAVING CIRCUIT BOARD WITH CO-LAYOUT DESIGN OF MULTIPLE CONNECTOR PLACEMENT SITES AND RELATED CIRCUIT BOARD THEREOF - An electronic device includes an integrated circuit, a connector, and a circuit board. The integrated circuit includes a first signal processing circuit, a second signal processing circuit, and an interface multiplexer having a first input port electrically connected to the first signal processing circuit, a second input port electrically connected to the second signal processing circuit, and an output port arranged to be electrically connected to the first input port or the second input port. The circuit board carries the integrated circuit and has a plurality of connector placement sites, including at least a first connector placement site each dedicated to the first signal processing circuit and at least a second connector placement site each dedicated to the second signal processing circuit. The connector placement sites and the output port of the interface multiplexer are electrically connected in series. The connector is installed on one of the connector placement sites. | 05-15-2014 |
20140157220 | LAYOUT DESIGN APPARATUS AND LAYOUT DESIGN METHOD - A layout design apparatus includes: a memory unit to store design data of a hierarchical layout of a multilayer circuit including a macro; a channel count calculation unit to calculate a channel count of channels available to lead wiring from a terminal of the macro to a wiring layer based on the design data stored in the memory unit; and a path calculation unit to calculate a path for leading wiring from a terminal of the macro to the wiring layer in ascending order of the channel count. | 06-05-2014 |
20140173544 | METHOD FOR GENERATING A TOPOGRAPHY OF AN FDSOI INTEGRATED CIRCUIT - An IC including first and second FDSOI UTBOX cells arranged in a row, the first having an nMOS transistor arranged plumb with and above a ground plane and an N-type well, and a pMOS transistor arranged plumb with and above a ground plane and a P-type well, the N-type well and the P-type well being arranged on either side of a row axis, wherein the second includes a diode protecting against antenna effects or a well tap cell, the second cell comprising a P-type well arranged in the alignment of the P-type well of the pMOS transistor and comprising an N-type well arranged in the alignment of the N-type well of the nMOS transistor, the second cell comprising a metal connection coupled to its P-type well and coupled to a higher-level metal connection element arranged plumb with the N-type well, the metal connection extending on either side of the axis. | 06-19-2014 |
20140173545 | PLACING TRANSISTORS IN PROXIMITY TO THROUGH-SILICON VIAS - Roughly described, the invention involves ways to characterize, take account of, or take advantage of stresses introduced by TSV's near transistors. The physical relationship between the TSV and nearby transistors can be taken into account when characterizing a circuit. A layout derived without knowledge of the physical relationships between TSV and nearby transistors, can be modified to do so. A macrocell can include both a TSV and nearby transistors, and a simulation model for the macrocell which takes into account physical relationships between the transistors and the TSV. A macrocell can include both a TSV and nearby transistors, one of the transistors being rotated relative to others. An IC can also include a transistor in such proximity to a TSV as to change the carrier mobility in the channel by more than the limit previously thought to define an exclusion zone. | 06-19-2014 |
20140201694 | Wrap Based Fill In Layout Designs - Techniques for “wrapping” functional geometric elements with fill geometric elements are provided. With some implementations, functional geometric elements, such as geometric elements representing metal contact and interconnect structures, are identified in layout design data. Next, fill regions requiring fill geometric elements are identified. If a portion of a functional geometric element faces a fill region, then that portion of the functional geometric element is “wrapped” with fill structures. Typically, the exposed portions of the functional geometric elements are wrapped before the remaining fill region is populated with fill geometric elements. By wrapping the exposed portions of the functional geometric elements, a designer can surround the functional geometric elements with a predictable pattern of fill geometric elements that can serve to protect the functional geometric elements from, for example, the capacitive effect of other fill geometric elements in the fill region. | 07-17-2014 |
20140208283 | DUMMY SHOULDER STRUCTURE FOR LINE STRESS REDUCTION - Semiconductor integrated circuit line structures for improving a process window in the vicinity of dense-to-isolated pattern transition areas and a technique to implement the line structures in the layout process are described in this disclosure. The disclosed structure includes a semiconductor substrate, and a material layer above the substrate. The material layer has a closely spaced dense line structure, an isolated line structure next to the dense line structure, and a dummy line shoulder structure formed in the vicinity of the dense line and the isolated line structures. One end of the dummy line shoulder structure connects to the isolated line structure and another end extends away from the isolated line structure in an orientation substantially perpendicular to the isolated line structure. | 07-24-2014 |
20140258960 | INTEGRATING OPTIMAL PLANAR AND THREE-DIMENSIONAL SEMICONDUCTOR DESIGN LAYOUTS - An approach and apparatus are provided for optimizing and combining different semiconductor technologies into a single graphic data system. Embodiments include generating a planar semiconductor layout design, generating a three-dimensional (e.g., FinFET) semiconductor layout design, and combining the planar design and the FinFET design in a common graphic data system. | 09-11-2014 |
20140304671 | MANIPULATING PARAMETERIZED CELL DEVICES IN A CUSTOM LAYOUT DESIGN - A system, apparatus and computer-implemented method for manipulating a parameterized cell device into a custom layout design. The method begins by receiving at least one parameterized cell representing a physical circuit from, for example, a database or configuration file. The parameterized cell has a plurality of configurable attributes. The method continues by adjusting one of the configurable attributes of the parameterized cell according to a capability associated with the one attribute. The attributes may include one or more of a parameter mapping capability, a port mapping capability, an abutment capability, a directional extension capability, a channel width capability, and a boundary layer capability. The method then calculates a new configuration for the parameterized cell based upon the adjustment, and applies the new configuration for the parameterized cell to a layout of the represented physical circuit. | 10-09-2014 |
20140325465 | CHIP WITH FLEXIBLE PAD SEQUENCE MANIPULATION AND ASSOCIATED METHOD - A chip with flexible pad sequence manipulation is provided. The chip can be a memory controller, and includes a hub unit. The hub unit, formed by a gate array, is placed in a hub region predetermined during placing and routing procedures, and is capable of supporting re-placing and re-routing for changing interior interconnections and a pad sequence of the chip. | 10-30-2014 |
20140325466 | Stretch Dummy Cell Insertion in FinFET Process - A method embodiment includes identifying, by a processor, an empty region in an integrated circuit (IC) layout, wherein the empty region is a region not including any active fins. The method further includes providing a standard dummy fin cell and forming an expanded dummy fin cell. The standard dummy fin cell includes a plurality of partitions. The expanded dummy fin cell is larger than the standard dummy fin cell, and the expanded dummy fin cell includes integer multiples of each of the plurality of partitions. The empty region is filled with a plurality of dummy fin cells, wherein the plurality of dummy fin cells includes the expanded dummy fin cell. The plurality of dummy fin cells is implemented in an IC. | 10-30-2014 |
20140331197 | SEQUENTIAL STATE ELEMENTS IN TRIPLE-MODE REDUNDANT (TMR) STATE MACHINES - The disclosure relates generally to triple-redundant sequential state (TRSS) machines formed as integrated circuits on a semiconductor substrate, such as CMOS, and computerized methods and systems of designing the triple-redundant sequential state machines. Of particular focus in this disclosure are sequential state elements (SSEs) used to sample and hold bit states. The sampling and holding of bits states are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines. In particular, the clock signal may oscillate between a first clock state and a second clock state to synchronize the operation of the SSE according to the timing provided by the clock states. The SSEs has a self-correcting mechanism to protect against radiation induced soft errors. The SSE may be provided in a pipeline circuit of a TRSS machine to receive and store a bit state of bit signal generated by combinational circuits within the pipeline circuit. | 11-06-2014 |
20140344770 | APPARATUS AND METHOD FOR DESIGNING AN INTEGRATED CIRCUIT LAYOUT HAVING A PLURALITY OF CELL TECHNOLOGIES - A system and method of designing a layout for a plurality of different logic operation (LOP) cell technologies includes defining a priority for each LOP cell technology in the plurality of different LOP technologies and forming a layout of the plurality of different LOP cells for formation on a substrate with at least some of the LOP cells of higher priority LOP technologies overlapping LOP cells of lower priority LOP technologies. The system can include a processor coupled to memory where stored code defines the priority for each different cell technology in the plurality of LOP cells and (when the code is executed) the processor forms the layout of a plurality of different LOP cells. All of the LOP cells of higher priority LOP technologies overlap LOP cells of lower priority. The system or method also avoids the overlap of higher priority LOP cells by lower priority LOP cells. | 11-20-2014 |
20140359546 | STRUCTURED PLACEMENT OF HIERARCHICAL SOFT BLOCKS DURING PHYSICAL SYNTHESIS OF AN INTEGRATED CIRCUIT - Integrated circuit design uses a library of structured soft blocks (SSBs) composed of pre-defined sets of cells with their logic implementation and placement templates with their relative placement information. A compiler receives a circuit description which includes an instance of an SSB and unfolds the instance according to the placement template to generate a modified circuit description which includes the relative placement information. The placement of circuit objects is optimized while maintaining relative locations for cells of the SSB instance according to the relative placement information. The SSB may be hierarchical. Gate resizing of cells in the SSB instance may result in a change in its bounds. A timing optimization procedure for the modified circuit description may be carried out while hiding internal details of the SSB instance. For example, buffers may be inserted in nets external to the SSB instance while preventing insertion of buffers in any internal nets. | 12-04-2014 |
20140359547 | HIERARCHICAL DESIGN OF INTEGRATED CIRCUITS WITH MULTI-PATTERNING REQUIREMENTS - Systems and methods for avoiding restrictions on cell placement in a hierarchical design of integrated circuits with multi-patterning requirements are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to assign a color to each pattern shape in a first cell, assign a color to each pattern shape in a second cell, characterize quantities of interest for each pattern shape in the first cell, determine that the colors assigned in the first cell are all one to one mappable to the colors assigned in the second cells, characterize quantities of interest for each pattern shape in the second cell using the quantities of interest characterized for the first cell, and model the quantities of interest for the first cell and the second cell. | 12-04-2014 |
20140380259 | LAYOUT MIGRATION WITH HIERARCHICAL SCALE AND BIAS METHOD - A method for migrating a hierarchical layout between manufacturing processes is accomplished without specification of a technology file and design rules. Different scaling factors and bias values in the X and Y directions may be applied to each layer in the source hierarchical layout during the migration. In addition, the target hierarchical layout maintains connectivity, and is free of notches, jogs and small edges. A cell hierarchy tree is created, which guides expansion of the target hierarchical database to resolve issues related to rounding of floating point numbers to integers. Boolean operations are performed to determine the differences between target flat database and the target hierarchical database. The differences are eliminated by modifying the target hierarchical database to match the layout in the flat database. | 12-25-2014 |
20140380260 | Scalable Meta-Data Objects - A method is disclosed for defining an integrated circuit. The method includes generating a digital data file that includes both electrical connection information and physical topology information for a number of circuit components. The method also includes operating a computer to execute a layout generation program. The layout generation program reads the electrical connection and physical topology information for each of the number of circuit components from the digital data file and automatically creates one or more layout structures necessary to form each of the number of circuit components in a semiconductor device fabrication process, such that the one or more layout structures comply with the physical topology information read from the digital data file. The computer is also operated to store the one or more layout structures necessary to form each of the number of circuit components in a digital format on a computer readable medium. | 12-25-2014 |
20150012901 | FIXED-OUTLINE FLOORPLANNING APPROACH FOR MIXED-SIZE MODULES - A fixed-outline floorplanning approach for mixed-size modules is disclosed. Firstly, evenly distribute mixed-size circuit modules to whole chip area based on different requirements such as wire-length, routability, or thermal in the global distribution stage. To maintain the global distribution result and satisfy the fixed-outline constraint, generate a slicing tree by recursively applying partition algorithm to divide modules distributed in a given region into several sub-regions. Then, to remove overlap between circuit modules and find a best solution, use bottom-up shape curve merging and top-down back tracing procedure to generate a slicing tree. The shape curve for each leaf in the tree is built first by enumerated packing. Then, the curves in the tree are merged iteratively from bottom to top, and feasible solutions in the shape curve of the root node are identified according to the fixed-outline constraint. Finally, the best solution is determined by a top-down back tracing procedure. | 01-08-2015 |
20150040091 | METHODS FOR MODIFYING AN INTEGRATED CIRCUIT LAYOUT DESIGN - Methods for modifying a layout design of an integrated circuit are provided. In one embodiment, a method for modifying an integrated circuit layout design includes providing an initial circuit layout design comprising a lower metal layer, an upper metal layer, and a first via electrically connecting the lower metal layer to the upper metal layer. The method further includes altering the initial circuit layout design by providing a second via, the second via being in electrical contact with no more than one of the upper metal layer and the lower metal layer, and the second via further being in proximity to the first via. Further, the method includes further altering the initial circuit layout design by providing a subresolution assist feature in proximity to the second via. | 02-05-2015 |
20150040092 | Stress Migration Mitigation - A computer-implemented method of configuring a semiconductor device includes identifying an interconnect having an interconnect path length greater than a stress-induced void formation characteristic length of the semiconductor device, and placing, with a processor, a conductive structure adjacent the interconnect to define a pair of segments of the interconnect. Each segment has a length no greater than the stress-induced void formation characteristic length of the interconnect, and the conductive structure is selected from the group consisting of a decoy via connected to the interconnect, a floating tile disposed along the interconnect, a tab that laterally extends outward from the interconnect, and a jumper from a first metal layer in which the interconnect is disposed to a second metal layer. | 02-05-2015 |
20150046894 | Constrained Placement of Connected Elements - An improved method for the placement and routing of compound elements, each comprising a series/parallel combination of nominally identical elements, is disclosed. The method treats each compound element as a separate cell (the sub-circuit construct commonly used in silicon chip design) so as to treat as a unit all the nominally identical elements that make up a compound value, and place them as a single group in the design of a chip. This results in the compound elements being placed as units and routed in such a way that all of the nominal elements are located together and any effects between compound values are thus relatively localized and optimally isolated. | 02-12-2015 |
20150106777 | METHOD AND SYSTEM FOR THREE-DIMENSIONAL LAYOUT DESIGN OF INTEGRATED CIRCUIT ELEMENTS IN STACKED CMOS - A method includes providing a design of a semiconductor device such as a stacked CMOS device comprising a plurality of circuit elements to be assigned into a layout of a plurality of tiers, and identifying at least one first type of circuit element within the plurality of circuit elements based on at least one predetermined criterion. Each respective one of the at least one first type of circuit element is to be assigned to a respective designated one of the plurality of tiers. The method further includes dividing the remainder of the plurality of circuit elements into at least two groups of circuit elements based on circuit density, and assigning the at least one first type of circuit element and the at least two groups of circuit elements to respectively different ones of the plurality of tiers of the semiconductor device. | 04-16-2015 |
20150113492 | SRAM LAYOUTS - Roughly described, the cell layout in an SRAM array is re-arranged such that the gate electrodes for transistors for which flexibility to use one channel length is desired, are formed along a different track from those for transistors for which flexibility to use a different channel length is desired. Not only does such a re-arrangement permit optimization of device ratios, but also in certain implementations can also reduce, rather than increase, cell area. Specific example layouts are described. The invention also involves layout files, macrocells, lithographic masks and integrated circuit devices incorporating these principles, as well as fabrication methods. | 04-23-2015 |
20150135156 | SEMICONDUCTOR STRUCTURES WITH DEEP TRENCH CAPACITOR AND METHODS OF MANUFACTURE - An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins. | 05-14-2015 |
20150149975 | METHOD AND APPARATUS FOR PROVIDING A DESIGN DIAGRAM OF A SEMICONDUCTOR DEVICE - A method for providing a design diagram of a semiconductor device is provided. The method includes generating a circuit diagram representing connections among a supply voltage, a ground voltage and a plurality of components in the semiconductor device and displaying a plurality of layout restrictions on the circuit diagram by using a plurality of graphic symbols. | 05-28-2015 |
20150370938 | Measurement of Aggressor/Victim Capacitive Coupling Impact on Timing - A circuit for modeling capacitive coupling comprising a victim line to be tested, a first aggressor line, running alongside the victim line, creating a coupling capacitance between the victim line and the first aggressor line, and a sensor circuit coupled to the victim line, to detect effects of the first aggressor line on the victim line, the sensor circuit measuring timing effects in pseudo-real time. | 12-24-2015 |
20150370947 | DESIGN TOOLS FOR INTEGRATED CIRCUIT COMPONENTS INCLUDING NANOWIRES AND 2D MATERIAL STRIPS - An integrated circuit design tool includes a cell library. An entry in the cell library comprises a specification of the cell including a first transistor and a second transistor. The first transistor can include a first set of nanowires or 2D material strips arranged in parallel to form a channel structure, and a gate conductor disposed across the first set of nanowires or 2D material strips. The second transistor can include a second set of nanowires or 2D material strips arranged in parallel to form a channel structure, and a gate conductor disposed across the first set of nanowires or 2D material strips. The number of nanowires or 2D material strips in the first set can be different from the number of nanowires or 2D material strips in the second set, so that the drive power of the individual transistors can be set with finer granularity. | 12-24-2015 |
20150370948 | MEMORY CELLS HAVING TRANSISTORS WITH DIFFERENT NUMBERS OF NANOWIRES OR 2D MATERIAL STRIPS - An integrated circuit design tool includes a cell library. The cell library includes entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library can comprise a specification of physical structures and timing parameters of a memory cell including a plurality of transistors, at least some of the transistors in the plurality having channels comprising respective sets of one or more nanowires or 2D material strips, and wherein the channel of one of the transistors in the plurality has a different number of nanowires or 2D material strips than a channel of another transistor in the plurality. An integrated circuit including the memory cell is described. | 12-24-2015 |
20150370949 | NANOWIRE OR 2D MATERIAL STRIPS INTERCONNECTS IN AN INTEGRATED CIRCUIT CELL - An integrated circuit design tool includes a cell library. The cell library includes entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library can comprise a specification of physical structures and timing parameters of a circuit including a first transistor, a second transistor, and an interconnect connecting a terminal of the first transistor to a terminal of the second transistor, the interconnect comprising one or more nanowires or 2D material strips arranged in parallel. An integrated circuit including the circuit is described. | 12-24-2015 |
20150370950 | ARRAY WITH INTERCELL CONDUCTORS INCLUDING NANOWIRES OR 2D MATERIAL STRIPS - An integrated circuit design tool includes a cell library. The cell library includes entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library can comprise a specification of physical structures and timing parameters of an array of circuit cells, the circuit cells including one or more transistors and a cell interconnect terminal; and a conductor configured to connect interconnect terminals of a plurality of the circuit cells in the array, the conductor comprising one or more nanowires or 2D material strips arranged in parallel. An integrated circuit including the array of circuit cells is described. | 12-24-2015 |
20150370951 | CELLS HAVING TRANSISTORS AND INTERCONNECTS INCLUDING NANOWIRES OR 2D MATERIAL STRIPS - An integrated circuit design tool includes a cell library. The cell library includes entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library can comprise a specification of physical structures and timing parameters of a plurality of transistors and an interconnect; wherein a transistor in the plurality has a channel comprising one or more nanowires or 2D material strips arranged in parallel, and the interconnect comprises one or more nanowires or 2D material strips arranged in parallel and connected to terminals of more than one of the transistors in the plurality of transistors. An integrated circuit including the plurality of transistors and the interconnect is described. | 12-24-2015 |
20160012169 | GATE PAD LAYOUT PATTERNS OF STANDARD CELL HAVING DIFFERENT GATE PAD PITCHES | 01-14-2016 |
20160034629 | METHOD OF CONVERTING BETWEEN NON-VOLATILE MEMORY TECHNOLOGIES AND SYSTEM FOR IMPLEMENTING THE METHOD - A method of designing a charge trapping memory array includes designing a memory array layout. The memory array layout includes a first type of transistors; electrical connections between memory cells of the memory array layout; a first input/output (I/O) interface; and a charge pump. The method further includes modifying the memory array layout, using a processor, to replace the first type of transistors with a second type of transistors different than the first type of transistors. The method further includes modifying the memory array layout, using the processor, to modify the charge pump based on an operating voltage of the second type of transistors. | 02-04-2016 |
20160055284 | Standard Cell Library and Methods of Using the Same - A standard cell library and a method of using the same may include information regarding a plurality of standard cells stored on a non-transitory computer-readable storage medium, wherein at least one of the plurality of standard cells includes a pin through which an input signal or an output signal of the at least one standard cell passes and including first and second regions perpendicular to a stack direction. When the via is disposed in the pin, the second region can provide a resistance value of the via smaller than that of the first region. The standard cell library may further include marker information corresponding to the second region. | 02-25-2016 |
20160055286 | METHOD OF DESIGNING LAYOUT OF INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING INTEGRATED CIRCUIT - A method of designing a layout of an integrated chip (IC) includes designing a first layout by place and route a plurality of standard cells that define the IC, and generating a second layout by modifying the first layout during a mask data preparation process related to the first layout, wherein the second layout is generated by connecting first and second patterns from among first layer patterns that correspond to a first layer of the first layout, such that the number of masks necessary for forming the first layer patterns is reduced. | 02-25-2016 |
20160092624 | FILLER INSERTION IN CIRCUIT LAYOUT - A method for filler insertions in a circuit layout having a cell row of standard cells and gaps between the standard cells is disclosed. First, a set of filler classes, each filler class having a set of filler cells, is classified that are configured to fill the gaps depending on a design requirement. Then, a filler insertion pattern based on a required ratio is identified such that horizontal and vertical density of the set of filler classes in the circuit layout are as per the required ratio and the cell row of the circuit layout has at least one filler cell from each of the set of filler classes. | 03-31-2016 |
20160092625 | INTEGRATED CIRCUIT INDUCTORS - An integrated circuit inductor design is provided in which the path crossings are designed such that the voltage differences between the adjacent paths in the loops are (in total) minimised. | 03-31-2016 |
20160110489 | METHODS, APPARATUS, AND SYSTEM FOR USING FILLER CELLS IN DESIGN OF INTEGRATED CIRCUIT DEVICES - At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device. A design for an integrated circuit device is received; The design comprises a first functional cell and a second functional cell. The first functional cell is placed on a circuit layout. A determination is made as to whether the first cell comprises a vertical boundary that is electrically floating. A filler cell is placed adjacent to the vertical boundary on the circuit layout in response to determining that the first cell comprises the vertical boundary that is electrically floating. The second functional cell is placed adjacent to the filler cell to form a contiguous active area on the circuit layout. | 04-21-2016 |
20160117431 | INTEGRATED CIRCUIT AND METHOD OF DESIGNING LAYOUT OF THE SAME - A method of designing a layout of an integrated circuit (IC) includes: preparing a standard cell library that stores first and second standard cells, each of the first and second standard cells including a plurality of conductive lines that extend in a first direction, placing the first and second standard cells to be adjacent to each other in a first boundary parallel to the plurality of conductive lines, and generating a decoupling capacitor by using at least one first conductive line of the plurality of conductive lines when a same voltage is applied to a first pattern adjacent to the first boundary in the first standard cell and a second pattern adjacent to the first boundary in the second standard cell, the at least one first conductive line being adjacent to the first boundary. | 04-28-2016 |
20160132628 | METHOD OF DESIGNING AN INTEGRATED CIRCUIT AND COMPUTER PROGRAM PRODUCT - A method of designing an integrated circuit is described. The integrated circuit comprises a plurality of circuit components, including one or more functional components and one or more tile shapes. A pcell instance may be defined to specify a functional component along with one or more tile shapes. The tile shapes are thus associated with the functional component. A netlist may be arranged to specify interconnections between the functional components of the integrated circuit as well as electrical interactions between the tile shapes and functional components. | 05-12-2016 |
20160140279 | METHOD AND DEVICE FOR DESIGNING ELECTRICAL CIRCUIT - A method may be used for designing an electrical circuit. The method may be implemented using a device that includes hardware. The method may include the following steps: generating a schematic model that represents the electrical circuit; placing representations of a set of elements of the electrical circuit for forming a pre-route layout model; and using the pre-route layout model and a set of layout-dependent effect parameter values to perform a pre-route simulation. The set of layout-dependent effect parameter values may pertain to the set of elements of the electrical circuit. | 05-19-2016 |
20160140282 | METHODS AND SYSTEMS FOR DETERMINING OBSTRUCTION SETBACKS IN A PHOTOVOLTAIC SYSTEM - A computer-implemented method for determining boundary offsets in a photovoltaic (PV) system based on shadow simulations is implemented by a design automation computer system in communication with a memory. The method includes identifying a set of obstructions wherein the set of obstructions includes a set of obstruction elevations and a set of obstruction offsets, simulating a set of shadow effects using a first coarse shadow algorithm based on the set of obstructions, refining the set of shadow effects using a second fine shadow algorithm based on the set of obstructions and the set of shadow effects, and defining a plurality of boundary of boundary offsets based on the refined set of shadow effects. | 05-19-2016 |
20160147925 | GENERATING PLACE AND ROUTE ABSTRACTS - Generating place and route abstracts, including: for each of a plurality of cells, generating a wire diagram; for each generated wire diagram, generating, in dependence upon a cell architecture layout, a cell architecture description; for each cell architecture description: generating, in dependence upon the wire diagrams and the cell architecture descriptions, a blockage map specifying locations where the placement of cells or routing structures is prohibited; and generating, in dependence upon the blockage maps and one or more design rules, a library exchange format (‘LEF’) abstract. | 05-26-2016 |
20160163685 | TUNABLE SCALING OF CURRENT GAIN IN BIPOLAR JUNCTION TRANSISTORS - Methods for designing and fabricating a bipolar junction transistor. A predetermined size for a device region of the bipolar junction transistor is determined based on a given current gain. A trench isolation layout is determined for a plurality of trench isolation regions to be formed in a substrate to surround the device region. The trench isolation regions are laterally spaced relative to each other in the trench isolation layout in order to set the predetermined size of the device region. An interconnect layout is determined that specifies one or more contacts coupled with a terminal of the bipolar junction transistor. The specification of the one or more contacts in the interconnect layout is unchanged by the determination of the trench isolation layout. | 06-09-2016 |
20160378900 | NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM, CIRCUIT DESIGN SUPPORT METHOD, AND INFORMATION PROCESSING DEVICE - A non-transitory computer-readable storage medium storing a circuit design support program that causes a computer to execute a process including generating topology data indicating wiring states of components in a circuit to be designed based on circuit data, the topology data including at least one coupling line between each pair of nodes including at least one first node and at least one second node, each of the at least one first node corresponding to each of the components and each of the at least one second node corresponding to each of at least one branch point in a wiring of the circuit when the wiring includes the at least one branch point, and displaying the generated topology data and an input field for receiving an input of restrictive data indicating restrictive requirements for each of the at least one coupling line between each of the nodes. | 12-29-2016 |
20170235865 | PLACING AND ROUTING METHOD FOR IMPLEMENTING BACK BIAS IN FDSOI | 08-17-2017 |