| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 716123000 | Iteration | 22 |
| 20110167400 | METHOD AND MECHANISM FOR EXTRACTION AND RECOGNITION OF POLYGONS IN AN IC DESIGN - Disclosed is an improved approach for organizing, analyzing, and operating upon polygon data which significantly reduces the amount of data required for processing while keeping elements non-interfacing with each other. According to one approach, clusters of elements are extracted which are then handled separately. In some approaches, a set of polygons forms a cluster if for any two polygons from the set of polygons there exists a sequence of polygons from the set such that the distance between any sequential polygons are less than or equal to a given threshold number. Rather than analyzing each and every polygon in the design, repetitive unique patterns are analyzed once, which are then replicated for all clusters which have the same repetitive pattern. | 07-07-2011 |
| 20110202897 | HIERARCHY-BASED ANALYTICAL PLACEMENT METHOD CAPABLE OF MACRO ROTATION WITHIN AN INTEGRATED CIRCUIT - A placer produces a global placement plan specifying positions of cell instances and orientations of macros within an integrated circuit (IC) by initially clusterizing cell instances and macros to form a pyramidal hierarchy of blocks. Then the placer iteratively repeats the declusterization and routability improvement process from the highest level to the lowest level of the hierarchy. An objective function is provided in Cartesian coordinate for representing the position of each movable instance and in polar coordinate for representing the orientation of a macro relative to its the center. For each movable instance and each rotatable macro, its position or orientation is determined by conjugate gradient method to minimize total wire length. Finally, the placer uses a look-ahead legalization technique to rotate rotatable macros to legal orientations and move cell instances to legal positions in the end of global placement. | 08-18-2011 |
| 20110219346 | Apparatus and Method for preventing Congestive Placement - A congestive placement preventing apparatus for modifying a circuit layout includes an analyzing module, a defining module and an extension module. The analyzing module performs a congestion analysis on the circuit layout to generate an analysis result. The defining module defines a congestion region and a share region adjacent to the congestion region on the circuit layout according to the analysis result. A density of electronic cells of the congestion region is higher than that of electronic cells of the share region. The extension module arranges a plurality of electronic cells in the congestion region to the congestion region and the share region, thereby reducing the density of electronic cells in the congestion region. | 09-08-2011 |
| 20120017192 | METHOD AND APPARATUS FOR LOW POWER SEMICONDUCTOR CHIP LAYOUT AND LOW POWER SEMICONDUCTOR CHIP - A layout system is described comprising a layout unit configured to layout cells in a mask design for a semiconductor chip based on library cells for a specified process node; a non-critical path determination unit configured to determine a non-critical path in the semiconductor chip; a cell determination unit configured to determine a group of cells in the mask design that form a part of the non-critical path and determine the corresponding library cell for at least one of the group of cells; a library cell modifying unit configured to modify one or more corresponding library cells to form a corresponding modified library cell; and a cell replacement unit configured to replace a library cell in the group of cells in the mask design that form a part of the non-critical path with the corresponding modified library cell. | 01-19-2012 |
| 20120159417 | TASK-BASED MULTI-PROCESS DESIGN SYNTHESIS - A task-based multi-process design synthesis methodology relies on a plurality of child processes to assist a parent process in performing optimizations on an integrated circuit design. Objects from an integrated circuit design are grouped into subsets and assigned to child processes, with each child process performing a transform on each of the objects in the subset assigned to that child process and determining which of the objects in the subset are candidate objects for which performance of the transform has been successful. The child processes then notify the parent process of those objects that qualify as candidate objects, so that the parent process only has to perform the transform on the candidate objects, thereby relieving the parent process from the overhead associated with performing the transform on non-candidate objects for which the transform has been determined by the child processes as not being successful. | 06-21-2012 |
| 20130061195 | Methods and Apparatuses for Circuit Design and Optimization - In one aspect of an embodiment, a method implemented on a data processing system for circuit design, includes identifying one or more first portions of a design of a circuit, each of the one or more first portions containing a set of elements interconnected via timing nets and generating weights for the timing critical nets, the weights being generated after identifying the one or more first portions and executing a placer algorithm which uses the weights for the timing critical nets to place the set of elements on a representation of the design. In this method, in one embodiment, the weights for the timing critical nets can be generated to have values that differ from weights for non-critical nets. The placer algorithm can be any one of a variety of conventional placer algorithms such as a weighted wire length driven placer algorithm or a force directed timing driven placer algorithm or a min-cut placer algorithm. | 03-07-2013 |
| 20130097573 | ALIGNMENT NET INSERTION FOR STRAIGHTENING THE DATAPATH IN A FORCE-DIRECTED PLACER - An automated method for aligning a critical datapath in an integrated circuit design inserts an artificial alignment net in the netlist which interconnects all cells in the bit stack of the datapath. The cells are placed using a wirelength optimization which assigns weights to wire sections based on the alignment direction. The rate of change of the alignment weighting value can vary during different stages of global placement. The invention is particularly suited for a force-directed placer which uses a linear system solver to obtain a globally optimum solution for placement of the cells having some overlap among the cells, and thereafter spreads the cells to reduce the overlap. Pseudo nets are also inserted which interconnect a cell and an expected location of the cell after spreading for that iteration. | 04-18-2013 |
| 20130097574 | METHOD OF ANALYTICAL PLACEMENT WITH WEIGHTED-AVERAGE WIRELENGTH MODEL - A computer-implemented method to generate a placement for a plurality of instances for an integrated circuit (IC) by utilizing a novel weighted-average (WA) wirelength model, which outperforms a well-known log-sum-exp wirelength model, to approximate the total wirelength. The placement is determined by performing an optimization process on an objective function which includes a wirelength function approximated by the WA wirelength model. The method can be extended to generate a placement for a plurality of instances for a three-dimensional (3D) integrated circuit (IC) which considers the sizes of through-silicon vias (TSVs) and the physical positions for TSV insertion. With the physical positions of TSVs determined during placement, 3D routing can easily be accomplished with better routed wirelength, TSV counts, and total silicon area. | 04-18-2013 |
| 20130254732 | Enforcement of Semiconductor Structure Regularity for Localized Transistors and Interconnect - A global placement grating (GPG) is defined for a chip level to include a set of parallel and evenly spaced virtual lines. At least one virtual line of the GPG is positioned to intersect each contact that interfaces with the chip level. A number of subgratings are defined. Each subgrating is a set of equally spaced virtual lines of the GPG that supports a common layout shape run length thereon. The layout for the chip level is partitioned into subgrating regions. Each subgrating region has any one of the defined subgratings allocated thereto. Layout shapes placed within a given subgrating region in the chip level are placed in accordance with the subgrating allocated to the given subgrating region. Non-standard layout shape spacings at subgrating region boundaries can be mitigated by layout shape stretching, layout shape insertion, and/or subresolution shape insertion, or can be allowed to exist in the final layout. | 09-26-2013 |
| 20130290921 | SWAPPING PORTS TO CHANGE THE TIMING WINDOW OVERLAP OF ADJACENT NETS - In an embodiment, a list of ports and a physical location of the ports specified in a circuit design is created. Physically adjacent port pairs are determined within the list of the ports that are physically adjacent. For each respective physically adjacent port pair, the following elements are performed: calculating a timing window overlap for a current port and a next port in the respective physically adjacent port pair, computing a timing window overlap for the current port and each following port that is within a predetermined physical distance, and if the timing window overlap between the respective physically adjacent port pair is not smaller than the timing window overlap for the current port and each following port, swapping a physical location of the adjacent port with a physical location of the following port that has a smallest timing window overlap with the current port. | 10-31-2013 |
| 20140007036 | SEPARATE REFINEMENT OF LOCAL WIRELENGTH AND LOCAL MODULE DENSITY IN INTERMEDIATE PLACEMENT OF AN INTEGRATED CIRCUIT DESIGN | 01-02-2014 |
| 20140040848 | Controllable Turn-Around Time For Post Tape-Out Flow - A typical post-out flow data path at the IC Fabrication has following major components of software based processing—Boolean operations before the application of resolution enhancement techniques (RET) and optical proximity correctin (OPC), the RET and OPC step [etch retargeting, sub-resolution assist feature insertion (SRAF) and OPC], post-OPCRET Boolean operations and sometimes in the same flow simulation based verification. There are two objectives that an IC Fabrication tapeout flow manager wants to achieve with the flow—predictable completion time and fastest turn-around time (TAT). At times they may be competing. An alternative method of providing target turnaround time and managing the priority of jobs while not doing any upfront resource modeling and resource planning is disclosed. The methodology systematically either meets the turnaround time need and potentially lets the user know if it will not as soon as possible. | 02-06-2014 |
| 20140109034 | Timing Closure Methodology Including Placement with Initial Delay Values - An automated method for designing an integrated circuit layout using a computer based upon an electronic circuit description and based upon cells which are selected from a cell library, each of the cells having an associated area, comprising the steps of: (a) placing each of the cells in the integrated circuit layout so that the cells can be coupled together by wires to form a circuit path having an associated predetermined delay constraint wherein the cells are coupled together based upon the electronic circuit description input to the computer; (b) connecting the cells together with the wires to form the circuit path; and (c) adjusting an area of at least one of the cells to satisfy the associated predetermined delay constraint of the circuit path. | 04-17-2014 |
| 20140149958 | 3D FLOORPLANNING USING 2D AND 3D BLOCKS - The disclosed embodiments are directed to systems and method for floorplanning an integrated circuit design using a mix of 2D and 3D blocks that provide a significant improvement over existing 3D design methodologies. The disclosed embodiments provide better floorplan solutions that further minimize wirelength and improve the overall power/performance envelope of the designs. The disclosed methodology may be used to construct new 3D IP blocks to be used in designs that are built using monolithic 3D integration technology. | 05-29-2014 |
| 20140181776 | WHAT-IF PARTITIONING AND TIMING - Methods and apparatuses are described for facilitating a user to explore and evaluate different options during floorplanning. Some embodiments display a graphical representation of a circuit design floorplan, wherein the graphical representation includes a set of blocks and a set of flylines between blocks, wherein each block corresponds to a portion of the circuit design, and wherein each flyline corresponds to one or more relationships between two blocks. Additionally, a set of metrics associated with one or more blocks or one or more flylines can be displayed. Next, in response to receiving a modification to one or more blocks in the graphical representation, the embodiments can update the set of metrics without performing expensive netlist modification, placement, routing, and/or propagation of timing information through multiple levels of logic, and then display the updated set of metrics. | 06-26-2014 |
| 20140282344 | LAYOUT BOUNDARY METHOD - Some embodiments of the present disclosure relates to a method and apparatus to achieve a layout that is compatible with a multiple-patterning process. Two or more unit cells are constructed with layouts which satisfy the properties of the multiple-patterning process, and are each decomposed into two or more colors to support the multiple-patterning process. An active layout feature is merged with a dummy wire at a shared boundary between two unit cells. In the event of a short between two active layout features at the shared boundary, an automatic post-layout method can rearrange the layout features in a vicinity of the shared boundary to separate the active layout features to achieve cell functionality while satisfying the multiple-patterning properties. | 09-18-2014 |
| 20150143323 | Generating Guiding Patterns For Directed Self-Assembly - Aspects of the invention relate to techniques of generating guiding patterns for via-type feature groups. A guiding pattern may be constructed for a via-type feature group that comprises two or more via-type features in a layout design. A backbone structure may then be determined for the guiding pattern. Based on the backbone structure and a self-assembly model, simulated locations of the two or more via-type features are computed. The simulated locations are compared with targeted locations. If the simulated locations do not match the targeted locations based on a predetermined criterion, the simulated locations adjusted to derive modified locations. Using the modified locations, the above operations may be repeated until the simulated locations match the targeted location based on a predetermined criterion or for a predetermined number of times. | 05-21-2015 |
| 20150339426 | NEGATIVE PLANE USAGE WITH A VIRTUAL HIERARCHICAL LAYER - A virtual hierarchical layer (VHL) is constructed for a semiconductor design in order to reduce the computational requirement of design rules checking (DRC) and design rules for manufacture (DRM) procedures. In order to form the VHL, a negative plane is created. A cell and multiple instances of the cell are then identified in the semiconductor design and polygons which overlap the cell and its instances are determined. The polygons are pushed into the negative plane to create holes in the plane. Shapes overlapping other instances of the cell which fall onto holes in the solid virtual cell plane are ignored. The resulting holed solid virtual cell plane can then be inverted to create a VHL to be used for design simulation and verification. | 11-26-2015 |
| 20160071260 | Enhanced Patterned Wafer Geometry Measurements Based Design Improvements for Optimal Integrated Chip Fabrication Performance - Methods and systems enabling ultra-high resolution topography measurements of patterned wafers are disclosed. Measurements obtained utilizing the ultra-high resolution metrology may be utilized to improve wafer metrology measurement accuracies. Additionally, measurements obtained utilizing the ultra-high resolution metrology may also be utilized to provide feedback and/or calibration control to improve fabrication and design of wafers. | 03-10-2016 |
| 20160132624 | MICROELECTROMECHANICAL SYSTEM LAYOUT USING GENOTYPE PERFORMANCE SIMULATION - Methods for producing layout data for devices are described. One method includes using a genetic algorithm to determine a structure of a thermally.operated actuator. Reference system performance characteristics are received and structure genotypes produced, each structure genotype including geometric and thermal properties of each of a plurality of links in the microelectromechanical system, the geometric and thermal properties selected randomly. Respective system performance characteristics of the genotypes are simulated and respective fitness ratings determined with respect to the reference. A second population of structure genotypes is produced using the first population and the determined fitness ratings. The steps are iterated until one of the structure genotypes satisfies selected termination criteria. Layout data corresponding to the geometric properties in the one of the structure genotypes are automatically produced using the controller. | 05-12-2016 |
| 20160162620 | RACETRACK LAYOUT FOR RADIO FREQUENCY SHIELDING - Aspects of the present disclosure relate to determining a layout of a racetrack that forms part of an RF isolation structure of a packaged module and the resulting RF isolation structures. The racetrack layout can be determined based on identifying low radiating areas of a module and/or areas of a module that are less sensitive to external radiation. The racetrack can be disposed below a surface of a module on which a radio frequency component is disposed. The racetrack and a conductive layer over the radio frequency component can form part of a radio frequency isolation structure around the RF component. | 06-09-2016 |
| 20160203254 | METHODS FOR REDUCING CONGESTION REGION IN LAYOUT AREA OF IC | 07-14-2016 |
