| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 716121000 | For PLDs | 7 |
| 20100299648 | MODULAR ARRAY DEFINED BY STANDARD CELL LOGIC - Disclosed herein is an ASIC having a base array of function blocks. Each function block includes a plurality of primitive cells. Each primitive cell is defined by a component from a standard cell library. The base array is prefabricated for use later with a custom circuit design. | 11-25-2010 |
| 20120216165 | REASSEMBLING SCATTERED LOGIC BLOCKS IN INTEGRATED CIRCUITS - Techniques for reassembling scattered logic blocks in an integrated circuit (IC) are provided. The techniques include identifying a virtual memory block to be reassembled in an IC design. The virtual memory block is formed by a plurality of memory blocks that are connected by a plurality of logic circuitry. The plurality of memory blocks and the plurality logic circuitry that connect the memory blocks within the virtual memory block are identified. The identified logic circuitry and memory blocks are removed from the virtual memory block. The virtual memory block is replaced with a custom memory block that is functionally comparable to the plurality of connected memory blocks in the virtual memory block. | 08-23-2012 |
| 20130191803 | METHOD AND APPARATUS FOR CAMOUFLAGING A STANDARD CELL BASED INTEGRATED CIRCUIT - A method and apparatus for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic is disclosed. The method adds functionally inert elements to the logical description or provides alternative definitions of standard logic cells to make it difficult for reverse engineering programs to be used to discover the circuit's function. | 07-25-2013 |
| 20140130003 | STANDARD CELL PLACEMENT METHOD TO EXERCISE PLACEMENT PERMUTATIONS OF STANDARD CELL LIBRARIES - A method for validating standard cells stored in a standard cell library and for use in design of an integrated circuit device is described. Each standard cell of the standard cells is iteratively placed adjacent to each side and corner of itself and each other standard cell of the standard cells to produce an interim test layout comprising a first plurality of cell pair permutations. The cell pair permutations are reduced by identifying at least one of: illegal or redundant left-right and top-bottom boundaries, and removing any cell pair permutations using the identified boundaries to generate a final test layout comprising a second plurality of cell pair permutations. | 05-08-2014 |
| 20140245247 | Integrated Circuit Designed and Manufactured Using Diagonal Minimum-Width Patterns - An integrated circuit comprising a plurality of standard cell circuit elements is disclosed, wherein for at least one layer of the integrated circuit, a majority of minimum-width patterns are in a preferred diagonal orientation. | 08-28-2014 |
| 20150143320 | METHOD FOR PRODUCING MROM MEMORY BASED ON OTP MEMORY - A method of producing a MROM memory based on an OTP memory is provided. The method includes: removing the floating gate of the second PMOS transistor of the OTP memory cell for storing data “0” in the OTP memory map, such that the OTP memory cell being transferred to a MROM memory cell for storing data “0”, and retaining the original structure of the OTP memory cell for storing data “1” in the OTP memory map, such that the original structure being used as a MROM memory cell for storing data “1”, thus forming a MROM memory map; and producing a MROM memory according to the MROM memory map. According to the present invention, the OTP memory map which is debugged and has determined data can be changed into the MROM memory map, and the OTP process can be transferred into the MROM process by adjusting only one mask during the producing process. The present invention greatly saves the time and cost of the device programming and testing, thus simplifying the process and saving the cost, increasing the profit. | 05-21-2015 |
| 20150143321 | Methods for Cell Phasing and Placement in Dynamic Array Architecture and Implementation of the Same - A semiconductor chip is defined to include a logic block area having a first chip level in which layout features are placed according to a first virtual grate, and a second chip level in which layout features are placed according to a second virtual grate. A rational spatial relationship exists between the first and second virtual grates. A number of cells are placed within the logic block area. Each of the number of cells is defined according to an appropriate one of a number of cell phases. The appropriate one of the number of cell phases causes layout features in the first and second chip levels of a given placed cell to be aligned with the first and second virtual grates as positioned within the given placed cell. | 05-21-2015 |
