Class / Patent application number | Description | Number of patent applications / Date published |
716124000 | With partitioning | 23 |
20100306729 | SYSTEM AND METHOD FOR GENERATING FLAT LAYOUT - The present invention provides a method for generating flat layout design view that comprises importing port definitions of a first hierarchical block of digital instances from a source as a schematic symbol, importing port definitions of digital instances within the first hierarchical block from the source, instantiating the schematic symbol as a hierarchical layout instance in the flat layout, binding the hierarchical layout instance to the schematic symbol, and embedding digital layout block instances within the design layout by replacing the digital instances of a digital layout block with digital layout instances of a top layout module of the design layout. | 12-02-2010 |
20110004859 | Adjustable Dummy Fill - A method of placing a dummy fill layer on a substrate is disclosed (FIG. | 01-06-2011 |
20110126166 | Apparatus for Preventing Congestive Placement and Associated Method - A congestive placement preventing apparatus applied to a circuit layout including electrical devices is provided. The congestive placement preventing apparatus includes an analyzing module, a reserving module and a placing module. The analyzing module performs a routing congestion analysis on the circuit layout to generate an analysis result of the circuit layout. The reserving module correspondingly disposes a plurality of blockages in the circuit layout according to the analysis result, so that a first space with the blockages and a second space are formed in the circuit layout. After the placing module places the electrical devices in the second space, the placing module removes the blockages from the first space, and redistributes the electrical devices in the first space and the second space according to a redistribution rule. | 05-26-2011 |
20110289468 | Circuit Macro Placement Using Macro Aspect Ratio Based on Ports - Fixed outline shaped and modifiable outline shaped random logic macros of an electronic circuit design are manipulated by modifying an outline of a modifiable outline shape macro based on criteria consisting of any one of a macro port weight value, a macro port ordering; a macro rapport constraint or a macro logic depth and placing resulting macros at locations on an integrated circuit (chip). | 11-24-2011 |
20120192138 | GRAPH PARTITIONING WITH NATURAL CUTS - Graph partitioning techniques are based on the notion of natural cuts. A filtering phase performs a series of minimum cut computations to identify and contract dense regions of the graph. This reduces the graph size significantly, but preserves its general structure. An assembly phase uses a combination of greedy and local search heuristics to assemble the final partition. The techniques may be used on road networks, which have an abundance of natural cuts (such as bridges, mountain passes, and ferries). | 07-26-2012 |
20120254818 | METHODS, SYSTEMS, AND ARTICLES OF MANUFACTURE FOR IMPLEMENTING FULL-CHIP OPTIMIZATION WITH REDUCED PHYSICAL DESIGN DATA - Disclosed are methods, systems, and articles of manufacture for implementing full-chip optimization across block boundaries with reduced physical design data. Some embodiments create a partial netlist and reduced physical data by identifying and including side instance(s) or side path(s) in the reduced physical data and then include or exclude side instance(s) or side path(s) in the reduced physical data. The method or the system may then perform full-chip optimization across individual block boundaries with the reduced physical data. Some embodiments further merge the post-optimization data back into the original data while reducing logic and physical disturbance to existing designs. Some embodiments anchor driver instance(s) that correspond to excluded side instance(s) or side path(s) to ensure LEC cleanliness and may further trim timing graph(s) based at least on the partial netlist. Some embodiments account for parasitics without static parasitic files. Various embodiments apply to both hierarchical and non-hierarchical designs. | 10-04-2012 |
20120311518 | METHOD, A SYSTEM AND A PROGRAM STORAGE DEVICE FOR MODELING THE RESISTANCE OF A MULTI-CONTACTED DIFFUSION REGION - Disclosed are embodiments of a method and program storage device for modeling the resistance of a multi-contacted diffusion region of a semiconductor device, such as a metal oxide semiconductor field effect transistor (MOSFET), a metal oxide semiconductor capacitor (MOS capacitor), a bipolar transistor, etc. The embodiments provide a formula for determining the total parasitic resistance (R | 12-06-2012 |
20130080989 | SPARE LATCH DISTRIBUTION - Aspects of the invention provide for spare latch distribution for an integrated circuit design. In one embodiment, aspects of the invention include a method of generating a computer system for spare latch distribution in an integration circuit design, the method including: providing a computer system operable to: receive design data for the integrated circuit design, the design data including a plurality of latches; segment the integrated circuit design into a plurality of equal sections; determine a latch density within each of the equal sections; and determine a number of spare latches, based on the latch density, for each of the equal sections. Further, it is understood that the above are performed for each clock domain within the integrated circuit design. | 03-28-2013 |
20130167100 | METHODS FOR INTEGRATED CIRCUIT C4 BALL PLACEMENT - Methods and systems for improving the reliability of C4 solder ball contacts performed at the design stage to reduce the incidence of thermally-induced failures, including those due to electromigration and thermal cycling. | 06-27-2013 |
20140123093 | METHODS AND SYSTEMS CONFIGURED TO COMPUTE A GUARD ZONE OF A THREE-DIMENSIONAL OBJECT - Techniques generally disclosed herein relate to computation of a guard zone of a three-dimensional object. In some examples, guard zones may be computed by identifying intersection lines that couple adjacent planes of an object, and categorizing an external angle at an intersection line between adjacent planes as concave or convex. In some embodiments, for convex angles, a cylindrical surface can be determined that is located about an outside surface of the object and centered along the intersection line between the adjacent planes. In some embodiments, for concave angles, the external angle can be bisected with a bisection plane. A guard zone may be formed by one or more of (i) providing a guard zone plane parallel to the object that is a tangent to a given cylindrical surface, (ii) providing a guard zone plane parallel to the object that intersects a given bisection plane, and/or (iii) coupling adjacent guard zone planes. | 05-01-2014 |
20140215425 | ADJUSTABLE DUMMY FILL - A method of placing a dummy fill layer on a substrate is disclosed (FIG. | 07-31-2014 |
20140250416 | CONTENT ADDRESSABLE MEMORY - A method of designing a content-addressable memory (CAM) includes associating CAM cells with a summary circuit. The summary circuit includes a first level of logic gates and a second level of logic gates. The first level of logic gates have inputs each configured to receive an output of a corresponding one of the plurality of CAM cell. The second level of logic gates have inputs each configured to receive an output of a corresponding one of the first level of logic gates. Logic gates in at least one of the first level of logic gates or the second level of logic gates are selected to have an odd number of input pins so that an input pin and an output pin share a layout sub-slot. | 09-04-2014 |
20140258963 | PLACEMENT AND ROUTING ON A CIRCUIT - Methods and apparatuses to place and route cells on integrated circuit chips along paths is described. In one embodiment, the method to layout an integrated circuit, the method comprises routing a wire to connect a first cell of the integrated circuit and a second cell of the integrated circuit, and placing a third cell of the integrated circuit after said routing the wire to connect the first cell and the second cell. | 09-11-2014 |
20140359549 | Generating A Convergent Circuit Design From A Functional Description Using Entities Having Access To The Functional Description And To Physical Design Information - A method of designing a circuit is described. In an embodiment, a physical design implementation for the circuit is created using a plurality of entities. These entities are named “genomes”. Each entity includes a portion of a functional description of the circuit that has been synthesized into a gate-level implementation. An entity is selected to facilitate the physical design implementation meeting a plurality of design constraints. Several steps (e.g., beginning with selection of an entity) of this method are repeated several times to meet the design constraints. As a consequence, the physical design implementation provides more accurate information for use in a final physical design implementation. Moreover, the physical design implementation can be created faster than prior techniques while still allowing a global view of the physical design implementation in meeting design constraints. | 12-04-2014 |
20150379182 | Method and System for the Modular Design and Layout of Integrated Circuits - An integrated circuit (IC) and fabrication method thereof is provided that include the steps of specifying a plurality of required tile modules suitable for a particular end application, each of the modular tiles being configured to perform a predetermined function and constructed to have approximately the same length and width dimensions. The modular tiles are used to form the IC in a standard IC fabrication process. In many implementations, physical layout of the IC does not include the step of routing. Capabilities also include configuring the modular tiles to have programmable performance parameters and configuring the modular tiles to cooperate usefully with one another based on a programmable parameter. | 12-31-2015 |
20160004807 | METHOD OF MAKING STACKED CHIP LAYOUT - A method of making a stacked chip layout includes placing a first active circuit block over a central processing chip having a first area, the first active circuit block having a second area less than the first area. The method further includes placing a second active circuit block over the first active circuit block, the second active circuit block having a third area less than the first area, wherein the second active circuit block partially overlaps the first active circuit block and exposes a portion of the first active circuit block. The method further includes placing a third active circuit block over the second active circuit block wherein the third active circuit block partially overlaps at least one of the first active circuit block or the second active circuit block, and the third active circuit block exposes at least a portion of the first and second active circuit blocks. | 01-07-2016 |
20160019329 | INTERLACED BI-SENSOR SUPER-RESOLUTION ENHANCEMENT - Interlaced bi-sensor super-resolution enhancement techniques and a resultant scalable pixel array suitable for a mega-pixel design are disclosed. The method includes interlacing a first array of pixels of a first size with a second array of pixels of a second size. The interlacing of the first array of pixels with the second array of pixels avoids crossing two or more photosensitive areas of the first array of pixels and the second array of pixels. | 01-21-2016 |
20160042110 | HIGH QUALITY PHYSICAL DESIGN FOR MONOLITHIC THREE-DIMENSIONAL INTEGRATED CIRCUITS (3D IC) USING TWO-DIMENSIONAL INTEGRATED CIRCUIT (2D IC) DESIGN TOOLS - A method of designing a multi-tier three-dimensional integrated circuit (3D IC) is provided that allows the use of two-dimensional integrated circuit (2D IC) design tools. When a 2D IC design tool is used, a macro for each of the tiers indicating areas available and unavailable for placement of circuit elements in each tier is created, and the macros are superimposed on one another. Circuit elements to be implemented in the 3D IC, such as logic cells and interconnects, are shrunk and then placed and repopulated on the superimposed macro. The repopulated circuit elements on the superimposed macro are then partitioned into tiers. Monolithic inter-tier via (MIV) placement and tier-to-tier routing are designed to provide electrical connections between circuit elements in different tiers. Power, performance and area (PPA) optimization may also be performed to optimize the 3D IC layout. | 02-11-2016 |
20160048625 | Using a Barycenter Compact Model for a Circuit Network - Any primitive cells or blocks can be represented physically by a Barycenter compact model (or Barycenter model), and any black box model can also be physically represented by a Barycenter compact model physically. A hierarchical boundary condition between blocks is formulated by the Barycenter compact model. Hierarchical boundary condition problems between blocks can be limited within two levels only if using the Barycenter compact model. | 02-18-2016 |
20160085898 | AUTOMATED LAYOUT FOR INTEGRATED CIRCUITS WITH NONSTANDARD CELLS - Methods, systems, and devices are disclosed for automatically generating physical layouts of integrated circuits. A circuit is partitioned into one or more cells based on a circuit description. The method further checks availability of a layout of a cell for all the cells generated during the partition step. If a layout of a cell is not available, the method generates a layout of the cell by an automatic tool, and packages the generated layout in a form of a standard cell compatible with a standard cell placement and routing tool. Afterwards, the generated layout may be exported to the standard cell placement and routing tool. Finally, the standard cell placement and routing tool may merge individual layouts of the one or more cells of the circuit to generate a layout for the circuit. | 03-24-2016 |
20160125119 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING DIFFERENTIAL AMPLIFIER AND METHOD OF ARRANGING THE SAME - A semiconductor integrated circuit comprises: a transistor region having a center line; a first block arranged in one side of the center line of the transistor region, and comprising a plurality of first and second groups each having a plurality of first and second segment transistors constituting first and second transistors of a differential amplifier; and a second block arranged in the other side of the center line, and having an arrangement corresponding to the arrangement of the first and second groups of the first block. | 05-05-2016 |
20160154920 | DESIGN METHOD AND DESIGN APPARATUS | 06-02-2016 |
20160171145 | METHODS FOR MINIMIZING LAYOUT AREA OF IC | 06-16-2016 |