Entries |
Document | Title | Date |
20100318955 | Statistical Integrated Circuit Package Modeling For Analysis At The Early Design Age - In designing an integrated circuit on a die having a set of die bumps, a method to generate a set of lumped circuit parameter values associated with the set of die bumps, based upon distances between the set of die bumps and the center of the die, the method also based upon a sample-data distribution function of a die bump distance variable and a sample-data distribution function of a lumped circuit parameter variable. Other embodiments are described and claimed. | 12-16-2010 |
20100325599 | VISUALIZATION OF TRADEOFFS BETWEEN CIRCUIT DESIGNS - A system may include a database configured to store information including characteristics of a plurality of components. The system may further include a server in communication with the database and configured to receive design requirements indicative of desired power supply designs; query the database for components that satisfy the design requirements; determine a plurality of power supply designs in accordance with the components and the design parameters; determine key parameters of at least a subset of the determined power supply designs; and rank the power supply designs. | 12-23-2010 |
20110004858 | METHOD FOR CONCURRENT MIGRATION AND DECOMPOSITION OF INTEGRATED CIRCUIT LAYOUT - A method for concurrent migration and decomposition of an integrated circuit layout applicable to double patterning lithography techniques is provided. The method includes cutting a sub-pattern of an initial pattern to configure a potentially conflicting pattern having separate or cutting sections; removing odd cycles in the potential conflicting pattern so as to cut the separate or cutting sections; configuring the double patterning constraint based upon corresponding location relations between each and adjacent cut sections; and assigning a first color layer or a second color layer to the cut sections according to the double patterning constraint to obtain a final layout pattern. Therefore, disadvantageous factors and patterning conflicts caused by separate processes as encountered in the prior art are avoided. | 01-06-2011 |
20110023000 | GENERATING INTEGRATED CIRCUIT FLOORPLAN LAYOUTS - A method of generating a floorplan layout of an integrated circuit (IC) that is amenable to implementation in a computer-aided design tool. The method is capable of performing placement and routing processing for the IC while requiring very little information about the specific circuitry used in various functional blocks of the IC. For example, at the time of the placement and routing processing, one or more functional blocks of the IC can be specified as empty functional blocks and/or functional blocks that are only partially rendered in gates. | 01-27-2011 |
20110023001 | DYNAMIC RULE CHECKING IN ELECTRONIC DESIGN AUTOMATION - Some embodiments provide a system that provides design rule checking in an electronic design automation (EDA) application. During operation, the system detects a change to a schematic by a user of the EDA application. Next, the system automatically applies a set of dynamic design rules to the schematic upon detecting the change. Finally, the system notifies the user of a rule violation if the schematic violates one or more of the dynamic design rules. The system allows the user to specify which dynamic rules to apply when the user is modifying the schematic. | 01-27-2011 |
20110047523 | DIFFERENTIAL VOLTAGE DEFECTIVITY MONITORING METHOD - A method uses a differential voltage response to identify fabrication process defects that would result if an IC design is fabricated (without re-designing to correct such defects). The method uses two stacks, whose respective outputs may be compared by a comparator, and comparator's output used to determine defectivity. In some embodiments, each stack includes a first-type device (e.g. a p-channel device) and at least two second-type devices (e.g. n-channel devices). The first-type device is used as a current source or as a select switch (depending on the mode of operation of the differential voltage defectivity monitoring circuit). One second-type device may be used as a select switch and for back-bias control, while another second-type device may be used as a blocking switch and/or a select switch. The method may use an addressable array of multiple test structures that have digitally multiplexed control lines, in some embodiments. | 02-24-2011 |
20110055783 | CODE TILING SCHEME FOR DEEP-SUBMICRON ROM COMPILERS - A method includes receiving instructions for designing a ROM array, generating netlists for the ROM array, generating a data file representing a physical layout of the ROM array on a semiconductor wafer, and storing the data file in a computer readable storage medium. The instructions for the ROM array define a layout for a first unit including a first bit cell coupled to a first word line, a bus that may be coupled and uncoupled to a first power supply having a first voltage level, a layout for a second unit coupled to a second word line, and a layout for a third unit having an isolation device and being configured to share a bit line contact with the second unit or another third unit. The layout for the second unit is configured to be arranged at an edge of the ROM array and includes a dummy device. | 03-03-2011 |
20110061037 | Generating Net Routing Constraints For Place And Route - A method of generating net routing constraints for nets of an IC design includes generating a file with hashes organized by nets. Each hash has attributes of a net, e.g. net name, length, fanout, total actual route (AR) resistance, a corresponding virtual route (VR) resistance, and a number of vias. A wire only AR resistance for each net can be calculated. Wire scaling factors can be calculated using the wire only AR resistances and their corresponding VR resistances. Wire scaling factors can be binned by one or more net characteristics. An average wire scaling factor can be calculated for each bin. Code used by a place and route tool can then be generated, wherein the code applies the average wire scaling factors to nets of the design to improve pre-route and post-route correlation. | 03-10-2011 |
20110066992 | Hardware Description Language (HDL) Generation Systems and Methods For Custom Circuit Boards - A system comprises an input and a hardware description language (HDL) module. The input receives design specifications for a custom circuit board. The design specifications are selected from predetermined design options for custom circuit boards. The hardware description language (HDL) module generates HDL corresponding to the design specifications and outputs the HDL to a circuit board producer. | 03-17-2011 |
20110066993 | PRINTED CIRCUIT BOARD LAYOUT SYSTEM AND METHOD THEREOF - A method for merging polygons of a printed circuit board layout system is provided. The system generates PCB files according to the input wiring diagram, and generates polygons and records the profile attributes of each of the generated polygons. The method includes obtaining the profile attributes in response to user input. Then storing the obtained profile attributes and selecting two profile attributes. Then determining whether the polygons are overlapping and recording a new file attribute describing the shape of a new polygon of the two polygons combined shape excluding the lines indicating the overlapping portions of the two polygons. Finally, updating the opened PCB file with the new profile attribute if the polygons are overlapping. A related system is also provided. | 03-17-2011 |
20110066994 | SYSTEM AND METHOD OF ASSISTING CIRCUIT DESIGN - A circuit design assist system that receives a user instruction for registering an interface section of at least two circuits as a template, and generates a plurality of circuit patterns of the interface section, each pattern having a different combination of electrical properties of at least one device included in the interface section for evaluation. When an evaluation result indicates that the interface section operates normally for each of the circuit patterns, the circuit design assist system registers the interface section as the template. | 03-17-2011 |
20110072407 | Automatic Positioning of Gate Array Circuits in an Integrated Circuit Design - An automated method and apparatus for positioning gate array circuits in an integrated circuit design. An initial integrated circuit design includes logic cells and gate array fill circuits positioned thereon. The gate array fill circuits are positioned in available space between the adjacent logic cells so as to fill the available space with the maximum gate array fill circuits. A gate array logic element to be positioned in the integrated circuit design, such as may be required by an engineering change to the circuit design, is automatically positioned between adjacent logic cells so as to allow for full utilization of any space remaining between the adjacent logic cells by gate array fill circuits. | 03-24-2011 |
20110078647 | Design Method for Circuit Layout and Rapid Thermal Annealing Method for Semiconductor Apparatus - The present invention provides a design method for circuit layout and a rapid thermal annealing method for a semiconductor apparatus. The design method includes: establishing a ternary relationship among a device electric parameter, an annealing temperature and a distributing density of STI patterns, and establishing a binary relationship between the device electric parameter and a gate pattern length; obtaining a difference between distributing densities of STI patterns in a particular region and in a target region; obtaining an electric parameter difference corresponding to the difference between the distributing densities of STI patterns according to the ternary relationship; obtaining a gate pattern length difference corresponding to the electric parameter difference according to the binary relationship; and adjusting a gate pattern length in the particular region according to the gate pattern length difference. As compared with a traditional design method, the design method for circuit layout provided by the invention does not need adding dummy structure patterns, thereby avoiding negative influence to normal electric performance of the semiconductor apparatus by adding dummy structures. | 03-31-2011 |
20110107286 | METHOD AND APPARATUS FOR LEGALIZING A PORTION OF A CIRCUIT LAYOUT - A layout-legalizing system modifies a portion of a circuit layout that is selected by a user to generate a modified portion that satisfies a set of technology constraints and a set of design constraints. The system receives as input the set of technology constraints which a semiconductor manufacturing foundry requires the circuit layout to satisfy for manufacturability purposes. The system also receives a set of design constraints from the user which restricts how objects in the portion of the circuit layout can be modified to satisfy the set of technology constraints. The system can further receive a selection input from the user which identifies the portion of the circuit layout which is to be legalized. The system then modifies the identified portion of the circuit layout to obtain a modified portion which satisfies the set of design constraints and at least a subset of the set of technology constraints. | 05-05-2011 |
20110107287 | Methods of deriving switch networks - A method of determining the lowest possible number of serial switches in a pull-up plane or a pull-down plane of a network implementing a logic function. The same method may be used in any multi-value function. Also, the method may be used in generating switch networks to be implemented as standard cells implementations of combinational logic cells. The minimum number of switches can also be used as a criterion for technology mapping devoted to automatic cell generation. The method is based on the use of a covering table to derive a sum of products where individual cubes have a minimum literal count. | 05-05-2011 |
20110107288 | Methods of deriving switch networks - A method of determining the lowest possible number of serial switches in a pull-up plane or a pull-down plane of a network implementing a logic function. The same method may be used in any multi-value function. Also, the method may be used in generating switch networks to be implemented as standard cells implementations of combinational logic cells. The minimum number of switches can also be used as a criterion for technology mapping devoted to automatic cell generation. The method is based on the use of a covering table to derive a sum of products where individual cubes have a minimum literal count. | 05-05-2011 |
20110119647 | PRINTED CIRCUIT BOARD LAYOUT SYSTEM AND METHOD THEREOF - A printed circuit board layout system and a method thereof are provided. The method includes the following steps: obtaining the outline information, the boundary information, and the auxiliary line information, when a command for recording position information of points within each of the boundaries is input; obtaining position information of the points within each of the boundaries; setting corresponding height values as height limit of height restriction areas corresponding to the points within each of the boundaries. | 05-19-2011 |
20110126165 | SYSTEM AND PROCESS FOR CLIENT DRIVEN AUTOMATED CIRCUITING AND BRANCH CIRCUIT WIRING - A computer aided design application modifies a CAD drawing having one or more electrical components by optimizing a plurality of circuits and associated panels, and assigning circuit and panel identifiers to each component for producing an engineering drawing. Further such identified components can be placed in home run groups, implementing shortest path calculations for various wire types and using neutral wires sharing options for producing an engineering drawing illustrating the home run grouping and identifiers, panel schedules and complete bills of materials. | 05-26-2011 |
20110131541 | SPICE CORNER MODEL GENERATING METHOD AND APPARATUS - In one embodiment, a SPICE corner model generating method for generating a SPICE corner model of an MOSFET includes preparing a table of a ratio X regarding a combination of two kinds of MOSFETs selected from N kinds of MOSFETs, the ratio X being a magnitude of a variation of an MOSFET in a case where directions of variations of the two kinds of MOSFETs are opposite directions to a magnitude of a variation of an MOSFET in a case where the directions of the variations of the two kinds of MOSFETs are the same direction, where N is an integer of 2 or greater. The method further includes reading out, when a combination of two kinds of MOSFETs is designated among the N kinds of MOSFETs, a value of the ratio X corresponding the designated combination from the table of the ratio X. The method further includes forming two kinds of corner models of opposite directional variations, the two kinds of corner models including a first corner model generated by applying the value of the ratio X to a fast-side corner of a first MOSFET of the two kinds of MOSFETs and to a slow-side corner of a second MOSFET of the two kinds of MOSFETs, and a second corner model generated by applying the value of the ratio X to a slow-side corner of the first MOSFET and to a fast-side corner of the second MOSFET. | 06-02-2011 |
20110145775 | CELL LIBRARY, LAYOUT METHOD, AND LAYOUT APPARATUS - In a cell library that is used for layout design of a semiconductor integrated circuit and is a library of design data of cells each realizing a unit function, each of the design data includes attribute information of each edge of a cell associated with an attribute value indicating whether the cell easily causes a defect in a cell adjacently placed across the edge and whether a defect is easily caused by a cell adjacently placed across the edge. | 06-16-2011 |
20110161909 | Methods for Designing Semiconductor Device with Dynamic Array Section - A method is provided for designing an integrated circuit device. The method includes placing four transistors of a first transistor type and four transistors of a second transistor type within a gate electrode level. Each of the transistors includes a respective linear-shaped gate electrode segment positioned to extend lengthwise in a first direction. The transistors of the first and second transistor types are placed according to a substantially equal centerline-to-centerline spacing as measured perpendicular to the first direction. A first linear conductive segment is placed to electrically connect the gate electrodes of the first transistors of the first and second transistor types. A second linear conductive segment is placed to electrically connect the gate electrodes of the fourth transistors of the first and second transistor types. A third linear conductive segment is placed beside either the first or second linear conductive segment. | 06-30-2011 |
20110167399 | DESIGN TOOL FOR THE TYPE AND FORM OF A CIRCUIT PRODUCTION - The invention relates to a method for influencing a selecting a “type and form of a circuit implementation” in at least one layer (L | 07-07-2011 |
20110185328 | System and Method for Circuit Design Floorplanning - Circuit floorplanning is performed on a combination central processing unit and multiprocessor. A B*-tree data structure of a floorplan and circuit related constants reside in a central processing unit data storage. The B* tree structure of a floorplan along and said circuit related constants are copied to a multiprocessor data storage where multiple thread blocks, each consisting of a single thread, copy the tree to their own shared memories. The multiprocessor concurrently evaluates different moves in different thread blocks. The multiprocessor then evaluates objective function results and stores those results. The best result for floorplanning is selected from the multiple circuit evaluations. | 07-28-2011 |
20110231807 | CIRCUIT DESIGN AIDING APPARATUS AND COMPUTER-READABLE RECORDING MEDIUM STORING CIRCUIT DESIGN AIDING PROGRAM - A circuit design aiding apparatus includes a circuit data storage that stores circuit data for each circuit diagram, the circuit data containing elements in a circuit, connection between the elements, and links to constraints, a constraint data storage that stores constraint data representing design constraints, a circuit edit controller that receives and edits the circuit data through user's operation and holds an element having been edited, a constraint edit controller that receives and edits the constraint data through user's operation, a constraint updater that updates, when the circuit data is edited, the constraint data set to the edited element based on the type of the constraint and the type of the edited element, a display unit that displays the circuit data and other information, and an output data generator | 09-22-2011 |
20110239178 | LAYOUT DESIGN APPARATUS, LAYOUT DESIGN METHOD, AND COMPUTER READABLE MEDIUM HAVING A LAYOUT DESIGN PROGRAM - A layout design apparatus that designs a layout of a semiconductor integrated circuit having a plurality of layers, the apparatus includes an extractor configured to extract, when given a lower module used at multiple locations inside an upper module, information regarding upper layer wiring near respective placement locations where the lower module is placed, and a layout design unit configured to lay out the lower module by setting prohibited wiring regions in a layout database based on the upper layer wiring information extracted from multiple locations. The prohibited wiring regions are specific regions that prohibit wiring processes therein, and the layout database is data for laying out the lower module. | 09-29-2011 |
20110239179 | DESIGN METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - To considerably reduce the cell layout change after timing optimization to reduce the term of layout design by estimating timing and an area after the timing optimization. | 09-29-2011 |
20110246958 | METHOD FOR REDUCING SURFACE AREA OF PAD LIMITED SEMICONDUCTOR DIE LAYOUT - A method for reducing a surface area of a pad limited semiconductor die layout includes choosing an outer die pad row from a group of outer die pad rows on the semiconductor die, each of the outer die pad rows being adjacent an edge of the semiconductor die. Next, the method performs selecting, from the outer die pad row, a common die pad group with die pads that are arranged to be electrically connected to an external connection pad. The method then performs repositioning a subgroup of the common die pad group on an inner die pad row, the inner pad row being adjacent the outer die pad row. After he repositioning there is performed a step of adjusting positions of at least some of the remaining pads in the outer die pad row thereby reducing an overall length of the outer die pad row. The method then provides for repeating the above steps until the surface area of a pad limited semiconductor die cannot be reduced any further by the step of adjusting positions or until every common die pad group, on every one of the outer die pad rows, has been selected by the selecting step. | 10-06-2011 |
20110289467 | Layout method and layout apparatus for semiconductor integrated circuit - A layout method of a semiconductor integrated circuit by using cell library data includes specifying a gate in a predetermined cell as a reference gate, and automatically arranging a plurality of cells by a computer such that a number of gates arranged in an area in a predetermined distance from the reference gate meets a preset gate data density condition. | 11-24-2011 |
20110296364 | METHOD AND APPARATUS FOR CUSTOM MODULE GENERATION - Some embodiments of the present invention create a layout for a circuit design which includes one or more circuit modules. The system can receive a nominal implementation of a circuit module, and a user-defined module generator capable of generating one or more custom implementations of the circuit module from an existing implementation of the circuit module. Next, the system can create the layout for the circuit design by executing the user-defined module generator on at least one processor to generate one or more custom implementations of the circuit module from the nominal implementation. The system can then use the one or more custom implementations of the circuit module in the layout. | 12-01-2011 |
20110296365 | EXTRACTING METHODS FOR CIRCUIT MODELS - The present invention relates to an extracting method for a circuit model, configured to represent output driving capability and an input capacitor of an interface pin of an application circuit. The extracting method comprises: receiving a netlist describing a circuit structure of the application circuit, which comprises a plurality of transistors; selecting an interface pin of the application circuit in the netlist; selecting a bias pin of the application circuit in the netlist; selecting at least one path between the interface pin and the bias pin in the netlist; and obtaining sum of equivalent width/length ratios according to the width/length ratios of all first transistors coupled to the at least one path. | 12-01-2011 |
20110314435 | ETCHING TECHNIQUE FOR CREATION OF THERMALLY-ISOLATED MICROSTRUCTURES - There is described a method for creating a thermally-isolated microstructure on a slab of mono-crystalline silicon which uses a hybrid dry-then-wet etch technique that when controlled, can produce microstructures without any silicon adhering underneath, microstructures having small masses of silicon adhering underneath, and microstructures that are still attached to the slab of mono-crystalline silicon via a waisted silicon body. When creating the microstructures with a waisted silicon body, the thermal isolation of the microstructure can be designed by controlling the depth of the etching and the size of the waist. | 12-22-2011 |
20110320998 | LIGHT-EMITTING DIODE SYSTEM DESIGNER - A system may include a database configured to store information including characteristics of a plurality of components. The system may further include a server in communication with the database and configured to receive design parameters indicative of characteristics of an LED lighting solution; determine a plurality of LED lighting array designs, each design including at least one of a parallel and a series arrangement of LEDs and configured to provide an amount of light specified by the design parameters; for each one of at least a subset of the plurality of LED lighting array designs, determine an LED driver design configured to power the one of the LED lighting array designs; and generate at least one LED lighting solution, each LED lighting solution including one of the LED lighting array designs combined with one of the LED driver designs configured to power the one of the LED lighting arrays. | 12-29-2011 |
20120023472 | METHOD, APPARATUS, AND ARTICLE OF MANUFACTURE FOR PROVIDING IN SITU, CUSTOMIZABLE INFORMATION IN DESIGNING ELECTRONIC CIRCUITS WITH ELECTRICAL AWARENESS - Disclosed are a method, system, and computer program product for providing customizable information in designing electronic circuits with electrical awareness. The method or the system displays a portion of a physical design of an electronic circuit in a first display area. The method or the system receives or identifies a user's or a system's manipulation of the portion of the physical design of the electronic circuit. The method or the system then determines and displays an in situ response to the manipulation in the first display area. The method or the system may further display, in the first display area or in another display area, result(s) relating to the physical data of a component, electrical parasitic(s) associated with the physical data, electrical characteristic(s) associated with the physical data or the electrical characteristic(s), or other element(s) of the physical design that is impacted by the manipulation. | 01-26-2012 |
20120036491 | Constraint Programming Based Method for Bus-Aware Macro-Block Pin Placement in a Hierarchical Integrated Circuit Layout - Assigning pins to macro-blocks of an Integrated Circuit (IC) chip is described. The macro-block pin assignments are automatically placed using Constraint Programming (CP) techniques to position the pins on the periphery of a macro-block. Bus-ordering and pin-spacing constraints are performed considering all the nets forming the IC design simultaneously. The CP formulation includes modeling detailed and discrete constraints required to achieve an optimal pin-assignment. A stochastic CSP solver is used to define the cost function on search points giving full assignments to all the variables. The macro-block pins are ultimately moved to computed locations. | 02-09-2012 |
20120066659 | METHODS FOR GENERATING DEVICE LAYOUTS BY COMBINING AN AUTOMATED DEVICE LAYOUT GENERATOR WITH A SCRIPT - Methods for generating a device layout are provided. First, design rules corresponding to a specific technology are received. A selection of at least one element and a parameter value corresponding to at least one parameter on the selected element are received. A draft device layout corresponding to the selected element is generated by a device generator by referencing the parameter value and the design rules. A script is then executed to modify the draft device layout to generate an updated device layout. The script includes at least one command, and when the script is executed, the at least one command is performed to modify the parameter value of the at least one parameter of the selected element and cause the device generator to delete the old draft device layout and generate a new draft device layout by referencing the modified parameter value and the design rules. | 03-15-2012 |
20120079444 | COMPUTER AIDED DESIGN SYSTEM AND METHOD - A computer aided design system comprises a dividing module, a storage, an interface creating module, a selecting module, and a display module. The dividing module divides the names into groups according to a predetermined rule. The group comprises a plurality of the targets set on the different layers. The storage records the relationship between the groups and the targets. The interface creating module creates a user interface base on the groups and selects at least one group in the same user interface from the operation of the user. The selecting module selects targets according to the selected groups. The display module displays the selected targets. | 03-29-2012 |
20120079445 | CIRCUIT BOARD DESIGNING DEVICE AND NON-TRANSITORY COMPUTER-READABLE MEDIUM - A circuit board designing device has a database that stores an another-component arrangement forbidden range table, a related component information table, and a relative-arranging position table, and a processing unit that executes arrangement of the components, determines the another-component arrangement forbidden range which is set to forbid arrangement of another component in the predetermined range on the basis of the arranging position of the basic component with reference to the another-component arrangement forbidden range table when arrangement of the basic component is instructed, acquires related component information corresponding to the related component to be combined with the basic components with reference to the related component information table, acquires a relative-arranging position of the related component from the relative-arranging position table on the basis of the acquired related component information, and sets the acquired related component in the another-component arrangement forbidden range when a predetermined condition is satisfied. | 03-29-2012 |
20120079446 | SEMICONDUCTOR MODULE DESIGN METHOD AND SEMICONDUCTOR MODULE - A semiconductor module made from a compound semiconductor or diamond and loaded with high performance power semiconductor devices can be obtained at low cost. In a semiconductor module, four (semiconductor chips) of same specifications are arranged in array, two longitudinally and two transversally, on a single lead frame. Achieving a high yield of manufacturing diode chips and reducing the unuseful area of diode chips need to be satisfied at the same time to obtain such a semiconductor module at low cost. The use of an index, which is the product of the yield Y | 03-29-2012 |
20120110535 | INTEGRATED CIRCUIT MANUFACTURING METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT - In layout design step of the semiconductor integrated circuit manufacturing method, when it is found that the wiring length between an external terminal and an IO block (external terminal I/F circuit) corresponding to the external terminal increases after a floorplan of a circuit including a functional block and the IO block is determined, placement of the IO block is determined such that the IO block is placed close to the external terminal to alleviate constraints on the wiring between the IO block and the external terminal, and timing adjustment circuits whose number is determined according to the wiring length of a bus (or a shared bus) connecting a data transfer circuit and the IO block is inserted into the bus. | 05-03-2012 |
20120124541 | IMPLEMENTING SPARE LATCH PLACEMENT QUALITY DETERMINATION - A method, system and computer program product are provided for implementing spare latch placement quality (SLPQ) determination in a floor plan design of an integrated circuit chip. A spare latch placement quality (SLPQ) metric data function is defined and compared to a spare latch placement input with a series of calculations performed. The spare latch placement quality (SLPQ) determination is made based upon the compared SLPQ metric data function and the spare latch placement input. Then associated reports including textual and visual reports are generated responsive to the SLPQ determination. In addition, a new spare latch placement can be constructed with an algorithm responsive to the SLPQ determination. | 05-17-2012 |
20120131533 | METHOD OF FABRICATING AN INTEGRATED CIRCUIT PROTECTED AGAINST REVERSE ENGINEERING - The disclosure relates to a method of fabricating an integrated circuit on a semiconductor chip, the method comprising: designing an architecture of the integrated circuit comprising at least first and second standard cells implementing a same basic function; designing for the standard cell at least first and second cell layouts presenting random differences; designing an integrated circuit layout corresponding to the integrated circuit architecture; fabricating the integrated circuit according to the integrated circuit layout; using the first cell layout to implement the first standard cell in the integrated circuit layout; and using the second cell layout to implement the second standard cell in the integrated circuit layout. The method can be used for protection of an integrated circuit against reverse engineering. | 05-24-2012 |
20120131534 | Automatically Creating Vias in a Circuit Design - Creating and detecting crossings of conductive traces on different layers of an integrated circuit or a conducting trace over a device contact in a system. Values are stored by a system simulator corresponding to a galvanic potential or same “net”. According to a set of rule based instructions vias are automatically displayed, correct-by-construction, and via connections between the traces, or the trace and device contact, to short circuit the paths. The via structure will not be created if it will short-circuit a conducting trace not associated with the net in question. By connecting traces on different layers using automatically created via structures so as not to short circuit other net traces, errors are eliminated and design cycles reduced when compared to a manual design scheme of inserting via connections. There is an interactive mode which allows the via to be easily resized by the use of familiar control handles. | 05-24-2012 |
20120167031 | METHOD FOR DESIGNING A SEMICONDUCTOR DEVICE BASED ON LEAKAGE CURRENT ESTIMATION - A method of designing a semiconductor device includes preparing a first design for a semiconductor device and estimating leakage current for the first design. The method also includes determining a leakage current cumulative distribution function (CDF) for the first design. The method further includes preparing a second design for the semiconductor device based on determination of the leakage current CDF for the first design. Further, the method includes estimating leakage current for the second design. The method also includes determining a leakage current CDF for the second design in accordance to the determination of the leakage current CDF for the first design. Moreover, the method includes selecting one of the first design and the second design based on a comparison of the leakage current CDF for the first design and the leakage CDF for the second design. | 06-28-2012 |
20120174051 | Method and System for Generating a Placement Layout of a VLSI Circuit Design - A method and a system for generating a placement layout is disclosed. The method includes receiving one or more user provided schematic with circuit data, placement parameters of circuit elements, default values, and user specified function calls and variables for calculating placement parameters; evaluating variables and function calls to discrete placement parameters; evaluating justification values and adjusting relative parameter values; calculating absolute placement coordinates for all cells from relative placement parameters for each instance; adjusting placement coordinates for alignment options; and generating a layout/hierarchical layout with placement circuit elements based on the calculated absolute placement coordinates. | 07-05-2012 |
20120198406 | UNIVERSAL INTER-LAYER INTERCONNECT FOR MULTI-LAYER SEMICONDUCTOR STACKS - An apparatus, program product and method facilitate the design of a multi-layer circuit arrangement incorporating a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers. | 08-02-2012 |
20120210289 | WIDE PROCESS RANGE LIBRARY FOR METROLOGY - Methods of generating wide process range libraries for metrology are described. For example, a method includes generating a first library having a first process range for a first parameter. A second library is generated having a second process range for the first parameter. The second process range is overlapping with the first process range. The second library is stitched to the first library to generate a third library having a third process range for the first parameter. The third process range is wider than each of the first and second process ranges. | 08-16-2012 |
20120227025 | SYSTEM AND METHOD TO IMPROVE CHIP YEILD, RELIABILITY AND PERFORMANCE - Improving semiconductor chip yield and reliability by connecting adjacent metal traces that are on a same network with metal shorts. This reduces and/or eliminates the need for redundant vias formerly employed in semiconductor chip design. Additionally, the metal shorts are placed in conformance with one or more pre-determined design rules. Once placed, the metal shorts are checked to ensure that each metal short connects groundrule clean, thereby ensuring the placement is correct-by-construction. | 09-06-2012 |
20120233581 | DESIGN SUPPORT APPARATUS FOR SEMICONDUCTOR DEVICE, DESIGN SUPPORT PROGRAM, AND LAYOUT INFORMATION GENERATING METHOD - A design support apparatus according to an aspect of the present invention includes: a terminal position setting unit that obtains, from a floor plan result generated from circuit design information, positional information on first and second connection terminals of a connection target circuit area to be connected to an inductor to be generated, and sets third and fourth connection terminals at respective positions where the first and third connection terminals and the second and fourth connection terminals can be respectively connected by a shortest wiring, the third and fourth connection terminals connecting the inductor to another circuit; and a pattern generation unit that generates a wiring pattern of the inductor based on the positions of the third and fourth connection terminals, and generates layout information on the inductor based on the wiring pattern. | 09-13-2012 |
20120266124 | Placement of Structured Nets - Mechanisms are provided for performing placement of cells in a design of a semiconductor device. An initial design of the semiconductor device is generated, the initial design comprising a first placement of cells. A preferred direction of placement associated with the cells is determined. The preferred direction is a direction along which spreading of the cells is preferred. A second design of the semiconductor device is generated by modifying the first placement of the cells to generate a second placement of cells, different from the first placement cells, based on the preferred direction of placement associated with the cells. | 10-18-2012 |
20120266125 | BONDING CONTROLLER GUIDED ASSESSMENT AND OPTIMIZATIONFOR CHIP-TO-CHIP STACKING - A method, system, and computer program product for performance-based chip-to-chip stacking are provided in the illustrative embodiments. A first candidate chip is selected from a set of candidate chips for stacking, each candidate chip in the set of candidate chips including an integrated circuit. A part of a | 10-18-2012 |
20120278781 | SYSTEM AND METHODS FOR CONVERTING PLANAR DESIGN TO FINFET DESIGN - A method for generating a layout for a device having FinFETs from a first layout for a device having planar transistors is disclosed. The planar layout is analyzed and corresponding FinFET structures are generated in a matching fashion. The resulting FinFET structures are then optimized. Dummy patterns and a new metal layer may be generated before the FinFET layout is verified and outputted. | 11-01-2012 |
20120278782 | Methods and Systems Configured to Compute a Guard Zone of a Three-Dimensional Object - Techniques generally disclosed herein relate to computation of a guard zone of a three-dimensional object. In some examples, guard zones may be computed by identifying intersection lines that couple adjacent planes of an object, and categorizing an external angle at an intersection line between adjacent planes as concave or convex. In some embodiments, for convex angles, a cylindrical surface can be determined that is located about an outside surface of the object and centered along the intersection line between the adjacent planes. In some embodiments, for concave angles, the external angle can be bisected with a bisection plane. A guard zone may be formed by one or more of (i) providing a guard zone plane parallel to the object that is a tangent to a given cylindrical surface, (ii) providing a guard zone plane parallel to the object that intersects a given bisection plane, and/or (iii) coupling adjacent guard zone planes. | 11-01-2012 |
20120284682 | Relative Positioning of Circuit Elements in Circuit Design - Methods and apparatuses are disclosed for generating a placed, routed, and optimized circuit design. Other embodiments are a circuit design and circuit created with the technology. The placed, routed, and optimized circuit design obeys relative positioning rules of a set of the circuit elements. Such relative positioning rules were created specifically for these circuit elements. | 11-08-2012 |
20120297354 | METHOD AND APPARATUS FOR APPROXIMATING DIAGONAL LINES IN PLACEMENT - Some embodiments of the invention provide a method for placing circuit modules in an integrated circuit (“IC”) layout. The method computes a placement metric for the IC layout. In some embodiments, computing the placement metric includes partitioning a region the IC layout into several sub-regions by using a cut graph, where the cut graph is an approximation of a diagonal cut line. These embodiments then generate congestion-cost estimates by measuring the number of nets cut by the cut graph. In some embodiments, the cut graph is a staircase cut graph. These staircase cut graphs include several horizontal and vertical cut lines. In some embodiments, the cut graph is a cut arc. | 11-22-2012 |
20120311517 | PARALLEL SOLVING OF LAYOUT OPTIMIZATION - Solutions for optimizing an integrated circuit layout for implementation in an integrated circuit are disclosed. In one embodiment, a computer-implemented method is disclosed including: obtaining a plurality of hierarchical constraints in mathematical form, the plurality of hierarchical constraints defining a first integrated circuit layout; partitioning the plurality of hierarchical constraints into groups according to one or more partitioning rules; determining whether a boundary condition exists between two of the groups, and distributing a slack or a gap between the two of the groups in the case that the boundary condition exists; creating a plurality of integer linear programming problems associated with each of the groups; determining a solution for each of the plurality of integer linear programming problems; and integrating each solution together to form a second integrated circuit layout. | 12-06-2012 |
20130007688 | GENERATING A CONVERGENT CIRCUIT DESIGN FROM A FUNCTIONAL DESCRIPTION USING ENTITIES HAVING ACCESS TO THE FUNCTIONAL DESCRIPTION AND TO PHYSICAL DESIGN INFORMATION - A method of designing a circuit is described. In an embodiment, a physical design implementation for the circuit is created using a plurality of entities. These entities are named “genomes”. Each entity includes a portion of a functional description of the circuit that has been synthesized into a gate-level implementation. An entity is selected to facilitate the physical design implementation meeting a plurality of design constraints. Several steps (e.g., beginning with selection of an entity) of this method are repeated several times to meet the design constraints. As a consequence, the physical design implementation provides more accurate information for use in a final physical design implementation. Moreover, the physical design implementation can be created faster than prior techniques while still allowing a global view of the physical design implementation in meeting design constraints. | 01-03-2013 |
20130036397 | Standard Cell Placement Technique For Double Patterning Technology - A method for generating legal colorable multiple patterning standard cell placement is provided. In this method, a standard cell library including color information can be accessed. For each standard cell, edge labels can be assigned based on colors of objects within a predetermined distance from each edge. A truth table, which indicates legal spacing between pairs of standard cells based on their edge labels, can be accessed. A plurality of standard cells of a design can then be placed based on the truth table. | 02-07-2013 |
20130042217 | STRUCTURAL MIGRATION OF INTEGRATED CIRCUIT LAYOUT - Methods and systems for migrating circuit layouts. A floorplan layout is built for a target circuit using a subset of constraints that characterize a layout structure of an original circuit. Shape-constraint-based scaling is used on the floorplan layout by scaling parts of the floorplan layout in accordance with a plurality of different scaling ratios such that portions of the floorplan layout are concurrently scaled with the plurality of different scaling ratios. Cells are placed at locations defined by the floorplan layout. The floorplan layout is checked with shape-constraint-based legalization using all of the constraints to produce a migrated layout. | 02-14-2013 |
20130055186 | SYSTEM AND METHOD FOR CLOCK NETWORK META-SYNTHESIS - In accordance with some embodiments of the present disclosure a method for constructing a clock network comprises receiving design specifications for a clock network. The method further comprises determining a topology of the clock network based on the design specifications. The topology indicates at least one of a plurality of levels of the clock network, a buffer type for each level and a buffer fanout for each level. The method additionally comprises determining design parameters for the clock network based on the determined topology and generating a clock network synthesis tool specification file that includes the design parameters. The method also comprises synthesizing the clock network using the specification file such that the clock network includes the determined topology and such that the clock network synchronously distributes a clock signal from a clock generator to endpoints of the clock network. | 02-28-2013 |
20130055187 | FLOORPLAN CREATION INFORMATION GENERATING METHOD, FLOORPLAN CREATION INFORMATION GENERATING PROGRAM, FLOORPLAN CREATION INFORMATION GENERATING DEVICE, FLOORPLAN OPTIMIZING METHOD, FLOORPLAN OPTIMIZING PROGRAM, AND FLOORPLAN OPTIMIZING DEVICE - A floorplan creation information generating method according to this embodiment includes setting a group to a plurality of circuit modules based on a netlist and group setting information, calculating a distance that satisfies a timing constraint between the set groups, and generating floorplan creation information for creating a floorplan including the calculated distance between the groups. | 02-28-2013 |
20130055188 | SEMICONDUCTOR LAYOUT SETTING DEVICE, SEMICONDUCTOR LAYOUT SETTING METHOD, AND SEMICONDUCTOR LAYOUT SETTING PROGRAM - A semiconductor device for layout has first and second power supply domains and has wiring connected to and from cells belonging to a second power supply domain. A wiring inhibited/allowed area setting unit sets an exclusive wiring inhibited area and a pass-through wiring allowed area within the first power supply domain based on a repeater wire maximum length being a maximum wire length which a repeater buffer can drive. A wiring setting unit modifies wiring based on the exclusive wiring inhibited area and the pass-through wiring allowed area. A repeater insertion unit sets a repeater buffer to be inserted on a wire according to the repeater wire maximum length. The exclusive wiring inhibited area allows wiring connecting cells within the first power supply domain and inhibits pass-through wiring. The pass-through wiring allowed area, being the first power supply domain excluding the exclusive wiring inhibited area, allows pass-through wiring. | 02-28-2013 |
20130061194 | LAYOUT METHOD, LAYOUT APPARATUS, AND PROGRAM FOR SEMICONDUCTOR INTEGRATED CIRCUIT - A layout method, upon performing layout of layer blocks each including internal elements, with respect to mounting area where internal element resources, to which internal elements can be assigned, are arranged, comprises: arranging, when first layer block and second layer block overlap in overlapping area, first layer block and the second layer block such that sum of number of first internal elements included in the overlapping area, among internal elements of first layer block, and number of second internal elements included in the overlapping area, among internal elements of second layer block, is not greater than number of internal element resources included in the overlapping area; and assigning the internal element resources included in the overlapping area to first layer block and second layer block, in accordance with ratio of number of first internal elements to number of second internal elements. | 03-07-2013 |
20130074028 | METHOD FOR ENSURING DPT COMPLIANCE WITH AUTOROUTED METAL LAYERS - A method of generating an integrated circuit with a DPT compatible interconnect pattern using a reduced DPT compatible design rule set and color covers. A method of operating a computer to generate an integrated circuit with a DPT compatible interconnect pattern using a reduced DPT compatible design rule set and using color covers. A reduced DPT compatible design rule set. | 03-21-2013 |
20130091481 | METHOD OF SCHEMATIC DRIVEN LAYOUT CREATION - A computer-implemented method is disclosed for layout pattern or layout constraint reuse by identifying sub-circuits with identical or similar schematic structure based on a topology comparison strategy. The selected sub-circuit is transformed into a topology representing the relative positions among the instances of the selected sub-circuit. Based on the topology, one or more sub-circuits with identical or similar topologies in a predefined scope of a schematic are recognized and identified. Accordingly, the layout or the layout constraint of the selected sub-circuit is copied and associated to each of the identified sub-circuits. Furthermore, once the sub-circuits are identified, they can be listed on a user interface with notations to allow users to confirm each of the identified sub-circuits respectively. | 04-11-2013 |
20130097571 | METHOD FOR DUMMY METAL AND DUMMY VIA INSERTION - A method of inserting dummy metal and dummy via in an integrated circuit design. The method includes inserting, by a computer, dummy metals using a place and route tool, wherein the place and route tool has timing-awareness to improve a timing performance of the integrated circuit design. The method further includes inserting, by the computer, dummy vias using a design-rule-checking utility separately from the inserting of the dummy metals, wherein at least one of the dummy vias has a different size than at least another of the dummy vias. | 04-18-2013 |
20130097572 | METHOD AND SYSTEM FOR IMPLEMENTING GRAPHICALLY EDITABLE PARAMETERIZED CELLS - Disclosed is an improved mechanism and method for implementing electronic designs. According to some approaches, a method, mechanism, and compute program product is disclosed for implementing electronic designs that allows visual editing of complex objects with advanced editing features, which also provides for automated correspondence of the editing results to parametric values for a programmable object in the design. | 04-18-2013 |
20130159956 | WIRELESS ENERGY TRANSFER MODELING TOOL - A method includes defining and storing one or more attributes of a source resonator and a device resonator forming a system, defining and storing the interaction between the source resonator and the device resonator, modeling the electromagnetic performance of the system to derive one or more modeled values and utilizing the derived one or more modeled values to design an impedance matching network. | 06-20-2013 |
20130174112 | METHOD OF GENERATING A BIAS-ADJUSTED LAYOUT DESIGN OF A CONDUCTIVE FEATURE AND METHOD OF GENERATING A SIMULATION MODEL OF A PREDEFINED FABRICATION PROCESS - A method of generating a bias-adjusted layout design of a conductive feature includes receiving a layout design of the conductive feature. If a geometry configuration of the layout design is within a first set of predetermined criteria, the bias-adjusted layout design of the conductive feature is generated according to a first layout bias rule. If the geometry configuration of the layout design is within a second set of predetermined criteria, the bias-adjusted layout design of the conductive feature is generated according to a second layout bias rule. | 07-04-2013 |
20130174113 | FLOORPLAN ESTIMATION - The disclosed invention gives an estimation of the placement location of the units comprising a NoC within the floorplan of a chip. From that, and with knowledge of the number of wires of links within the NoC topology, an estimation of the wire density at each point is calculated. Furthermore, an estimate is made of the locations of the critical timing paths within the chip. The timing path calculation is also used to generate IO constraints for the synthesis of modules comprising different parts of the NoC. Further still, a scenario of traffic through the NoC is combined with the wire map and information about the width of links within the topology to generate an estimation of power consumption. | 07-04-2013 |
20130174114 | CHANGING THE LOCATION OF A BUFFER BAY IN A NETLIST - In an embodiment, a buffer bay is represented with a moveable object that has a location within a unit in a netlist. The location of the moveable object that represents the buffer bay is changed to a new location in the netlist if changing the location improves placement within the unit. In an embodiment, a net weight of a net that connects the moveable object to an artificial pin is considered in determining whether to change the location to the new location. In an embodiment a bounding area that encompasses the location is considered in determining whether to change the location to the new location. | 07-04-2013 |
20130205272 | ALIGNMENT NET INSERTION FOR STRAIGHTENING THE DATAPATH IN A FORCE-DIRECTED PLACER - An automated method for aligning a critical datapath in an integrated circuit design inserts an artificial alignment net in the netlist which interconnects all cells in the bit stack of the datapath. The cells are placed using a wirelength optimization which assigns weights to wire sections based on the alignment direction. The rate of change of the alignment weighting value can vary during different stages of global placement. The invention is particularly suited for a force-directed placer which uses a linear system solver to obtain a globally optimum solution for placement of the cells having some overlap among the cells, and thereafter spreads the cells to reduce the overlap. Pseudo nets are also inserted which interconnect a cell and an expected location of the cell after spreading for that iteration. | 08-08-2013 |
20130219353 | CONCURRENT PLACEMENT AND ROUTING USING HIERARCHICAL CONSTRAINTS - An automated layout method allows designing advanced integrated circuits with design rules of high complexity. In particular, a hierarchical constrained layout process is applicable and useful for analog and mixed-signal integrated circuit designs and may be based on an incremental concurrent placement and routing. Use of constraints from multiple levels of a circuit description hierarchy allows computationally efficient processing of logical circuit increments and produces high-quality outcomes. Users such as circuit designers can exercise a high degree of predictability and control over the resulting physical layout construction by either user-specified or computer-generated constraints. | 08-22-2013 |
20130246992 | Generating Capacitance Look-up Tables for Wiring Patterns in the Presence of Metal Fills - A computer system selects a signal conductor from an electronic circuit design layout and assigns a first potential to the selected signal conductor. Next, the computer system assigns a second potential to other signal conductors included in the electronic circuit design layout. The computer system then selects a metal fill from the electronic circuit design layout, which is void from carrying an electrical signal, and generates a zero charge equation for the selected metal fill. The zero charge equation establishes that a total charge residing on the selected metal fill is equal to zero. The computer system includes the zero charge equation in a system of equations, which includes grid point potential equations, and solves the system of equations. In turn, the computer system computes capacitance values for the signal conductors based upon the system of equation solutions, and simulates the electronic circuit design layout using the computed capacitance values. | 09-19-2013 |
20130246993 | METHOD FOR ASSIGNING TERMINAL OF SEMICONDUCTOR PACKAGE, APPARATUS, AND SEMICONDUCTOR PACKAGE - An assignment method of terminals of a semiconductor package executed by an assignment supporting apparatus includes: deciding a maximum allowable distance to be a constraint condition regarding a relative distance between each of the pads and a terminal to be assigned to the pad, and extracting one or a plurality of assigned terminal candidates for each of the pads so that the relative distance between each of the pads and a terminal selected for the pad falls within a range of the maximum allowable distance; and deciding one of the terminals as a assigned terminal based on the assigned terminal candidates and assigning the one of the terminals to one of the pads. The process is a process to assign one of the terminals with priority to a pad having a smallest number of assigned terminal candidates in a not-assigned condition based on the assigned terminal candidates. | 09-19-2013 |
20130263077 | SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF DESIGNING THE SAME - According to example embodiments of inventive concepts, a method of designing a semiconductor integrated circuit includes: creating a marking layer that indicates at least one semiconductor device of a plurality of semiconductor devices that is to be changed in at least one of width, height, and space thereof from an adjacent semiconductor device; and applying the marking layer to a previously created layout to generate a new library of the at least one semiconductor device that is changed in at least one of width, height, and space from an adjacent semiconductor device. The marking layer may be based on a change in characteristics of the at least one semiconductor device of the plurality of semiconductor devices. | 10-03-2013 |
20130268908 | VIA SELECTION IN INTEGRATED CIRCUIT DESIGN - Solutions for efficiently implementing a via into a multi-level integrated circuit layout are disclosed. In various embodiments, a method of creating a multi-level integrated circuit layout with at least one via is disclosed, the method including: providing at least two layers of the multi-level integrated circuit layout; and selecting a via for connecting the at least two layers, wherein the selecting includes retrieving the via from a via library including a plurality of via types, the plurality of via types prioritized in the via library according to a predicted manufacturing yield for each of the plurality of vias. | 10-10-2013 |
20130283225 | DATAPATH PLACEMENT USING TIERED ASSIGNMENT - Datapath placement defines tiers for placement sets of a cell cluster, assigns cells to the tiers constrained by the datapath width, and then orders cells within each tier. Clusters are identified using machine-learning based datapath extraction. Datapath width is determined by computing a size of a bounding box for cells in the cluster. Placement sets are identified using a breadth-first search beginning with input cells for the cluster. Tiers are initially defined using logic depth assignment. A cell may be assigned to a tier by pulling the cell from the next higher tier to fill an empty location or by pushing an excess cell into the next higher tier. Cells are ordered within each tier using greedy cell assignment according to a wirelength cost function. The datapath placement can be part of an iterative process which applies spreading constraints to the cluster based on computed congestion information. | 10-24-2013 |
20130283226 | FLOORPLANNING METHOD FOR AN ANALOG INTEGRATED CIRCUIT LAYOUT - A floorplanning method for an analog integrated circuit layout is disclosed. A first-type block is defined as a movable and deformable block with rectangle constraint, and a second-type block is defined as a fixed-size block without rectangle constraint. Each block in the floorplan is classified to the first-type or the second-type block. In a shape determination stage, a target shape is determined among candidates of the first-type block, the first-type block accordingly being modified to the target shape, resulting in at least one overlap in the floorplan. In an overlap elimination stage, neighboring blocks of each said overlap are analyzed, the overlap being then eliminated by utilizing surrounding space, resulting in unused space in the floorplan. In an enlargement stage, the unused space is utilized for enlarging the first-type block. | 10-24-2013 |
20130298099 | METHOD AND SYSTEM FOR ESTIMATING A DIFFUSION POTENTIAL OF A DIFFUSIVE PROPERTY - Methods, systems, and techniques for estimating a transient diffusion potential of a diffusive property involve modeling, as a circuit, diffusive behavior of a diffusion region and then simulating operation of the circuit to estimate the transient diffusion potential at a location in the diffusion region by determining circuit potential at a node in the circuit that corresponds to the location in the diffusion region. The circuit has steady-state and transient portions that model the steady-state and transient behavior of the diffusion region, respectively. The transient behavior is modeled using a capacitive circuit element. The diffusive property diffuses linearly within the diffusion region and generation of the diffusive property is distributed within the diffusion region. | 11-07-2013 |
20130311964 | MODIFIED DESIGN RULES TO IMPROVE DEVICE PERFORMANCE - A method of designing a layout of devices includes designing a layout of gate structures and diffusion regions of a plurality of devices. The method further includes identifying an edge device of the plurality of devices. The method further includes adding a dummy device next to the edge device and a dummy gate structure next to the dummy device, wherein the dummy device shares a diffusion region with the edge device, and wherein a gate structure of the dummy device is considered to be one of two dummy gate structures added next to the edge device. | 11-21-2013 |
20130326455 | ELEMENT PLACEMENT IN CIRCUIT DESIGN BASED ON PREFERRED LOCATION - An improved circuit design system may include a computer processor to perform a placement for a circuit by physical synthesis. The system may also include a controller to compute a preferred location of at least one selected element of the circuit, and to calculate placement constraints for each selected element. The system may further include an updated design for the circuit generated by performing another round of physical synthesis with the placement constraints. | 12-05-2013 |
20130326456 | DESIGNING A ROBUST POWER EFFICIENT CLOCK DISTRIBUTION NETWORK - An electronic automation design tool with a sink locator unit creates clusters of loads from a plurality of loads within a sector of a clock network design based on balancing magnitudes of the loads among the clusters of loads and based on minimal delays of each of the clusters and respective ones of a plurality of sink locations in the sector of the clock network design. The tool determines centers of the clusters of loads, and sink locations corresponding to the centers of the clusters for connecting output terminal points of sector buffers are determined. Each of the sector buffers drive a clock signal to a corresponding one of the clusters of loads. | 12-05-2013 |
20130326457 | INTEGRATED ELECTRONIC DESIGN AUTOMATION SYSTEM - An electronic design automation system combines features of discrete EDA/CAD systems and manufacturing systems into a monolithic system to enable a layperson to efficiently design, construct and have manufactured a specific class of custom electronic device, namely a computer processing unit with embedded software. A Graphical User Interface (GUI) is provided as the front-end to a Computer Aided Design (CAD) server that generates sophisticated control and manufacturing instructions that are delivered to a fabrication supply chain, which produces a specified device that is then transported via managed logistics into inventory and ordering systems at vendors for delivery to a designated customer. | 12-05-2013 |
20130339918 | MICROELECTROMECHANICAL SYSTEM DESIGN AND LAYOUT - Methods for producing layout data for devices are described. One method includes using a genetic algorithm to determine a structure of a thermally-operated actuator. Another method includes receiving a three-dimensional model of a device, a design-rule set, and parameter ranges. Layout data are produced for devices having various combinations of parameter values in the parameter ranges. | 12-19-2013 |
20130346936 | Method and Apparatus to Generate Pattern-Based Estimated RC Data with Analysis of Route Information - A method and apparatus for improving physical synthesis of a circuit design is described. In one exemplary embodiment, post-route information of nets in the circuit design is analyzed. The post-route information includes, for each of the nets, a predicted route property, a post-route property, and a set of physical and/or timing attributes for that net. For each of the attributes, a set of attribute ranges is derived for the corresponding attribute to bin the nets into a Gaussian distribution for that attribute. Net routing constraints are generated for the circuit design based on the attribute ranges derived. The net routing constraints are applied to one or more of the nets during subsequent placement-based optimizations of the circuit design. | 12-26-2013 |
20130346937 | METHOD AND APPARATUS TO GENERATE PATTERN-BASED ESTIMATED RC DATA WITH ANALYSIS OF ROUTE INFORMATION - A method and apparatus for improving physical synthesis of a circuit design is described. In one exemplary embodiment, preliminary routing information of nets in the circuit design is analyzed. The preliminary routing information includes track assignment information. Timing-critical nets are identified based on statistical distribution of the preliminary routing information of the nets. The identified timing-critical nets are assigned to a set of routing layers and removed from future net pattern matching. The remaining nets are clustered into multiple net patterns based on their physical attributes. The scaling factor for each net pattern is updated based on the scaling factor standard deviation and net length of the net pattern. Nets that are outside multiple standard deviations of a net pattern are assigned to routing layers. The scaling factors of the net patterns and the layer assignments are applied to the next phase of placement-based optimizations. | 12-26-2013 |
20140019931 | SYSTEMS AND METHODS FOR FIXING PIN MISMATCH IN LAYOUT MIGRATION - Approaches are provided for fixing pin mismatches from swapping library cells in layout migration. Specifically, a method is provided that includes collecting information about a first technology pin from a library cell in a first technology. The method further includes swapping the library cell in the first technology with a library cell in a second technology. The method further includes collecting information about a second technology pin from the library cell in the second technology. The method further includes building a pin-mapping table that is configured to map the first technology pin to the second technology pin. The method further includes scaling a layout from the first technology to the second technology. The method further includes modifying the layout based on the pin-mapping table to match the at least one first technology pin to the at least one second technology pin while satisfying ground rules of the second technology. | 01-16-2014 |
20140019932 | SYSTEM AND METHOD FOR INTEGRATED CIRCUIT DESIGN AND IMPLEMENTATION USING MIXED CELL LIBRARIES - A system and method for designing circuits, such as integrated circuits, that allow a designer to employ mixed cell libraries. In one embodiment, the system includes: (1) a cell placement EDA tool configured to transform a logical circuit representation into a physical circuit representation by placing cells from mixed cell libraries into clusters corresponding to the mixed cell libraries and (2) an interconnect routing EDA tool associated with the cell placement EDA tool and configured to route interconnects in buffer zones separating the clusters. | 01-16-2014 |
20140033153 | Method For Assisting in Logic Circuit Design to Place Cells on IC Substrate and Optimize Wiring, Device For Assisting in Logic Circuit Design Using This Method, and Computer Program Executable By This Device - A method of assisting in the design of a logic circuit enabling the placement and wiring of cells (logic operation elements) to be optimized on an IC substrate in a short period of time even when the logic circuit has multiple levels, to provide a device assisting in the design of a logic circuit using this method, and to provide a computer program executable by this device. The cells of all levels are placed in a placement area formed on a grid, and a port enabling connection to a cell in another level is placed in a boundary portion between the placement area having cells already placed and a placement area enabling placement of new cells. Cells in the same level are wired between cells and cells in another level are wired between a cell and a port so that the sum total of the wiring lengths may be minimized. | 01-30-2014 |
20140033154 | Scheduling for Parallel Processing of Regionally-Constrained Placement Problem - Scheduling of parallel processing for regionally-constrained object placement selects between different balancing schemes. For a small number of movebounds, computations are assigned by balancing the placeable objects. For a small number of objects per movebound, computations are assigned by balancing the movebounds. If there are large numbers of movebounds and objects per movebound, both objects and movebounds are balanced amongst the processors. For object balancing, movebounds are assigned to a processor until an amortized number of objects for the processor exceeds a first limit above an ideal number, or the next movebound would raise the amortized number of objects above a second, greater limit. For object and movebound balancing, movebounds are sorted into descending order, then assigned in the descending order to host processors in successive rounds while reversing the processor order after each round. The invention provides a schedule in polynomial-time while retaining high quality of results. | 01-30-2014 |
20140053123 | DENSITY-BASED INTEGRATED CIRCUIT DESIGN ADJUSTMENT - The disclosed technology is related to adjusting an integrated circuit design while accounting for a local density of the design. In particular exemplary embodiments, a local density value for a layout design that defines a plurality of geometric shapes is derived. Subsequently, one or more of the geometric shapes are adjusted such that the local density value is preserved. With some implementations, the local density value is preserved if the adjusted local density value is within a threshold amount of the derived local density value. | 02-20-2014 |
20140068540 | INTEGRATED CIRCUIT DESIGN FLOW WITH LAYOUT-DEPENDENT EFFECTS - A design system for designing an integrated circuit that includes a processor, a memory coupled to the processor, and instructions to generate and edit a schematic of the integrated circuit, generate at least one recommended layout parameter of an integrated circuit device within the integrated circuit, extract the at least one recommended layout parameter during a layout stage of the integrated circuit, and calculate a circuit performance parameter of the integrated circuit using the at least one recommended layout parameter, and a user interface configured to display at least one of the circuit performance parameter and layout constraints of the integrated circuit device of the integrated circuit. | 03-06-2014 |
20140075404 | GROUP BOUNDING BOX REGION-CONSTRAINED PLACEMENT FOR INTEGRATED CIRCUIT DESIGN - Among other things, one or more systems and techniques for defining a group bounding box for related cells of an integrated circuit, and generating a new layout for the integrated circuit comprising the group bounding box are provided herein. That is, one or more group bounding boxes are defined based upon positional values of related cells. Such group bounding boxes are placed within the new layout based upon a placement technique, such as an objective function that takes into account wire length, timing, and cell density, for example. The one or more group bounding boxes are sized or reshaped to reduce cell overlap within the new layout. In this way, the new layout comprises related cells, bound by one or more group bounding boxes, that are placed within the new layout according to a configuration that mitigates wire length and timing delay of the integrated circuit. | 03-13-2014 |
20140089883 | AREA EFFICIENT POWER SWITCH - A method of generating an area efficient power switch cell includes receiving, by a cell library design tool, a specification of a power switch circuit to be established as a power switch cell in a cell library. The cell library design tool also receives one or more attributes of the power switch cell including a height of the cell boundary and receiving, by the cell library design tool, a layout placement constraint requiring the power switch cell to be placed in a semiconductor layout so as to bridge two parallel rows of doped wells. The parallel rows of doped wells are interleaved with doped substrate and the doping of the wells is of a different type than that of the substrate. Based on the specification of the power switch circuit, the one or more attributes, and the layout placement constraint, the cell library design tool generates the power switch cell. | 03-27-2014 |
20140109033 | INTEGRATED CIRCUIT LAYOUT - A layout of a portion of an integrated circuit includes first and second cell structures, each including a first or second dummy gate electrode disposed on a first or second boundary of the corresponding first or second cell structure, a first or second edge gate electrode disposed adjacent to the corresponding first or second dummy gate electrode, and a first or second oxide definition (OD) region having a first or second edge. The second boundary faces the first boundary without abutting the first boundary. The first edge of the first OD region is substantially aligned with the closest edge of the first dummy gate electrode or overlaps the first dummy gate electrode. A distance from the first edge gate electrode to the farthest edge of the first dummy gate electrode is greater than the distance from the first edge gate electrode to the first edge of the first OD region. | 04-17-2014 |
20140115554 | METHOD OF GENERATING A LAYOUT OF AN INTEGRATED CIRCUIT COMPRISING BOTH STANDARD CELLS AND AT LEAST ONE MEMORY INSTANCE - A method of generating a layout of an integrated circuit is disclosed, the layout incorporating both standard cells and at least one memory instance generated by a memory compiler to define a memory device of the integrated circuit. Input data is received specifying one or more properties of a desired memory instance. The memory compiler generates the desired memory instance based on the input data and using the specified memory architecture. A standard cell library is provided. The memory compiler references at least one property of the standard cell library in order to generate the desired memory instance. The layout is then generated by populating standard cell rows with standard cells selected from the standard cell library in order to provide the functional components required by the integrated circuit, and integrating into the layout the desired memory instance provided by the memory compiler. | 04-24-2014 |
20140123091 | HIERARCHICAL DESIGN OF INTEGRATED CIRCUITS WITH MULTI-PATTERNING REQUIREMENTS - Systems and methods for avoiding restrictions on cell placement in a hierarchical design of integrated circuits with multi-patterning requirements are described. The method may be provided implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to assign a color to each pattern shape in a first cell, assign a color to each pattern shape in a second cell, characterize quantities of interest for each pattern shape in the first cell, determine that the colors assigned in the first cell are all one to one mappable to the colors assigned in the second cells, characterize quantities of interest for each pattern shape in the second cell using the quantities of interest characterized for the first cell, and model the quantities of interest for the first cell and the second cell. | 05-01-2014 |
20140123092 | METHOD AND SYSTEM FOR ESTIMATING A DIFFUSION POTENTIAL OF A DIFFUSIVE PROPERTY - Methods, systems, and techniques for estimating a transient diffusion potential of a diffusive property involve modeling, as a circuit, diffusive behavior of a diffusion region and then simulating operation of the circuit to estimate the transient diffusion potential at a location in the diffusion region by determining circuit potential at a node in the circuit that corresponds to the location in the diffusion region. The circuit has steady-state and transient portions that model the steady-state and transient behavior of the diffusion region, respectively. The transient behavior is modeled using a capacitive circuit element. The diffusive property diffuses linearly within the diffusion region and generation of the diffusive property is distributed within the diffusion region. | 05-01-2014 |
20140130004 | INTEGRATED CIRCUIT SCHEMATICS HAVING IMBEDDED SCALING INFORMATION FOR GENERATING A DESIGN INSTANCE - A non-transitory computer-readable memory including first data representative of a topology of a circuit including a first circuit element and a second circuit element, and second data representative of a scaling rule for the first circuit element as a function of the second circuit element. A data processing method comprising retrieving first data representative of a topology of a circuit comprising a first circuit element and a second circuit element from a memory, retrieving second data representative of a scaling rule for the first circuit element as a function of the second circuit element from the memory, receiving a user input representative of a scaling factor, generating third data representative of an instance of the second circuit element using the scaling factor, and generating data representative of an instance of the first circuit element using the scaling factor, the scaling rule and the third data. | 05-08-2014 |
20140137066 | CIRCUIT LAYOUT ADJUSTING METHOD - A circuit layout adjusting method is provided. A data file is generated according to a circuit board engineering drawing. The dada file includes at least one parameter of the circuit board engineering drawing. The data file is imported to a circuit layout drawing. At least one corresponding parameter of the circuit layout drawing are adjusted according to the data file. | 05-15-2014 |
20140149957 | STRUCTURED PLACEMENT OF LATCHES/FLIP-FLOPS TO MINIMIZE CLOCK POWER IN HIGH-PERFORMANCE DESIGNS - A latch placement tool determines a shape for a cluster of latches from a preliminary layout (or based on a netlist), including an aspect ratio of the shape, and generates a template for placement of the latches in conformity with the shape. Latches are placed around a local clock buffer (LCB) based on latch size, from largest latch first to smallest latch last, and based on their ideal locations given the target aspect ratio. The ideal locations may be further based on the clock driver pin configuration of the LCB. The final template preferably has an aspect ratio that is approximately equal to the aspect ratio of the shape of the cluster, but the latch placement may be constrained by clock routing topology. Latch placement within a cluster can be further optimized by swapping one of the latches with another to minimize total wirelength of the design. | 05-29-2014 |
20140165020 | METHOD OF FORMING A LAYOUT INCLUDING CELLS HAVING DIFFERENT THRESHOLD VOLTAGES, A SYSTEM OF IMPLEMENTING AND A LAYOUT FORMED - A method including developing a circuit schematic diagram, the circuit schematic diagram including a plurality of cells. The method further includes generating cell placement rules for the plurality of cells based on the circuit schematic diagram and developing a circuit layout diagram for the plurality of cells based on the cell placement rules. The method further includes grouping the plurality of cells of the circuit layout diagram based on threshold voltages and inserting threshold voltage compliant fillers into the circuit layout diagram. A system for implementing the method is described. A layout formed by the method is also described. | 06-12-2014 |
20140181774 | NON-INTEGER HEIGHT STANDARD CELL LIBRARY - A standard cell library for designing integrated circuits is provided. In some aspects, the standard cell library includes a plurality of standard cells having a cell height that is a non-integer multiple of a wiring pitch of routing tracks associated with the standard cell library. The standard cell library further includes a plurality of landing pins for connecting to the routing tracks arranged in the plurality of standard cells, wherein each of the plurality of landing pins is extended by half of the wiring pitch in opposite directions orthogonal to an orientation of the routing tracks. | 06-26-2014 |
20140181775 | UNIT CAPACITOR MODULE, AUTOMATIC CAPACITOR LAYOUT METHOD THEREOF AND AUTOMATIC CAPACITOR LAYOUT DEVICE THEREOF - A unit capacitor module for automatic capacitor-layout, includes a capacitor unit; at least one first connecting port, coupled to a first side of the capacitor unit; at least one second connecting port, coupled to a second side of the capacitor unit; at least one third connecting port, coupled to a third side of the capacitor unit; and at least one fourth connecting port, coupled to a fourth side of the capacitor unit; wherein the number of first connecting ports equals the number of second connecting ports, and the first connecting port and the second connecting port are symmetrical; and the number of third connecting ports equals the number of fourth connecting ports, and the third connecting port and the fourth connecting port are symmetrical. | 06-26-2014 |
20140195997 | METHOD AND LAYOUT OF AN INTEGRATED CIRCUIT - An integrated circuit layout includes a P-type active region, an N-type active region, a first metal connection, a second metal connection and a plurality of trunks. The plurality of trunks is formed substantially side-by-side, and in parallel with each other. The first metal connection is substantially disposed over the P-type active region, and is electrically connected with drain regions of PMOS transistors in the P-type active region. The second metal connection is substantially disposed over the N-type active region, and is electrically connected with drain regions of NMOS transistors in the N-type active region. The plurality of trunks is electrically connected with and is substantially perpendicular to the first metal connection and the second metal connection. A first trunk of the plurality of trunks has a width wider than a width of other trunks of the plurality of trunks and is arranged to be located between two groups of trunks. | 07-10-2014 |
20140208284 | METHOD AND SYSTEM FOR DESIGNING 3D SEMICONDUCTOR PACKAGE - A three-dimensional semiconductor package and method for making the same include providing a first package layout parameter for a plurality of first terminals included in a first package, a second package layout parameter for a plurality of second terminals included in a second package disposed above or below the first package, and a connection terminal layout parameter for a plurality of connection terminals electrically connecting the first package and the second package; providing a first wiring connection layout between the first and second terminals and the connection terminals by applying a first process to the first package, second package, and connection terminal layout parameters; and providing a second wiring connection layout between the first and second terminals and the connection terminals by applying a second process, which is different from the first process, to the first wiring connection layout. | 07-24-2014 |
20140245248 | Cell and Macro Placement on Fin Grid - A die includes at least one standard cell, which includes a first boundary and a second boundary opposite to the first boundary. The first boundary and the second boundary are parallel to a first direction. The at least one standard cell further includes a first plurality of FinFETs including first semiconductor fins parallel to the first direction. The die further includes at least one memory macro, which has a third boundary and a fourth boundary opposite to the third boundary. The third boundary and the fourth boundary are parallel to the first direction. The at least one memory macro includes a second plurality of FinFETs including second semiconductor fins parallel to the first direction. All semiconductor fins in the at least one standard cell and the at least one memory macro have pitches equal to integer times of a minimum pitch of the first and the second semiconductor fins. | 08-28-2014 |
20140258961 | Stretch Dummy Cell Insertion in FinFET Process - A method embodiment includes identifying an empty region in an integrated circuit (IC) layout, wherein the empty region is a region not including any active fins and outside a minimum spacing boundary, applying a grid map over the empty region, wherein the grid map comprises a plurality of grids inside the empty region, and filling the empty region with a plurality of dummy fin cells by placing a dummy fin cell in each of the plurality of grids, wherein applying the grid map and filling the empty region is performed using a computer. | 09-11-2014 |
20140258962 | Parasitic Capacitance Extraction for FinFETs - A method includes generating a three-dimensional table. The table cells of the three-dimensional table comprise normalized parasitic capacitance values selected from the group consisting essentially of normalized poly-to-fin parasitic capacitance values and normalized poly-to-metal-contact parasitic capacitance values of Fin Field-Effect Transistors (FinFETs). The three-dimensional table is indexed by poly-to-metal-contact spacings of the FinFETs, fin-to-fin spacings of the FinFETs, and metal-contact-to-second-poly spacings of the FinFETs. The step of generating the three-dimensional table is performed using a computer. | 09-11-2014 |
20140282339 | AUTOMATIC TAP DRIVER GENERATION IN A HYBRID CLOCK DISTRIBUTION SYSTEM - A hybrid clock distribution system uses a distribution fabric to distribute clock signals across longer physical distances and local sub-distribution networks to distribute clock signals more locally and to implement logic functions such as clock gating. A set of tap drivers connect the distribution fabric to the sub-distribution networks. A design tool automatically generates and places the set of tap drivers. | 09-18-2014 |
20140282340 | METHOD FOR PROVISIONING DECOUPLING CAPACITANCE IN AN INTEGRATED CIRCUIT - A method of provisioning an integrated circuit with decoupling capacitance includes identifying in an initial design of the integrated circuit lacking decoupling elements, a standard cell instance satisfying a transient power or frequency switching criteria. Based on a transient power characteristic of the standard cell instance, a decoupling capacitance requirement for the standard cell instance is determined. The decoupling capacitance requirement indicates a capacitance sufficient to bring the standard cell instance into compliance with a stability constraint on a supply voltage node of the standard cell instance. A decoupling capacitor satisfying the decoupling capacitance requirement is provisioned by appending an appropriate sized decap transistor having one or more gate electrode elements to the standard cell instance. The size of the decap transistor may be derived from the required decoupling capacitance, the amount of decoupling capacitance contributed by each gate electrode element, and the area required for each gate electrode element. | 09-18-2014 |
20140282341 | FLEXIBLE PATTERN-ORIENTED 3D PROFILE FOR ADVANCED PROCESS NODES - The present disclosure relates to a method of RC extraction that provides for a fast development time and easy maintenance. In some embodiments, the method provides a graphical representation of an integrated chip layout having a plurality of integrated chip components. A plurality of pattern based graphical features are then determined. Respective pattern based graphical features define a structural aspect of an integrated chip component. One of the plurality of integrated chip components is defined as a pattern oriented function having inputs of one or more of the pattern based graphical features. The pattern oriented function determines a shape of the one of the plurality of integrated chip components based upon a relation between the plurality of inputs. By determining a shape of an integrated chip component using a pattern oriented function, the complexity of RC profiles can be reduced. | 09-18-2014 |
20140282342 | SYSTEMS AND METHODS FOR TUNING TECHNOLOGY FILES - A method generally comprises arranging a plurality of layer combinations into a plurality of groups such that each of the layer combinations is assigned to at least one group. A shifting analysis is performed on a plurality of benchmark circuits for each of the groups. At least one tuning vector value is calculated based, at least in part, on a plurality of criteria vectors of the benchmark circuits. A shift is applied on each of the groups by the tuning vector value and a technology file, such as a 2.5 dimensional RC techfile, is regenerated. | 09-18-2014 |
20140282343 | PRIORITIZED SOFT CONSTRAINT SOLVING - A design problem can include a mixture of hard constraints and soft constraints. The soft constraints can be prioritized and the design problem solved. One or more soft constraints may not be honored in the midst of the solving of the design problem. Debugging can be performed and the unsatisfied soft constraints identified. Root-cause analysis can evaluate the challenges within the design problem which caused soft constraints not to be honored. | 09-18-2014 |
20140289691 | CIRCUIT DESIGN SUPPORT APPARATUS, CIRCUIT DESIGN SUPPORT METHOD, AND COMPUTER PRODUCT - A circuit design support apparatus includes a processor that is configured to generate area information that indicates a plurality of areas obtained by dividing a predetermined area in a circuit by a constant interval; generate first layout data that indicates arrangement of buffer cells capable of supplying clock signals to other cells, at least one buffer cell being disposed in each of the areas indicated by the area information; generate based on the first layout data, second layout data that indicates arrangement of the buffer cells and arrangement of flip-flop cells disposed in the predetermined area; and output the second layout data. | 09-25-2014 |
20140289692 | ELEMENT REMOVAL DESIGN IN MICROWAVE FILTERS - A method of designing a microwave filter using a computerized filter optimizer, comprises generating a filter circuit design in process (DIP) comprising a plurality of circuit elements having a plurality of resonant elements and one or more non-resonant elements, optimizing the DIP by inputting the DIP into the computerized filter optimizer, determining that one of the plurality of circuit elements in the DIP is insignificant, removing the one insignificant circuit element from the DIP, deriving a final filter circuit design from the DIP, and manufacturing the microwave filter based on the final filter circuit design. | 09-25-2014 |
20140304672 | Hierarchical Testing Architecture Using Core Circuit with Pseudo-Interfaces - A core circuit that can be connected in a hierarchical manner, and configured to test a multiple circuits is disclosed. The core circuit includes at least one real input for receiving scan-in data for controlling operation of the core circuit. The core circuit further includes an input register coupled to the at least one real input and configured to store data. The core circuit further includes at least one scan chain coupled a subset if registers of the register chain and configured to generate scan-out data representing the presence of faults in an circuit. Furthermore, the core circuit includes at least one control pseudo-output coupled to the input register and configured to route at least a subset of the data to another register chain in the core circuit or to another core circuit. | 10-09-2014 |
20140304673 | INTEGRATED CIRCUIT DESIGN SYSTEM - A design system for designing an integrated circuit, and the design system includes a processor and a computer readable medium embodying computer program code. The computer program code includes instructions executable by the processor and configured to cause the processor to: modify a circuit design of the integrated circuit to compensate for an impact of layout parameters of the circuit design; generate at least one recommended layout parameter of an integrated circuit device within the integrated circuit; calculate a circuit performance parameter of the integrated circuit using the at least one recommended layout parameter; and generate a layout design of the modified circuit design of the integrated circuit according to the at least one recommended layout parameter. | 10-09-2014 |
20140317586 | SUPPORT DEVICE, DESIGN SUPPORT METHOD, AND COMPUTER-READABLE RECORDING MEDIUM - A design support device includes placement determination unit, logic extraction unit, and logic placement unit. The placement determination unit performs the process of determining the optimum position of a first terminal of a first cell as a first position in which the inter-terminal wiring between the first cell and a second cell connected to the first cell through the first terminal is short. Furthermore, the logic placement unit performs the process of extracting one or more logical blocks including a logical block having the first terminal from the first cell, and arranging one or more logical blocks so that the first terminal may become close to the first position. | 10-23-2014 |
20140344771 | OPTICAL SEMICONDUCTOR DEVICE, SOCKET, AND OPTICAL SEMICONDUCTOR UNIT - An optical semiconductor unit of the present invention has an LED device provided with an LED (Light Emitting Diode) and a socket to which the LED device is mounted, the LED device has a main body to which the LED is mounted, the main body has a first surface to which block-shaped electrode portions are connected. | 11-20-2014 |
20140359548 | ORTHOGONAL CIRCUIT ELEMENT ROUTING - Various embodiments include computer-implemented methods, computer program products and systems for aligning a set of orthogonal circuit elements in an integrated circuit (IC) layout. In some embodiments, a computer-implemented method for aligning a set of orthogonal circuit elements in an IC layout includes: classifying each orthogonal circuit element in the set of orthogonal circuit elements as including a first space-designated edge and a second space-designated edge; and aligning each orthogonal circuit element on an edge placement grid according to the first space-designated edge and the second space-designated edge, the edge placement grid having a first set of space-designated grid lines separated by a first distance, and a second set of space-designated grid lines separated by a second distance, wherein the first set of space-designated grid lines is separated from the second set of space-designated grid lines by an offset distance. | 12-04-2014 |
20150052493 | METHOD OF GENERATING A SIMULATION MODEL OF A PREDEFINED FABRICATION PROCESS - A method of generating a simulation model of a predefined fabrication process according to a sample conductive feature includes receiving a geometry configuration and layout design of the conductive feature. A circuit-level simulation model of the sample conductive feature based on the geometry configuration of the sample conductive feature is generated. A hardware processor converts the circuit-level simulation model of the sample conductive feature into at least a first layout bias rule corresponding to a first set of predetermined criteria of the layout design and a second layout bias rule, different from the first layout bias rule, corresponding to a second set of predetermined criteria of the layout design. | 02-19-2015 |
20150067629 | DIAGNOSIS AND DEBUG USING TRUNCATED SIMULATION - Patterns used to detect a failure in a semiconductor chip are analyzed to determine a subset of logic in a design where a semiconductor chip, fabricated based on the design, contains a fault in the subset. Parts of the semiconductor chip can be pre-calculated to identify a key subsection of logic, based on the patterns, with that subsection being stored in a computer readable file. Good-machine simulation is performed on the subsection of logic using truncated rank-ordered simulation. The results are compared to the results of the testing of the physical semiconductor chip. | 03-05-2015 |
20150095869 | METHOD OF MAKING SEMICONDUCTOR DEVICE AND A CONTROL SYSTEM FOR PERFORMING THE SAME - A method of making a semiconductor device includes arranging a first cell and a second cell, determining, by a processor, a first pattern density of a first cell, determining a second pattern density of a second cell, determining a pattern density gradient from the first pattern density to the second pattern density, determining whether the pattern density gradient exceeds a pattern density gradient threshold, and indicating a design change if the pattern density gradient exceeds than the pattern density gradient threshold. | 04-02-2015 |
20150095870 | Methods for Double-Patterning-Compliant Standard Cell Design - A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells. | 04-02-2015 |
20150113494 | AUTOMATED RESIDUAL MATERIAL DETECTION - Methods, systems, and structures for detecting residual material on semiconductor wafers are provided. A method includes scanning a test structure including topographic features on a surface of a semiconductor wafer. The method further includes determining, based on the scanning, that the test structure includes an amount of a residual material of a sacrificial layer that exceeds a predetermined threshold. | 04-23-2015 |
20150113495 | DESIGN STRUCTURE FOR LOGIC CIRCUIT AND SERIALIZER-DESERIALIZER STACK - Serializer-deserializer (SERDES) and integrated circuit package including a package substrate, first and second SERDES dies having a SERDES circuit, and a logic die having a logic circuit. The SERDES circuit communicatively connected to the package substrate. The first and second SERDES dies positioned adjacent, in a plane, and disposed on the package substrate. The logic circuit communicatively connected to the SERDES circuit and to the package substrate. The logic die stacked vertically and disposed on the first and second SERDES dies. A method of assembling a SERDES and integrated circuit package including providing a SERDES structure selected from a menu of SERDES die and SERDES circuit combinations. A design structure of a SERDES and integrated circuit package including a package substrate, first and second SERDES dies having a SERDES circuit, and a logic die having a logic circuit. The SERDES circuit communicatively connected to the package substrate. | 04-23-2015 |
20150128101 | PROMOTING EFFICIENT CELL USAGE TO BOOST QOR IN AUTOMATED DESIGN - A method of designing integrated circuits includes forming a restricted cell library from a first cell library by selecting only those cells in the first cell library that are most efficient according to predetermined efficiency criteria and executing an integrated circuit design operation in an electronic design automation program while directing the electronic design automation program to make cell selections exclusively from the restricted cell library. The integrated circuit design operation is one that can be directed to make cell selections from any of the cells in the first cell library without changing its essential purpose. The method improves QoR for the resulting circuit design. | 05-07-2015 |
20150143322 | SWITCH CELL - A designer uses an option device to switch one or more signal flows in a schematic design to create different versions for the same design. Currently, there is no related automatic tool for the automatic placement of option devices. In various embodiments, option device instances are used to decide option device positions. Option devices can be automatically placed and routing considered and adjusted as needed. | 05-21-2015 |
20150149977 | PARTITIONING METHOD AND SYSTEM FOR 3D IC - A method comprises: receiving a circuit design comprising networks of first devices fabricated by a first fabrication process; selecting second devices to be fabricated by a second process; substituting the second devices for the first devices in the networks of the circuit design; sorting the second devices within a selected one of the networks by device area from largest device area to smallest device area; and assigning each second device in the selected network to be fabricated in a respective one of a plurality of tiers of a 3D IC for which a total area of second devices previously assigned to that tier is smallest, the second devices being assigned sequentially according to the sorting. | 05-28-2015 |
20150294059 | DESIGN SUPPORT APPARATUS AND DESIGN SUPPORT METHOD - A non-transitory computer-readable recording medium having stored therein a program for causing a computer to execute a process is provided. The process includes calculating and outputting difficulty degrees on an index basis when a change instruction to change an arrangement of parts is received with respect to parts and wirings on a substrate in a design diagram, the difficulty degrees being related to the wiring between the parts after the change according to the change instruction; and calculating and outputting difficulty degrees on an index basis when a change instruction to change the wiring between the parts is received, the difficulty degrees being related to the wiring between the parts after the change according to the change instruction. | 10-15-2015 |
20150331985 | Area Optimized Driver Layout - A computerized method for designing a layout of a driver includes analyzing a schematic circuit. PMOSFETs coupled between first common nodes are grouped into one or more first classes. NMOSFETs coupled between second common nodes are grouped into one or more second classes. The method further includes generating the layout for each MOSFET at each location in a layout area of the driver by generating a super parameterized cell (PCELL) layout block comprising a master MOSFET PCELL and a master guard ring PCELL for each of the first class and the second class. The master MOSFET PCELL includes a first set of parameters for the MOSFET and the master guard ring PCELL includes a second set of parameters for the guard ring around the MOSFET. A child PCELL of the master MOSFET PCELL and the master guard ring PCELL are instantiated at each location in the layout area. | 11-19-2015 |
20150339425 | CONTACT WINDOW ARRANGING APPARATUS AND CONTACT WINDOW ARRANGING METHOD THEREOF - A contact window arranging apparatus and a contact window arranging method thereof are provided. A first contact window arrangement number and a second contact window arrangement number respectively corresponding to a first boundary and a second boundary are determined according to a first preset distance, and a third contact window arrangement number and a fourth contact window arrangement number respectively corresponding to the first boundary and the second boundary are determined according to a second preset distance, so as to select a total contact window arrangement number with more contact windows. Through taking a horizontal center line and a vertical center line of a rectangular area as benchmarks the contact windows are arranged in a manner corresponding to the total contact window arrangement number. | 11-26-2015 |
20150356224 | METHOD AND CONTROL DEVICE FOR CIRCUIT LAYOUT MIGRATION - A method for circuit layout migration comprises creating a list of layout components in a source layout; determining a plurality of first groups of layout components being regularly aligned horizontally or vertically; determining first subsets of layout components which each belong to at least two of a respective set of determined first groups; determining a plurality of second groups of layout components, each second group comprising mutually exclusive ones of the first subsets of layout components; determining symmetry axes for pairs of second groups; building a constraint graph of the layout components of the source layout using alignment constraints for the alignment of layout components within each of the second groups and distance constraints for preserving a regularity pattern within each of the second groups and symmetry constraints for the determined symmetry axes for pairs of second groups; and performing constraint-graph-based compaction of the source layout. | 12-10-2015 |
20150356235 | GENERATING A SEMICONDUCTOR COMPONENT LAYOUT - A method includes generating a first set of configurations of a layout of semiconductor components. The configurations of the first set of configurations each satisfy a first sub-set of a set of design rules. The method also includes generating a second set of configurations of the layout of semiconductor components. The second set of configurations are generated by eliminating one or more configurations of the first set of configurations based on a determination that the eliminated one or more configurations of the first set of configurations fail to satisfy a second sub-set of the set of design rules. The method further includes manufacturing a semiconductor device having semiconductor components arranged based on one of the configurations of the second set of configurations. | 12-10-2015 |
20160004806 | COMPUTER IMPLEMENTED METHOD FOR PERFORMING EXTRACTION - A computer implemented method for performing extraction is provided in the present invention. First, a layout of a semiconductor circuit having a resistor is imported by using a computer wherein a device region is defined in the layout and the resistor is located within the device region. Next, the device region of the layout are extracted, and a compensation value of Rs (Rc) is obtained according to the extracting step. An adjustment process is performed according to Rc to obtained a refined R value. | 01-07-2016 |
20160012171 | Tool and Method for Refining A Circuit Including Parametric Analog Elements | 01-14-2016 |
20160034630 | AREA EFFICIENT POWER SWITCH - A method of generating an area efficient power switch cell includes receiving, by a cell library design tool, a specification of a power switch circuit to be established as a power switch cell in a cell library. The cell library design tool also receives one or more attributes of the power switch cell including a height of the cell boundary and receiving, by the cell library design tool, a layout placement constraint requiring the power switch cell to be placed in a semiconductor layout so as to bridge two parallel rows of doped wells. The parallel rows of doped wells are interleaved with doped substrate and the doping of the wells is of a different type than that of the substrate. Based on the specification of the power switch circuit, the one or more attributes, and the layout placement constraint, the cell library design tool generates the power switch cell. | 02-04-2016 |
20160042109 | ACTIVE REGION DESIGN LAYOUT - The integrated circuit (IC) device includes a substrate, an isolation feature, a first gate structure, a second gate structure, a first contact feature and a first supplementary active region. The isolation feature is disposed in the substrate, and the isolation feature defines a boundary between a first active region and a second active region of the substrate. The first gate structure is disposed over the first active region. The second gate structure is disposed over the second active region. The first contact feature is disposed over the first active region, in which a portion of the first active region is disposed between the first gate structure and the isolation feature. The first supplementary active region is disposed adjacent to the portion of the first active region, in which a thickness of the first supplementary active region is substantially in a range from 5 nm to 10 nm. | 02-11-2016 |
20160048629 | AUTOMATIC GENERATION OF TEST LAYOUTS FOR TESTING A DESIGN RULE CHECKING TOOL - A method of automatically generating a set of test layouts for testing a design rule checking tool is described. A layout is a point in a space of several coordinates, and the design rule comprises N design constraints numbered 1 to N, wherein N is greater or equal two and each design constraint is a boolean-valued function of one or more of the coordinates. The set of test layouts includes: one or more zero-error layouts; one or more one-error layouts; and one or more two-error layouts. A zero-error layout is a layout that satisfies all of the design constraints. A one-error layout is a layout that violates exactly one of the design constraints. A two-error layout is a layout that violates exactly two of the design constraints. | 02-18-2016 |
20160055285 | METHODS OF GENERATING INTEGRATED CIRCUIT LAYOUT USING STANDARD CELL LIBRARY - Methods of generating an integrated circuit layout include forming a standard cell by providing a first active area adjacent to a first cell boundary line. The first active area is spaced apart from the first cell boundary line by a first distance. A second active area is provided adjacent to a second cell boundary line. The second cell boundary line opposes the first cell boundary line. The second active area is spaced apart from the second cell boundary line by a second distance. Fins are formed on the first and second active areas. The fins extend in a first direction and parallel to one another in a second direction substantially perpendicular to the first direction. The first cell boundary line is parallel to the fins. The first distance and the second distance remain constant when a number of the fins on the first and second active areas is changed. | 02-25-2016 |
20160063167 | METHOD AND SYSTEM FOR VIA RETARGETING - Embodiments of the present invention provide a system and method for SAV (self-aligned via) retargeting. The SAV (Self Aligned Vias) process aids in the alignment of the vias with the metal above (Mx+1) during the dual damascene process. The retargeting enables an increase the area of the via during photolithography without affecting the final critical dimension. SAV retargeting is the via retargeting during the mask tape-out to reshape the via and protect it against possible via-to-Mx+1 overlay error. With embodiments of the present invention, the via edge movement is linked to the actual driver behind the SAV retargeting, which is maintaining a minimum area coverage with the metal above at extreme overlay error conditions. Accordingly, for a via edge to get SAV retargeted, a calculation is first made to determine how much its opposite via edge is subject to be cut during SAV due to overlay error. | 03-03-2016 |
20160078165 | IC PHYSICAL DESIGN USING A TILING ENGINE - In general, embodiments of the present invention provide systems, methods and computer readable media for generating a tiling for a physical placement of a plurality of circuits. The method includes generating a tiling including a plurality of tiles, where each tile identifies a tile geometric area, and a list of one or more of the circuits to be placed in the tile geometric area. The tiling is based on a description of one or more user constraints, where each user constraint identifies a constraint geometric area, and a characteristic of circuits to be placed in the constraint geometric area. | 03-17-2016 |
20160085897 | METHOD OF DESIGNING LAYOUT OF SEMICONDUCTOR DEVICE - A method of designing a layout of a semiconductor device includes receiving information on a size of a target chip and a unit placement width for forming a gate line through a self-align double patterning process by a layout design system. The method also includes allocating an input and output area, a hard macro area, and a standard cell area at the target chip, and adjusting a width of the standard cell area by applying a gate generation rule for setting a width of at least one cell row located in the standard cell area to an odd number multiple of the unit placement width. The unit placement width corresponds to a width between centers of a pair of gate lines in the self-align double patterning process. | 03-24-2016 |
20160103940 | METHOD OF GENERATING A TARGET LAYOUT ON THE BASIS OF A SOURCE LAYOUT - Generating a target layout of an integrated circuit includes providing a source layout comprising one or more source pcells having one or more shapes; providing a set of connectivity constraints for connecting each shape of each source pcell to none, one, or more other components of the integrated circuit; for each shape of each source pcell, determining a corresponding target shape having a contour composed of edges with defined lengths, inserting none, one, or more edges into the contour of the shape, or into the contour of the corresponding target shape, determining a corresponding edge of the corresponding target shape; for each edge, defining an edge length constraint for constraining the edge to have the length of the edge of the corresponding target shape; applying a legalization procedure to the source layout based on the connectivity constraints, the target design constraints, and the edge length constraints. | 04-14-2016 |
20160125116 | METHODOLOGY USING FIN-FET TRANSISTORS - A computer implemented method for designing a circuit is presented. The method includes forming, using the computer, a multitude of cells, each cell characterized by at least first and second boundaries positioned along a first direction, and a plurality of first shapes extending along the first direction. Each first shape is spaced, along a second direction substantially orthogonal to the first direction, from a neighboring first shape in accordance with a first pitch. The first and second boundaries are further positioned in accordance with an integer multiple of the first pitch when the computer is invoked to form the plurality of cells representing the circuit. | 05-05-2016 |
20160147926 | METHOD AND SYSTEM OF FORMING LAYOUT DESIGN - A method of forming a layout design for fabricating an integrated circuit is disclosed. The method includes identifying a line pattern of a first set of grid lines with respect to a second set of grid lines within a region of the layout design; and placing a k-th standard cell layout of the K standard cell layouts at the region of the layout design if the line pattern is determined to match a k-th predetermined line pattern of K predetermined line patterns. K is an integer equal to or greater than two, and k is an order index ranging from 1 to K. The region of the layout design is sized to fit one of K different standard cell layouts corresponding to a same standard cell functionality. | 05-26-2016 |
20160157355 | Design Support System, Design Support Method and Design Support Program | 06-02-2016 |
20160188787 | SOLID-STATE IMAGING DEVICE, LAYOUT DATA GENERATING DEVICE AND LAYOUT DATA GENERATING METHOD - A solid-state imaging device includes pixels respectively having photoelectric conversion units and arranged in matrix in basic pattern units, and an optical member arranged on the incidence side of incident light than the pixels and having constituent elements respectively corresponding to the pixels. The pixels include first, second and third wavelength range light pixels. Each basic pattern is comprised of a combined arrangement pattern of the wavelength range light pixels. Misregistration constituent elements with the occurrence of misregistration exist in the constituent elements. The misregistration increases toward the misregistration constituent elements separated from a center position of a pixel array of the pixels. The misregistration of the misregistration constituent element for the first wavelength range light pixel and that of the misregistration constituent element for the third wavelength range light pixel are smaller and larger than that of the misregistration constituent element for the second wavelength range light pixel, respectively. | 06-30-2016 |
20190147133 | VARIANT CELL HEIGHT INTEGRATED CIRCUIT DESIGN | 05-16-2019 |