| Entries |
| Document | Title | Date |
|---|
| 20080220596 | Delivery of Low Pressure Dopant Gas to a High Voltage Ion Source - A system for delivery of low-pressure dopant gas to a high-voltage ion source in the doping of semiconductor substrates, in which undesired ionization of the gas is suppressed prior to entry into the high-voltage ion source, by modulating electron energy upstream of the high-voltage ion source so that electron acceleration effects are reduced to below a level supporting an electronic ionization cascade. The gas delivery system in a specific application includes a gas flow passage, a voltage generator electrically coupled with at least a portion of the gas flow passage to impose an electric field thereon, and an obstructive structure that is deployed to modulate acceleration length of electrons of the low-pressure gas in relation to ionization potential of the gas, to suppress ionization in the gas flow passage. | 09-11-2008 |
| 20080261384 | METHOD OF REMOVING PHOTORESIST LAYER AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE USING THE SAME - A method of removing a photoresist layer is provided. An ion implantation process has been performed on the photoresist layer to transform a surface of the photoresist layer to a crust and a soft photoresist layer remains within the crust. The method includes performing a first removing step to remove the crust, such that the soft photoresist layer is exposed. Thereafter, a second removing step is performed to remove the soft photoresist layer. The first and the second removing steps are performed in difference chambers, and a temperature for performing the first removing step is lower than that for performing the second removing step and lower than a gasification temperature of a solvent in the soft photoresist layer. | 10-23-2008 |
| 20080305620 | METHODS OF FORMING DEVICES INCLUDING DIFFERENT GATE INSULATING LAYERS ON PMOS/NMOS REGIONS - Provided is a method of manufacturing a semiconductor device, in which the thickness of a gate insulating layer of a CMOS device can be controlled. The method can include selectively injecting fluorine (F) into a first region on a substrate and avoiding injecting the fluorine (F) into a second region on the substrate. A first gate insulating layer is formed of oxynitride layers on the first and second regions to have first and second thicknesses, respectively, where the first thickness is less than the second thickness. A second gate insulating layer is formed on the first gate insulating layer and a gate electrode pattern is formed on the second gate insulating layer. | 12-11-2008 |
| 20090017604 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device is provided. The method for fabricating the semiconductor device comprises providing a substrate. Under an atmosphere containing a fluoride nitride compound, a plasma treatment process is performed to simultaneously fluorinate and nitrify a surface of the substrate. Thereafter, a dielectric layer is formed on the substrate. | 01-15-2009 |
| 20090053879 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device includes providing a semiconductor substrate in which a gate insulating layer and a pad layer are formed in an active region. A first trench is formed in an isolation region of the substrate. A passivation film is formed to cover the pad layer and fill the first trench. A second trench is formed by patterning the pad layer and removing an exposed semiconductor substrate, the second trench being formed within the first trench. An ion implantation process is performed on the semiconductor substrate exposed through the second trench. | 02-26-2009 |
| 20090087969 | METHOD TO IMPROVE A COPPER/DIELECTRIC INTERFACE IN SEMICONDUCTOR DEVICES - Embodiments of methods for improving a copper/dielectric interface in semiconductor devices are generally described herein. Other embodiments may be described and claimed. | 04-02-2009 |
| 20090087970 | Method of producing a dopant gas species - This invention relates to a method of producing B | 04-02-2009 |
| 20090111251 | EXPOSURE MASK AND METHOD FOR FABRICATING THIN-FILM TRANSISTOR - An exposure mask includes a transparent substrate; a first pattern portion formed on the transparent substrate using at least one light-shielding pattern having a predetermined shape; and a translucent layer which is formed at a section including a first pattern region having the first pattern portion, which allows exposure light to pass therethrough, and which has a transmittance greater than that of the light-shielding pattern. | 04-30-2009 |
| 20090124068 | Non-Uniformly Doped High Voltage Drain-Extended Transistor and Method of Manufacture Thereof - The present invention provides, in one embodiment, a transistor ( | 05-14-2009 |
| 20090181527 | Graphite Member for Beam-Line Internal Member of Ion Implantation Apparatus - The problem of the present invention is to provide, in high current-low energy type ion implantation apparatuses, a graphite member for a beam line inner member of an ion implantation apparatus, which graphite member can markedly reduce particles incorporated in a wafer surface. This problem can be solved by the graphite member of the present invention, which is a graphite member for a beam line inner member of an ion implantation apparatus, which member having a bulk density of not less than 1.80 Mg/m | 07-16-2009 |
| 20090203199 | ION BEAM IRRADIATING APPARATUS, AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE - An ion beam irradiating apparatus has a field emission electron source | 08-13-2009 |
| 20090280629 | INTEGRATED CIRCUIT SYSTEM EMPLOYING GRAIN SIZE ENLARGEMENT - An integrated circuit system that includes: providing a substrate including an active device with a gate top surface exposed; implanting a dopant within the gate to alter the grain size of the gate material; forming a dielectric layer over the active device and the substrate; and annealing the integrated circuit system to transfer the stress of the dielectric layer into the active device. | 11-12-2009 |
| 20090291547 | Method for Reducing Plasma Discharge Damage During Processing - A semiconductor process and apparatus to provide a way to reduce plasma-induced damage by applying a patterned layer of photoresist ( | 11-26-2009 |
| 20090305489 | MULTILAYER ELECTROSTATIC CHUCK WAFER PLATEN - This layered assembly utilizes two-piece construction, with an electrically nonconductive layer and a thermally conductive layer. Rather than using metal, the thermally conductive layer is made from a composite material, having both metal and a CTE modifying agent. This composite material may a coefficient of thermal expansion close to or identical to that of the nonconductive layer, thereby eliminating many of the drawbacks of the prior art. In one embodiment, the composite material is a mixture of aluminum and carbon (or graphite) fiber. In a further embodiment, one or more fluid conduits are placed in the mold before the layer is cast. These conduits serve as the fluid passageways in the electrostatic chuck. In another embodiment, the composite material is a mixture of a semiconductor material, such as silicon, and aluminum where the conduits are formed by machining and bonding. | 12-10-2009 |
| 20090317964 | PLATEN FOR REDUCING PARTICLE CONTAMINATION ON A SUBSTRATE AND A METHOD THEREOF - Techniques for reducing particle contamination on a substrate are disclosed. In one particular exemplary embodiment, the technique may be realized with a platen having different regions, where the pressure levels in the regions may be substantially equal. For example, the platen may comprise a platen body comprising first and second recesses, the first recess defining a fluid region for holding fluid for maintaining a temperature of the substrate at a desired temperature, the second recess defining a first cavity for holding a ground circuit; a first via defined in the platen body, the first via having first and second openings, the first opening proximate to the fluid region and the second opening proximate to the first cavity, wherein pressure level of the fluid region may be maintained at a level that is substantially equal to pressure level of the first cavity. | 12-24-2009 |
| 20100029071 | METHOD OF FORMING SEMICONDUCTOR DEVICES CONTAINING METAL CAP LAYERS - Embodiments of methods for improving electrical leakage performance and minimizing electromigration in semiconductor devices containing metal cap layers are generally described herein. According to one embodiment, a method of forming a semiconductor device includes planarizing a top surface of a workpiece to form a substantially planar surface with conductive paths and dielectric regions, forming metal cap layers on the conductive paths, and exposing the top surface of the workpiece to a dopant source from a gas cluster ion beam (GCIB) to form doped metal cap layers on the conductive paths and doped dielectric layers on the dielectric regions. According to some embodiments the metal cap layers and the doped metal cap layers contain a noble metal selected from Pt, Au, Ru, Rh, Ir, and Pd. | 02-04-2010 |
| 20100035420 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes a first step of forming an ion implantation mask on a portion of a surface of a semiconductor; a second step of implanting ions of a first dopant into at least a portion of an exposed region of the surface of the semiconductor other than the region where the ion implantation mask is formed, to form a first dopant implantation region; a third step of, after forming the first dopant implantation region, removing a portion of the ion implantation mask to increase the exposed region of the surface of the semiconductor; and a fourth step of implanting ions of a second dopant into at least a portion of the increased exposed region of the surface of the semiconductor to form a second dopant implantation region. | 02-11-2010 |
| 20100035421 | SEMICONDUCTOR WELL IMPLANTED THROUGH PARTIALLY BLOCKING MATERIAL PATTERN - A method for forming a partially blocking layer for an ion implantation process, which may be varied across the IC to form regions with different dopant concentrations, and regions with varying dopant concentrations in each contiguously implanted region, is disclosed. One or more temporary and/or permanent layers may form the partially blocking layer, including a combination of different materials such as polysilicon, silicon dioxide, silicon nitride, and photoresist. The partially blocking layer may be a uniform continuous sheet which transmits a uniform fraction of dopants, or a reticulated screen which transmits dopants through multiple open areas. Several partially blocking layers, each absorbing a different fraction of implanted dopants, may be formed on an IC to produce instances of a component with different performance parameters such as operation voltage, sheet resistance or gain. | 02-11-2010 |
| 20100055886 | SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film. | 03-04-2010 |
| 20100093160 | METHODS OF FORMING NANO-DEVICES USING NANOSTRUCTURES HAVING SELF-ASSEMBLY CHARACTERISTICS - Provided are methods of forming nano-devices. One of the methods includes forming a nano-scale self-assembly material layer on a substrate formed of at least one layer, forming a mask layer on the self-assembly material layer, performing a surface treatment process on the substrate using the mask layer as a mask, and removing the self-assembly material layer. | 04-15-2010 |
| 20100099243 | METHOD FOR FORMING DIODE IN PHASE CHANGE RANDOM ACCESS MEMORY DEVICE - A method for forming a diode of a phase change random access memory device includes preparing a semiconductor substrate having a dopant area formed thereon. An insulating layer on the semiconductor substrate is formed and a contact hole is formed by etching a part of the insulating layer such that a specific region of the dopant area is exposed. A silicon layer doped with a first-type dopant is formed in the contact hole. A part of the silicon layer is doped with a second-type dopant source gas through a gas cluster ion beam process. | 04-22-2010 |
| 20100159680 | Method for Manufacturing Semiconductor Device - A method for manufacturing a semiconductor device is disclosed. The method includes the steps of forming a nitride film on a semiconductor substrate, forming a photoresist pattern on the nitride film, the photoresist pattern exposing a portion of the semiconductor substrate, implanting in a portion of the semiconductor substrate using the photoresist pattern as a mask, removing the photoresist pattern by ashing and/or stripping, washing the resulting structure to remove photoresist pattern splinters, fragments or particles on the nitride film, and removing the nitride film by wet etching. | 06-24-2010 |
| 20100178757 | PROCESS SIMULATION METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND PROCESS SIMULATOR - A process simulation method includes: converting condition data of plasma doping for introducing an impurity into a semiconductor in a plasma atmosphere to corresponding condition data of ion implantation for implanting impurities as an ion beam into the semiconductor; and calculating device structure data on the basis of the ion implantation condition data converted from the plasma doping condition data. | 07-15-2010 |
| 20100197124 | Methods of Forming Semiconductor Devices Using Plasma Dehydrogenation and Devices Formed Thereby - A semiconductor integrated circuit device with enhanced reliability is provided. The semiconductor integrated circuit device includes a semiconductor substrate; a gate insulation film that is provided on the semiconductor substrate; a gate electrode that is provided on the gate insulation film; and a sidewall spacer that is provided on side walls of the gate insulation film and the gate electrode and includes, wherein the sidewall spacer has a first sidewall spacer in contact with the gate electrode and a second sidewall spacer formed on the side walls of the first sidewall spacer, and a ratio of an Si—OH area to an Si—O area in at least one of the first and second sidewall spacers is 0.05 or less, as measured by Fourier Transform InfraRed (FTIR). | 08-05-2010 |
| 20100197125 | TECHNIQUE FOR PROCESSING A SUBSTRATE - An improved technique for processing a substrate is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for processing a substrate. The method may comprise ion implanting a substrate disposed downstream of the ion source with ions generated in an ion source; and disposing a first portion of a mask in front of the substrate to expose the first portion of the mask to the ions, the mask being supported by the first and second mask holders, the mask further comprising a second portion wound in the first mask holder. | 08-05-2010 |
| 20100240200 | SUBSTRATE PROCESSING SYSTEM AND SUBSTRATE PROCESSING METHOD - A substrate processing system includes a processing chamber that performs a preset process on a plurality of substrates in a batch-type manner; a substrate mounting table, installed within the processing chamber, configured to mount the plurality of substrates on a concentric circle and configured to be rotatable forward and backward; substrate accommodation units configured to accommodate the plurality of substrates in multi-stages in a vertical direction; substrate holders and configured to transfer the substrates between the substrate accommodation units and the processing chamber; elevating mechanisms configured to move the substrate accommodation units up and down. Unprocessed substrates are mounted on the substrate mounting table while the substrate mounting table is being rotated in one direction. After the completion of the processing of the substrates, unloading of processed substrates and loading of new unprocessed substrates are performed while the substrate mounting table is rotated in the another direction. | 09-23-2010 |
| 20100267225 | Method of manufacturing semiconductor device - A method of manufacturing a semiconductor device, the method including forming a photoresist film on a substrate, and removing the photoresist film from the substrate using a composition that includes a sulfuric acid solution, a hydrogen peroxide solution, and a corrosion inhibitor. | 10-21-2010 |
| 20100273321 | WET SOLUBLE LITHOGRAPHY - A system to form a wet soluble lithography layer on a semiconductor substrate includes providing the substrate, depositing a first layer comprising a first material on the substrate, and depositing a second layer comprising a second material on the substrate. In an embodiment, the first material comprises a different composition than the second material and one of the first layer and the second layer includes silicon. | 10-28-2010 |
| 20100304554 | PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE - In a production method for a semiconductor device relating to the present invention, first, a pattern of a resist film made of organic polymers is formed on a semiconductor substrate. Next, impurity ions with 1×10 | 12-02-2010 |
| 20100330787 | APPARATUS AND METHOD FOR ULTRA-SHALLOW IMPLANTATION IN A SEMICONDUCTOR DEVICE - Methods and devices for forming an ultra-thin doping layer in a semiconductor substrate include introducing a thin film of a dopant onto a surface of the substrate and driving at least a portion of the thin dopant layer into a surface of the semiconductor. Gas ions used in the driving-in process may be inert to minimize contamination during the drive in process. The thin films can be deposited using know methods, such as physical deposition and atomic layer deposition. The dopant layers can be driven into the surface of the semiconductor using known techniques, such as pulsed plasma discharge and ion beam. In some embodiments, a standard ion implanter can be retrofit to include a deposition source. | 12-30-2010 |
| 20100330788 | THIN WAFER HANDLING STRUCTURE AND METHOD - A thin wafer handling structure includes a semiconductor wafer, a release layer that can be released by applying energy, an adhesive layer that can be removed by a solvent, and a carrier, where the release layer is applied on the carrier by coating or laminating, the adhesive layer is applied on the semiconductor wafer by coating or laminating, and the semiconductor wafer and the carrier is bonded together with the release layer and the adhesive layer in between. The method includes applying a release layer on a carrier, applying an adhesive layer on a semiconductor wafer, bonding the carrier and the semiconductor wafer, releasing the carrier by applying energy on the release layer, e.g. UV or laser, and cleaning the semiconductor's surface by a solvent to remove any residue of the adhesive layer. | 12-30-2010 |
| 20110034012 | PATTERNING METHOD AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - In one embodiment, a patterning method is disclosed. The method includes applying an uncured imprint material containing a first curing agent and a second curing agent onto a substrate. The method includes pressing a template against the imprint material. The method includes reacting the first curing agent with the template pressed against the imprint material. The method includes stripping the template from the imprint material. In addition, the method includes reacting the second curing agent. | 02-10-2011 |
| 20110086499 | METHOD FOR REMOVING PHOTORESIST - A method for removing a photoresist is disclosed. First, a substrate including a patterned photoresist is provided. Second, an ion implantation is carried out on the substrate. Then, a non-oxidative pre-treatment is carried out on the substrate. The non-oxidative pre-treatment provides hydrogen, a carrier gas and plasma. Later, a photoresist-stripping step is carried out so that the photoresist can be completely removed. | 04-14-2011 |
| 20110086500 | IMPURITY IMPLANTATION METHOD AND ION IMPLANTATION APPARATUS - An impurity is implanted by ion implantation into an object to be processed. The ion implantation is performed using an ion beam which is diverged after being temporarily converged. | 04-14-2011 |
| 20110086501 | Technique for Processing a Substrate Having a Non-Planar Surface - A method of processing a substrate having horizontal and non-horizontal surfaces is disclosed. The substrate is implanted with particles using an ion implanter. During the ion implant, due to the nature of the implant process, a film may be deposited on the surfaces, wherein the thickness of this film is thicker on the horizontal surfaces. The presences of this film may adversely alter the properties of the substrate. To rectify this, a second process step is performed to remove the film deposited on the horizontal surfaces. In some embodiments, an etching process is used to remove this film. In some embodiments, a material modifying step is used to change the composition of the material comprising the film. This material modifying step may be instead of, or in addition to the etching process. | 04-14-2011 |
| 20110117733 | Methods Of Utilizing Block Copolymers To Form Patterns - Some embodiments include methods of forming patterns utilizing copolymer. A copolymer composition is formed across a substrate. The composition includes subunits A and B, and will be self-assembled to form core structures spaced center-to-center by a distance of L | 05-19-2011 |
| 20110159670 | Method and Apparatus of Patterning a Semiconductor Device - Provided is a photoresist that includes a polymer having a backbone that is breakable and a photo acid generator that is free of bonding from the polymer. Further, provided is a method of fabricating a semiconductor device. The method includes providing a device substrate. A material layer is formed over the substrate. A photoresist material is formed over the material layer. The photoresist material has a polymer that includes a backbone. The photoresist material is patterned to form a patterned photoresist layer. A fabrication process is then performed to the material layer, wherein the patterned photoresist layer serves as a mask in the fabrication process. Thereafter, the patterned photoresist layer is treated in a manner that breaks the backbone of the polymer. The patterned photoresist layer is then removed. | 06-30-2011 |
| 20110159671 | ISOTOPICALLY-ENRICHED BORON-CONTAINING COMPOUNDS, AND METHODS OF MAKING AND USING SAME - An isotopically-enriched, boron-containing compound comprising two or more boron atoms and at least one fluorine atom, wherein at least one of the boron atoms contains a desired isotope of boron in a concentration or ratio greater than a natural abundance concentration or ratio thereof. The compound may have a chemical formula of B | 06-30-2011 |
| 20110183503 | SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - There is disclosed a substrate processing apparatus including a processing chamber housing a substrate, pipes for supplying gas into the processing chamber, and heaters provided in the middle of the pipes, and heating the gas. In the substrate processing apparatus, the heaters heat the gas to a temperature lower than a temperature at which exhaust gas is generated from the pipes to dry the substrate in the heated gas. | 07-28-2011 |
| 20110207308 | TECHNIQUE FOR LOW-TEMPERATURE ION IMPLANTATION - A technique for low-temperature ion implantation is disclosed. In one particular exemplary embodiment, the technique may be realized as an apparatus for low-temperature ion implantation. The apparatus may comprise a pre-chill station located in proximity to an end station in an ion implanter; a cooling mechanism within the pre-chill station configured to cool a wafer from ambient temperature to a predetermined range less than ambient temperature; a loading assembly coupled to the pre-chill station and the end station; and a controller in communication with the loading assembly and the cooling mechanism to coordinate loading a wafer into the pre-chill station, cooling the wafer down to the predetermined temperature range before any ion implantation into the wafer, and loading the cooled wafer into the end station where the cooled wafer undergoes an ion implantation process. | 08-25-2011 |
| 20110207309 | SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes forming a mask layer on a first-conductivity-type semiconductor substrate, etching the semiconductor substrate using the mask layer as a mask, thereby forming a projecting semiconductor layer, forming a first insulating layer on the semiconductor substrate to cover a lower portion of the projecting semiconductor layer, doping a first-conductivity-type impurity into the first insulating layer, thereby forming a high-impurity-concentration layer in the lower portion of the projecting semiconductor layer, forming gate insulating films on side surfaces of the projecting semiconductor layer which upwardly extend from an upper surface of the first insulating layer, and forming a gate electrode on the gate insulating films and on the first insulating film. | 08-25-2011 |
| 20110212607 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming junction area for a bit line contact (BLC) and a junction area for a storage node contact (SNC) by performing ion implantation in a substrate having a buried gate; forming a first insulation pattern having an opening to expose the junction areas; forming a buffer layer to fill the openings; forming a second insulation pattern over the first insulation pattern after filling the openings, wherein the second insulation pattern has openings to expose the buffer layer in an area of the buffer layer that lies over the junction area for the SNC; and forming an SNC to fill the opening of the second insulation patterns. | 09-01-2011 |
| 20110212608 | Sputtering-Less Ultra-Low Energy Ion Implantation - Methods of implanting dopants into a silicon substrate using a predeposited sacrificial material layer with a defined thickness that is removed by sputtering effect is provided. | 09-01-2011 |
| 20110212609 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - Provided is a technology capable of improving a production yield of a semiconductor device having, for example, IGBG as a semiconductor element. After formation of an interconnect on the surface side of a semiconductor substrate, a supporting substrate covering the interconnect is bonded onto the interconnect. Then, a BG tape is overlapped and bonded onto the supporting substrate and the semiconductor substrate is ground from the backside. The BG tape is then peeled off and an impurity is introduced into the backside of the semiconductor substrate by ion implantation. Then, the supporting substrate is peeled off, followed by heat treatment of the semiconductor substrate. | 09-01-2011 |
| 20110250740 | METHOD AND DEVICE FOR THE TREATMENT OF A SEMICONDUCTOR SUBSTRATE - Method for the treatment of a semiconductor substrate ( | 10-13-2011 |
| 20110275202 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD - A semiconductor device in one embodiment has a first connection region, a second connection region and a semiconductor volume arranged between the first and second connection regions. Provision is made, within the semiconductor volume, in the vicinity of the second connection region, of a field stop zone for spatially delimiting a space charge zone that can be formed in the semiconductor volume, and of an anode region adjoining the first connection region. The dopant concentration profile within the semiconductor volume is configured such that the integral of the ionized dopant charge over the semiconductor volume, proceeding from an interface of the anode region which faces the second connection region, in the direction of the second connection region, reaches a quantity of charge corresponding to the breakdown charge of the semiconductor device only near the interface of the field stop zone which faces the second connection region. | 11-10-2011 |
| 20120015508 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - Provided is a method of manufacturing a semiconductor device capable of preventing a relative displacement of the positions between a range where impurity ions are injected and a range where charged particles are injected. The method of manufacturing the semiconductor device includes: irradiating impurity ions in a state in which a mask is disposed between an impurity ion irradiation apparatus and a semiconductor substrate; and irradiating charged particles to form a short carrier lifetime region, in a state in which the mask is disposed between a charged particle irradiation apparatus and the semiconductor substrate. A relative positional relationship between the mask and the semiconductor substrate is not changed from a beginning of one of the irradiating the impurity ions and the irradiating the charged particles to a completion of both of the irradiating the impurity ions and the irradiating the charged particles. | 01-19-2012 |
| 20120015509 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor device includes forming junction area for a bit line contact (BLC) and a junction area for a storage node contact (SNC) by performing ion implantation in a substrate having a buried gate; forming a first insulation pattern having an opening to expose the junction areas; forming a buffer layer to fill the openings; forming a second insulation pattern over the first insulation pattern after filling the openings, wherein the second insulation pattern has openings to expose the buffer layer in an area of the buffer layer that lies over the junction area for the SNC; and forming an SNC to fill the opening of the second insulation patterns. | 01-19-2012 |
| 20120064705 | VAPORIZER - Vapor delivery systems and methods that control the heating and flow of vapors from solid feed material, especially material that comprises cluster molecules for semiconductor manufacture. The systems and methods safely and effectively conduct the vapor to a point of utilization, especially to an ion source for ion implantation. Ion beam implantation is shown employing ions from the cluster materials. The vapor delivery system includes reactive gas cleaning of the ion source, control systems and protocols, wide dynamic range flow-control systems and vaporizer selections that are efficient and safe. Borane, decarborane, carboranes, carbon clusters and other large molecules are vaporized for ion implantation. Such systems are shown cooperating with novel vaporizers, ion sources, and reactive cleaning systems. | 03-15-2012 |
| 20120064706 | SEMICONDCUTOR DEVICE AND METHOD OF PRODUCING THE SAME - A semiconductor device is provided in which a semiconductor substrate can be prevented from being broken while elements can be prevented from being destroyed by a snap-back phenomenon. After an MOS gate structure is formed in a front surface of an FZ wafer, a rear surface of the FZ wafer is ground. Then, the ground surface is irradiated with protons and irradiated with two kinds of laser beams different in wavelength simultaneously to thereby form an N | 03-15-2012 |
| 20120108043 | PATTERN FORMING PROCESS - A resist pattern is formed by coating a first positive resist composition comprising a polymer comprising 20-100 mol % of aromatic group-containing recurring units and adapted to turn alkali soluble under the action of an acid onto a substrate to form a first resist film, coating a second positive resist composition comprising a C | 05-03-2012 |
| 20120108044 | ISOTOPICALLY-ENRICHED BORON-CONTAINING COMPOUNDS, AND METHODS OF MAKING AND USING SAME - An isotopically-enriched, boron-containing compound comprising two or more boron atoms and at least one fluorine atom, wherein at least one of the boron atoms contains a desired isotope of boron in a concentration or ratio greater than a natural abundance concentration or ratio thereof. The compound may have a chemical formula of B | 05-03-2012 |
| 20120129326 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes the steps of: preparing a substrate made of silicon carbide; forming, on one main surface of the substrate, a detection film having a light transmittance different from that of silicon carbide; confirming presence of the substrate by applying light to the detection film; and forming an active region in the substrate whose presence has been confirmed. | 05-24-2012 |
| 20120142175 | DUAL SPACER FORMATION IN FLASH MEMORY - A method and manufacture for memory device fabrication is provided. In one embodiment, at least one oxide-nitride spacer is formed as follows. An oxide layer is deposited over a flash memory device such that the deposited oxide layer is at least 250 Angstroms thick. The flash memory device includes a substrate and dense array of word line gates with gaps between each of the word lines gate in the dense array. Also, the deposited oxide layer is deposited such that it completely gap-fills the gaps between the word line gates of the dense array of word line gates. Next, a nitride layer is depositing over the oxide layer. Then, the nitride layer is etched until the at least a portion of the oxide layer is exposed. Next, the oxide layer is etched until at least a portion of the substrate is exposed. | 06-07-2012 |
| 20120149180 | COMBINATORIAL PROCESS SYSTEM - A combinatorial processing chamber is provided. The combinatorial processing chamber is configured to isolate a radial portion of a rotatable substrate support, which in turn is configured to support a substrate. The chamber includes a plurality of clusters process heads in one embodiment. An insert having a base plate disposed between the substrate support and the process heads defines a confinement region for a deposition process in one embodiment. The base plate has an opening to enable access of the deposition material to the substrate. Through rotation of the substrate and movement of the opening, multiple regions of the substrate are accessible for performing combinatorial processing on a single substrate. | 06-14-2012 |
| 20120220112 | POSITIVE RESIST COMPOSITION AND PATTERNING PROCESS - A positive resist composition based on a polymer comprising recurring units of (meth)acrylate having a cyclic acid labile group and a dihydroxynaphthalene novolak resin, and containing a photoacid generator is improved in resolution, step coverage and adhesion on a highly reflective stepped substrate, has high resolution, and forms a pattern of good profile and minimal edge roughness through exposure and development. | 08-30-2012 |
| 20120231617 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a MOSFET includes the steps of preparing a substrate with an epitaxial growth layer made of silicon carbide, performing ion implantation into the substrate with the epitaxial growth layer, forming a protective film made of silicon dioxide on the substrate with the epitaxial growth layer into which the ion implantation was performed, and heating the substrate with the epitaxial growth layer on which the protective film was formed to a temperature range of 1600° C. or more in an atmosphere containing gas including an oxygen atom. | 09-13-2012 |
| 20120244690 | ION IMPLANTED RESIST STRIP WITH SUPERACID - According to certain embodiments, a resist is placed over the surface of a semiconductor structure, wherein the resist covers a portion of the semiconductor structure. Dopants are implanted into the semiconductor structure using an ion implantation beam in regions of the semiconductor structure not covered by the resist. Due to exposure to the ion implantation beam, at least a portion of the resist is converted by exposure to the ion beam to contain an inorganic carbonized material. The semiconductor structure with resist is contacted with a superacid composition containing a superacid species to remove the resist containing inorganic carbonized materials from the semiconductor structure. | 09-27-2012 |
| 20120244691 | ION IMPLANTATION METHOD AND ION IMPLANTATION APPARATUS - An ion implantation method includes reciprocally scanning an ion beam, mechanically scanning a wafer in a direction perpendicular to the ion beam scanning direction, implanting ions into the wafer, and generating an ion implantation amount distribution in a wafer surface of an isotropic concentric circle shape for correcting non-uniformity in the wafer surface in other semiconductor manufacturing processes, by controlling a beam scanning speed in the ion beam scanning direction and a wafer scanning speed in the mechanical scanning direction at the same time and independently using the respective control functions defining speed correction amounts. | 09-27-2012 |
| 20120252194 | ION IMPLANTATION METHOD AND ION IMPLANTATION APPARATUS - An ion implantation method includes reciprocally scanning an ion beam, mechanically scanning a wafer in a direction perpendicular to a beam scanning direction, and implanting ions into the wafer. The wafer is divided into a plurality of implantation regions, a beam scanning speed in the beam scanning direction is set to be varied for each of the implantation regions, an ion implantation amount distribution for each of the implantation regions is controlled by changing and controlling the beam scanning speed, and the ion implantation amount for each of the implantation regions is controlled and a beam scanning frequency and a beam scanning amplitude in the control of the beam scanning speed for each of the implantation regions is made to be constant by setting a wafer mechanical scanning speed and controlling the wafer mechanical scanning speed for each of the implantation regions. | 10-04-2012 |
| 20120252195 | ION IMPLANTATION SYSTEM AND METHOD - An ion implantation system and method, providing cooling of dopant gas in the dopant gas feed line, to combat heating and decomposition of the dopant gas by arc chamber heat generation, e.g., using boron source materials such as B2F4 or other alternatives to BF3. Various arc chamber thermal management arrangements are described, as well as modification of plasma properties, specific flow arrangements, cleaning processes, power management, eqillibrium shifting, optimization of extraction optics, detection of deposits in flow passages, and source life optimization, to achieve efficient operation of the ion implantation system. | 10-04-2012 |
| 20120276723 | ION INJECTION SIMULATION METHOD, ION INJECTION SIMULATION DEVICE, METHOD OF PRODUCING SEMICONDUCTOR DEVICE, AND METHOD OF DESIGNING SEMICONDUCTOR DEVICE - An ion injection simulation method includes: calculating a reinjection dose injected into a substrate and a structure formed on the substrate and reinjected from a side face of the structure; and calculating concentration distribution of impurities injected into the substrate from a distribution function and reinjection conditions of the reinjection dose. | 11-01-2012 |
| 20120302049 | METHOD FOR IMPLANTING WAFER - The disclosure provides a method for wafer implantation including the following steps: providing a wafer, wherein the wafer comprises a central circular portion, and a peripheral annular portion adjacent to a edge of the wafer, and wherein the central circular portion and the peripheral annular portion are concentric; and implanting ion beams into the wafer, wherein the central circular portion has a first average implantation dose and the peripheral annular portion has a second average implantation dose, and the first average implantation dose and the second first average implantation dose are different. | 11-29-2012 |
| 20120322247 | METHOD FOR FABRICATING HIGH VOLTAGE TRANSISTOR - A method for fabricating a high voltage transistor includes the following steps. Firstly, a substrate is provided. A first sacrificial oxide layer and a hard mask layer are sequentially formed over the substrate. The hard mask layer is removed, thereby exposing the first sacrificial oxide layer. Then, a second sacrificial oxide layer is formed on the first sacrificial oxide layer. Afterwards, an ion-implanting process is performed to introduce a dopant into the substrate through the second sacrificial oxide layer and the first sacrificial oxide layer, thereby producing a high voltage first-type field region of the high voltage transistor. | 12-20-2012 |
| 20120322248 | ION IMPLANTATION APPARATUS AND ION IMPLANTATION METHOD - An ion implantation method in which an ion beam is scanned in a beam scanning direction and a wafer is mechanically scanned in a direction perpendicular to the beam scanning direction, includes setting a wafer rotation angle with respect to the ion beam so as to be varied, wherein a set angle of the wafer rotation angle is changed in a stepwise manner so as to implant ions into the wafer at each set angle, and wherein a wafer scanning region length is set to be varied, and, at the same time, a beam scanning speed of the ion beam is changed, in ion implantation at each set angle in a plurality of ion implantation operations during one rotation of the wafer, such that the ions are implanted into the wafer and dose amount non-uniformity in a wafer surface in other semiconductor manufacturing processes is corrected. | 12-20-2012 |
| 20120329256 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND ION IMPLANTER - According to an embodiment, a method of manufacturing a semiconductor device is provided. This method of manufacturing a semiconductor device sets a first voltage to be applied to an electrode configured to extract an ion beam from an ion source, and a second voltage to be applied to a decelerator through which an ion beam extracted from the ion source is to pass, on the basis of a second impurity profile which is formed in a substrate by neutral particles included in the ion beam. | 12-27-2012 |
| 20130005126 | APPLICATION OF CLUSTER BEAM IMPLANTATION FOR FABRICATING THRESHOLD VOLTAGE ADJUSTED FETS - Semiconductor structures including a high k gate dielectric material that has at least one surface threshold voltage adjusting region located within 3 nm or less from an upper surface of the high k gate dielectric are provided. The at least one surface threshold voltage adjusting region is formed by a cluster beam implant step in which at least one threshold voltage adjusting impurity is formed directly within the high k gate dielectric or driven in from an overlying threshold voltage adjusting material which is subsequently removed from the structure following the cluster beam implant step. | 01-03-2013 |
| 20130012007 | METHODS OF IMPLANTING DOPANT IONS - Methods of implanting dopant ions in a substrate include depositing a sacrificial material on a substrate. Dopant ions are implanted into the substrate while sputtering the sacrificial material, without substantially sputtering the substrate. Substantially no sacrificial material remains on the substrate after the implanting of the dopant ions. Some methods include forming a sacrificial material over a substrate, and implanting dopant ions into the substrate while removing substantially all the sacrificial material from the substrate. Substantially no sputtering of the substrate occurs during the implanting of the dopant ions. Methods of doping a substrate include implanting dopant ions into a substrate having a sacrificial material thereon, and sputtering the sacrificial material while implanting the dopant ions without substantially sputtering the substrate. Substantially no sacrificial material remains on the substrate after implanting the dopant ions. | 01-10-2013 |
| 20130045591 | NEGATIVE TONE DEVELOP PROCESS WITH PHOTORESIST DOPING - A method of semiconductor processing includes coating a top surface of a substrate having a semiconductor surface with a positive photoresist layer. The positive photoresist layer is exposed using a reticle or a mask that defines a pattern. The positive photoresist layer is doped by introducing at least one material modifying species after exposing. The positive photoresist layer is developed with a negative tone developer to form a patterned positive photoresist layer which provides masked portions of the top surface and unmasked portions of the top surface. A selective process is then performed to the unmasked portions of the top surface. | 02-21-2013 |
| 20130045592 | METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE AND DEVICE FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE - A method for manufacturing a SiC semiconductor device includes: a step of forming an oxide film on a surface of a SiC substrate; and a step of removing the oxide film. In the step of forming the oxide film, ozone gas is used. In the step of removing the oxide film, it is preferable to use halogen plasma or hydrogen plasma. In this way, problems associated with a chemical solution can be reduced while obtaining a method and device for manufacturing a SiC semiconductor device, by each of which a cleaning effect can be improved. | 02-21-2013 |
| 20130052812 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device, includes a wafer grinding step of, by means of a revolving grinding stone, forming a thinned portion in a wafer while at the same time forming a slope surrounding said thinned portion, wherein during said formation of said slope, said grinding stone is positioned so that there is always a space between said slope and the facing side of said grinding stone, wherein said thinned portion is thinner than a peripheral portion of said wafer, and wherein said slope extends along and defines an inner circumferential side of said peripheral portion and forms an angle of 75° or more but less than 90° with respect to a main surface of said wafer. The method of manufacturing a semiconductor device further includes a step of forming a semiconductor device in said thinned portion. | 02-28-2013 |
| 20130072008 | TECHNIQUE FOR ION IMPLANTING A TARGET - A technique for ion implanting a target is disclosed. In accordance with one exemplary embodiment, the technique may be realized as a method for ion implanting a target, the method comprising: providing a predetermined amount of processing gas in an arc chamber of an ion source, the processing gas containing implant species and implant species carrier, where the implant species carrier may be one of O and H; providing a predetermined amount of dilutant into the arc chamber, wherein the dilutant may comprise a noble species containing material; and ionizing the processing gas and the dilutant. | 03-21-2013 |
| 20130084694 | JUNCTION AVOIDANCE ON EDGES OF WORKPIECES - A method of implanting ions into a workpiece without the formation of junctions, which impact the performance of the workpiece, is disclosed. To counteract the effect of dopant being implanted into the edge of the workpiece, components made of material having an opposite conductivity are placed near the workpiece. As ions from the beam strike these components, ions from the material are sputtered. These ions have the opposite conductivity as the implanted ions, and therefore inhibit the formation of junctions. | 04-04-2013 |
| 20130095643 | METHODS FOR IMPLANTING DOPANT SPECIES IN A SUBSTRATE - Methods for processing a substrate are provided herein. In some embodiments, a method of processing a substrate may include implanting a dopant species into the one or more regions of the substrate using a first dopant precursor comprising a hydride of the dopant species; and implanting the dopant species into the one or more regions of the substrate using a second dopant precursor comprising fluorine and the dopant species. In some embodiments, the first and second dopant precursors may be provided simultaneously. In some embodiments, the first dopant precursor may be provided for a first time period, followed by providing the first dopant precursor and the second dopant precursor for a second period of time. In some embodiments, the flow of the first dopant precursor and the flow of the second dopant precursor may be alternated until a desired implant level is reached. | 04-18-2013 |
| 20130115764 | SUBSTRATE PROCESSING SYSTEM AND METHOD - A system for processing substrates has a vacuum enclosure and a processing chamber situated to process wafers in a processing zone inside the vacuum enclosure. Two rail assemblies are provided, one on each side of the processing zone. Two chuck arrays ride, each on one of the rail assemblies, such that each is cantilevered on one rail assemblies and support a plurality of chucks. The rail assemblies are coupled to an elevation mechanism that places the rails in upper position for processing and at lower position for returning the chuck assemblies for loading new wafers. A pickup head assembly loads wafers from a conveyor onto the chuck assemblies. The pickup head has plurality of electrostatic chucks that pick up the wafers from the front side of the wafers. Cooling channels in the processing chucks are used to create air cushion to assist in aligning the wafers when delivered by the pickup head. | 05-09-2013 |
| 20130130483 | ELECTRO-STATIC DISCHARGE PROTECTION DEVICE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING ELECTRO-STATIC DISCHARGE PROTECTION DEVICE - An electro-static discharge protection device including a gate electrode formed on a substrate. First and second diffusion regions of a first conductivity type are formed in the substrate with the gate electrode located in between. A first silicide layer is formed in the first diffusion region. A silicide block region is formed between the gate electrode and the first silicide layer. A third diffusion region is formed below the first silicide layer to partially overlap the first diffusion region. The third diffusion region and first silicide layer have substantially the same shapes and dimensions. The third diffusion region and a portion below the gate electrode located at the same depth as the third diffusion region contain impurities of a second conductivity type. The third diffusion region has an impurity concentration that is higher than that of the portion below the gate electrode. | 05-23-2013 |
| 20130130484 | ION IMPLANTER AND ION IMPLANT METHOD THEREOF - An ion implanter and an ion implant method are disclosed. Essentially, the wafer is moved along one direction and an aperture mechanism having an aperture is moved along another direction, so that the projected area of an ion beam filtered by the aperture is two-dimensionally scanned over the wafer. Thus, the required hardware and/or operation to move the wafer may be simplified. Further, when a ribbon ion beam is provided, the shape/size of the aperture may be similar to the size/shape of a traditional spot beam, so that a traditional two-dimensional scan may be achieved. Optionally, the ion beam path may be fixed without scanning the ion beam when the ion beam is to be implanted into the wafer, also the area of the aperture may be adjustable during a period of moving the aperture across the ion beam. | 05-23-2013 |
| 20130137251 | Uniform Shallow Trench Isolation Regions and the Method of Forming the Same - A method includes performing a plasma treatment on a first surface of a first material and a second surface of a second material simultaneously, wherein the first material is different from the second material. A third material is formed on treated first surface of the first material and on treated second surface of the second material. The first, the second, and the third materials may include a hard mask, a semiconductor material, and an oxide, respectively. | 05-30-2013 |
| 20130137252 | PATTERN FORMING METHOD - In a pattern forming method, a pattern having at least either a recess or a protrusion of a curable composition is formed of a curable composition by curing the curable composition into a cured film with a mold having a surface provided with at least either a recess or a protrusion, and separating the mold from the curable composition. The method includes (i) forming a gas generation region containing a gas generator agent so that the gas generation region will be disposed in contact with both the mold and the cured film between the mold and the cured film, (ii) generating a gas from the gas generation region, and (iii) separating the mold from the cured film during or after the step of (ii). | 05-30-2013 |
| 20130149848 | METHOD FOR MANUFACTURING VERTICAL-CHANNEL TUNNELING TRANSISTOR - The present invention belongs to the technical field of semiconductors and specifically relates to a method for manufacturing a vertical-channel tunneling transistor. In the present invention, the surrounding gate gate structure improves the control capacity of the gate and the source of narrow band gap material can enhance the device driving current. The method for manufacturing a vertical-channel tunneling transistor put forward by the present invention capable of controlling the channel length precisely features simple process, easy control and reduction of production cost. | 06-13-2013 |
| 20130171810 | METHODS OF FABRICATING SEMICONDUCTOR DEVICE USING HIGH-K LAYER FOR SPACER ETCH STOP AND RELATED DEVICES - Methods of fabricating a semiconductor device, and related devices, include forming a gate electrode on a substrate, forming a first buffer layer, a second buffer layer and a third buffer layer on side surfaces of the gate electrode and on the substrate near the gate electrode, forming a spacer covering the side surfaces of the gate electrode on the third buffer layer, the third buffer layer on the substrate being exposed, exposing the second buffer layer on the substrate by removing the exposed third buffer layer, exposing the first buffer layer on the substrate by removing the exposed second buffer layer, forming deep junction in the substrate using the spacer as a mask, and removing the spacer. The third buffer layer is a material layer having a higher dielectric constant than the second buffer layer. The spacer includes a material layer different than the third, second and first buffer layers. | 07-04-2013 |
| 20130183816 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, a method of manufacturing a semiconductor device is provided. In the method of manufacturing a semiconductor device, a first layer containing Si is formed on a semiconductor substrate. An impurity region and a non-impurity region are formed in the first layer by selectively diffusing an impurity into the first layer. A second layer containing a metal material is formed on the first layer. The metal material is diffused into the non-impurity region by annealing the second layer. | 07-18-2013 |
| 20130295753 | ION BEAM DIMENSION CONTROL FOR ION IMPLANTATION PROCESS AND APPARATUS, AND ADVANCED PROCESS CONTROL - A process control method is provided for ion implantation methods and apparatuses, to produce a high dosage area on a substrate such as may compensate for noted non-uniformities. In an ion implantation tool, separately controllable electrodes are provided as multiple sets of opposed electrodes disposed outside an ion beam. Beam blockers are positionable into the ion beam. Both the electrodes and beam blockers are controllable to reduce the area of the ion beam that is incident upon a substrate. The electrodes and beam blockers also change the position of the reduced-area ion beam incident upon the surface. The speed at which the substrate scans past the ion beam may be dynamically changed during the implantation process to produce various dosage concentrations in the substrate. | 11-07-2013 |
| 20130309851 | SILICON CARBIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR - In the manufacture of a silicon carbide semiconductor device having a termination region being a JTE region or FLR, the margin of the amount of etching for removing a damage layer formed in the surface of the termination region is enlarged. A silicon carbide semiconductor device has a termination region being a JTE (Junction Termination Extension) region or an FLR (Field Limiting Ring) at a termination of the semiconductor elements. The termination region is formed by one step of ion implantation in which the kind of impurity and the implant energy are fixed. In the impurity concentration profile of the termination region in the depth direction, the concentration peak in the shallowest position is in a position deeper than 0.35 μm from the surface, and the concentration in the surface portion is not more than one-tenth of the shallowest concentration peak. | 11-21-2013 |
| 20130330917 | APPARATUS AND PROCESS FOR INTEGRATED GAS BLENDING | 12-12-2013 |
| 20140011346 | CLUSTER ION IMPLANTATION OF ARSENIC AND PHOSPHORUS - An ion implantation method, in which a dopant source composition is ionized to form dopant ions, and the dopant ions are implanted in a substrate. The dopant source composition includes cluster phosphorus or cluster arsenic compounds, for achieving P- and/or As-doping, in the production of doped articles of manufacture, e.g., silicon wafers or precursor structures for manufacturing microelectronic devices. | 01-09-2014 |
| 20140073121 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A MOSFET includes a semiconductor substrate having a trench formed in a main surface, a gate oxide film, a gate electrode, and a source interconnection. A semiconductor substrate includes an n-type drift layer and a p-type body layer. The trench is formed to penetrate the body layer and to reach the drift layer. The trench includes an outer peripheral trench arranged to surround an active region when viewed two-dimensionally. On the main surface opposite to the active region when viewed from the outer peripheral trench, a potential fixing region where the body layer is exposed is formed. The source interconnection is arranged to lie over the active region when viewed two-dimensionally. The potential fixing region is electrically connected to the source interconnection. | 03-13-2014 |
| 20140099782 | METHOD AND APPARATUS FOR THERMAL CONTROL OF ION SOURCES AND SPUTTERING TARGETS - A method and apparatus are disclosed for controlling a semiconductor process temperature. In one embodiment a thermal control device includes a heat source and a housing comprising a vapor chamber coupled to the heat source. The vapor chamber includes an evaporator section and a condenser section. The evaporator section has a first wall associated with the heat source, the first wall having a wick for drawing a working fluid from a lower portion of the vapor chamber to the evaporator section. The condenser section coupled to a cooling element. The vapor chamber is configured to transfer heat from the heat source to the cooling element via continuous evaporation of the working fluid at the evaporator section and condensation of the working fluid at the condenser section. Other embodiments are disclosed and claimed. | 04-10-2014 |
| 20140099783 | METHOD OF ADDING AN ADDITIONAL MASK IN THE ION-IMPLANTATION PROCESS - The present invention discloses a method of adding an additional mask in the ion-implantation process. It relates to technical field of ion implantation. This invention comprises: a mask plate is added upon the said MPW and the nitrogen element is implanted in the said MPW; the implanted nitrogen element is used for amorphizing the upper surface of the MPW. The advantageous effects of the above technical solution are as follows: the steps of the production process are simplified; the ion implantation mask will achieve 4 different doping concentrations of the ion implantation when the wafer is implanted. It means that it is possible to form 4 different gate oxide layers of different in thickness. However, it is essential to apply the photomask three times to achieve the same effect in the process of prior art. Consequently, the method of the present invention can reduce both the cost and the term of production process. | 04-10-2014 |
| 20140134833 | ION IMPLANTATION APPARATUS AND ION IMPLANTATION METHOD - An ion implantation apparatus includes a beamline device for transporting ions from an ion source to an implantation processing chamber. The implantation processing chamber includes a workpiece holder for mechanically scanning a workpiece with respect to a beam irradiation region. The beamline device may be operated under a first implantation setting configuration suitable for transport of a low energy/high current beam for high-dose implantation into the workpiece, or a second implantation setting configuration suitable for transport of a high energy/low current beam for low-dose implantation into the workpiece. A beam center trajectory being a reference in a beamline is equal from the ion source to the implantation processing chamber in the first implantation setting configuration and the second implantation setting configuration. | 05-15-2014 |
| 20140134834 | Method of Fabricating Power Transistor with Protected Channel - A transistor includes a substrate, a well formed in the substrate, a drain including a first impurity region implanted in the well, a source including a second impurity region implanted in the well and spaced apart from the first impurity region, a channel for current flow from the drain to the source, and a gate to control a depletion region between the source and the drain. The channel has an intrinsic breakdown voltage, and the well, drain and source are configured to provide an extrinsic breakdown voltage lower than the intrinsic breakdown voltage and such that breakdown occurs in a breakdown region in the well located outside the channel and adjacent the drain or the source. | 05-15-2014 |
| 20140141604 | SYSTEMS AND METHODS FOR PREPARING FILMS USING SEQUENTIAL ION IMPLANTATION, AND FILMS FORMED USING SAME - Systems and methods for preparing films using sequential ion implantation, and films formed using same, are provided herein. A structure prepared using ion implantation may include a substrate; an embedded structure having pre-selected characteristics; and a film within or adjacent to the embedded structure and including ions having a perturbed arrangement arising from the presence of the embedded structure. The perturbed arrangement may include the ions being covalently bonded to each other, to the embedded structure, or to the substrate, whereas the ions instead may be free to diffuse through the substrate in the absence of the embedded structure. The embedded structure may inhibit or impede the ions from diffusing through the substrate, such that the ions instead covalently bond to each other, to the embedded structure, or to the substrate. The film may include, for example, diamond-like carbon, graphene, or SiC having a pre-selected phase. | 05-22-2014 |
| 20140179090 | STORAGE AND SUB-ATMOSPHERIC DELIVERY OF DOPANT COMPOSITIONS FOR CARBON ION IMPLANTATION - A supply source for delivery of a CO-containing dopant gas composition is provided. The composition includes a controlled amount of a diluent gas mixture such as xenon and hydrogen, which are each provided at controlled volumetric ratios to ensure optimal carbon ion implantation performance. The composition can be packaged as a dopant gas kit consisting of a CO-containing supply source and a diluent mixture supply source. Alternatively, the composition can be pre-mixed and introduced from a single source that can be actuated in response to a sub-atmospheric condition achieved along the discharge flow path to allow a controlled flow of the dopant mixture from the interior volume of the device into an ion source apparatus. | 06-26-2014 |
| 20140235042 | ION IMPLANTATION METHOD AND ION IMPLANTATION APPARATUS - An ion implantation method includes reciprocally scanning an ion beam, mechanically scanning a wafer in a direction perpendicular to the ion beam scanning direction, implanting ions into the wafer, and generating an ion implantation amount distribution in a wafer surface of an isotropic concentric circle shape for correcting non-uniformity in the wafer surface in other semiconductor manufacturing processes, by controlling a beam scanning speed in the ion beam scanning direction and a wafer scanning speed in the mechanical scanning direction at the same time and independently using the respective control functions defining speed correction amounts. | 08-21-2014 |
| 20140242786 | METHOD OF MANUFACTURING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE - According to one embodiment, a method includes forming first and second gate patterns each including a structure stacked in order of a first insulating layer, a floating gate layer, a charge trap layer, a second insulating layer and a dummy layer on a semiconductor layer, implanting impurities in the semiconductor layer by an ion implantation using the first and second gate patterns as a mask, forming a third insulating layer on the semiconductor layer, the third insulating layer covering side surfaces of the first and second gate patterns, and forming first and second concave portions, the first concave portion formed by removing the dummy layer of the first gate pattern, the second concave portion formed by removing the dummy layer, the second insulating layer, the charge trap layer and the floating gate layer of the second gate pattern. | 08-28-2014 |
| 20140242787 | PHOTOSENSITIVE RESIN COMPOSITION AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE - Disclosed is a photosensitive resin composition which exhibits positive or negative photosensitivity and is used as a mask in an ion implantation step, the photosensitive resin composition including, as a resin, (A) a polysiloxane. The photosensitive resin composition of the present invention has high heat resistance and is capable of controlling a pattern shape, and also has excellent ion implantation mask performance, thus enabling application to a low-cost high-temperature ion implantation process. | 08-28-2014 |
| 20140256122 | Methods And Apparatus For Carbon Ion Source Head - Methods and apparatus for a carbon ion source head. An ionization chamber is configured to receive a process gas containing carbon and a noble carrier gas; a cathode is disposed in the ionization chamber and configured to emit electrons in thermionic emission; a graphite coating is provided on at least a portion of the cathode; and an outlet on the ionization chamber is configured to output carbon ions. A method for ion implantation of carbon is disclosed. Additional alternative embodiments are disclosed. | 09-11-2014 |
| 20140273420 | ION IMPLANTATION - One or more techniques or systems for ion implantation are provided herein. A pressure control module is configured to maintain a substantially constant pressure within an ion implantation or process chamber. Pressure is maintained based on an attribute of an implant layer, pressure data, feedback, photo resist (PR) outgassing, a PR coating rate, a space charge effect associated with the implant layer, etc. By maintaining pressure within the process chamber, effects associated with PR outgassing are mitigated, thereby mitigating neutralization of ions. By maintaining charged ions, better control over implantation of the ions is achieved, thus allowing ions to be implanted at a desired depth. | 09-18-2014 |
| 20140295654 | METHOD OF FORMING AN INTEGRATED CIRCUIT - A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, the patterned mask layer having a plurality of first features with a first pitch. The method includes patterning the material layer by using the patterned mask layer as a mask to form the first features in the material layer. The method includes trimming the patterned mask layer, after patterning the material layer, to form a trimmed patterned mask layer. The method further includes introducing a plurality of dopants into the material layer exposed by the trimmed patterned mask layer to form doped regions having a second pitch, wherein the second pitch is different from the first pitch. The method further includes removing the trimmed patterned mask layer to expose un-doped regions in the material layer; and removing the un-doped regions to form a plurality of second features corresponding to the respective doped regions. | 10-02-2014 |
| 20140302667 | Method of Manufacturing a Semiconductor Device Including an Edge Area - A method of manufacturing a semiconductor device includes providing a doped layer containing a first dopant of a first conductivity type and forming a counter-doped zone in the doped layer in an edge area surrounding an element area of the semiconductor device. The counter-doped zone contains at least the first dopant and a second dopant of a second conductivity type which is the opposite of the first conductivity type. A concentration of the second dopant is at least 20% and at most 100% of the concentration of the first dopant. | 10-09-2014 |
| 20140302668 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An improvement is achieved in the performance of semiconductor device including a nonvolatile memory. In a split-gate nonvolatile memory, between a memory gate electrode and a p-type well and between a control gate electrode and the memory gate electrode, an insulating film is formed. Of the insulating film, the portion between the lower surface of the memory gate electrode and the upper surface of a semiconductor substrate has silicon oxide films, and a silicon nitride film interposed between the silicon oxide films. Of the insulating film, the portion between a side surface of the control gate electrode and a side surface of the memory gate electrode is formed of a silicon oxide film, and does not have the silicon nitride film. | 10-09-2014 |
| 20140322902 | METHODS FOR USING ISOTOPICALLY ENRICHED LEVELS OF DOPANT GAS COMPOSITIONS IN AN ION IMPLANTATION PROCESS - A novel process for using enriched and highly enriched dopant gases is provided herein that eliminates the problems currently encountered by end-users from being able to realize the process benefits associated with ion implanting such dopant gases. For a given flow rate within a prescribed range, operating at a reduced total power level of the ion source is designed to reduce the ionization efficiency of the enriched dopant gas compared to that of its corresponding non-enriched or lesser enriched dopant gas. The temperature of the source filament is also reduced, thereby mitigating the adverse effects of fluorine etching and ion source shorting when a fluorine-containing enriched dopant gas is utilized. The reduced levels of total power in combination with a lower ionization efficiency and lower ion source temperature can interact synergistically to improve and extend ion source life, while beneficially maintaining a beam current that does not unacceptably deviate from previously qualified levels. | 10-30-2014 |
| 20140322903 | ENRICHED SILICON PRECURSOR COMPOSITIONS AND APPARATUS AND PROCESSES FOR UTILIZING SAME - Isotopically enriched silicon precursor compositions are disclosed, as useful in ion implantation to enhance performance of the ion implantation system, in relation to corresponding ion implantation lacking such isotopic enrichment of the silicon precursor composition. The silicon dopant composition includes at least one silicon compound that is isotopically enriched above natural abundance in at least one of | 10-30-2014 |
| 20140329377 | SUPPLY SOURCE AND METHOD FOR ENRICHED SELENIUM ION IMPLANTATION - A novel method for ion implanting isotopically enriched selenium containing source material is provided. The source material is selected and enriched in a specific mass isotope of selenium, whereby the enrichment is above natural abundance levels. The inventive method allows reduced gas consumption and reduced waste. The source material is preferably stored and delivered from a sub-atmospheric storage and delivery device to enhance safety and reliability during the selenium ion implantation process. | 11-06-2014 |
| 20140363955 | UNDERLAYER FILM-FORMING COMPOSITION AND PATTERN FORMING PROCESS - In lithography, a composition comprising a novolak resin comprising recurring units derived from a phenolphthalein, Phenol Red, Cresolphthalein, Cresol Red, or Thymolphthalein is used to form a photoresist underlayer film. The underlayer film is strippable in alkaline water, without causing damage to ion-implanted Si substrates or SiO | 12-11-2014 |
| 20140363956 | UNDERLAYER FILM-FORMING COMPOSITION AND PATTERN FORMING PROCESS - In lithography, a composition comprising a novolak resin comprising recurring units of hydroxycoumarin is used to form a photoresist underlayer film. The underlayer film is strippable in alkaline water, without causing damage to ion-implanted Si substrates or SiO | 12-11-2014 |
| 20140363957 | UNDERLAYER FILM-FORMING COMPOSITION AND PATTERN FORMING PROCESS - In lithography, a composition comprising a novolak resin comprising recurring units of fluorescein is used to form a photoresist underlayer film. The underlayer film is strippable in alkaline water, without causing damage to ion-implanted Si substrates or SiO | 12-11-2014 |
| 20140363958 | UNDERLAYER FILM-FORMING COMPOSITION AND PATTERN FORMING PROCESS - In lithography, a composition comprising a novolak resin comprising recurring units derived from a naphtholphthalein is used to form a photoresist underlayer film. The underlayer film is strippable in alkaline water, without causing damage to ion-implanted Si substrates or SiO | 12-11-2014 |
| 20150017791 | FILM-FORMING COMPOSITION AND ION IMPLANTATION METHOD - There is provided an ion implantation method, a composition for forming an ion implantation film and a resist underlayer film-forming composition. An ion implantation method including the steps of: forming a film by applying a film-forming composition containing a compound including an element in group 13, group 14, group 15, or group 16 and an organic solvent onto a substrate and baking the film-forming composition; and implanting impurity ions into the substrate from above through the film and introducing the element in group 13, group 14, group 15, or group 16 in the film into the substrate. The film-forming composition is a film-forming composition for ion implantation containing a compound including an element in group 13, group 14, group 15, or group 16, and an organic solvent. In addition, the underlayer film-forming composition contains a compound having at least two borate ester groups. | 01-15-2015 |
| 20150024578 | METHODS FOR ETCHING DIELECTRIC MATERIALS IN THE FABRICATION OF INTEGRATED CIRCUITS - Methods for etching dielectric materials in the fabrication of integrated circuits are disclosed herein. In one exemplary embodiment, a method for fabricating an integrated circuit includes forming a layer of a first dielectric material over a gate electrode structure formed on a semiconductor substrate. The gate electrode structure includes a horizontal top surface and sidewall vertical surfaces adjacent to the horizontal top surface. The method further includes forming a layer of a second dielectric material over the layer of the first dielectric material. The first dielectric material is different than the second dielectric material. Still further, the method includes applying an etchant to the second material that fully removes the second material from the sidewall vertical surfaces while only partially removing the second material from the horizontal top surface and while substantially not removing any of the layer of the first dielectric material. | 01-22-2015 |
| 20150024579 | Method Of Improving Ion Beam Quality In An Implant System - A method for improving the ion beam quality in an ion implanter is disclosed. In some ion implantation systems, contaminants from the ion source are extracted with the desired ions, introducing contaminants to the workpiece. These contaminants may be impurities in the ion source chamber. This problem is exacerbated when mass analysis of the extracted ion beam is not performed, and is further exaggerated when the desired feedgas includes a halogen. | 01-22-2015 |
| 20150024580 | Method For Implant Productivity Enhancement - A method of processing a workpiece is disclosed, where the ion chamber is first coated with the desired dopant species and another species. Following this conditioning process, a feedgas, which comprises fluorine and the desired dopant, is introduced to the chamber and ionized. Ions are then extracted from the chamber and accelerated toward the workpiece, where they are implanted without being first mass analyzed. The other species used during the conditioning process may be a Group 3, 4 or 5 element. The desired dopant species may be boron. | 01-22-2015 |
| 20150037966 | METHOD FOR PRODUCING A PATTERN IN AN INTEGRATED CIRCUIT AND CORRESPONDING INTEGRATED CIRCUIT - At least one projecting block is formed in an element. The projecting block is then covered with a first cover layer so as to form a concave ridge self-aligned with the projecting block and having its concavity face towards the projecting block. A first trench is then formed in the ridge in a manner that is self-aligned with both the ridge and the projecting block. The first trench extends to a depth which reaches the projecting block. The projecting block is etched using the ridge and first trench as an etching mask to form a second trench in the projecting block that is self-aligned with the first trench. A pattern is thus produced by the second trench and unetched parts of the projecting block which delimit the second trench. | 02-05-2015 |
| 20150064887 | ION IMPLANTATION APPARATUS AND ION IMPLANTATION METHOD - An ion implantation apparatus includes an implantation processing chamber, a high voltage unit, and a high-voltage power supply system. In the implantation processing chamber ions are implanted into a workpiece. The high voltage unit includes an ion source unit for generating the ions, and a beam transport unit provided between the ion source unit and the implantation processing chamber. The high-voltage power supply system applies a potential to the high voltage unit under any one of a plurality of energy settings. The high-voltage power supply system includes a plurality of current paths formed such that a beam current flowing into the workpiece is returned to the ion source unit, and each of the plurality of energy settings is associated with a corresponding one of the plurality of current paths. | 03-05-2015 |
| 20150064888 | ION IMPLANTATION APPARATUS, BEAM PARALLELIZING APPARATUS, AND ION IMPLANTATION METHOD - An ion implantation apparatus includes a beam parallelizing unit and a third power supply unit. The beam parallelizing unit includes an acceleration lens, and a deceleration lens disposed adjacent to the acceleration lens in an ion beam transportation direction. The third power supply unit operates the beam parallelizing unit under one of a plurality of energy settings. The plurality of energy settings includes a first energy setting suitable for transport of a low energy ion, and a second energy setting suitable for transport of a high energy ion beam. The third power supply unit is configured to generate a potential difference in at least the acceleration lens under the second energy setting, and generate a potential difference in at least the deceleration lens under the first energy setting. A curvature of the deceleration lens is smaller than a curvature of the acceleration lens. | 03-05-2015 |
| 20150064889 | Method for Dopant Implantation of FinFET Structures - The present disclosure is related to a method for implanting dopant elements in a structure comprising a plurality of semiconductor fins separated by field dielectric areas. The method includes depositing an etch stop layer on the fins, depositing a BARC layer on the etch stop layer, depositing a resist layer on the BARC layer, removing a portion of the resist layer by lithography steps to thereby expose an area of the BARC layer, removing the BARC layer in the exposed area by a dry etch process using the remaining resist layer as a mask, implanting dopant elements into the fins present in the area, using the BARC and resist layers as a mask, and removing the remainder of the resist and BARC layers. | 03-05-2015 |
| 20150118832 | METHODS FOR PATTERNING A HARDMASK LAYER FOR AN ION IMPLANTATION PROCESS - Embodiments of the present invention provide a methods for patterning a hardmask layer with good process control for an ion implantation process, particularly suitable for manufacturing the fin field effect transistor (FinFET) for semiconductor chips. In one embodiment, a method of patterning a hardmask layer disposed on a substrate includes forming a planarization layer over a hardmask layer disposed on a substrate, disposing a patterned photoresist layer over the planarization layer, patterning the planarization layer and the hardmask layer uncovered by the patterned photoresist layer in a processing chamber, exposing a first portion of the underlying substrate, and removing the planarization layer from the substrate. | 04-30-2015 |
| 20150147874 | METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE - The present invention provides a manufacturing method for forming a semiconductor structure, in which first, a substrate is provided, a hard mask is disposed on the substrate, the hard mask is then patterned to form a plurality of fin hard masks and a plurality of dummy fin hard masks, afterwards, a pattern transferring process is performed, to transfer the patterns of the fin hard masks and the fin hard masks into the substrate, so as to form a plurality of fin groups and a plurality of dummy fins. Each dummy fin is disposed on the end side of one fin group, and a fin cut process is performed, to remove each dummy fin. | 05-28-2015 |
| 20150332924 | METHOD AND APPARATUS FOR BEAM DEFLECTION IN A GAS CLUSTER ION BEAM SYSTEM - Provided is a method of controlling a gas cluster ion beam (GCIB) system for processing structures on a substrate. A GCIB system comprises deflection plates for directing a GCIB towards a substrate, the GCIB system coupled to a substrate scanning device configured to move a substrate in three dimensions. The substrate is exposed to the GCIB while the substrate is being moved by the substrate scanning device. A controller is used to control a set of deflection operating parameters comprising a deflection angle φ, voltage differential of the deflection plates, frequency of the deflection plate power, beam current, substrate distance, pressure in the nozzle, gas flow rate in the process chamber, separation of beam burns, duration of the bean burn, and/or duty cycle of the beam deflector output. | 11-19-2015 |
| 20150340458 | ZENER DIODE HAVIING A POLYSILICON LAYER FOR IMPROVED REVERSE SURGE CAPABILITY AND DECREASED LEAKAGE CURRENT - A semiconductor device such as a Zener diode includes a first semiconductor material of a first conductivity type and a second semiconductor material of a second conductivity type in contact with the first semiconductor material to form a junction therebetween. A first oxide layer is disposed over a portion of the second semiconductor material such that a remaining portion of the second semiconductor material is exposed. A polysilicon layer is disposed on the exposed portion of the second semiconductor material and a portion of the first oxide layer. A first conductive layer is disposed on the polysilicon layer. A second conductive layer is disposed on a surface of the first semiconductor material opposing a surface of the first semiconductor material in contact with the second semiconductor material. | 11-26-2015 |
| 20150371857 | LOWER DOSE RATE ION IMPLANTATION USING A WIDER ION BEAM - In an exemplary process for lower dose rate ion implantation of a work piece, an ion beam may be generated using an ion source and an extraction manipulator. The extraction manipulator may be positioned at a gap distance from an exit aperture of the ion source. A current of the ion beam exiting the extraction manipulator may be maximized when the extraction manipulator is positioned at an optimal gap distance from the exit aperture. The gap distance at which the extraction manipulator is positioned from the exit aperture may differ from the optimal gap distance by at least 10 percent. A first potential may be applied to a first set of electrodes. An x-dimension of the ion beam may increase as the ion beam passes through the first set of electrodes. The work piece may be positioned in the ion beam to implant ions into the work piece. | 12-24-2015 |
| 20150380116 | SHIELDING DEVICE FOR SUBSTRATE EDGE PROTECTION AND METHOD OF USING SAME - A shielding device for shielding an edge of a semiconductor substrate can include a multisided frame defining a perimeter of an enclosed area, and a shield coupled to the frame. The shield may be configured to move between a first position where the shield is retracted to the perimeter and a second position where shield advanced into the enclosed area. A method for processing a semiconductor substrate includes placing a semiconductor substrate in position in an implantation chamber, covering edges of the semiconductor substrate by pushing shields into engagement with the edges, performing an ion implantation procedure, and retracting the shields from the edges. | 12-31-2015 |
| 20160027638 | Methods of Forming Patterns - Some embodiments include methods of forming patterns. A first mask is formed over a material. The first mask has features extending therein and defines a first pattern. The first pattern has a first level of uniformity across a distribution of the features. A brush layer is formed across the first mask and within the features to narrow the features and create a second mask from the first mask. The second mask has a second level of uniformity across the narrowed features which is greater than the first level of uniformity. A pattern is transferred from the second mask into the material. | 01-28-2016 |
| 20160049296 | METHOD FOR FORMING A SEMICONDUCTOR DEVICE - A method for forming a semiconductor device includes carrying out an anodic oxidation of a surface region of a semiconductor substrate to form an oxide layer at a surface of the semiconductor substrate by generating an attracting electrical field between the semiconductor substrate and an external electrode within an electrolyte to attract oxidizing ions of the electrolyte, causing an oxidation of the surface region of the semiconductor substrate. Further, the method includes reducing the number of remaining oxidizing ions within the oxide layer, while the semiconductor substrate is within an electrolyte. | 02-18-2016 |
| 20160064220 | METHOD FOR PRODUCING SEMICONDUCTOR APPARATUS SUBSTRATE - A method for producing a semiconductor apparatus substrate includes steps of: forming silicon-containing film having silicon content of 1% by mass or more and 30% by mass or less on an organic under layer film formed on an substrate; forming a resist film on silicon-containing film; forming a resist pattern by exposing and developing resist film; transferring pattern to silicon-containing film using resist pattern as a mask; transferring pattern to organic under layer film using silicon-containing film as a mask to leave part or all of silicon-containing film on organic under layer film; implanting ions into substrate using organic under layer film as a mask; and peeling organic under layer film used as mask for ion implantation on which part or all of silicon-containing film remains, with peeling liquid. | 03-03-2016 |
| 20160086763 | ION SOURCE DEVICES AND METHODS - An ion source includes a chamber defining an interior cavity for ionization, an electron beam source at a first end of the interior cavity, an inlet for introducing ionizable gas into the chamber, and an arc slit for extracting ions from the chamber. The chamber includes an electrically conductive ceramic. | 03-24-2016 |
| 20160170313 | SUBSTRATE HOLDING DEVICE, LITHOGRAPHY APPARATUS, AND ARTICLE PRODUCTION METHOD | 06-16-2016 |
