| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438525000 | Using oblique beam | 18 |
| 20080206971 | DIVERGENT CHARGED PARTICLE IMPLANTATION FOR IMPROVED TRANSISTOR SYMMETRY - The present invention provides a method for implanting charged particles in a substrate and a method for manufacturing an integrated circuit. The method for implanting charged particles in a substrate, among other steps, includes projecting a beam of charged particles ( | 08-28-2008 |
| 20080242066 | Method Of Manufacturing Semiconductor - A method of producing ultra shallow junctions ( | 10-02-2008 |
| 20080286954 | Method of Forming Pattern of Semiconductor Device - A method of forming a pattern of a semiconductor device comprises forming a first hard mask film, a first resist film, and a second hard mask film over an underlying layer of a semiconductor substrate; forming a second resist pattern over the second hard mask film; etching the second hard mask film using the second resist pattern as an etching mask to form a second hard mask pattern; performing an ion-implanting process on the first resist film with the second hard mask pattern as an ion implanting mask to form an ion implanting layer in a portion of the first resist film, and selectively etching the first resist film with the second hard mask pattern and an ion implanting layer as an etching mask to form a first resist pattern. | 11-20-2008 |
| 20080311732 | Method for Forming Non-Amorphous, Ultra-Thin Semiconductor Devices Using Sacrificial Implantation Layer - A method for forming a semiconductor device includes defining a sacrificial layer ( | 12-18-2008 |
| 20090004837 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - Provided is a method of fabricating a semiconductor device having an impurity region with an impurity concentration of a first dose in a substrate. In the method, first impurity ions of a first conductivity type are implanted into the substrate, and a rapid thermal processing (RTP) is performed on the substrate to activate the first impurity ions. Second impurity ions of the first conductivity type are implanted into the substrate having the activated first impurity ions. | 01-01-2009 |
| 20090029535 | ION IMPLANTATION METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD - In the ion implantation method and semiconductor device manufacturing method relating to the present invention, a disc on which multiple semiconductor substrates are mounted is positioned in the manner that a first angle β | 01-29-2009 |
| 20090075462 | Method of Fabricating a Semiconductor Device - The invention relates to a method of fabricating an integrated circuit, including the steps of providing at least one layer; performing a first implantation step, wherein particles are implanted into the layer under a first direction of incidence; performing a second implantation step, wherein particles are implanted into the layer under a second direction of incidence which is different from the first direction of incidence; performing a removal step, wherein the layer is partially removed depending on the local implant dose generated by the first and the second implantation step. | 03-19-2009 |
| 20090124069 | METHODS OF CHANGING THRESHOLD VOLTAGES OF SEMICONDUCTOR TRANSISTORS BY ION IMPLANTATION - A method for forming a semiconductor structure. The method includes providing a semiconductor structure including a semiconductor substrate. The semiconductor substrate includes (i) a top substrate surface which defines a reference direction perpendicular to the top substrate surface and (ii) a semiconductor body region. The method further includes implanting an adjustment dose of dopants of a first doping polarity into the semiconductor body region by an adjustment implantation process. Ion bombardment of the adjustment implantation process is in the reference direction. The method further includes (i) patterning the semiconductor substrate resulting in side walls of the semiconductor body region being exposed to a surrounding ambient and then (ii) implanting a base dose of dopants of a second doping polarity into the semiconductor body region by a base implantation process. Ion bombardment of the base implantation process is in a direction which makes a non-zero angle with the reference direction. | 05-14-2009 |
| 20100210095 | POLARITY DEPENDENT SWITCH FOR RESISTIVE SENSE MEMORY - Methods of forming polarity dependent switches for resistive sense memory are described. Methods for forming a memory unit include implanting dopant material more heavily in a source contact than a bit contact of a semiconductor transistor, and electrically connecting a resistive sense memory cell to the bit contact. The resistive sense memory cell is configured to switch between a high resistance state and a low resistance state upon passing a current through the resistive sense memory cell. | 08-19-2010 |
| 20110039403 | Method for Implanting Ions In Semiconductor Device - The present invention provides various methods for implanting ions in a semiconductor device that substantially compensate for a difference in threshold voltages between a central portion and edge portions of a substrate generated while performing uniform ion implantation to entire surfaces of a substrate. Other methods for fabricating a semiconductor device improve distribution of transistor parameters across a substrate by forming a nonuniform channel doping layer or by forming a nonuniform junction profile, across the substrate. | 02-17-2011 |
| 20110201186 | METHOD AND APPARATUS FOR REDUCING FLICKER NOISE IN A SEMICONDUCTOR DEVICE - Some embodiments discussed relate to an integrated circuit and methods for making it. In an example, a method can include providing a semiconductor wafer including a fin, and introducing a noise-reducing dopant into a sidewall of the fin. | 08-18-2011 |
| 20110275203 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE INCLUDING ION IMPLANTATION AT A TILT ANGLE IN EXPOSED REGIONS - A method of fabricating a semiconductor device includes forming a mask pattern for defining a region of a semiconductor substrate. An impurity layer for adjusting the threshold voltage of a cell will be formed in the defined region. Dopant ions are implanted into the defined region of the semiconductor substrate at a tilt angle of approximately 4.4° to 7°. | 11-10-2011 |
| 20110275204 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE INCLUDING ION IMPLANTATION AT A TILT ANGLE IN EXPOSED REGIONS - A method of fabricating a semiconductor device includes forming a mask pattern for defining a region of a semiconductor substrate. An impurity layer for suppressing punch-through will be formed in the defined region. Dopant ions are implanted into the defined region of the semiconductor substrate at a tilt angle of approximately 4.4° to 7°. | 11-10-2011 |
| 20110275205 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE INCLUDING ION IMPLANTATION AT A TILT ANGLE IN EXPOSED REGIONS - A method of fabricating a semiconductor device includes forming a mask pattern for defining a region on a semiconductor substrate. A well will be formed in the defined region. Dopant ions are implanted into the defined region of the semiconductor substrate at a tilt angle of approximately 4.4° to 7°. | 11-10-2011 |
| 20120015510 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE INCLUDING ION IMPLANTATION AT A TILT ANGLE IN EXPOSED REGIONS - A method of fabricating a semiconductor device includes forming a mask pattern for defining a region of a semiconductor substrate. A field stop dopant layer will be formed in the defined region. Dopant ions are implanted into the defined region of the semiconductor substrate at a tilt angle of approximately 4.4° to 7°. | 01-19-2012 |
| 20130183817 | Methods of Reducing Gate Leakage - Disclosed herein are various methods of reducing gate leakage in semiconductor devices such as transistors. In one example, a method disclosed herein includes performing an etching process to define a gate insulation layer of a transistor, wherein the gate insulation layer has an etched edge, performing an angled ion implantation process to implant ions into the gate insulation layer proximate the etched edge of the gate insulation layer and, after performing the angled ion implantation process, performing an anneal process. | 07-18-2013 |
| 20130288468 | METHODS OF FORMING SELF-ALIGNED CONTACTS FOR A SEMICONDUCTOR DEVICE FORMED USING REPLACEMENT GATE TECHNIQUES - One illustrative method disclosed herein involves forming an etch stop layer above a plurality of sacrificial gate structures, performing an angled ion implant process to implant an etch-inhibiting species into less than an entirety of the etch stop layer, and forming a layer of insulating material above the etch stop layer. The method further includes removing the sacrificial gate structures, forming replacement gate structures, forming a hard mask layer above the replacement gate structures and layer of insulating material, forming a patterned hard mask layer, performing another etching process through the patterned hard mask layer to define an opening in the layer of insulating material to expose a portion of the etch stop layer, performing another etching process on the exposed portion to define a contact opening therethrough that exposes a doped region and forming a conductive contact in the opening that is conductively coupled to the doped region. | 10-31-2013 |
| 20160133469 | METHOD FOR ION IMPLANTATION - A method for an ion implantation is provided. First, a non-parallel ion beam is provided. Thereafter, a relative motion between a workpiece and the non-parallel ion beam, so as to enable each region of the workpiece to be implanted by different portions of the non-parallel ion beam successively. Particularly, when at least one three-dimensional structure is located on the upper surface of the workpiece, both the top surface and the side surface of the three-dimensional structure may be implanted properly by the non-parallel ion beam when the workpiece is moved across the non-parallel ion beam one and only one times. Herein, the non-parallel ion beam can be a divergent ion beam or a convergent ion beam (both may be viewed as the integrated divergent beam), also can be generated directly from an ion source or is modified from a parallel ion beam, a divergent ion beam or a convergent ion beam. | 05-12-2016 |
