Class / Patent application number | Description | Number of patent applications / Date published |
438524000 | Into grooved semiconductor substrate region | 13 |
20090011580 | METHOD FOR FABRICATING SEMICONDUCTOR MEMORY DEVICE - A method for fabricating a semiconductor memory device includes forming a channel region in a substrate, selectively etching the substrate to form a first trench, performing an impurity ion implantation process on the channel region, and etching a lower portion of the first trench to form a second trench. | 01-08-2009 |
20090042376 | INTEGRATED CIRCUIT FABRICATION PROCESS WITH MINIMAL POST-LASER ANNEALING DOPANT DEACTIVATION - Post-laser annealing dopant deactivation is minimized by performing certain low temperature process steps prior to laser annealing. | 02-12-2009 |
20090053880 | Method of manufacturing semiconductor device - A method of manufacturing a semiconductor device of the present invention consists of forming a trench in a trench-type cell transistor region; forming a gate insulating film and a gate material layer on a semiconductor substrate; forming a photoresist layer on the semiconductor substrate so as to expose extension region formation portions of the trench-type cell transistor region and a high breakdown voltage transistor region; forming extension regions in each region by performing ion implantation in the semiconductor substrate surface of the trench-type cell transistor region and the high breakdown voltage transistor region and then patterning gates, and forming extension regions of an ordinary breakdown voltage transistor by covering the trench-type cell transistor region and the high breakdown voltage transistor region with a photoresist layer and implanting ions in the ordinary breakdown voltage transistor region. | 02-26-2009 |
20090137106 | USING ION IMPLANTATION TO CONTROL TRENCH DEPTH AND ALTER OPTICAL PROPERTIES OF A SUBSTRATE - A method for using ion implantation to create a precision trench in a mask or semiconductor substrate and to alter the optical properties of a mask or semiconductor substrate. In one embodiment, the method may include providing a semiconductor substrate or a mask, forming a damage layer in semiconductor substrate or the mask via ion implantation; wherein the damage layer is formed to a desired depth of the trench; etching the semiconductor substrate or mask to create the trench to the desired depth. In another embodiment, ion implantation is used to alter the optical properties of a mask. | 05-28-2009 |
20090258480 | METHOD OF SELECTIVELY ADJUSTING ION IMPLANTATION DOSE ON SEMICONDUCTOR DEVICES - A first semiconductor region and a second semiconductor region separated by a shallow trench isolation region are formed in a semiconductor substrate. A photoresist is applied and patterned so that the first semiconductor region is exposed, while the second semiconductor region is covered. Depending on the setting of parameters for the location of an edge of the patterned photoresist, the slope of sidewalls of the photoresist, the thickness of the photoresist, and the direction of ion implantation, ions may, or may not, be implanted into the entirety of the surface portion of the first semiconductor region by shading or non-shading of the first semiconductor region. The semiconductor substrate may further comprise a third semiconductor region into which the dopants are implanted irrespective of the shading or non-shading of the first semiconductor region. The selection of shading or non-shading may be changed from substrate to substrate in manufacturing. | 10-15-2009 |
20110045664 | TRANSISTOR STRUCTURE HAVING A TRENCH DRAIN - A semiconductor device is formed having a trench adjacent to a current carrying region of the device. The trench is formed having a depth greater than the depth of a tub region of the device. Increasing the trench depth moves a region of higher field strength from the tub region to a region along the trench. The region along the trench does not have a junction and may withstand the higher field strength. | 02-24-2011 |
20110159672 | Novel Manufacturing Approach for Collector and N Type Buried Layer Of Bipolar Transistor - This invention disclosed a manufacturing approach of collector and buried layer of a bipolar transistor. One aspect of the invention is that a pseudo buried layer, i.e, collector buried layer, is manufactured by ion implantation and thermal anneal. This pseudo buried layer has a small area, which makes deep trench isolation to divide pseudo buried layer unnecessary in subsequent process. Another aspect is, the doped area, i.e, collector, is formed by ion implantation instead of high cost epitaxy process. This invention simplified the manufacturing process, as a consequence, saved manufacturing cost. | 06-30-2011 |
20110256697 | RECESSED-GATE TRANSISTOR DEVICE HAVING A DIELECTRIC LAYER WITH MULTI THICKNESSES AND METHOD OF MAKING THE SAME - A recessed-gate transistor device includes a gate electrode embedded in a gate trench formed in a semiconductor substrate, wherein the gate trench includes a vertical sidewall and a U-shaped bottom. A source region is provided at one side of the gate trench within the semiconductor substrate. A drain region is provided at the other side thereof. An asymmetric gate dielectric layer is formed between the gate electrode and the semiconductor substrate. The asymmetric gate dielectric layer has a first thickness between the gate electrode and the drain region and a second thickness between the gate electrode and the source region, wherein the first thickness is thicker than the second thickness. | 10-20-2011 |
20120295429 | SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - There is disclosed a substrate processing apparatus including a processing chamber housing a substrate, pipes for supplying gas into the processing chamber, and heaters provided in the middle of the pipes, and heating the gas. In the substrate processing apparatus, the heaters heat the gas to a temperature lower than a temperature at which exhaust gas is generated from the pipes to dry the substrate in the heated gas. | 11-22-2012 |
20130034952 | TRANSISTOR STRUCTURE HAVING A TRENCH DRAIN - A semiconductor device is formed having a trench adjacent to a current carrying region of the device. The trench is formed having a depth greater than the depth of a tub region of the device. Increasing the trench depth moves a region of higher field strength from the tub region to a region along the trench. The region along the trench does not have a junction and may withstand the higher field strength. | 02-07-2013 |
20130171812 | SELF-ALIGNED PATTERNING WITH IMPLANTATION - A method of fabricating a plurality of features of a semiconductor device includes providing a dielectric layer over a silicon layer, and etching the dielectric layer and the silicon layer to form a plurality of first apertures in the dielectric layer and the silicon layer, wherein adjacent apertures of the plurality of first apertures are set apart by a first pitch. The method further includes etching a plurality of second apertures in the dielectric layer, each aperture of the plurality of second apertures having a greater width than and centered about a respective aperture of the plurality of first apertures, implanting a plurality of dopants into the silicon layer aligned through the plurality of second apertures in the dielectric layer, wherein doped portions of the silicon layer are set apart by a second pitch less than the first pitch, and removing undoped portions of the silicon layer. | 07-04-2013 |
20130196491 | METHOD OF PREVENTING DOPANT FROM DIFFUSING INTO ATMOSPHERE IN A BICMOS PROCESS - A method of preventing dopant from diffusing into atmosphere in a BiCMOS process is disclosed. The BiCMOS process includes the steps of: depositing a first silicon oxide layer and a silicon nitride layer over surface of a silicon substrate; etching the silicon substrate to form a plurality of shallow trenches therein; depositing a second silicon oxide layer over surface of the silicon substrate and forming silicon oxide sidewalls over inner side faces of each of the plurality of shallow trenches; forming a heavily doped pseudo buried layer under a bottom of one of the plurality of shallow trenches by implanting a dopant with a high concentration; performing an annealing process to promote diffusion of the dopant contained in the pseudo buried layer, wherein the method includes growing, by thermal oxidation, a silicon oxide layer over a bottom of each of the plurality of shallow trenches during the annealing process. | 08-01-2013 |
20160071950 | TRENCH SCHOTTKY RECTIFIER DEVICE AND METHOD FOR MANUFACTURING THE SAME - A method for fabricating a trench Schottky rectifier device is provided. At first, a plurality of trenched are formed in a substrate of a first conductivity type. An insulating layer is formed on sidewalls of the trenches. Then, an ion implantation procedure is performed through the trenches to form a plurality of doped regions of a second conductivity type under the trenches. Subsequently, the trenches are filled with conductive structure such as poly-silicon structure or tungsten structure. At last, an electrode overlying the conductive structure and the substrate is formed. Thus, a Schottky contact appears between the electrode and the substrate. Each doped region and the substrate will form a PN junction to pinch off current flowing toward the Schottky contact to suppress the current leakage in a reverse bias mode. | 03-10-2016 |