| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 438530000 | Including heat treatment | 61 |
| 20080200018 | SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - There is disclosed a substrate processing apparatus including a processing chamber housing a substrate, pipes for supplying gas into the processing chamber, and heaters provided in the middle of the pipes, and heating the gas. In the substrate processing apparatus, the heaters heat the gas to a temperature lower than a temperature at which exhaust gas is generated from the pipes to dry the substrate in the heated gas. | 08-21-2008 |
| 20080213988 | SUBSTRATE HEATING APPARATUS AND SEMICONDUCTOR FABRICATION METHOD - A substrate heating apparatus having a heating unit for heating a substrate placed in a process chamber which can be evacuated includes a suscepter which is installed between the heating unit and a substrate, and on which the substrate is mounted, and a heat receiving member which is installed to oppose the suscepter with the substrate being sandwiched between them, and receives heat from the heating unit via the suscepter. A ventilating portion which allows a space formed between the heat receiving member and substrate to communicate with a space in the process chamber is formed. | 09-04-2008 |
| 20080213989 | SILICON WAFER FOR MANUFACTURING SOI WAFER, SOI WAFER, AND METHOD FOR MANUFACTURING SOI WAFER - A silicon wafer includes a principal face for forming electronic devices; an end region; and a tapered region which is located between the principal face and the end region, in which the thickness of the silicon wafer is gradually reduced, and which has a slope that makes an angle of greater than zero degree and less than 9.5 degrees or an angle of greater than 19 degrees with the principal face. An SOI wafer prepared by forming a buried oxide layer in a silicon wafer includes a principal face, end region, and tapered region that are substantially the same as those described above. A method for manufacturing an SOI wafer includes the steps of implanting oxygen ions into a silicon wafer; and heat-treating the resulting silicon wafer such that a buried oxide layer is formed in the silicon wafer. | 09-04-2008 |
| 20080220597 | Photoresists and methods for use thereof - New photoresists are provided that can be applied and imaged with reduced undesired outgassing and/or as thick coating layers. Preferred resists of the invention are chemically-amplified positive-acting resists that contain photoactive and resin components. | 09-11-2008 |
| 20080248637 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - In one embodiment, a gate insulating layer, a conductive layer, and a metal layer are formed over a semiconductor substrate. An ion implantation region is formed in an interface of the conductive layer and the metal layer by performing an ion implantation process. A flash annealing process is performed on the ion-implanted semiconductor substrate. The metal layer, the conductive layer, and the gate insulating layer are patterned. | 10-09-2008 |
| 20080254604 | METHOD FOR FABRICATING A HYBRID ORIENTATION SUBSTRATE - A method for fabricating a hybrid orientation substrate includes steps of providing a direct silicon bonding (DSB) wafer having a first substrate with (100) crystalline orientation and a second substrate with (110) crystalline orientation directly bonded on the first substrate, forming and patterning a first blocking layer on the second substrate to define a first region not covered by the first blocking layer and a second region covered by the first blocking layer, performing an amorphization process to transform the first region of the second substrate into an amorphized region, and performing an annealing process to recrystallize the amorphized region into the orientation of the first substrate and to make the second region stressed by the first blocking layer. | 10-16-2008 |
| 20080268627 | TRANSISTOR PERFORMANCE USING A TWO-STEP DAMAGE ANNEAL - A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation. | 10-30-2008 |
| 20080280428 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device including heating a semiconductor substrate, has forming a cap film on a surface of said semiconductor substrate; selectively removing said cap film at least from an upper surface of an edge of said semiconductor substrate, a bevel surface of the edge of said semiconductor substrate and a side surface of the edge of said semiconductor substrate; selectively removing at least a device forming film formed on the upper surface of the edge of said semiconductor substrate, the bevel surface of the edge of said semiconductor substrate and the side surface of the edge of said semiconductor substrate; and heating said semiconductor substrate by irradiating said semiconductor substrate with light having a pulse width of 0.1 milliseconds to 100 milliseconds from a light source after removing said device forming film, wherein said cap film has a lower reflectance at a peak wavelength of said light than said semiconductor substrate. | 11-13-2008 |
| 20080299750 | MULTIPLE MILLISECOND ANNEALS FOR SEMICONDUCTOR DEVICE FABRICATION - A method of forming a doped region includes, in one embodiment, implanting a dopant into a region in a semiconductor substrate, recrystallizing the region by performing a first millisecond anneal, wherein the first millisecond anneal has a first temperature and a first dwell time, and activating the region using as second millisecond anneal after recrystallizing the region, wherein the second millisecond anneal has a second temperature and a second dwell time. In one embodiment, the first millisecond anneal and the second millisecond anneal use a laser. In one embodiment, the first temperature is the same as the second temperature and the first dwell time is the same as the second dwell time. In another embodiment, the first temperature is different from the second temperature and the first dwell time is different from the second dwell time. | 12-04-2008 |
| 20090011581 | CARBON CONTROLLED FIXED CHARGE PROCESS - Carbon may be implanted into a p-type silicon channel to form a carbon region in an n-type metal oxide semiconductor (NMOS) transistor. After an annealing process, the implanted carbon may diffuse from the channel into an interface of a gate dielectric layer and the channel. The diffusion may cause an increase in fixed charge at the silicon surface. Thus, the threshold voltage of the NMOS transistor may be reduced. | 01-08-2009 |
| 20090023276 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes forming an impurity diffusion layer in a surface of a semiconductor substrate, wherein the forming the impurity diffusion layer comprises irradiating material including M | 01-22-2009 |
| 20090068824 | FABRICATING METHOD OF SEMICONDUCTOR DEVICE - A method for fabricating a semiconductor substrate is provided. A substrate having a region adjacent to a surface of the substrate as a channel region is provided. An ion implantation process is performed to form an amorphized silicon layer in the substrate below the channel region. A thermal treatment process is performed to re-crystallize the amorphized silicon layer so as to form an epitaxial material layer. The epitaxial material layer may enhance the stress on the channel region in the substrate. | 03-12-2009 |
| 20090081859 | Metallization process - A metallization process is provided. The metallization process comprises the following steps. First, a semiconductor base having at least a silicon-containing conductive region is provided. Afterwards, nitrogen ions are implanted into the silicon-containing conductive region. Next, a first thermal process is performed on the semiconductor base for repairing the surface of the semiconductor base. Then, a metal layer is formed on the surface of the semiconductor base and the metal layer covers the silicon-containing conductive region. Lastly, a second thermal process is performed on the semiconductor base covered with the metal layer so as to form a metal silicide layer on the silicon-containing conductive region. | 03-26-2009 |
| 20090104762 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - Ion implantation is carried out to form a p-well region and a source region in parts of a high resistance SiC layer on a SiC substrate, and a carbon film is deposited over the substrate. With the carbon film deposited over the substrate, annealing for activating the implanted dopant ions is performed, and then the carbon film is removed. Thus, a smooth surface having hardly any surface roughness caused by the annealing is obtained. Furthermore, if a channel layer is epitaxially grown, the surface roughness of the channel layer is smaller than that of the underlying layer. Since the channel layer having a smooth surface is provided, it is possible to obtain a MISFET with a high current drive capability. | 04-23-2009 |
| 20090111252 | METHOD FOR FORMING DEEP WELL REGION OF HIGH VOLTAGE DEVICE - A method of fabricating a deep well region of a high voltage device is provided. The method includes designating a deep well region that includes a designated highly doped region and a designed scarcely doped region in a substrate. A mask layer, which covers a periphery of the designated deep well region, is formed over the substrate, wherein the mask layer includes a plurality of shielding parts to cover a portion of the designated scarcely doped region. Using the mask layer as an implantation mask, an ion implantation process is performed to implant dopants into the substrate exposed by the mask and to form a plurality of undoped regions in the designated scarcely doped region covered by the shielding parts. The dopants in the designated scarcely doped region are then induced to diffuse to the undoped regions. | 04-30-2009 |
| 20090130831 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method for fabricating a semiconductor device having a CMOS transistor including a gate electrode with low resistance. In the CMOS transistor in accordance with embodiments, the impurities implanted into the gate electrode have a higher density than the impurities implanted into the source/drain region. Embodiments also reduce the amount of impurities included in channel regions. | 05-21-2009 |
| 20090280630 | Method for making very low Vt metal-gate/high-k CMOSFETs using self-aligned low temperature shallow junctions - This invention proposes a method for making very low threshold voltage (V | 11-12-2009 |
| 20090298270 | METHOD FOR PRODUCING A SEMICONDUCTOR - A method for producing a semiconductor is disclosed. One embodiment provides a p-doped semiconductor body having a first side and a second side. An n-doped zone is formed in the semiconductor body by implantation of protons into the semiconductor body via the first side down to a specific depth of the semiconductor body and by subsequent heating at least of the proton-implanted region of the semiconductor body. A pn junction arises in the semiconductor body. The second side of the semiconductor body is removed at least as far as a space charge zone spanned at the pn junction. | 12-03-2009 |
| 20090325368 | METHOD FOR MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE - The resist film after high-concentration ion implantation has a hard modified layer on the surface thereof, and is difficult to remove in the temperature region as low as about 150 degrees centigrade. This is because the etching rate of the modified layer sharply decreases with a decrease in temperature. The temperature is increased up to about 250 degrees centigrade to perform an ashing treatment in vacuum in order to increase the etching rate of the modified layer. Then, there occurs a popping phenomenon that the inside resist solvent swells and breaks. The residues scattered thereby of the modified layer and the like seize the wafer surface, and also become difficult to remove even in the subsequent cleaning. According to the present application, in order to remove the resist hardened by ion implantation and the like, the to-be-treated wafer is baked under atmospheric pressure, and then, is subjected to a plasma ashing treatment within the temperature region as high as around 300 degrees centigrade under an oxygen gas atmosphere substantially including an oxygen gas. | 12-31-2009 |
| 20100048005 | PREPARATION OF ULTRA-SHALLOW SEMICONDUCTOR JUNCTIONS USING INTERMEDIATE TEMPERATURE RAMP RATES AND SOLID INTERFACES FOR DEFECT ENGINEERING - Described herein are processing conditions, techniques, and methods for preparation of ultra-shallow semiconductor junctions. Methods described herein utilize semiconductor surface processing or modification to limit the extent of dopant diffusion under annealing conditions (e.g. temperature ramp rates between 100 and 5000° C./second) previously thought impractical for the preparation of ultra-shallow semiconductor junctions. Also described herein are techniques for preparation of ultra-shallow semiconductor junctions utilizing the presence of a solid interface for control of dopant diffusion and activation. | 02-25-2010 |
| 20100075490 | DEFECT-FREE JUNCTION FORMATION USING LASER MELT ANNEALING OF OCTADECABORANE SELF-AMORPHIZING IMPLANTS - A method and apparatus for implanting a semiconductor substrate with boron clusters. A substrate is implanted with octadecaborane by plasma immersion or ion beam implantation. The substrate surface is then melted, resolidified, and annealed to completely dissociate and activate the boron clusters. | 03-25-2010 |
| 20100087052 | DOPANT ACTIVATION ANNEAL TO ACHIEVE LESS DOPANT DIFFUSION (BETTER USJ PROFILE) AND HIGHER ACTIVATION PERCENTAGE - A method and apparatus for forming a semiconductor device. A semiconductor substrate is implanted with dopants. The substrate is subjected to a cleaning process employing electrically neutral nitrogen and fluorine radicals to produce an oxygen-free surface having dangling bonds. Before any further exposure to oxidizing gases, the substrate is annealed by thermal treatment to activate and distribute the dopants. A gate oxide layer is formed over the annealed surface. The apparatus performs all such treatments without breaking vacuum. | 04-08-2010 |
| 20100144131 | METHOD FOR PRODUCING BONDED WAFER - A bonded wafer is produced by a step of forming an oxygen ion implanted layer, a step of forming a wafer composite, a step of exposing the oxygen ion implanted layer, and a step of obtaining an active layer, wherein the exposed oxygen ion implanted layer is removed by sequentially subjecting to a first HF treatment, a given oxidation heat treatment, and then a second HF treatment. | 06-10-2010 |
| 20100248462 | METHOD FOR MANUFACTURING A POWER SEMICONDUCTOR DEVICE - An exemplary method is disclosed for manufacturing a power semiconductor device which has a first electrical contact on a first main side and a second electrical contact on a second main side opposite the first main side and at least a two-layer structure with layers of different conductivity types, and includes providing an n-doped wafer and creating a surface layer of palladium particles on the first main side. The wafer is irradiated on the first main side with ions. Afterwards, the palladium particles are diffused into the wafer at a temperature of not more than 750° C., by which diffusion a first p-doped layer is created. Then, the first and second electrical contacts are created. At least the irradiation with ions is performed through a mask. | 09-30-2010 |
| 20110008952 | METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE - According to one embodiment, in a method for manufacturing a semiconductor device, a surface region of a semiconductor substrate is modified into an amorphous layer. A microwave is irradiated to the semiconductor substrate in which the amorphous layer is formed in a dopant-containing gas atmosphere so as to form a diffusion layer in the semiconductor substrate. The dopant is diffused into the amorphous layer and is activated. | 01-13-2011 |
| 20110034014 | COLD IMPLANT FOR OPTIMIZED SILICIDE FORMATION - A method of applying a silicide to a substrate while minimizing adverse effects, such as lateral diffusion of metal or “piping” is disclosed. The implantation of the source and drain regions of a semiconductor device are performed at cold temperatures, such as below 0° C. This cold implant reduces the structural damage caused by the impacting ions. Subsequently, a silicide layer is applied, and due to the reduced structural damage, metal diffusion and piping into the substrate is lessened. In some embodiments, an amorphization implant is performed after the implantation of dopants, but prior to the application of the silicide. By performing this pre-silicide implant at cold temperatures, similar results can be obtained. | 02-10-2011 |
| 20110070724 | DEFECT-FREE JUNCTION FORMATION USING OCTADECABORANE SELF-AMORPHIZING IMPLANTS - A method and apparatus for implanting a semiconductor substrate with boron clusters. A substrate is implanted with octadecaborane by plasma immersion or ion beam implantation. The substrate surface is then annealed to completely dissociate and activate the boron clusters. The annealing may take place by melting the implanted regions or by a sub-melt annealing process. | 03-24-2011 |
| 20110076842 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE - An ion implantation is performed to implant ions into a silicon substrate, and a microwave irradiation is performed to irradiate the silicon substrate with microwaves after the ion implantation. After the microwave irradiation, the silicon substrate is transferred to a heat-treatment apparatus, where the silicon substrate is treated with heat by being irradiated with light having a pulse width ranging from 0.1 milliseconds to 100 milliseconds, both inclusive. | 03-31-2011 |
| 20110092058 | ION IMPLANTED SUBSTRATE HAVING CAPPING LAYER AND METHOD - In an ion implantation method, a substrate is placed in a process zone and ions are implanted into a region of the substrate to form an ion implanted region. A porous capping layer comprising dispersed gas pockets is deposited on the ion implanted region. | 04-21-2011 |
| 20110151653 | SPIN-ON FORMULATION AND METHOD FOR STRIPPING AN ION IMPLANTED PHOTORESIST - A spin-on formulation that is useful in stripping an ion implanted photoresist is provided that includes an aqueous solution of a water soluble polymer containing at least one acidic functional group, and at least one lanthanide metal-containing oxidant. The spin-on formulation is applied to an ion implanted photoresist and baked to form a modified photoresist. The modified photoresist is soluble in aqueous, acid or organic solvents. As such one of the aforementioned solvents can be used to completely strip the ion implanted photoresist as well as any photoresist residue that may be present. A rinse step can follow the stripping of the modified photoresist. | 06-23-2011 |
| 20110151654 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - First, a first layer made of Ni or an alloy including Ni may be formed on an upper surface of a semiconductor layer. Next, a second layer made of silicon oxide may be formed on an upper surface of the first layer. Next, a part, which corresponds to a semiconductor region, of the second layer may be removed. Next, second conductive type ion impurities may be injected from upper sides of the first and second layers to the semiconductor layer after the removing step. | 06-23-2011 |
| 20110201188 | SELF-ALIGNED ION IMPLANTATION FOR IBC SOLAR CELLS - An improved method of doping a substrate is disclosed. The method is particularly beneficial to the creation of interdigitated back contact (IBC) solar cells. A paste having a dopant of a first conductivity is applied to the surface of the substrate. This paste serves as a mask for a subsequent ion implantation step, allowing ions of a dopant having an opposite conductivity to be introduced to the portions of the substrate which are exposed. After the ions are implanted, the mask can be removed and the dopants may be activated. Methods of using an aluminum-based and phosphorus-based paste are disclosed. | 08-18-2011 |
| 20110244669 | METHOD FOR LOW TEMPERATURE ION IMPLANTATION - Techniques for low temperature ion implantation are provided to improve the throughput. During a low temperature ion implantation, an implant process may be started before the substrate temperature is decreased to be about to a prescribed implant temperature by a cooling process, and a heating process may be started to increase the substrate temperature before the implant process is finished. Moreover, one or more temperature adjust process may be performed during one or more portion of the implant process, such that the substrate temperature may be controllably higher than the prescribe implant temperature during the implant process. | 10-06-2011 |
| 20110263109 | ELECTROOPTICAL DEVICE - In an electrooptical device including an electrooptical modulating layer between a first substrate | 10-27-2011 |
| 20110269302 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - The invention relates to a method of fabricating a semiconductor device. The method includes: providing a semiconductor substrate and locally heating the semiconductor substrate by using a heated tip structure. Locally heating the semiconductor substrate is carried out to locally modify the electrical properties of the semiconductor substrate. The semiconductor substrate can be implanted with dopants, so that locally heating step causes a local activation of the implanted dopants. Furthermore, the semiconductor substrate can be provided with a dopant layer, so that locally heating step causes dopants to diffuse into the semiconductor substrate. | 11-03-2011 |
| 20110318910 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device that sufficiently activates a deep ion injection layer and fully recovers lattice defects generated in the ion injection process. Laser light pulses are successively emitted to form substantially CW (continuous wave) laser light. This feature of the invention stably performs activation of a deep ion injection layer at about 2 μs with few defects. | 12-29-2011 |
| 20120034769 | LOW TEMPERATURE MICROWAVE ACTIVATION OF HEAVY BODY IMPLANTS - Semiconductor devices and methods for making such devices are described. The semiconductor devices contain dopant regions that have been formed by low temperature, microwave activation of implanted dopants. In some configurations, the low temperature microwave activation can be used to control the final location of the implant, with or without additional drive-in or implant processes. In some configurations, this control can be used to create heavy body implants. Microwave activation of source regions and well regions in the semiconductor devices can also be used to optimize the implants where supplemental drive-in processes may be necessary to get the required final implant depth. By activating the implanted dopants using lower temperatures, many of the unwanted features introduced into the semiconductor devices by high temperature Rapid Thermal Process (RTP) can be avoided. Other embodiments are described. | 02-09-2012 |
| 20120083103 | METHOD FOR MINIMIZING DEFECTS IN A SEMICONDUCTOR SUBSTRATE DUE TO ION IMPLANTATION - Defects in a semiconductor substrate due to ion implantation are minimized by forming an implant region in the semiconductor substrate and subjecting the semiconductor substrate to a first anneal to recrystallize the semiconductor substrate. The semiconductor substrate is subjected to a second anneal to suppress diffusion of implanted ions in the semiconductor substrate. The first anneal being at a lower temperature and longer duration than the second anneal. | 04-05-2012 |
| 20120088356 | INTEGRATED PLATFORM FOR IN-SITU DOPING AND ACTIVATION OF SUBSTRATES - An integrated platform for processing substrates, comprising: a vacuum substrate transfer chamber; a doping chamber coupled to the vacuum substrate transfer chamber, the doping chamber configured to implant or deposit dopant elements in or on a surface of a substrate; a dopant activation chamber coupled to the vacuum substrate transfer chamber, the dopant activation chamber configured to anneal the substrate and activate the dopant elements; and a controller configured to control the integrated platform, the controller comprising a computer readable media having instructions stored thereon that, when executed by the controller, causes the integrated platform to perform a method, the method comprising: doping a substrate with one or more dopant elements in the doping chamber; transferring the substrate under vacuum to the dopant activation chamber; and annealing the substrate in the dopant activation chamber to activate the dopant elements. | 04-12-2012 |
| 20120115318 | METHOD FOR LOW TEMPERATURE ION IMPLANTATION - Techniques for low temperature ion implantation are provided to improve the throughput. During a low temperature ion implantation, an implant process may be started before the substrate temperature is decreased to be about to a prescribed implant temperature by a cooling process, and a heating process may be started to increase the substrate temperature before the implant process is finished. Moreover, one or more temperature adjust process may be performed during one or more portion of the implant process, such that the substrate temperature may be controllably higher than the prescribe implant temperature during the implant process. | 05-10-2012 |
| 20120276724 | SPIN-ON FORMULATION AND METHOD FOR STRIPPING AN ION IMPLANTED PHOTORESIST - A spin-on formulation that is useful in stripping an ion implanted photoresist is provided that includes an aqueous solution of a water soluble polymer containing at least one acidic functional group, and at least one lanthanide metal-containing oxidant. The spin-on formulation is applied to an ion implanted photoresist and baked to form a modified photoresist. The modified photoresist is soluble in aqueous, acid or organic solvents. As such one of the aforementioned solvents can be used to completely strip the ion implanted photoresist as well as any photoresist residue that may be present. A rinse step can follow the stripping of the modified photoresist. | 11-01-2012 |
| 20120315747 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD - A semiconductor device in one embodiment has a first connection region, a second connection region and a semiconductor volume arranged between the first and second connection regions. Provision is made, within the semiconductor volume, in the vicinity of the second connection region, of a field stop zone for spatially delimiting a space charge zone that can be formed in the semiconductor volume, and of an anode region adjoining the first connection region. The dopant concentration profile within the semiconductor volume is configured such that the integral of the ionized dopant charge over the semiconductor volume, proceeding from an interface of the anode region which faces the second connection region, in the direction of the second connection region, reaches a quantity of charge corresponding to the breakdown charge of the semiconductor device only near the interface of the field stop zone which faces the second connection region. | 12-13-2012 |
| 20120329257 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device, the method including forming a front face structure of a semiconductor device on a first main face of a semiconductor substrate, grinding a second main face of the semiconductor substrate and reducing the semiconductor substrate in thickness to a thickness equal to or less than 100 μm, ion implanting a dopant into the second main face of the semiconductor substrate of reduced thickness, and activating the dopant by irradiating the second main face with laser light and performing laser annealing while the semiconductor substrate of reduced thickness is heated. | 12-27-2012 |
| 20130017676 | DEEP CONTACTS OF INTEGRATED ELECTRONIC DEVICES BASED ON REGIONS IMPLANTED THROUGH TRENCHES - An embodiment of an integrated circuit includes first and second semiconductor layers and a contact region disposed in the second layer. The first semiconductor layer is of a first conductivity, and the second semiconductor layer is disposed over the first layer and has a surface. The contact region is contiguous with the surface, contacts the first layer, includes a first inner conductive portion, and includes an outer conductive portion of the first conductivity. The contact region may extend deeper than conventional contact regions, because where the inner conductive portion is formed from a trench, doping the outer conductive portion via the trench may allow one to implant the dopants more deeply than conventional techniques allow. | 01-17-2013 |
| 20130040446 | Backside Surface Treatment of Semiconductor Chips - A method includes performing a grinding to a backside of a semiconductor substrate, wherein a remaining portion of the semiconductor substrate has a back surface. A treatment is then performed on the back surface using a method selected from the group consisting essentially of a dry treatment and a plasma treatment. Process gases that are used in the treatment include oxygen (O | 02-14-2013 |
| 20130072009 | METHOD FOR PREPARING A SUBSTRATE BY IMPLANTATION AND IRRADIATION - A method for preparing a substrate for detaching a layer by irradiation of the substrate with a light flux for heating a buried region of the substrate and bringing about decomposition of the material of that region to detach said detachment layer. The method includes fabricating an intermediate substrate including a first buried layer, and a second covering layer that covers all or part of the first layer, with the covering layer being substantially transparent to the light flux and with the buried layer formed by implantation of particles into the substrate, followed by absorbing the flux, and selectively and adiabatically irradiating a treated region of the buried layer until at least partial decomposition of the material constituting it ensues. | 03-21-2013 |
| 20130137255 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - To provide a semiconductor device including an oxide semiconductor which is capable of having stable electric characteristics and achieving high reliability, by a dehydration or dehydrogenation treatment performed on a base insulating layer provided in contact with an oxide semiconductor layer, the water and hydrogen contents of the base insulating layer can be decreased, and by an oxygen doping treatment subsequently performed, oxygen which can be eliminated together with the water and hydrogen is supplied to the base insulating layer. By formation of the oxide semiconductor layer in contact with the base insulating layer whose water and hydrogen contents are decreased and whose oxygen content is increased, oxygen can be supplied to the oxide semiconductor layer while entry of the water and hydrogen into the oxide semiconductor layer is suppressed. | 05-30-2013 |
| 20130196493 | SILICON-ON-INSULATOR SUBSTRATE AND METHOD OF FORMING - Silicon-on-insulator (SOI) structures and related methods of forming such structures. In one case, a method includes providing a silicon-on-insulator (SOI) handle substrate having: a substantially uniform resistivity profile along a depth of the handle substrate; and an interstitial oxygen (O | 08-01-2013 |
| 20130203248 | INTEGRATED CIRCUIT HAVING A JUNCTIONLESS DEPLETION-MODE FET DEVICE - A method for producing an integrated circuit, including, in this order: a) producing at least one MOS electronic circuit and/or at least one level of electrical interconnections on a substrate; b) uniformly implantating dopants in at least a portion of a layer of crystalline semiconductor; c) thermally activating the dopants implanted in the portion of the crystalline semiconductor layer; d) rigidly connecting the crystalline semiconductor layer to the substrate; and e) producing at least one junctionless depletion-mode FET device including a part of the portion of the crystalline semiconductor layer. | 08-08-2013 |
| 20130267084 | METHOD FOR FORMING SUPERACTIVE DEACTIVATION-RESISTANT JUNCTION WITH LASER ANNEAL AND MULTIPLE IMPLANTS - A pulsed-laser anneal technique includes performing an implant of a selected region of a semiconductor wafer. A co-constituent implant of the selected region is performed, and the pulsed-laser anneal of the selected region performed. A pre-amorphizing implant of the selected region can also be performed. In one embodiment, the implant of the selected region is performed as an insitu implant. In another embodiment, the co-constituent implant is performed as an insitu non-donor implant. In yet another embodiment, the implant and the co-constituent implant of the selected region are performed as an insitu donor and co-constituent implant. | 10-10-2013 |
| 20140038396 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME - According to one embodiment, a semiconductor device includes a substrate, a first stacked body, a memory film, a first channel body, a second stacked body, a gate insulating film and a second channel body. A step part is formed between a side face of the select gate and the second insulating layer. A film thickness of a portion covering the step part of the second channel body is thicker than a film thickness of a portion provided between the second insulating layers of the second channel body. | 02-06-2014 |
| 20140057423 | METHOD FOR TRANSFERRING INP FILM - A method for transferring InP film onto a stiffener substrate, the method including: providing a structure comprising an InP surface layer and an underlying doped thin InP layer; implanting hydrogen ions through the surface layer so as to create a weakened plane in the doped thin layer, delimiting a film comprising the surface layer; placing the surface layer in close contact with a stiffener substrate; and applying heat treatment to obtain splitting at the weakened plane and transfer of the film onto the stiffener substrate. | 02-27-2014 |
| 20140187027 | ION IMPLANTATION METHODS - Provided are methods of forming an ion implanted region in a semiconductor device. The methods comprise: (a) providing a semiconductor substrate having a plurality of regions to be ion implanted; (b) forming a photoresist pattern on the semiconductor substrate, wherein the photoresist pattern is formed from a chemically amplified photoresist composition comprising a matrix polymer having acid labile groups, a photoacid generator and a solvent; (c) coating a descumming composition over the photoresist pattern, wherein the descumming composition comprises: a matrix polymer; a free acid; and a solvent; (d) heating the coated semiconductor substrate; (e) contacting the coated semiconductor substrate with a rinsing agent to remove residual descumming composition and scum from the substrate; and (f) ion implanting the plurality of regions of the semiconductor substrate using the photoresist pattern as an implant mask. The methods find particular applicability in the manufacture of semiconductor devices. | 07-03-2014 |
| 20140273421 | High-Throughput System and Method for Post-Implantation Single Wafer Warm-Up - A high throughput system for warming a wafer to a desired temperature after undergoing a low-temperature implantation process includes an implantation chamber, a wafer warming chamber configured to uniformly warm a single wafer, and a plurality of robotic arms to transfer wafers throughout the system. At each stage in the fabrication process, the robotic arms simultaneously work with multiple wafers and, therefore, the system provides a high throughput process. Also, the warming chamber may be a vacuum environment, thus eliminating the mist-condensation problem that results in wafer spotting. | 09-18-2014 |
| 20140342538 | ION IMPLANTATION SYSTEM AND METHOD - An ion implantation system and method, providing cooling of dopant gas in the dopant gas feed line, to combat heating and decomposition of the dopant gas by arc chamber heat generation, e.g., using boron source materials such as B | 11-20-2014 |
| 20150011080 | METHOD FOR ELECTRICAL ACTIVATION OF DOPANT SPECIES IN A GaN FILM - The method includes the steps of a) Providing a stack having a support substrate and a film of GaN having dopant species, b) Directly bonding a shielding layer having a thickness higher than 2 micrometers to the surface of the film of GaN, so as to form an activation structure, and c) Applying a thermal budget to the activation structure according to conditions allowing to electrically activate at least one portion of the dopant species. | 01-08-2015 |
| 20150371858 | Method for Treating a Semiconductor Wafer - A Magnetic Czochralski semiconductor wafer having opposing first and second sides arranged distant from one another in a first vertical direction is treated by implanting first particles into the semiconductor wafer via the second side to form crystal defects in the semiconductor wafer. The crystal defects have a maximum defect concentration at a first depth. The semiconductor wafer is heated in a first thermal process to form radiation induced donors. Implantation energy and dose are chosen such that the semiconductor wafer has, after the first thermal process, an n-doped semiconductor region arranged between the second side and first depth, and the n-doped semiconductor region has, in the first vertical direction, a local maximum of a net doping concentration between the first depth and second side and a local minimum of the net doping concentration between the first depth and first maximum. | 12-24-2015 |
| 20150380285 | HIGH THROUGHPUT HEATED ION IMPLANTATION SYSTEM AND METHOD - An ion implantation system has an ion implantation apparatus coupled to first and second dual load lock assemblies, each having a respective first and second chamber separated by a common wall. Each first chamber has a pre-heat apparatus configured to heat a workpiece to a first temperature. Each second chamber has a post-cool apparatus configured to cool the workpiece to a second temperature. A thermal chuck retains the workpiece in a process chamber for ion implantation, and the thermal chuck is configured to heat the workpiece to a third temperature. A pump and vent are in selective fluid communication with the first and second chambers. A controller is configured to heat the workpiece to the first temperature in an atmospheric environment via the pre-heat apparatus, to heat the workpiece to the second temperature via the thermal chuck, to implant ions into the workpiece via the ion implantation apparatus, and to transfer the workpiece between atmospheric and vacuum environments via a control of the pre-heat apparatus, post-cool apparatus, pump, vent, and thermal chuck. | 12-31-2015 |
| 20160079085 | SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR MANUFACTURING APPARATUS - Flash light is emitted from flash lamps to the surface of a semiconductor substrate on which a metal layer has been formed for one second or less to momentarily raise temperature on the surface of the semiconductor substrate including the metal layer and an impurity region to a processing temperature of 1000° C. or more. Heat treatment is performed by emitting flash light to the surface of the semiconductor substrate in a forming gas atmosphere containing hydrogen. By heating the surface of the semiconductor substrate to a high temperature in the forming gas atmosphere for an extremely short time period, contact resistance can be reduced without desorbing hydrogen taken in the vicinity of an interface of a gate oxide film for hydrogen termination. | 03-17-2016 |
| 20160104768 | Method of Forming a Super Junction Semiconductor Device Having Stripe-Shaped Regions of the Opposite Conductivity Types - A super junction semiconductor device is formed by forming at least a portion of a drift layer on a doped layer of a first conductivity type, implanting first dopants of a first conductivity type and second dopants of a second conductivity type into the drift layer using one or more implant masks with openings to form stripe-shaped first implant regions of the first conductivity type and stripe-shaped second implant regions of the second conductivity type in alternating order, and performing a heat treatment for controlling a diffusion of dopants from the implant regions to form stripe-shaped first regions of the first conductivity type and stripe-shaped second regions of the second conductivity type. | 04-14-2016 |
| 20190148306 | SEMICONDUCTOR BACKMETAL AND OVER PAD METALLIZATION STRUCTURES AND RELATED METHODS | 05-16-2019 |
