| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257272000 |
Junction field effect transistor in integrated circuit
| 61 |
| 257263000 |
Vertical controlled current path
| 42 |
| 257280000 |
With Schottky gate
| 39 |
| 257262000 |
Combined with insulated gate field effect transistor (IGFET)
| 31 |
| 257270000 |
Plural, separately connected, gates control same channel region
| 18 |
| 257257000 |
Light responsive or combined with light responsive device
| 12 |
| 257279000 |
Pn junction gate in compound semiconductor material (e.g., GaAs)
| 8 |
| 257285000 |
With profiled channel dopant concentration or profiled gate region dopant concentration (e.g., maximum dopant concentration below surface)
| 7 |
| 257268000 |
Enhancement mode
| 6 |
| 257287000 |
With multiple channels or channel segments connected in parallel, or with channel much wider than length between source and drain (e.g., power JFET) | 5 |
| 20080217664 | Gate self aligned low noise JFET - The disclosure herein pertains to fashioning a low noise junction field effect transistor (JFET) where transistor gate materials are utilized in forming and electrically isolating active areas of a the JFET. More particularly, active regions are self aligned with patterned gate electrode material and sidewall spacers which facilitate desirably locating the active regions in a semiconductor substrate. This mitigates the need for additional materials in the substrate to isolate the active regions from one another, where such additional materials can introduce noise into the JFET. This also allows a layer of gate dielectric material to remain over the surface of the substrate, where the layer of gate dielectric material provides a substantially uniform interface at the surface of the substrate that facilitates uninhibited current flow between the active regions, and thus promotes desired device operation. | 09-11-2008 |
| 20080272409 | JFET Having a Step Channel Doping Profile and Method of Fabrication - A junction field effect transistor comprises a semiconductor substrate, a source region formed in the substrate, a drain region formed in the substrate and spaced apart from the source region, and a gate region formed in the substrate. The transistor further comprises a first channel region formed in the substrate and spaced apart from the gate region, and a second channel region formed in the substrate and between the first channel region and the gate region. The second channel region has a higher concentration of doped impurities than the first channel region. | 11-06-2008 |
| 20090108303 | SEMICONDUCTOR COMPONENT AND METHOD - A semiconductor component and method of making a semiconductor component. One embodiment provides a first metallization structure electrically coupled to charge compensation zones via an ohmic contact and to drift zones via a Schottky contact. A second metallization structure, which is arranged opposite the first metallization structure, is electrically coupled to the charge compensation zones via a Schottky contact and to drift zones via an ohmic contact. | 04-30-2009 |
| 20120319178 | DOUBLE GATE PLANAR FIELD EFFECT TRANSISTORS - A stacked planar device and method for forming the same is shown that includes forming, on a substrate, a stack of layers having alternating sacrificial and channel layers, patterning the stack such that sides of the stack include exposed surfaces of the sacrificial and channel layers, forming a dummy gate structure over a region of the stack to establish a planar area, forming a dielectric layer around the dummy gate structure to cover areas adjacent to the planar area, removing the dummy gate structure to expose the stack, selectively etching the stack to remove the sacrificial layers from the channel layers in the planar area, and forming a gate conductor over and in between the channel layers to form a transistor device. | 12-20-2012 |
| 20130134485 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A non-planar JFET device having a thin fin structure is provided. A fin is formed projecting upwardly from or through a top surface of a substrate, where the fin has a first semiconductor layer portion formed from a first semiconductor material of a first conductivity type. The first semiconductor layer portion has a source region and a drain region, a channel region extending between the source region and the drain region. Two or more channel control regions are formed adjoining the channel region for generating charge depletion zones at and extending into the channel region for thereby controlling current conduction through the channel region. A gate is provided so as to adjoin and short together the at least two channel control regions from the outer sides of the channel control regions. | 05-30-2013 |
| 257260000 |
Same channel controlled by both junction and insulated gate electrodes, or by both Schottky barrier and pn junction gates (e.g., "taper isolated" memory cell) | 5 |
| 20080203443 | Independently-Double-Gated Transistor Memory (IDGM) - Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells may use one, two or three transistors. Single transistor cells are constructed either with or without a bit storage capacitor, and both NAND- and NOR-type Non-Volatile NVRAM cells, as well as Ferroelectric FeRAM cells, are described. For all cells, top gates provide conventional access while independent bottom gates provide control to optimize memory retention for given speed and power parameters as well as to accommodate hardening against radiation. In a single transistor cell without a capacitor, use of the bottom gate allows packing to a density approaching 2 F | 08-28-2008 |
| 20080210988 | Insulated-gate field effect transistor - In a heterostructure field effect transistor (MISHFET), a source ohmic electrode | 09-04-2008 |
| 20080246060 | TRANSISTOR - A transistor includes a nitride semiconductor layer and a gate electrode layer. The gate electrode layer includes a tantalum nitride layer being formed on the nitride semiconductor layer. The tantalum nitride layer forms a Schottky junction with the nitride semiconductor layer. The transistor also includes an insulating film formed on the nitride semiconductor layer. The insulating film surrounds the gate electrode layer. The portion of the gate electrode layer in contact with the nitride semiconductor layer has a higher nitrogen mole fraction than the other portion of the gate electrode layer. | 10-09-2008 |
| 20130099293 | SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME - A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a first doped region and a semiconductor region. The first doped region has a first type conductivity. The semiconductor region is in the first doped region. A source electrode and a drain electrode are respectively electrically connected to parts of the first doped region on opposite sides of the semiconductor region. | 04-25-2013 |
| 20140284666 | INSULATED GATE FIELD EFFECT TRANSISTOR HAVING PASSIVATED SCHOTTKY BARRIERS TO THE CHANNEL - A transistor having at least one passivated Schottky barrier to a channel includes an insulated gate structure on a p-type substrate in which the channel is located beneath the insulated gate structure. The channel and the insulated gate structure define a first and second undercut void regions that extend underneath the insulated gate structure toward the channel from a first and a second side of the insulated gate structure, respectively. A passivation layer is included on at least one exposed sidewall surface of the channel and metal source and drain terminals are located on respective first and second sides of the channel, including on the passivation layer and within the undercut void regions beneath the insulated gate structure. At least one of the metal source and drain terminals comprises a metal that has a work function near a valence band of the p-type substrate. | 09-25-2014 |
| 257259000 |
Elongated active region acts as transmission line or distributed active element (e.g., "transmission line" field effect transistor) | 3 |
| 20090095989 | MULTI-FINGER TRANSISTORS INCLUDING PARTIALLY ENCLOSING CONDUCTIVE LINES - A multi-finger transistor includes gate fingers disposed on a substrate, at least one gate wiring connected to end portions of the gate fingers, source regions and drain regions disposed between the gate fingers, a conductive line partially enclosing the gate fingers and the gate wiring, and substrate plugs electrically connecting the conductive line to the substrate. The conductive line is separated from the gate fingers and the gate wiring. Since the conductive line and the substrate plugs may partially, but not fully, enclose a portion of the substrate where the gate fingers and the gate wiring are positioned, parasitic capacitances caused by the conductive line and the substrate plugs may be considerably reduced to thereby allow high RF frequency characteristics of the multi-finger transistor. | 04-16-2009 |
| 20090189200 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD OF THE SEMICONDUCTOR DEVICE - A semiconductor device and a fabrication method of the semiconductor device, the semiconductor device including: a gate electrode, a source electrode, and a drain electrode which are placed on a first surface of a substrate, and have a plurality of fingers; a gate terminal electrode, a source terminal electrode, and the drain terminal electrode which governed and formed a plurality of fingers for every the gate electrode, the source electrode, and the drain electrode; an active area placed on an underneath part of the gate electrode, the source electrode, and the drain electrode, on the substrate between the gate electrode and source electrode, and on the substrate between the gate electrode and the drain electrode; a sealing layer which is placed on the active area, the gate electrode, the source electrode, and the drain electrode through a cavity part, and performs a hermetic seal of the active area, the gate electrode, the source electrode, and the drain electrode. Accordingly, the semiconductor element itself can have air-tightness, it is not necessary to cover the gate electrode surface with a damp-proof protective film, gate capacitance of the semiconductor element is reduced, and high frequency characteristics and gain of the semiconductor element improve. | 07-30-2009 |
| 20130277717 | FREQUENCY CONTROL DEVICE HAVING IMPROVED ISOLATION FEATURE - A switch device using a frequency control device having an improved isolation feature is provided. The switch device may include a transmission line comprising an input terminal and an output terminal, and a frequency control device to switch a frequency input to the input terminal so that the frequency is selectively transferred to the output terminal. The transmission line may be formed in the form of an air bridge, in an upper portion of the frequency control device. | 10-24-2013 |
| 257261000 |
Junction gate region free of direct electrical connection (e.g., floating junction gate memory cell structure) | 1 |
| 20110147806 | Double-Gated Transistor Memory - Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells may use one, two or three transistors. Single transistor cells are constructed either with or without a bit storage capacitor, and both NAND- and NOR-type Non-Volatile NVRAM cells, as well as Ferroelectric FeRAM cells, are described. For all cells, top gates provide conventional access while independent bottom gates provide control to optimize memory retention for given speed and power parameters as well as to accommodate hardening against radiation. In a single transistor cell without a capacitor, use of the bottom gate allows packing to a density approaching 2 F | 06-23-2011 |
| Entries |
| Document | Title | Date |
|---|
| 20080217662 | Space-efficient package for laterally conducting device - Efficient utilization of space in a laterally-conducting semiconductor device package is enhanced by creating at least one supplemental downbond pad portion of the diepad for receiving the downbond wire from the ground contact of the device. The supplemental diepad portion may occupy area at the end or side of the package formerly occupied by non-integral leads. By receiving the substrate downbond wire, the supplemental diepad portion allows a greater area of the main diepad to be occupied by a die having a larger area, thereby enhancing space efficiency of the package. | 09-11-2008 |
| 20080230810 | INSULATED GATE SEMICONDUCTOR DEVICE - An isolation region is provided around a sense part. The isolation region is provided to have a depth that suppresses spread of a region with an uneven current distribution, which occurs at a peripheral edge of the sense part. Thus, in the sense part, an influence of the region with the uneven current distribution can be suppressed. Since the current distribution can be set more even throughout the sense part, the on-resistance in the sense part can be set closer to its designed value. Thus, a current ratio corresponding to a cell ratio can be obtained as designed. Consequently, current detection accuracy is improved. | 09-25-2008 |
| 20080251818 | LOW NOISE JFET - Fashioning a low noise (1/f) junction field effect transistor (JFET) is disclosed, where multiple implants are performed to push a conduction path of the transistor away from the surface of a layer upon which the transistor is formed. In this manner, current flow in the conduction path is less likely to be disturbed by defects that may exist at the surface of the layer, thereby mitigating (1/f) noise. | 10-16-2008 |
| 20080258182 | Bicmos Compatible Jfet Device and Method of Manufacturing Same - A BiCMOS-compatible JFET device comprising source and drain regions ( | 10-23-2008 |
| 20080258183 | Method of manufacturing a device by locally heating one or more metallization layers and by means of selective etching - A method of manufacturing a device comprises depositing one or more metallization layers to a substrate, locally heating an area of the one or more metallization layers to obtain a substrate/metallization-layer compound or a metallization-layer compound, the compound comprising an etch-selectivity toward an etching medium which is different to that of the one or more metallization layers outside the area, and removing the one or more metallization layers in the area or outside the area, depending on the etching selectivity in the area or outside the area, by etching with the etching medium to form the device. | 10-23-2008 |
| 20080272401 | Inverted Junction Field Effect Transistor and Method of Forming Thereof - A junction field effect transistor includes a substrate and a well region on the substrate. A channel region lies in the well region. A source region lies in the channel region. A drain region lies in the channel region and apart from the source region. A gate region is isolated from the source, drain, and channel regions. The gate region is in contact with a portion of the well region. | 11-06-2008 |
| 20080272402 | JFET Device With Improved Off-State Leakage Current and Method of Fabrication - A junction field effect transistor comprises a semiconductor substrate. A first impurity region of a first conductivity type is formed in the substrate. A second impurity region of the first conductivity type is formed in the substrate and spaced apart from the first impurity region. A channel region of the first conductivity type is formed between the first and second impurity regions. A gate region of a second conductivity type is formed in the substrate between the first and second impurity regions. A gap region is formed in the substrate between the gate region and the first impurity region such that the first impurity region is spaced apart from the gate region. | 11-06-2008 |
| 20080272403 | JFET Device With Virtual Source and Drain Link Regions and Method of Fabrication - A junction field effect transistor comprises a semiconductor substrate. A source region of a first conductivity type is formed in the substrate. A drain region of the first conductivity type is formed in the substrate. A channel region of the first conductivity type is formed in the substrate. A gate region of a second conductivity type is formed in the substrate between the source and drain regions. A first virtual link region is formed in the substrate between the gate region and either the source region or the drain region. A dielectric material overlays the first virtual link region. A first electrode region overlays the dielectric material. | 11-06-2008 |
| 20080272404 | METHOD FOR APPLYING A STRESS LAYER TO A SEMICONDUCTOR DEVICE AND DEVICE FORMED THEREFROM - A semiconductor device includes a substrate of semiconductor material. A source region, a drain region, and a conducting region of the semiconductor device are formed in the substrate and doped with a first type of impurities. The conducting region is operable to conduct current between the drain region and the source region when the semiconductor device is operating in an on state. A gate region is also formed in the substrate and doped with a second type of impurities. The gate region abuts a channel region of the conducting region. A stress layer is deposited on at least a portion of the conducting region. The stress layer applies a stress to the conducting region along a boundary of the conducting region that strains at least a portion of the conducting region. | 11-06-2008 |
| 20080272405 | Content addressable memory cell including a junction field effect transistor - A semiconductor device that includes a memory cell having a junction field effect transistor (JFET) used to form a content addressable memory (CAM) cell is disclosed. The JFET may include a data storage region disposed between a first and second insulating region. The data storage region provides a first threshold voltage to the JFET when storing a first data value and provides a second threshold voltage to the JFET when storing a second data value. The memory cell is a dynamic random access memory (DRAM) cell and can be used to form a CAM cell. The CAM cell may be a ternary CAM cell formed with as few as two JFETs. | 11-06-2008 |
| 20080296636 | Devices and integrated circuits including lateral floating capacitively coupled structures - According to the present invention, semiconductor device breakdown voltage can be increased by embedding field shaping regions within a drift region of the semiconductor device. A controllable current path extends between two device terminals on the top surface of a planar substrate, and the controllable current path includes the drift region. Each field shaping region includes two or more electrically conductive regions that are electrically insulated from each other, and which are capacitively coupled to each other to form a voltage divider dividing a potential between the first and second terminals. One or more of the electrically conductive regions are isolated from any external electrical contact. Such field shaping regions can provide enhanced electric field uniformity in current-carrying parts of the drift region, thereby increasing device breakdown voltage. Further aspects of the invention relate to device integration, efficient fabrication of field shaping regions and device isolation features using the same mask for both, and improved device structures. | 12-04-2008 |
| 20090020790 | METHOD FOR FABRICATING POLYSILICON FILM, A GAS PHASE DEPOSITION APPARATUS AND AN ELECTRONIC DEVICE FORMED THEREBY - A method of directly depositing a polysilicon film at a low temperature is disclosed. The method comprises providing a substrate and performing a sequential deposition process. The sequential deposition process comprises first and second deposition steps. In the first deposition step, a first bias voltage is applied to the substrate, and plasma chemical vapor deposition is utilized to form a first polysilicon sub-layer on the substrate. In the second deposition step, a second bias voltage is applied to the substrate, and plasma chemical vapor deposition is utilized to form a second polysilicon sub-layer on the first sub-layer. The first and second sub-layers constitute the polysilicon film, and the first bias voltage differs from the second bias voltage. | 01-22-2009 |
| 20090032848 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING SAME - A method for manufacturing a semiconductor device. The method includes providing a semiconductor body of a conductivity type, wherein the semiconductor body comprises a first surface. At least one buried region of a second conductivity type is formed in the semiconductor body and at least a surface region of the second conductivity type is formed at the first surface of the semiconductor body, wherein the buried region and the surface region are formed such that they are spaced apart from each other. The buried region is formed by deep implantation of a first dopant of the second conductivity type. | 02-05-2009 |
| 20090057727 | Integrated Circuit Using Complementary Junction Field Effect Transistor and MOS Transistor in Silicon and Silicon Alloys - This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junction Field Effect Transistor which is operated in the enhancement mode. The speed-power performance of the JFETs becomes comparable with the CMOS devices at sub-70 nanometer dimensions. However, the maximum power supply voltage for the JFETs is still limited to below the built-in potential (a diode drop). To satisfy certain applications which require interface to an external circuit driven to higher voltage levels, this invention includes the structures and methods to build CMOS devices on the same substrate as the JFET devices. | 03-05-2009 |
| 20090072277 | System and Method for Enabling Higher Hole Mobility in a JFET - A junction field effect transistor comprises a semiconductor wafer having a ( | 03-19-2009 |
| 20090072278 | Method for Applying a Stress Layer to a Semiconductor Device and Device Formed Therefrom - A semiconductor device includes a substrate of semiconductor material. A source region, a drain region, and a conducting region of the semiconductor device are formed in the substrate and doped with a first type of impurities. The conducting region is operable to conduct current between the drain region and the source region when the semiconductor device is operating in an on state. A gate region is also formed in the substrate and doped with a second type of impurities. The gate region abuts a channel region of the conducting region. A stress layer is deposited on at least a portion of the conducting region. The stress layer applies a stress to the conducting region along a boundary of the conducting region that strains at least a portion of the conducting region. | 03-19-2009 |
| 20090134434 | SEMICONDUCTOR DEVICE - A semiconductor device is disclosed. One embodiment provides a top surface. A first lateral semiconductor region is arranged adjacent to the top surface and includes a transistor structure. The transistor structure includes a drain zone of a first conductivity type. A second lateral semiconductor region is arranged below the first semiconductor region and includes a junction field-effect transistor structure. The junction field-effect transistor structure includes a source zone of the first conductivity type which is electrically connected to the drain zone of the transistor structure. | 05-28-2009 |
| 20090159934 | FIELD EFFECT DEVICE WITH REDUCED THICKNESS GATE - A semiconductor structure is fabricated with reduced gate capacitance by thinning of a gate electrode to provide a reduced thickness gate electrode. The gate electrode is thinned after forming a spacer layer adjoining the gate electrode. In addition, the height of the spacer layer may also be reduced. The spacer layer thus has an enhanced horizontal width desired for locating an intrinsic source/drain with respect to an extension region and in particular, an enhanced horizontal width relative to the spacer height. The reduced thickness gate electrode may be fully silicided to provide decreased gate resistance. A raised source/drain layer may be located upon the intrinsic source/drain region. The raised source/drain layer may have a top surface higher than the reduced thickness gate electrode. In addition, the raised source/drain layer may have a top surface higher than the reduced height spacer layer. | 06-25-2009 |
| 20090179234 | FIELD EFFECT TRANSISTOR - A field effect transistor having a T-gate ( | 07-16-2009 |
| 20090206373 | FIELD EFFECT TRANSISTOR - A field effect transistor includes a GaN epitaxial substrate, a gate electrode formed on an electron channel layer of the substrate, and source and drain electrodes arranged spaced apart by a prescribed distance on opposite sides of the gate electrode. The source and drain electrodes are in ohmic contact with the substrate. At an upper portion of the gate electrode, a field plate is formed protruding like a visor to the side of drain electrode. Between the electron channel layer of the epitaxial substrate and the field plate, a dielectric film is formed. The dielectric film is partially removed at a region immediately below the field plate, to be flush with a terminal end surface of the field plate. The dielectric film extends from a lower end of the removed portion to the drain electrode, to be overlapped on the drain electrode. | 08-20-2009 |
| 20090212330 | METHOD OF FABRICATING A BURIED-GATE SEMICONDUCTOR DEVICE AND CORRESPONDING INTEGRATED CIRCUIT - A semiconductor device includes a semiconductive channel region and a gate region. The gate region has at least one buried part extending under the channel region. The buried part of the gate region is formed by forming a cavity under the channel region. That cavity is at least partial filled with silicon and a metal. An annealing step is performed so as to form a silicide of said metal in the cavity. The result is a totally silicided buried gate for the semiconductor device. | 08-27-2009 |
| 20090256177 | Semiconductor device including an ohmic layer - In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer is formed using tungsten silicide that includes tungsten and silicon with an atomic ratio within a range of about 1:5 to about 1:15. The tungsten silicide may be obtained in a chamber using a reaction gas including a tungsten source gas and a silicon source gas by a partial pressure ratio within a range of about 1.0:25.0 to about 1.0:160.0. The reaction gas may have a partial pressure within a range of about 2.05 percent to about 30.0 percent of a total internal pressure of the chamber. When the ohmic layer is employed for a conductive structure, such as a gate structure or a metal wiring, the conductive structure may have a reduced resistance. | 10-15-2009 |
| 20090302355 | STRUCTURE, STRUCTURE AND METHOD FOR FABRICATION JFET IN CMOS - A design structure, and more particularly, to a design structure for manufacturing a JFET in SOI, a JFET and methods of manufacturing the JFET are provided. The JFET includes a gate poly formed directly on an SOI layer and a gate oxide layer interposed between outer edges of the gate poly and the SOI layer. | 12-10-2009 |
| 20090302356 | SEMICONDUCTOR DEVICE PREVENTING FLOATING BODY EFFECT IN A PERIPHERAL REGION THEREOF AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device having a cell region and a peripheral region includes an silicon on insulator (SOI) substrate having a stack structure of a silicon substrate, a buried insulation layer, and a silicon layer. An epi-silicon layer is formed in the buried insulation layer of the peripheral region and connects a peripheral portion of a channel area of the silicon layer to the silicon substrate. A gate is formed on the silicon layer and junction areas are formed in the silicon layer on both sides of the gate. | 12-10-2009 |
| 20100019289 | Junction Field Effect Transistor Using Silicide Connection Regions and Method of Fabrication - A junction field effect transistor comprises a semiconductor substrate and a well region formed in the substrate. A source region of a first conductivity type is formed in the well region. A drain region of the first conductivity type is formed in the well region and spaced apart from the source region. A channel region of the first conductivity type is located between the source region and the drain region and formed in the well region. A gate region of a second conductivity type is formed in the well region. The transistor further includes first, second, and third connection regions. The first connection region is in ohmic contact with the source region and formed of silicide. The second connection region is in ohmic contact with the drain region and formed of silicide. The third connection region in ohmic contact with the gate region. | 01-28-2010 |
| 20100019290 | Junction Field Effect Transistor Using a Silicon on Insulator Architecture - A junction field effect transistor comprises a silicon-on-insulator architecture. A front gate region and a back gate region are formed in a silicon region of the SOI architecture. The silicon region has a thin depth such that the back gate region has a thin depth, and whereby a depletion region associated with the back gate region recedes substantially up to an insulating layer of the SOI architecture. | 01-28-2010 |
| 20100090259 | LATERAL JUNCTION FIELD-EFFECT TRANSISTOR | 04-15-2010 |
| 20100163934 | METHOD FOR FABRICATING A JUNCTION FIELD EFFECT TRANSISTOR AND THE JUNCTION FIELD EFFECT TRANSISTOR ITSELF - A method for fabricating a junction field effect transistor includes the steps of the type I semiconductor at the base thereof being doped with the type II semiconductor to form a type II well with a hole; then, a drive-in process of the type II semiconductor is performed to allow the implant dosage of the type II well getting less gradually from the surroundings of the hole toward the center of the hole; and finally, the gate, the source and the drain of the junction field effect transistor being formed successively on the type II well. The implant dosage at the hole, which is acted as a channel, is determined in accordance with the preset size of the hole during the type II well being formed such that it is capable being compatible with the output voltages of different junction field effect transistors to achieve the purpose of the adjustment of the pinch-off voltage of the junction field effect transistor without the need of the mask and the manufacturing process. | 07-01-2010 |
| 20100171154 | Silicon-On-Insulator Junction Field-Effect Transistor Having A Fully Depleted Body and Fabrication Method Therefor - Silicon-on-insulator JFET (SOI JFET) having a fully depleted body and fabrication methods therefor. SOI JFETs offer leakage advantages over bulk silicon JFETs. However, some SOI JFETs have poor switching characteristics (e.g., high switch on time). The devices and techniques include a fully-depleted body SOI-JFET, with improved switching characteristic over partially-depleted SOI JFET or bulk silicon devices. In one example, by tuning the thickness of the silicon containing layer of the SOI substrate, the body region of the JFET can be fully depleted during the OFF-state thus offering the performance benefits of suppressed leakage current. Additionally, improved AC performance (e.g., faster switching time) is achieved. | 07-08-2010 |
| 20100171155 | Body-biased Silicon-On-Insulator Junction Field-Effect Transistor Having A Fully Depleted Body and Fabrication Method Therefor - Silicon-on-insulator JFET having a body bias and a fully depleted body and fabrication methods therefore are disclosed. SOI JFETs offer leakage advantages over bulk silicon JFETs. However, some SOI JFETs have poor switching characteristics (e.g., high switch on time), and have poor leakage performance at high temperatures. The techniques herein introduced include a fully-depleted body SOI-JFET, with a non-zero bias applied to its body. In one example, the body region of the JFET can be fully depleted by tuning the thickness of the silicon containing layer of the SOI substrate. Additionally, the deep depletion can be induced by applying a non-zero bias to the body region, at a range of operating temperatures. Full body depletion and/or the application of body bias offers the benefits of suppressed leakage current at higher operating temperatures (e.g., between or above 25-115 C) and improved AC performance (e.g., faster switching time). | 07-08-2010 |
| 20100187576 | Method of processing resist, semiconductor device, and method of producing the same - A surface component film ( | 07-29-2010 |
| 20100219454 | FIELD-EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A field-effect transistor with improved moisture resistance without an increase in gate capacitance, and a method of manufacturing the field-effect transistor are provided. The field-effect transistor includes: a T-shaped gate electrode on a semiconductor layer; and a first highly moisture-resistant protective film including one of an insulating film and an organic film having high etching resistance, the first highly moisture-resistant protective film being located above the T-shaped gate electrodes over all of a region in which the T-shaped gate electrode is located. A cavity is located between the semiconductor layer and the first highly moisture-resistant protective film below a canopy of the T-shaped gate electrode. An end surface of the cavity is closed by a second highly moisture-resistant film. | 09-02-2010 |
| 20100295100 | INTEGRATED CIRCUIT HAVING A BULK ACOUSTIC WAVE DEVICE AND A TRANSISTOR - A bulk GaN layer is on a first surface of a substrate, wherein the bulk GaN layer has a GaN transistor region and a bulk acoustic wave (BAW) device region. A source/drain layer is over a first surface of the bulk GaN layer in the GaN transistor region. A gate electrode is formed over the source/drain layer. A first BAW electrode is formed over the first surface of the bulk GaN layer in the BAW device region. An opening is formed in a second surface of the substrate, opposite the first surface of the substrate, which extends through the substrate and exposes a second surface of the bulk GaN layer, opposite the first surface of the bulk GaN layer. A second BAW electrode is formed within the opening over the second surface of the bulk GaN layer. | 11-25-2010 |
| 20110062500 | SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF - A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor substrate which comprise a first type well and a second type well, and a plurality of junction regions therebetween, wherein each of the junction regions adjoins the first and the second type wells. A gate electrode disposed on the semiconductor substrate and overlies at least two of the junction regions. A source and a drain are in the semiconductor substrate oppositely adjacent to the gate electrode. | 03-17-2011 |
| 20110101423 | JUNCTION FIELD EFFECT TRANSISTOR - A field effect transistor having a drain, a gate and a source, where the drain and source are formed by semiconductor regions of a first type, and in which a further doped region is provided intermediate the gate and the drain. Field gradients around the drain are thereby reduced. | 05-05-2011 |
| 20110127585 | LATERAL JUNCTION FIELD-EFFECT TRANSISTOR - A lateral junction field-effect transistor capable of preventing the occurrence of leakage current and realizing a sufficient withstand voltage can be provided. In a lateral JFET according to the present invention, a buffer layer is located on a main surface of a SiC substrate and includes a p-type impurity. A channel layer is located on the buffer layer and includes an n-type impurity having a higher concentration than the concentration of the p-type impurity in the buffer layer. A source region and a drain region are of n-type and formed to be spaced from each other in a surface layer of the channel layer, and a p-type gate region is located in the surface layer of the channel layer and between the source region and the drain region. A barrier region is located in an interface region between the channel layer and the buffer layer and in a region located under the gate region and includes a p-type impurity having a higher concentration than the concentration of the p-type impurity in the buffer layer. | 06-02-2011 |
| 20110140179 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a rectifying element; an electrode pad electrically connected to the rectifying element; and a resistance and a depletion transistor arranged between the rectifying element and the electrode pad, and electrically connected to each other. The semiconductor device has a configuration in which the rectifying element, the resistance, the depletion transistor, and the electrode pad are serially connected. The semiconductor device is configured to generate a gate potential of the depletion transistor based on a difference in potential across the resistance and to produce a depletion layer in a channel of the depletion transistor based on the gate potential. As a result, a semiconductor device having reasonably large current at low voltage and small current at high voltage can be obtained. | 06-16-2011 |
| 20110204422 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a substrate, a compound semiconductor layer formed over the substrate, and a protective insulating film composed of silicon nitride, which is formed over a surface of the compound semiconductor layer and whose film density in an intermediate portion is lower than that in a lower portion. | 08-25-2011 |
| 20120001240 | Junction field effect transistor structure - A junction field effect transistor structure includes a grid electrode, a source electrode, a drain electrode and a substrate. The grid electrode includes a polysilicon layer and a P-type implanted layer. The source electrode includes an N-type implanted layer, an N-type well layer and a heavy-implanted N-type well layer. The drain electrode includes the N-type implanted layer, the N-type well layer and the heavy-implanted N-type well layer. The substrate is connected with a substrate connecting end by the P-type implanted layer, a P-type well layer, a heavy-implanted P-type well layer and a P-type buried layer. The junction field effect transistor structure of the present invention can be manufactured without adding any masking step based on the existing technologies, and has the high-voltage resistant characteristic to meet the requirements in practical applications. Furthermore, it has the compact structure and compatible technology. | 01-05-2012 |
| 20120074469 | ASYMMETRIC WEDGE JFET, RELATED METHOD AND DESIGN STRUCTURE - A junction gate field-effect transistor (JFET) for an integrated circuit (IC) chip is provided comprising a source region, a drain region, a lower gate, and a channel, with an insulating shallow trench isolation (STI) region extending from an inner edge of an upper surface of the source region to an inner edge of an upper surface of the drain region, without an intentionally doped region, e.g., an upper gate, coplanar with an upper surface of the IC chip between the source/drain regions. In addition, an asymmetrical quasi-buried upper gate can be included, disposed under a portion of the STI region, but not extending under a portion of the STI region proximate to the drain region. Embodiments of this invention also include providing an implantation layer, under the source region, to reduce R | 03-29-2012 |
| 20120104467 | SELF-ALIGNED CONTACT STRUCTURE TRENCH JFET - According to one embodiment, a self-aligned trench structure junction gate field-effect transistor (JFET) includes a silicon substrate, two or more trenches having a P-type polysilicon gate region near a bottom portion of the trench and an interlayer dielectric layer (ILDL) above the P-type polysilicon gate region, a channel region separating each trench including epitaxial silicon, an N+ source region above the channel region extending between a top of each trench, and a source metal above the N+ source region. In another embodiment, a self-aligned trench structure JFET includes a silicon substrate, two or more trenches having an N-type polysilicon gate region near a bottom portion of the trench and an ILDL above the N-type polysilicon gate region, a channel region separating each trench including epitaxial silicon, a P+ source region above the channel region extending between a top of each trench, and a source metal above the P+ source region. | 05-03-2012 |
| 20120139012 | METHOD AND APPARATUS FOR CONTROLLING A CIRCUIT WITH A HIGH VOLTAGE SENSE DEVICE - A high-voltage junction field-effect transistor (JFET) includes a semiconductor substrate, a well region, first, second, and third doped regions, and first, second, and third terminals. The first doped region is disposed in the well region and the second dope region is laterally displaced from the well region. The third doped region is disposed in the well region between the first and second doped regions. A portion of the well region is substantially depleted of free charge carriers when a first voltage between the first and second terminals is greater than or equal to a pinch-off voltage. A voltage output at the third terminal is substantially proportional to the first voltage when the first voltage is less than the pinch-off voltage, and the voltage output at the third terminal is substantially fixed and less than the first voltage when the first voltage is greater than or equal to the pinch-off voltage. | 06-07-2012 |
| 20120146104 | STRUCTURE AND LAYOUT OF A FET PRIME CELL - Method of making a semiconductor device that includes forming a source and a drain in a substrate, forming a gate on the substrate between the source and drain, forming a substrate contact in electrical contact with the source, and forming an electrical contact to the source, drain and gate, and the substrate. | 06-14-2012 |
| 20120153361 | FIELD-EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF - Disclosed are a field-effect transistor and a manufacturing method thereof. The disclosed field-effect transistor includes: a semiconductor substrate; a source ohmic metal layer formed on one side of the semiconductor substrate; a drain ohmic metal layer formed on another side of the semiconductor substrate; a gate electrode formed between the source ohmic metal layer and the drain ohmic metal layer, on an upper portion of the semiconductor substrate; an insulating film formed on the semiconductor substrate's upper portion including the source ohmic metal layer, the drain ohmic metal layer and the gate electrode; and a plurality of field electrodes formed on an upper portion of the insulating film, wherein the insulating film below the respective field electrodes has different thicknesses. | 06-21-2012 |
| 20120181583 | JUNCTION FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF - A junction field effect transistor includes a lower P-type substrate layer of a semiconductor substrate; an N-type channel layer which may be formed on and/or over the P-type substrate layer within an active area; an upper P-type diffusion layer which may be formed on and/or over the N-type channel layer at a prescribed depth over the entire active area; an additional P-type diffusion layer which may be formed in a ripple pattern in the upper P-type diffusion layer; a gate electrode which may be formed on and/or over the upper P-type diffusion layer; and a source electrode and a drain electrode which may be formed on and/or over both sides of the upper P-type diffusion layer within the active area on the semiconductor substrate. The additional P-type diffusion layer in the ripple pattern may be formed of a plurality of P-type diffusion layers which are formed to be separated from each other in the upper P-type diffusion layer. | 07-19-2012 |
| 20120187458 | Asymmetric High-Voltage JFET and Manufacturing Process - A high voltage JFET has a deep well of a first type of conductivity made in a semiconductor substrate, a further well of an opposite second type of conductivity arranged in the deep well, a shallow well of a first type of conductivity arranged in the further well, a first contact region for source and a second contact region for drain arranged in the further well, a third contact region for gate arranged between the first contact region and the second contact region in the shallow well, a first distance between the first contact region and the third contact region being smaller than a second distance between the second contact region and the third contact region, and an electrical connection between the first contact region and the second contact region via at least one channel region present between the deep well and the shallow well in the further well. | 07-26-2012 |
| 20130001654 | MASK-BASED SILICIDATION FOR FEOL DEFECTIVITY REDUCTION AND YIELD BOOST - A semiconductor device with reduced defect density is fabricated by forming localized metal silicides instead of full area silicidation. Embodiments include forming a transistor having a gate electrode and source/drain regions on a substrate, forming a masking layer with openings exposing portions of both the gate electrode and source/drain regions over the substrate, depositing metal in the openings on the exposed portions, forming silicides in the openings, and removing unreacted metal and the masking layer. | 01-03-2013 |
| 20130001655 | Heat Dissipation Structure of SOI Field Effect Transistor - The present invention discloses a heat dissipation structure for a SOI field effect transistor having a schottky source/drain, which relates to a field of microelectronics. The heat dissipation structure includes two holes connected with a drain terminal or with both a source terminal and a drain terminal, which are filled with an N-type material with high thermoelectric coefficient and a P-type material with high thermoelectric coefficient respectively. A metal wire for the N-type material with high thermoelectric coefficient in the vicinity of the drain terminal is applied a high potential with respect to the drain terminal, and a metal wire for the P-type material with high thermoelectric coefficient in the vicinity of the drain terminal is applied a low potential with respect to the drain terminal. A metal wire for the N-type material with high thermoelectric coefficient in the vicinity of the source terminal is applied a high potential with respect to the source terminal, and a metal wire for the P-type material in the vicinity of the source terminal is applied a lower potential with respect to the source terminal. By way of a Peltier effect, in the present invention heat can be absorbed at a contact portion between the thermoelectric material and the source/drain, and at the same time dissipated at a connection portion between the thermoelectric material and a bottom electrode metal, so that the heat generated in an active region of the device is effectively transferred to the substrate and dissipated through a heat sink. | 01-03-2013 |
| 20130069122 | Z.sup.2FET Field-effect transistor with a vertical subthreshold slope and with no impact ionization - The transistor comprises first and second source/drain electrodes formed in a semiconductor film by N-doped and P-doped areas, respectively. A polarization voltage is applied between the two source/drain electrodes in order to impose to the P-doped electrode a potential higher than that of the N-doped electrode. The transistor comprises first and second devices for generating a potential barrier in the semiconductor film. The two potential barriers are opposed to the passage of the charge carriers emitted by the first and second source/drain electrodes, respectively. The two potential barriers are shifted with respect to an axis connecting the two source/drain electrodes. The two devices for generating a potential barrier are configured to generate a potential barrier having a variable amplitude and it are electrically connected to the gate and to the counter electrode. | 03-21-2013 |
| 20130119442 | JUNCTION FIELD-EFFECT TRANSISTOR WITH RAISED SOURCE AND DRAIN REGIONS FORMED BY SELECTIVE EPITAXY - Junction field-effect transistors, methods for fabricating junction field-effect transistors, and design structures for a junction field-effect transistor. A source and a drain of the junction field-effect transistor are comprised of a semiconductor material grown by selective epitaxy and in direct contact with a top surface of a semiconductor layer. A gate is formed that is aligned with a channel laterally disposed in the semiconductor layer between the source and the drain. The source, the drain, and the semiconductor layer are each comprised of a second semiconductor material having an opposite conductivity type from a first semiconductor material comprising the gate. | 05-16-2013 |
| 20130168741 | COMPLEMENTARY JUNCTION FIELD EFFECT TRANSISTOR DEVICE AND ITS GATE-LAST FABRICATION METHOD - The disclosure relates to a complementary junction field effect transistor (c-JFET) and its gate-last fabrication method. The method of fabricating a semiconductor device includes: forming a dummy gate on a first conductivity type wafer, forming sidewall spacers on opposite sides of the dummy gate, forming a source and a drain regions on the opposite sides of the dummy gate, removing the dummy gate, forming a first semiconductor region of a second conductivity type in an opening exposed through the removing the dummy gate, and forming a gate electrode in the opening. | 07-04-2013 |
| 20130214333 | JFET ESD PROTECTION CIRCUIT FOR LOW VOLTAGE APPLICATIONS - An electrostatic discharge (ESD) protection circuit is disclosed. The circuit includes a first terminal ( | 08-22-2013 |
| 20130248944 | JUNCTION TYPE FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF - According to one embodiment, a junction type field effect transistor includes a first conductive type semiconductor substrate, a first conductive type drift layer, a second conductive type gate region, a first conductive type channel layer, a first conductive type source region, a source electrode, a drain electrode, a second conductive type gate contact layer, and a gate electrode. The drift layer is provided on a first main surface of the semiconductor substrate. The gate region is provided on a surface of the drift layer. The channel layer is provided on the drift layer and the gate region. The source region is provided on a surface of the channel layer to face the gate region, and has an impurity concentration higher than the channel layer. The source electrode is provided on the channel layer with Schottky contact and on the source region with ohmic contact. | 09-26-2013 |
| 20130299881 | ASYMMETRIC WEDGE JFET, RELATED METHOD AND DESIGN STRUCTURE - A junction gate field-effect transistor (JFET) for an integrated circuit (IC) chip is provided comprising a source region, a drain region, a lower gate, and a channel, with an insulating shallow trench isolation (STI) region extending from an inner edge of an upper surface of the source region to an inner edge of an upper surface of the drain region, without an intentionally doped region, e.g., an upper gate, coplanar with an upper surface of the IC chip between the source/drain regions. In addition, an asymmetrical quasi-buried upper gate can be included, disposed under a portion of the STI region, but not extending under a portion of the STI region proximate to the drain region. Embodiments of this invention also include providing an implantation layer, under the source region, to reduce R | 11-14-2013 |
| 20130313617 | Embedded JFETs for High Voltage Applications - A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET. | 11-28-2013 |
| 20130328110 | THIN FILM HYBRID JUNCTION FIELD EFFECT TRANSISTOR - Junction field effect transistors are provided which include a gate junction located on a surface of a crystalline semiconductor material of a first conductivity type. The gate junction can be selected from one of a doped hydrogenated crystalline semiconductor material layer portion of a second conductivity type which is opposite the first conductivity type, a doped hydrogenated non-crystalline semiconductor material layer portion of a second conductivity type which is opposite the first conductivity type, and a Schottky contact. | 12-12-2013 |
| 20140097478 | REDUCED CHARGE TRANSISTOR - Representative implementations of devices and techniques provide a reduced charge transistor arrangement. The capacitance and/or charge of a transistor structure may be reduced by minimizing an overlap of a top gate with respect to a drain of the transistor. | 04-10-2014 |
| 20140264476 | JUNCTION FET SEMICONDUCTOR DEVICE WITH DUMMY MASK STRUCTURES FOR IMPROVED DIMENSION CONTROL AND METHOD FOR FORMING THE SAME - A method for simultaneously forming JFET devices and MOSFET devices on a substrate includes using gate structures which serve as active gate structures in the MOSFET region, as dummy gate structures in the JFET portion of the device. The dummy gate electrodes are used as masks and determine the spacing between gate regions and source/drain regions, the width of the gate regions, and the spacing between adjacent gate regions according to some embodiments. The transistor channel is therefore accurately dimensioned. | 09-18-2014 |
| 20140306270 | MULTI-SOURCE JFET DEVICE - A junction field-effect transistor (JFET) device is provided. The JFET includes a drain region, a source region, and a junction gate region disposed between the drain region and the source region, and the source region includes two or more source terminals. | 10-16-2014 |
| 20150021669 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A non-planar JFET device having a thin fin structure is provided. A fin is formed projecting upwardly from or through a top surface of a substrate, where the fin has a first semiconductor layer portion formed from a first semiconductor material of a first conductivity type. The first semiconductor layer portion has a source region and a drain region, a channel region extending between the source region and the drain region. Two or more channel control regions are formed adjoining the channel region for generating charge depletion zones at and extending into the channel region for thereby controlling current conduction through the channel region. A gate is provided so as to adjoin and short together the at least two channel control regions from the outer sides of the channel control regions. | 01-22-2015 |
| 20150295053 | HIGH VOLTAGE FIELD EFFECT TRANSITOR FINGER TERMINATIONS - A field effect transistor having at least one structure configured to redistribute and/or reduce an electric field from gate finger ends is disclosed. Embodiments of the field effect transistor include a substrate, an active region disposed on the substrate, at least one source finger in contact with the active region, at least one drain finger in contact with the active region, and at least one gate finger in rectifying contact with the active region. One embodiment has at least one end of the at least one gate finger extending outside of the active region. Another embodiment includes at least one source field plate integral with the at least one source finger. The at least one source field plate extends over the at least one gate finger that includes a portion outside of the active region. Either embodiment can also include a sloped gate foot to further improve high voltage operation. | 10-15-2015 |
| 20150333138 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - A semiconductor device includes: a nitride semiconductor layer; a first silicon nitride film that is formed on the nitride semiconductor layer, has a first opening whose inner wall is a forward tapered shape; a second silicon nitride film that is formed on the first silicon nitride film, and has a second opening whose inner wall is an inverse tapered shape; and a gate electrode formed so as to cover the whole surface of the nitride semiconductor layer exposed on the inside of the first opening; wherein a side wall of the gate electrode separates from the first silicon nitride film and the second silicon nitride film via a cavity. | 11-19-2015 |
| 20160020335 | TRANSISTORS COMPRISING DOPED REGION-GAP-DOPED REGION STRUCTURES AND METHODS OF FABRICATION - Embodiments of the present invention provide transistors with controlled junctions and methods of fabrication. A dummy spacer is used during the majority of front end of line (FEOL) processing. Towards the end of the FEOL processing, the dummy spacers are removed and replaced with a final spacer material. Embodiments of the present invention allow the use of a very low-k material, which is highly thermally-sensitive, by depositing it late in the flow. Additionally, the position of the gate with respect to the doped regions is highly controllable, while dopant diffusion is minimized through reduced thermal budgets. This allows the creation of extremely abrupt junctions whose surface position is defined using a sacrificial spacer. This spacer is then removed prior to final gate deposition, allowing a fixed gate overlap that is defined by the spacer thickness and any diffusion of the dopant species. | 01-21-2016 |
| 20160056303 | Bootstrap MOS for High Voltage Applications - A device includes a p-well region, and a first High-Voltage N-type Well (HVNW) region and a second HVNW region contacting opposite edges of the p-well region. A P-type Buried Layer (PBL) has opposite edges in contact with the first HVNW region and the second HVNW region. An n-type buried well region is underlying the PBL. The p-well region and the n-type buried well region are in contact with a top surface and a bottom surface, respectively, of the PBL. The device further includes a n-well region in a top portion of the p-well region, an n-type source region in the n-well region, a gate stack overlapping a portion of the p-well region and a portion of the second HVNW region, and a channel region under the gate stack. The channel region interconnects the n-well region and the second HVNW region. | 02-25-2016 |
| 20160071835 | METAL GATE FOR ROBUST ESD PROTECTION - A method of forming a metal gate diode ESD protection device and the resulting device are provided. Embodiments include forming a metal gate diode including a metal gate on a substrate; forming an n-type cathode on a first side of the metal gate diode; and forming a p-type anode on a second side of the metal gate diode, opposite the first side. | 03-10-2016 |
