| Entries |
| Document | Title | Date |
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| 20080246059 | Device Fabrication by Anisotropic Wet Etch - A method of fabrication and a field effect device structure are presented that reduce source/drain capacitance and allow for device body contact. A Si based material pedestal is produced, the top surface and the sidewalls of which are oriented in a way to be substantially parallel with selected crystallographic planes of the pedestal and of a supporting member. The pedestal is wet etched with an anisotropic solution containing ammonium hydroxide. The sidewalls of the pedestal become faceted forming a segment in the pedestal with a reduced cross section. The dopant concentration in the reduced cross section segment is chosen to be sufficiently high for it to provide for electrical continuity through the pedestal. | 10-09-2008 |
| 20080277694 | SEMICONDUCTOR COMPONENT AND METHOD OF MANUFACTURE - A semiconductor component that includes a Schottky device, an edge termination structure, a non-Schottky semiconductor device, combinations thereof and a method of manufacturing the semiconductor component. A semiconductor material includes a first epitaxial layer disposed on a semiconductor substrate and a second epitaxial layer disposed on the first epitaxial layer. The second epitaxial layer has a higher resistivity than the semiconductor substrate. A Schottky device and a non-Schottky semiconductor device are manufactured from the second epitaxial layer. In accordance with another embodiment, a semiconductor material includes an epitaxial layer disposed over a semiconductor substrate. The epitaxial layer has a higher resistivity than the semiconductor substrate. A doped region is formed in the epitaxial layer. A Schottky device and a non-Schottky semiconductor device are manufactured from the epitaxial layer. | 11-13-2008 |
| 20080283874 | Field-Effect Transistors - The present invention provides a field-effect transistor and method for the fabrication of a field-effect transistor by deposition on a substrate ( | 11-20-2008 |
| 20080290378 | Transistor package with wafer level dielectric isolation - A low cost transistor package is provided for high power applications. The package provides high thermal conductivity and dissipation for a silicon transistor die, high current carrying capability and isolation, and high power and thermal cycle life performance and reliability. A dielectric layer is fixed to a silicon transistor die, for coupling to a heat conducting buffer and attachment to a substrate. The dielectric layer is fixed to the die by growing the dielectric layer, depositing the dielectric layer, or applying the dielectric layer using a plasma spray. In an aspect, a conductive layer is formed to the silicon transistor die by a thermal or kinetic spray process, and the dielectric layer is applied to the conductive layer. The dielectric layer may also be established either before or after the transistor fabrication. Electrical and thermal interconnects are advantageously positioned from opposite sides of the silicon transistor die. | 11-27-2008 |
| 20090001426 | Integrated Fin-Local Interconnect Structure - Embodiments of the invention generally relate to semiconductor devices, and more specifically to interconnecting semiconductor devices. A silicide layer may be formed on selective areas of a fin structure connecting one or more semiconductor devices or semiconductor device components. By providing silicided fin structures to locally interconnect semiconductor devices, the use of metal contacts and metal layers may be obviated, thereby allowing formation of smaller, less complex circuits. | 01-01-2009 |
| 20090020786 | SEMICONDUCTOR DEVICE - A method for forming a semiconductor device on a substrate having a first major surface lying in a plane and the semiconductor device are disclosed. In one aspect, the method comprises, after patterning the substrate to form at least one structure extending from the substrate in a direction substantially perpendicular to a major surface of the substrate, forming locally modified regions at locations in the substrate not covered by the structure, thus locally increasing etching resistance of these regions. Forming locally modified regions may prevent under-etching of the structure during further process steps in the formation of the semiconductor device. | 01-22-2009 |
| 20090020787 | SEMICONDUCTOR DEVICE USING SEMICONDUCTOR NANOWIRE AND DISPLAY APPARATUS AND IMAGE PICK-UP APPARATUS USING THE SAME - A semiconductor device, comprising a semiconductor nanowire having a first region with one of a PN junction and a PIN junction and a second region with a field effect transistor structure, a pair of electrodes connected to both ends of the semiconductor nanowire, and a gate electrode provided in at least a part of the second region via an insulating layer. The semiconductor nanowire has a P-type semiconductor portion and an N-type semiconductor portion, and one of the P-type semiconductor portion and the N-type semiconductor portion is a common structural element of both the first and second regions. | 01-22-2009 |
| 20090039394 | SEMICONDUCTOR DEVICE - The present invention enhances voltage conversion efficiency of a semiconductor device. In a non-isolated DC-DC converter that includes a high-side switch power MOSFET and a low-side switch power MOSFET, which are series-connected, the high-side switch power MOSFET and driver circuits for driving the high-side and low-side switch power MOSFETs are formed within one semiconductor chip, whereas the low-side switch power MOSFET is formed in another semiconductor chip. The two semiconductor chips are sealed in a single package. | 02-12-2009 |
| 20090114953 | Method For Achieving Uniform Etch Depth Using Ion Implantation And A Timed Etch - A method of performing a timed etch of a material to a precise depth is provided. In this method, ion implantation of the material is performed before the timed etch. This ion implantation process substantially enhances the etch rate of the material within a precisely controlled depth range corresponding to the range of implantation-induced damage. By using the ion implantation, the variation in vertical etch depth can be reduced by a factor approximately equal to the etch rate of the damaged material divided by the etch rate of the undamaged material. The vertical etch depth can be used to provide a vertical dimension of a non-planar semiconductor device. Minimizing vertical device dimension variations on a wafer can reduce device and circuit performance variations, which is highly desirable. | 05-07-2009 |
| 20090127588 | PATTERNING TECHNIQUES - A method of forming a patterned layer, including the steps of: (i) depositing via a liquid medium a first material onto a substrate to form a first body on said substrate; (ii) depositing via a liquid medium a second material onto said substrate to form a second body, wherein said first body is used to control said deposition of said second material so as to form a patterned structure including said first and second bodies; and (iii) using said patterned structure to control the removal of selected portions of a layer of material in a dry etching process or in a wet etching process using a bath of etchant. | 05-21-2009 |
| 20090184343 | ISOLATION STRUCTURE, NON-VOLATILE MEMORY HAVING THE SAME, AND METHOD OF FABRICATING THE SAME - A method of forming an isolation structure, comprising: (a) providing a base having a recess; (b) forming a stop layer on the base and in the recess; (c) forming a dielectric material on the stop layer so as to allow the rest of the recess to be filled with the dielectric material; (d) removing the dielectric material over the base by performing a chemical mechanical polishing (CMP) process until a part of the stop layer is exposed so as to form a dielectric layer in the recess; and (e) removing a part of the stop layer, wherein the another part of the stop layer and the dielectric layer filled in the recess constitute the isolation structure. | 07-23-2009 |
| 20090250727 | SUPER JUNCTION SEMICONDUCTOR DEVICE - In the specification and drawing a super junction semiconductor device is disclosed. The super junction semiconductor device comprises a P-type layer, a N | 10-08-2009 |
| 20090256175 | Method of doping transistor comprising carbon nanotube, method of controlling position of doping ion, and transistors using the same - Provided are a method of doping a carbon nanotube (CNT) of a field effect transistor and a method of controlling the position of doping ions. The method may include providing a source, a drain, the CNT as a channel between the source and the drain, and a gate, applying a first voltage to the gate, and adsorbing ions on a surface of the CNT. | 10-15-2009 |
| 20090294803 | METHODS AND DEVICES FOR FABRICATING AND ASSEMBLING PRINTABLE SEMICONDUCTOR ELEMENTS - The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations. | 12-03-2009 |
| 20090294804 | HIGH-EFFICIENCY THINNED IMAGER WITH REDUCED BORON UPDIFFUSION - A method for fabricating a back-illuminated semiconductor imaging device on an ultra-thin semiconductor-on-insulator wafer (UTSOI) is disclosed. The UTSOI wafer includes a mechanical substrate, an insulator layer, and a seed layer. At least one dopant is applied to the semiconductor substrate. A first portion of an epitaxial layer is grown on the seed layer. A predefined concentration of carbon impurities is introduced into the first portion of the epitaxial layer. A remaining portion of the epitaxial layer is grown. During the epitaxial growth process, the at least one dopant diffuses into the epitaxial layer such that, at completion of the growing of the epitaxial layer, there exists a net dopant concentration profile which has an initial maximum value at an interface between the seed layer and the insulator layer and which decreases monotonically with increasing distance from the interface within at least a portion of at least one of the semiconductor substrate and the epitaxial layer. | 12-03-2009 |
| 20090309137 | FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURE THEREOF - A field effect transistor comprising a semiconductor substrate comprising an electrically conducting channel layer therein; a plurality of source and drain fingers on a first face of the substrate, each finger separated from the adjacent finger by a gate channel; the gate channels comprising at least one active gate channel defined by a source finger and a drain finger arranged on the first face such that current is free to flow between them via the electrically conducting channel layer, and, a plurality of inactive gate channels, each inactive gate channel being defined by either two fingers of the same type or a source finger and a drain finger, the source finger and drain finger being arranged on the first face such that current is not free to flow between them via the electrically conducting channel layer; the gate channels being arranged such that each active gate channel has a gate channel on each side; each active gate channel comprising a gate therein for controlling current flow in the electrically conducting channel layer. | 12-17-2009 |
| 20100001322 | SEMICONDUCTOR DEVICE - The invention relates to a method of manufacturing a semiconductor device ( | 01-07-2010 |
| 20100025737 | Field-effect transistor - A field-effect transistor according to the present invention includes a source electrode that is formed in an active region, and a drain electrode that is formed in the active region. Further, the field-effect transistor includes a gate electrode that is formed in the active region and disposed between the source electrode and the drain electrode, a field plate electrode that is formed in a vicinity of the gate electrode outside a region disposed between the gate electrode and the source electrode, and an FP pad that is included in the FP electrode, the FP pad being formed outside the active region and being grounded. | 02-04-2010 |
| 20100044757 | SEMICONDUCTOR DEVICE HAVING A CONTACT PLUG AND MANUFACTURING METHOD THEREOF - There is provided a semiconductor device that includes: a transistor having a gate electrode, a source region, arid a drain region; a first inter-layer insulation film covering the transistor; a first contact plug formed penetrating through the first inter-layer insulation film and connected to either the source region or the drain region; a second inter-layer insulation film covering the first contact plug; a groove extending in the second inter-layer insulation film in a same direction as an extending direction of the gate electrode and exposing a top surface of the first contact plug at a bottom thereof; a second contact plug connected to the first contact plug and formed in the groove; and a wiring pattern extending on the second inter-layer insulation film so as to traverse the groove and integrated with the second contact plug. | 02-25-2010 |
| 20100109054 | PATTERN FORMATION IN SEMICONDUCTOR FABRICATION - Provided is a semiconductor device. The device includes a substrate having a photo acid generator (PAG) layer on the substrate. The PAG layer is exposed to radiation. A photoresist layer is formed on the exposed PAG layer. The exposed PAG layer generates an acid. The acid decomposes a portion of the formed photoresist layer. In one embodiment, the PAG layer includes organic BARC. The decomposed portion of the photoresist layer may be used as a masking element. | 05-06-2010 |
| 20100117122 | Optimized Device Isolation - A structure for a semiconductor device includes an isolated MOSFET (e.g., NFET) having triple-well technology adjacent to an isolated PFET which itself is adjacent to an isolated NFET. The structure includes a substrate in which is formed a deep n-band region underneath any n-wells, p-wells and p-band regions within the substrate. One p-band region is formed above the deep n-band region and underneath the isolated p-well for the isolated MOSFET, while another p-band region is formed above the deep n-band region and underneath all of the p-wells and n-wells, including those that are part of the isolated PFET and NFET devices within the substrate. The n-wells for the isolated MOSFET are connected to the deep n-band region. The resulting structure provides for improved device isolation and reduction of noise propagating from the substrate to the FETs while maintaining the standard CMOS spacing layout spacing rules and electrical biasing characteristics both external and internal to the triple-well isolation regions. | 05-13-2010 |
| 20100155786 | Methods and devices for forming nanostructure monolayers and devices including such monolayers - Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, formation of arrays in spin-on-dielectrics, solvent annealing after nanostructure deposition, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices). Methods for protecting nanostructures from fusion during high temperature processing are also provided. | 06-24-2010 |
| 20100181601 | SILICON BASED OPTO-ELECTRIC CIRCUITS - A semiconductor structure, comprising: a substrate; a seed layer over an upper surface of the substrate; a semiconductor layer disposed over the seed layer; a transistor device in the semiconductor layer; wherein the substrate has an aperture therein, such aperture extending from a bottom surface of the substrate and terminating on a bottom surface of the seed layer; and an opto-electric structure disposed on the bottom surface of the seed layer. | 07-22-2010 |
| 20100219453 | Nanotube Device - A device includes a nanotube source electrode located on a surface of a substrate between nanotube gate and nanotube drain electrodes. | 09-02-2010 |
| 20100230727 | Electric Circuit with Vertical Contacts - An electrical circuit includes at least two unit cells configured on a planar substrate which extends in one plane. The unit cells respectively have at least two contact points with a different function and include at least one dielectric layer disposed on the substrate and/or on the unit cells and at least two contact surfaces which are disposed parallel to the plane above the contact points and/or the substrate. The contact points with the same function are connected electrically to at least one common contact surface for at least a part of the contact points of the same function via at least one through-contacting through the dielectric layer and able to be contacted in common from outside via the corresponding contact surfaces. | 09-16-2010 |
| 20100237389 | DESIGN STRUCTURE FOR HEAVY ION TOLERANT DEVICE, METHOD OF MANUFACTURING THE SAME AND STRUCTURE THEREOF - The invention relates to a design structure, and more particularly, to a design structure for a heavy ion tolerant device, method of manufacturing the same and a structure thereof. The structure includes a first device having a diffusion comprising a drain region and source region and a second device having a diffusion comprising a drain region and source region. The first and second device are aligned in an end-to-end layout along a width of the diffusion of the first device and the second device. A first isolation region separating the diffusion of the first device and the second device. | 09-23-2010 |
| 20100244103 | STRUCTURE AND METHOD OF FABRICATING FINFET - A CMOS FinFET device and a method of manufacturing the same using a three dimensional doping process is provided. The method of forming the CMOS FinFET includes forming fins on a first side and a second side of a structure and forming spacers of a dopant material having a first dopant type on the fins on the first side of the structure. The method further includes annealing the dopant material such that the first dopant type diffuses into the fins on the first side of the structure. The method further includes protecting the first dopant type from diffusing into the fins on the second side of the structure during the annealing. | 09-30-2010 |
| 20110001169 | FORMING UNIFORM SILICIDE ON 3D STRUCTURES - By using a non-conformal diffusion barrier in conjunction with a similarly deposited non-conformal initial deposition of siliciding material, a substantially uniform and conformal silicide can be formed in a 3D structure such as the fin of a FinFET. The siliciding material may be nickel (Ni), the diffusion barrier may be titanium (Ti) or titanium nitride (TiN). Generally, the diffusion barrier may be any material which will inhibit, but not block, diffusion of the siliciding material into the silicon. In this manner, a non-conformal barrier deposition, in conjunction with a non-conformal silicide material deposition, after anneal, results in substantially conformal silicide formation. | 01-06-2011 |
| 20110037102 | HYBRID PLASMA-SEMICONDUCTOR OPTOELECTRONIC DEVICES AND TRANSISTORS - The invention provides combination semiconductor and plasma devices, including transistors and phototransistors. A preferred embodiment hybrid plasma semiconductor device has active solid state semiconductor regions; and a plasma generated in proximity to the active solid state semiconductor regions. Devices of the invention are referred to as hybrid plasma-semiconductor devices, in which a plasma, preferably a microplasma, cooperates with conventional solid state semiconductor device regions to influence or perform a semiconducting function, such as that provided by a transistor. The invention provides a family of hybrid plasma electronic/photonic devices having properties previously unavailable. In transistor devices of the invention, a low temperature, glow discharge is integral to the hybrid transistor. Example preferred devices include hybrid BJT and MOSFET devices. | 02-17-2011 |
| 20110062498 | EMBEDDED SILICON GERMANIUM SOURCE DRAIN STRUCTURE WITH REDUCED SILICIDE ENCROACHMENT AND CONTACT RESISTANCE AND ENHANCED CHANNEL MOBILITY - Semiconductor devices with embedded silicon germanium source/drain regions are formed with enhanced channel mobility, reduced contact resistance, and reduced silicide encroachment. Embodiments include embedded silicon germanium source/drain regions with a first portion having a relatively high germanium concentration, e.g., about 25 to about 35 at. %, an overlying second portion having a first layer with a relatively low germanium concentration, e.g., about 10 to about 20 at. %, and a second layer having a germanium concentration greater than that of the first layer. Embodiments include forming additional layers on the second layer, each odd numbered layer having relatively low germanium concentration, at. % germanium, and each even numbered layer having a relatively high germanium concentration. Embodiments include forming the first region at a thickness of about 400 Å to 28 about 800 Å, and the first and second layers at a thickness of about 30 Å to about 70 Å. | 03-17-2011 |
| 20110084315 | SEMICONDUCTOR DEVICE HAVING SILICON ON STRESSED LINER (SOL) - A method of fabricating an integrated circuit and an integrated circuit having silicon on a stress liner are disclosed. In one embodiment, the method comprises providing a semiconductor substrate comprising an embedded disposable layer, and removing at least a portion of the disposable layer to form a void within the substrate. This method further comprises depositing a material in that void to form a stress liner, and forming a transistor on an outside semiconductor layer of the substrate. This semiconductor layer separates the transistor from the stress liner. In one embodiment, the substrate includes isolation regions; and the removing includes forming recesses in the isolation regions, and removing at least a portion of the disposable layer via these recesses. In one embodiment, the depositing includes depositing a material in the void via the recesses. End caps may be formed in the recesses at ends of the stress liner. | 04-14-2011 |
| 20110127582 | MULTIPLYING PATTERN DENSITY BY SINGLE SIDEWALL IMAGING TRANSFER - A method for fabricating an integrated circuit includes patterning a mandrel over a layer to be patterned. Dopants are implanted into exposed sidewalls of the mandrel to foam at least two doped layers having at least one undoped region adjacent to the doped layers. The doped layers are selectively etched away to form pillars from the undoped regions. The layer to be patterned is etched using the pillars as an etch mask to form features for an integrated circuit device. A semiconductor device is also disclosed. | 06-02-2011 |
| 20110180855 | NON-DIRECT BOND COPPER ISOLATED LATERAL WIDE BAND GAP SEMICONDUCTOR DEVICE - Non-direct bond copper isolated lateral wide band gap semiconductor devices are provided. One semiconductor device includes a heat sink, a buffer layer directly overlying the heat sink, and an epitaxial layer formed of a group-III nitride overlying the buffer layer. Another semiconductor device includes a heat sink, a substrate directly overlying the heat sink, a buffer layer directly overlying the substrate, and an epitaxial layer formed of a group-III nitride overlying the buffer layer. Being formed of a group-III nitride enables the various epitaxial layers to be electrically isolated from their respective heat sinks. | 07-28-2011 |
| 20110198673 | FORMATION OF FINFET GATE SPACER - Gate spacers are formed in FinFETS having a bottom portion of a first material extending to the height of the fins, and a top portion of a second material extending above the fins. An embodiment includes forming a fin structure on a substrate, the fin structure having a height and having a top surface and side surfaces, forming a gate substantially perpendicular to the fin structure over a portion of the top and side surfaces, for example over a center portion, forming a planarizing layer over the gate, the fin structure, and the substrate, removing the planarizing layer from the substrate, gate, and fin structure down to the height of the fin structure, and forming spacers on the fin structure and on the planarizing layer, adjacent the gate. | 08-18-2011 |
| 20120025274 | SOI SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND SEMICONDUCTOR DEVICE - An SOI substrate having an SOI layer that can be used in practical applications even when a substrate with low upper temperature limit, such as a glass substrate, is used, is provided. A semiconductor device using such an SOI substrate, is provided. In bonding a single-crystal semiconductor layer to a substrate having an insulating surface or an insulating substrate, a silicon oxide film formed using organic silane as a material on one or both surfaces that are to form a bond is used. According to the present invention, a substrate with an upper temperature limit of 700° C. or lower, such as a glass substrate, can be used, and an SOI layer that is strongly bonded to the substrate can be obtained. In other words, a single-crystal semiconductor layer can be formed over a large-area substrate that is longer than one meter on each side. | 02-02-2012 |
| 20120091511 | MULTI-FIN DEVICE BY SELF-ALIGNED CASTLE FIN FORMATION - The present disclosure provides a method includes forming a multi-fin device. The method includes forming a patterned mask layer on a semiconductor substrate. The patterned mask layer includes a first opening having a first width W | 04-19-2012 |
| 20120139010 | INTERPOSER AND SEMICONDUCTOR DEVICE - An interposer includes a substrate includes a plurality of penetrating electrodes, and a wiring portion formed on the substrate, in which the wiring portion includes a wiring layer electrically connected to the penetrating electrodes and an insulating layer covering the wiring layer. The interposer includes a plurality of first UBM structures provided at a side opposite the substrate of the wiring portion, in which the first UBM structures are electrically connected to the wiring layer. The interposer includes a plurality of bumps provided at the side opposite the wiring portion of the substrate, in which the plurality of bumps is electrically connected to each of the penetrating electrodes via a plurality of second UBM structures. | 06-07-2012 |
| 20120153358 | INTEGRATED HEAT PILLAR FOR HOT REGION COOLING IN AN INTEGRATED CIRCUIT - The thermal energy transfer techniques of the disclosed embodiments utilize passive thermal energy transfer techniques to reduce undesirable side effects of trapped thermal energy at the circuit level. The trapped thermal energy may be transferred through the circuit with thermally conductive structures or elements that may be produced as part of a standard integrated circuit process. The localized and passive removal of thermal energy achieved at the circuit level rather just at the package level is both more effective and more efficient. | 06-21-2012 |
| 20120153359 | NICKEL-SILICIDE FORMATION WITH DIFFERENTIAL PT COMPOSITION - Embodiments of the invention provide a method of forming nickel-silicide. The method may include depositing first and second metal layers over at least one of a gate, a source, and a drain region of a field-effect-transistor (FET) through a physical vapor deposition (PVD) process, wherein the first metal layer is deposited using a first nickel target material containing platinum (Pt), and the second metal layer is deposited on top of the first metal layer using a second nickel target material containing no or less platinum than that in the first nickel target material; and annealing the first and second metal layers covering the FET to form a platinum-containing nickel-silicide layer at a top surface of the gate, source, and drain regions. | 06-21-2012 |
| 20120175684 | TRANSISTOR INCLUDING REDUCED CHANNEL LENGTH - A transistor includes a substrate. A first electrically conductive material layer, having a thickness, is positioned on the substrate. A second electrically conductive material layer is in contact with and positioned on the first electrically conductive material layer. The second electrically conductive material layer overhangs the first electrically conductive material layer. An electrically insulating material layer, having a thickness, is conformally positioned over the second electrically conductive material layer, the first electrically conductive material layer, and at least a portion of the substrate. The thickness of the first electrically conductive material layer is greater than the thickness of the electrically insulating material layer. | 07-12-2012 |
| 20120280283 | MULTIPLYING PATTERN DENSITY BY SINGLE SIDEWALL IMAGING TRANSFER - A method for fabricating an integrated circuit includes patterning a mandrel over a layer to be patterned. Dopants are implanted into exposed sidewalls of the mandrel to form at least two doped layers having at least one undoped region adjacent to the doped layers. The doped layers are selectively etched away to form pillars from the undoped regions. The layer to be patterned is etched using the pillars as an etch mask to form features for an integrated circuit device. A semiconductor device is also disclosed. | 11-08-2012 |
| 20130015504 | TSV STRUCTURE AND METHOD FOR FORMING THE SAMEAANM Kuo; Chien-LiAACI Hsinchu CityAACO TWAAGP Kuo; Chien-Li Hsinchu City TWAANM Yang; Chin-ShengAACI Hsinchu CityAACO TWAAGP Yang; Chin-Sheng Hsinchu City TWAANM Lin; Ming-TseAACI Hsinchu CityAACO TWAAGP Lin; Ming-Tse Hsinchu City TW - A TSV structure includes a wafer including a first side and a second side, a through via connecting the first side and the second side, a through via dielectric layer covering the inner wall of the through via, a conductive layer which fills up the through via and consists of a single material to be a seamless TSV structure, a first dielectric layer covering the first side and surrounding the conductive layer as well as a second dielectric layer covering the second side and part of the through via dielectric layer but partially covered by the conductive layer. | 01-17-2013 |
| 20130026543 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A semiconductor device includes a plurality of active areas disposed on a semiconductor substrate. A manufacturing method of the semiconductor device includes performing a first annealing process on the semiconductor substrate by emitting a first laser alone a first scanning direction, and performing a second annealing process on the semiconductor substrate by emitting a second laser alone a second scanning direction. The first scanning direction and the second scanning direction have an incident angle. | 01-31-2013 |
| 20130056799 | CIRCUIT SIMULATION METHOD AND SEMICONDUCTOR INTEGRATED CIRCUIT - A simulation method of a circuit in which a transistor is formed of a material (e.g., SiGe, etc.) having a lattice constant different from that of a semiconductor substrate, on source and drain regions, an adjacent active region is formed near the transistor, and a gate electrode is formed in the active region, where a region not overlapping with the gate electrode in the adjacent active region is formed of a material such as SiGe, includes a step of calculating an electrical characteristic (e.g., flowing current, threshold voltage, etc.) of the transistor based on a distance between an edge closer to the transistor, of both edges of the adjacent active region disposed near the transistor, and the gate electrode formed in the adjacent active region. Thus, circuit simulation can be performed with high accuracy with respect to an electrical characteristic of the transistor. | 03-07-2013 |
| 20130113023 | Multi-Fin Device by Self-Aligned Castle Fin Formation - The present disclosure provides a method includes forming a multi-fin device. The method includes forming a patterned mask layer on a semiconductor substrate. The patterned mask layer includes a first opening having a first width W | 05-09-2013 |
| 20130193489 | INTEGRATED CIRCUITS INCLUDING COPPER LOCAL INTERCONNECTS AND METHODS FOR THE MANUFACTURE THEREOF - Embodiments of a method for manufacturing an integrated circuit are provided. In one embodiment, a partially-fabricated integrated circuit is produced including a semiconductor substrate having source/drain regions, and a plurality of transistors including a plurality of gate conductors formed over the semiconductor substrate and between the source/drain regions. Device-level contacts are formed in ohmic contact with the gate conductors and with the source/drain regions. The device-level contacts terminate at substantially the same level above the semiconductor substrate. Copper interconnect lines are then formed in a level above the device-level contacts and in ohmic contact therewith to locally interconnect the plurality of transistors. | 08-01-2013 |
| 20130234213 | NISI REWORK PROCEDURE TO REMOVE PLATINUM RESIDUALS - The amount of Pt residues remaining after forming Pt-containing NiSi is reduced by performing a rework including applying SPM at a temperature of 130° C. in a SWC tool, if Pt residue is detected. Embodiments include depositing a layer of Ni/Pt on a semiconductor substrate, annealing the deposited Ni/Pt layer, removing unreacted Ni from the annealed Ni/Pt layer, annealing the Ni removed Ni/Pt layer, removing unreacted Pt from the annealed Ni removed Ni/Pt layer, analyzing the Pt removed Ni/Pt layer for unreacted Pt residue, and if unreacted Pt residue is detected, applying SPM to the Pt removed Ni/Pt layer in a SWC tool. The SPM may be applied to the Pt removed Ni'/Pt layer at a temperature of 130° C. | 09-12-2013 |
| 20140008702 | Semiconductor Packages Having Multiple Lead Frames and Methods of Formation Thereof - In accordance with an embodiment of the present invention, a semiconductor package includes a first lead frame having a first die paddle, and a second lead frame, which has a second die paddle and a plurality of leads. The second die paddle is disposed over the first die paddle. A semiconductor chip is disposed over the second die paddle. The semiconductor chip has a plurality of contact regions on a first side facing the second lead frame. The plurality of contact regions is coupled to the plurality of leads. | 01-09-2014 |
| 20140159120 | Conformal Doping - Methods for doping a three-dimensional semiconductor structure are disclosed. A conformal coating is formed on the three-dimensional semiconductor structure by Atomic Layer Deposition, and subsequent annealing causes dopant atoms to migrate into the three-dimensional semiconductor structure. Any residual conformal coating is then removed by etching. The semiconductor can be a type IV semiconductor such as Si, SiC, SiGe, or Ge, for which Sb and Te are suitable dopants. Sb and Te can be provided from a Ge | 06-12-2014 |
| 20190146154 | HETEROGENEOUS INTEGRATED CIRCUIT FOR SHORT WAVELENGTHS | 05-16-2019 |
| 20190148238 | LOW-K GATE SPACER AND FORMATION THEREOF | 05-16-2019 |
| 20190148239 | Low-K Gate Spacer and Formation Thereof | 05-16-2019 |
| 20190148502 | CELL ARCHITECTURE WITH CONTACT ON ACTIVE GATE COMPATIBLE WITH A SMALL CELL AREA HAVING SMALL CONTACTED POLY PITCH | 05-16-2019 |
