| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257285000 | With profiled channel dopant concentration or profiled gate region dopant concentration (e.g., maximum dopant concentration below surface) | 7 |
| 20080315266 | JUNCTION FIELD EFFECT TRANSISTOR WITH A HYPERABRUPT JUNCTION - A junction field effect transistor (JFET) has a hyperabrupt junction layer that functions as a channel of a JFET. The hyperabrupt junction layer is formed by two dopant profiles of opposite types such that one dopant concentration profile has a peak concentration depth at a tail end of the other dopant profile. The voltage bias to the channel is provided by a body that is doped with the same type of dopants as the gate. This is in contrast with conventional JFETs that have a body that is doped with the opposite conductivity type as the gate. The body may be electrically decoupled from the substrate by another reverse bias junction formed either between the body and the substrate or between a buried conductor layer beneath the body and the substrate. The capability to form a thin hyperabrupt junction layer allows formation of a JFET in a semiconductor-on-insulator substrate. | 12-25-2008 |
| 20100084693 | Method of Forming a Semiconductor Device and Semiconductor Device Thereof - According to one embodiment of the present invention, a method of forming a semiconductor device is provided, the method including: forming a substrate; forming a first gate on the substrate; forming a mask layer on the substrate, the mask layer including a first window covering an area within which the first gate is formed so that the first gate divides the substrate exposed by the first window into a first region and a second region; and doping the exposed substrate using rays inclined with respect to the substrate top surface, where the position of the first gate with respect to a border of the first window is chosen such that the inclined doping rays impinge more on the first region than on the second region. | 04-08-2010 |
| 20120104468 | FABRICATING HIGH VOLTAGE TRANSISTORS IN A LOW VOLTAGE PROCESS - Fabricating high voltage transistors includes forming a buried p-type implant on a p-substrate for each transistor, the transistor having a source side and a drain side, wherein the p-type implant is positioned adjacent the source and is configured to extend under a gate region; depositing a low doping epitaxial layer on the p-substrate and the p-type implant for each high voltage transistor, the low doping epitaxial layer extending from the source to the drain; forming an N-Well in the low doping epitaxial layer for each transistor, wherein the N-Well corresponds to a low voltage transistor N-Well fabricated using a low voltage transistor fabrication process; and forming a p-top diffusion region in or on the N-Well for each transistor, wherein the p-top diffusion region is configured to compensate for a dopant concentration of the N-Well at or near a surface of the N-Well opposing the substrate. | 05-03-2012 |
| 20120217551 | JUNCTION FIELD EFFECT TRANSISTOR WITH REGION OF REDUCED DOPING - A junction field effect transistor having a drain and a source, each defined by regions of a first type of semiconductor interconnected by a channel, and in which a dopant profile at a side of the drain facing the channel is modified so as to provide a region of reduced doping compared to a body region of the drain. The region of reduced doping and the body region can be defined by the same mask and doping step, but the mask is shaped to provide a lesser amount and thus less depth of doping for the region of reduced doping. | 08-30-2012 |
| 20140231884 | BOOTSTRAP MOS FOR HIGH VOLTAGE APPLICATIONS - A device includes a p-well region, and a first High-Voltage N-type Well (HVNW) region and a second HVNW region contacting opposite edges of the p-well region. A P-type Buried Layer (PBL) has opposite edges in contact with the first HVNW region and the second HVNW region. An n-type buried well region is underlying the PBL. The p-well region and the n-type buried well region are in contact with a top surface and a bottom surface, respectively, of the PBL. The device further includes a n-well region in a top portion of the p-well region, an n-type source region in the n-well region, a gate stack overlapping a portion of the p-well region and a portion of the second HVNW region, and a channel region under the gate stack. The channel region interconnects the n-well region and the second HVNW region. | 08-21-2014 |
| 20150137192 | HIGH VOLTAGE JUNCTION FIELD EFFECT TRANSISTOR - The present invention discloses a high voltage JFET. The high voltage JFET includes a second conductivity type drift region located on the first conductivity type epitaxial layer; a second conductivity type drain heavily doped region located in the second conductivity type drift region; a drain terminal oxygen region located on the second conductivity type drift region and at a side of the second conductivity type drain heavily doped region; a first conductivity type well region located at a side of the second conductivity type drift region; a second conductivity type source heavily doped region and a first conductivity type gate heavily doped region located on the first conductivity type well region, and a gate source terminal oxygen region; a second conductivity type channel layer located between the second conductivity type source heavily doped region and the second conductivity type drift region; a dielectric layer and a field electrode plate located on the second conductivity type channel layer. Wherein a drain electrode electrically is led out from the second conductivity type drain heavily doped region; a source electrode electrically is led out from a connection of the field electrode plate and the second conductivity type source heavily doped region; and a gate electrode electrically is led out from the first conductivity type gate heavily doped region. The transistor has a high breakdown voltage and easy to be integrated. | 05-21-2015 |
| 20150357481 | JUNCTION FIELD EFFECT TRANSISTOR - A junction field effect transistor is disclosed. The junction field effect transistor includes a first doped region and a second doped region. The first doped region includes a source and a drain. The second doped region includes a gate. The first doped region and the second doped region have a U-shape PN junction there between. The U-shape PN junction is between the source and the drain. | 12-10-2015 |
