| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 257268000 | Enhancement mode | 6 |
| 20100289067 | High Voltage III-Nitride Semiconductor Devices - A III-N device is described has a buffer layer, a first III-N material layer on the buffer layer, a second III-N material layer on the first III-N material layer on an opposite side from the buffer layer and a dispersion blocking layer between the buffer layer and the channel layer. The first III-N material layer is a channel layer and a compositional difference between the first III-N material layer and the second III-N material layer induces a | 11-18-2010 |
| 20110079825 | Cascoded high voltage junction field effect transistor - A cascoded junction field transistor (JFET) device comprises a first stage high voltage JFET cascoded to a second stage low voltage JFET wherein one of the first and second stages JFET is connected to a drain electrode of another JFET stage. | 04-07-2011 |
| 20120292669 | FIELD EFFECT TRANSISTOR STRUCTURE AND METHOD OF FORMING SAME - The disclosure relates generally to junction gate field effect transistor (JFET) structures and methods of forming the same. The JFET structure includes a p-type substrate having a p-region therein; an n-channel thereunder; and n-doped enhancement regions within the n-channel, each n-doped enhancement region separated from the p-region. | 11-22-2012 |
| 20140332858 | JUNCTION GATE FIELD-EFFECT TRANSISTOR (JFET), SEMICONDUCTOR DEVICE HAVING JFET AND METHOD OF MANUFACTURING - A junction gate field-effect transistor (JFET) includes a substrate, a source region formed in the substrate, a drain region formed in the substrate, a channel region formed in the substrate, and at least one gate region formed in the substrate. The channel region connects the source and drain regions. The at least one gate region is configured to cause a depletion region in one of the source and drain regions. | 11-13-2014 |
| 20140339608 | JFET ESD PROTECTION CIRCUIT FOR LOW VOLTAGE APPLICATIONS - An electrostatic discharge (ESD) protection circuit is disclosed. The circuit includes a first region having a first conductivity type ( | 11-20-2014 |
| 257269000 | With means to adjust barrier height (e.g., doping profile) | 1 |
| 20160181369 | JFET DEVICE AND ITS MANUFACTURING METHOD | 06-23-2016 |
