Entries |
Document | Title | Date |
20080222338 | Apparatus and method for sharing devices between multiple execution domains of a hardware platform - A method and apparatus for sharing peripheral devices between multiple execution domains of a hardware platform are described. In one embodiment, the method includes the configuration end-point devices, bridges and interconnects of a hardware platform including at least two execution domains. When a configuration requests is issued from an execution domain, the configuration requests may be intercepted. Hence, the received configuration request is not used to configure the peripheral end-points, bridges or interconnects of the hardware platform. Configuration information decoded from intercepted configuration request may be stored as virtual configuration information. In one embodiment, configuration information is read from a target of the configuration request to identify actual configuration information. This actual configuration information may be stored within a translation table and mapped to the virtual configuration information to enable translation of domain specific addresses to real (actual) addresses. Other embodiments are described and claimed. | 09-11-2008 |
20080222339 | Processor architecture with switch matrices for transferring data along buses - There is described a processor architecture, comprising: a plurality of first bus pairs, each first bus pair including a respective first bus running in a first direction (for example, left to right) and a respective second bus running in a second direction opposite to the first direction (for example right to left); a plurality of second bus pairs, each second bus pair including a respective third bus running in a third direction (for example downwards) and a respective fourth bus running in a fourth direction opposite to the third direction (for example upwards), the third and fourth buses intersecting the first and second buses; a plurality of switch matrices, each switch matrix located at an intersection of a first and a second pair of buses; a plurality of elements arranged in an array, each element being arranged to receive data from a respective first or second bus, and transfer data to a respective first or second bus. The elements in the array include processing elements, for operating on received data, and memory elements, for storing received data. The described architecture has the advantage that it requires relatively little memory, and the memory requirements can be met by local memory elements in the array. | 09-11-2008 |
20080250184 | ADAPTIVE TWO-WIRE BUS - Techniques for improving the quality or fidelity of a digital signal transmitted via a two-wire bus interconnect utilizing an open-terminal configuration at one or both end devices of the bus interconnect are disclosed. An intermediate two-wire bus is used to connect two open-terminal-based two-wire busses. A bus adapter device is utilized at each end of the intermediate two-wire bus, whereby the bus adapter device communicates signaling on the corresponding open-terminal-based two-wire bus using open-terminal ports and communicates signaling on the intermediate two-wire bus using push-pull ports. The bus adapter device can utilize control logic to implement a state machine or other function to control the interactions between the different two-wire buses. The bus adapter devices may be implemented as interchangeable integrated circuit devices that can change configuration based on connection, thereby permitting their implementation at either end of a bus transmission system. | 10-09-2008 |
20080250185 | Triple Voting Cell Processors for Single Event Upset Protection - In a system for operating three address concentrating processors, a common clock signal is transmitted to each of the three address concentrating processors. A common data unit is transmitted simultaneously to each of the three address concentrating processors. A received data unit is received simultaneously from each of the three address concentrating processors. Each of the received data units are compared to each other. An error correcting routine is activated when the data units received from the three address concentrating processors are not all identical. | 10-09-2008 |
20080256283 | Multimedia expansion module and computer device using the same - A multimedia expansion module suitable to be assembled in a computer device is provided. The multimedia expansion module includes a first group of pins, a second group of pins, a third group of pins, a first pin area and a second pin area. The first group of pins supports the transmission of universal serial bus (USB) signals. The second group of pins supports the transmission of serial disk drive interface signals. The third group of pins supports the transmission of peripheral component interconnect (PCI) express interface signal whose rate is at least 2.5 G bps. The third group of pins includes a first part of pins and a second part of pins. The first group of pins and the first part of pins are provided at the first pin area, and the second group of pins and the second part of pins are provided at the second pin area. | 10-16-2008 |
20080270667 | SERIALIZATION OF DATA FOR COMMUNICATION WITH MASTER IN MULTI-CHIP BUS IMPLEMENTATION - Bus communication for components of a system on a chip. In one aspect of the invention, a serializer for interfacing bus communications for a master in a bus system includes one or more shift registers that serialize information to send over a communication bus and deserialize information received from the communication bus. A mechanism provides parallel bus information from the master to the shift registers for serialization, where the mechanism provides deserialized information received from the shift registers to the master, and where the mechanism inserts one or more wait cycles in communication with the master during the serialization and deserialization. | 10-30-2008 |
20080282012 | MULTI-PROCESSOR DEVICE - The present invention intends to provide a high-performance multi-processor device in which independent buses and external bus interfaces are provided for each group of processors of different architectures, if a single chip includes a plurality of multi-processor groups. A multi-processor device of the present invention comprises a plurality of processors including first and second groups of processors of different architectures such as CPUs, SIMD type super-parallel processors, and DSPs, a first bus which is a CPU bus to which the first processor group is coupled, a second bus which is an internal peripheral bus to which the second processor group is coupled, independent of the first bus, a first external bus interface to which the first bus is coupled, and a second external bus interface to which the second bus is coupled, over a single semiconductor chip. | 11-13-2008 |
20080282013 | Method and Device for Transmission Service Using Backplane Service Buses - A method for transmission service using backplane service buses comprises the following steps: the service received from backplane interface is distributed into different services; the first backplane service bus and the second backplane service bus in the uplink interface of the backplane transmit the different services simultaneously; the first backplane service bus and the second backplane service bus in the downlink interface of the backplane transmit the different services simultaneously. A device for transmission service using backplane service buses comprises the first service board, the second service board, the first cross board, the second cross board and a service distributing unit. The service distributing unit is used to distribute the received service into different services, and control the first and second service boards to transmit the distributed different service to the first cross board and the second cross board simultaneously via different backplane service buses. The first cross board and second cross board transmit the cross service to the second and first service boards simultaneously. The second and first service boards receive the transmitted different service simultaneously. | 11-13-2008 |
20080301349 | Semiconductor Memory Arrangement - A semiconductor memory arrangement includes a circuit board having at least a first layer and a second layer, a plurality of memory units, and a first control device and a second control device adapted to receive command and address signals. A first bus system is disposed in the first layer of the circuit board and coupled to the first control device and to a first group of memory units of the plurality of memory units to transmit the command and address signals to the first group of memory units. A second bus system is disposed in the second layer of the circuit board and coupled to the second control device and to a second group of memory units of the plurality of memory units to transmit the command and address signals to the second group of memory units. | 12-04-2008 |
20080313379 | MULTIPLE BUS CHARGE SHARING - A charge-sharing circuit includes a first input bus pair, a second input bus pair, and an output bus pair. A capacitor is coupled between a first internal node and a second internal node. A first circuit selectively couples the first internal node to the first input bus pair, the second input bus pair and the output bus pair. A second circuit selectively couples the second internal node to the first input bus pair, the second input bus pair and the output bus pair. A third circuit selectively couples the first input bus pair to a reference voltage. A fourth circuit selectively couples the second input bus pair to the reference voltage. The third circuit is activated when the first input bus pair is inactive and charge is shared between the second bus pair and the output bus pair. The fourth circuit is activated when the second input bus pair is inactive and charge is shared between first bus pair and the output bus pair. | 12-18-2008 |
20090106473 | CROSSOVER OPERATION IN A 1+1 PROTECTION SWITCHING ENVIRONMENT - A communication unit comprises a first port; a second port, each of the first and second ports configured to transmit signals to and receive signals from another communication unit; a programmable logic unit configured to process signals transmitted and received by the first and second ports; and a processor configured to program the programmable logic unit for crossover operation based on detection of a crossover connection. | 04-23-2009 |
20090113108 | BUS TERMINATOR/MONITOR/BRIDGE SYSTEMS AND METHODS - Computing systems including first and second processors configured to control first and second buses, respectively, and a terminator-monitor-bridge (TMB) device coupled between the first and second buses are provided. The TMB device is configured to selectively enable the first processor and the second processor to control at least a portion of the second bus and the first bus, respectively. TMB devices and methods for operating the TMB devices in accordance with the above configuration are also provided. | 04-30-2009 |
20090157938 | ELECTRONIC DEVICES USING DIVIDED MULTI-CONNECTOR ELEMENT DIFFERENTIAL BUS CONNECTOR - In one example an electronic device includes a housing that includes an A/C input or DC input, and at least one circuit substrate that includes electronic circuitry, such as graphics processing circuitry that receives power based on the A/C input or DC input. The electronic device also includes a divided multi-connector element differential bus connector that is coupled to the electronic circuitry. The divided multi-connector element differential bus connector includes a single housing that connects with the circuit substrate and the connector housing includes therein a divided electronic contact configuration comprised of a first group of electrical contacts divided from an adjacent second group of mirrored electrical contacts wherein each group of electrical connects includes a row of at least lower and upper contacts. In one example, the electronic device housing includes air flow passages, such as grills, adapted to provide air flow through the housing. The electronic device housing further includes a passive or active cooling mechanism such as a fan positioned to cool the circuitry during normal operation. In one example, the electronic device does not include a host processor and instead a host processor is in a separate electronic device that communicates with the graphics processing circuitry through the divided multi connector element differential bus connector. In another example, a CPU (or one or more CPUs) is also co-located on the circuit substrate with the circuitry to provide a type of parallel host processing capability with an external device. | 06-18-2009 |
20090164690 | Methods and apparatuses for serial bus sideband communications - Methods and apparatuses that utilize a serial bus, such as a universal serial bus (USB), for communications between a communications network, a computing device, and an auxiliary device are disclosed. Some embodiments comprise methods handling sideband communications using serial buses. One or more of the embodiments comprise differentiating in-band data from out-of-band data, transferring information of the in-band data between a communications network and a computing device, and transferring information of the out-of-band data between the communications network and an auxiliary device. Some embodiments comprise an apparatus having a communications network interface, an auxiliary device interface, and a computing device interface. Of the interfaces, one or more may be a serial bus interface. The apparatus may differentiate between in-band and out-of-band data and communicate information of the out-of-band data to an auxiliary device. In some embodiments, the apparatus may also transfer control information. In some embodiments, information may be routed based upon cyclic redundancy check (CRC) information. | 06-25-2009 |
20090210605 | BRIDGE DEVICE FOR A DISK DRIVE - A bridge device for a disk drive has the I/O terminals to which an external automatic controlling apparatus is connected, so the external automatic controlling apparatus directly controls a disk tray of the disk drive to move in or move out without a computer. In addition, the bridge device also further has a computer connecting port, to which the external computer is connected. The computer controls operations of the disk drive. | 08-20-2009 |
20090307406 | Memory Device for Providing Data in a Graphics System and Method and Apparatus Thereof - A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data. | 12-10-2009 |
20090313411 | APPARATUS AND METHODS CRC ERROR INJECTION IN A STORAGE SYSTEM - Apparatus and methods for Cyclic Redundancy Check (CRC) error injection between storage controllers and storage devices in a storage system. A plurality of bridge devices are configured in a storage system each coupled persistently coupled to a corresponding one of the plurality of storage devices. Each bridge device may couple to one or more Serial Attached SCSI (SAS) initiators for transferring exchanges between one or more SAS initiators and the attached target storage device. Each bridge device receives parameters from a SAS initiator or an administrative client directing the bridge regarding injection of CRC errors. A log memory in each bridge may log information regarding the injected CRC errors. | 12-17-2009 |
20090327567 | DETECTING CIRCUIT FOR IEEE 1394 DEVICE - An IEEE 1394 device detecting circuit includes a south bridge chip, a control device, an IEEE 1394 interface, and a resistor. The control device includes a power reset pin, a bus reset pin, and a cable power pin. The control device is connected to the south bridge chip through the bus reset pin, which is further connected to the power reset pin. The cable power pin is connected to a direct current power through the resistor. The control device is further connected to the IEEE 1394 interface, which is connected to an IEEE 1394 device. | 12-31-2009 |
20090327568 | Data Replication method and apparatus - A data storage system, device, and method are provided for replicating data between different data storage systems or appliances. More specifically, the present invention affords communications between heterogeneous data storage systems that potential employ different communication protocols. A bridging communication protocol is utilized by one or both storage systems in order to accommodate different communication protocols. Alternatively, a storage appliance connecting the data storage systems may employ the bridging communication protocol. | 12-31-2009 |
20100088452 | Internal BUS Bridge Architecture and Method in Multi-Processor Systems - An internal bus bridge architecture and method is described. Embodiments include a system with multiple bus endpoints coupled to a bus root via a host bus bridge that is internal to at least one bus endpoint. In addition, the bus endpoints are directly coupled to each other. Embodiments are usable with known bus protocols. | 04-08-2010 |
20100100659 | COMPUTER SYSTEM - A computer system includes hard disc, and a control circuit electrically connected to the hard disc. The control circuit includes a connecting port electrically connected to an external connecting port for transmitting data signals with another computer, a switch, a voltage converter, and a signal transforming controller. The switch includes a first terminal electrically connected to the connecting port, and a second terminal. The voltage converter includes an input terminal electrically connected to the connecting port for receiving an external voltage, and an output terminal for outputting a converted voltage. The signal transforming controller includes a first signal terminal electrically connected to the second terminal of the switch, a voltage input terminal electrically connected to the output terminal of the voltage converter, and a second signal terminal electrically connected to the hard disc. | 04-22-2010 |
20100199014 | Microcontroller Peripheral Event Distribution Bus - A method and apparatus for distributing events. In one embodiment, the method includes a bus concurrently transmitting a first event-signal and a first event-identification (event-ID); wherein the first event-signal, when active, indicates that a first event has occurred, is occurring, or should occur. The first event-ID corresponds to the first event-signal. | 08-05-2010 |
20100199015 | SYSTEM AND METHOD FOR IDENTIFYING DATA STREAMS ASSOCIATED WITH MEDICAL EQUIPMENT - A system and method for uniquely identifying data streams associated with medical equipment are described. The system may be implemented in a variety of ways, including as a combination of a medical device, a data stream identifier, and a medical device identifier. The medical device generates a plurality of data streams. The data streams are uninterrupted transmissions of data from the medical device. The data streams include information regarding the operation of the medical device. The data stream identifier attaches a unique data tag to the data streams. The medical device identifier is configured to generate a medical device tag. The 10 medical device tag includes information to uniquely identify the medical device and is accessible from an external computer. The data stream identifier and the medical device identifier are secured to the medical device. | 08-05-2010 |
20100228902 | KVM SWITCH APPARATUS WITH BRIDGING FUNCTION - A KVM switch apparatus with bridging function includes a processor with a keyboard connection interface and a mouse connection interface; a keyboard/mouse switching circuit; a USB bridge unit and at least one computer interface unit electrically connected to at least one computer. The keyboard/mouse switching circuit and the USB bridge unit are selectively connected, whereby a switching of bridging channels is provided between at least two computers. | 09-09-2010 |
20100274942 | CONSTITUTING A CONTROL SYSTEM WITH VIRTUAL AND PHYSICAL BACKPLANES AND MODULES AS BUILDING BLOCKS - A custom control system created based on combinations of software applications and hardware control and communication modules overlaid in a virtual backplane. The user can select the modules of interest and map them together without the loss of communications between the modules while the control system is configured and overlaid. The user can then archive the system design and implement the system with a greater level of confidence in the ability of the design to meet the requirements of the application while reducing the costs of the implementation. | 10-28-2010 |
20100287323 | APPARATUS AND METHOD FOR DATA BYPASS FOR A BI-DIRECTIONAL DATA BUS IN A HUB-BASED MEMORY SUB-SYSTEM - A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data. | 11-11-2010 |
20100325333 | Method Allowing Processor with Fewer Pins to Use SDRAM - The invention is an apparatus and method to allow a microcontroller unit with fewer pins to use SDRAM. This invention uses the SDRAM burst mode in a favorable way. On an initial cycle of the burst access the microcontroller supplies an address one less than the actual initial address on a multiplexed address/data bus connected to both the address bus and the data bus of the SDRAM. DQM signals from the microcontroller to the SDRAM suppress all data writes. On the second and subsequent cycles of the burst assess, the microcontroller supplies the next data word to be written on the multiplexed address/data bus together with DQM signals permitting data writing. This technique prevents collisions of address and data on the microcontroller multiplexed address/data bus. | 12-23-2010 |
20110055449 | Logic Chip, Method and Computer Program for Providing a Configuration Information for a Configurable Logic Chip - A logic chip has a plurality of individually-addressable resource blocks, each comprising logic circuitry. The logic chip also has a bus comprising a plurality of bus information lines. A first of the resource blocks has a coupling between a first strict sub-set of the bus information lines and the logic circuitry of the first resource block. A second of the resource blocks, which is adjacent to the first resource block, has a coupling between a second strict sub-set of the bus information lines and the logic circuitry of the second resource blocks. The first and second sub-sets have different bus lines. | 03-03-2011 |
20110060858 | METHOD FOR ENHANCING PERFORMANCE OF DATA ACCESS BETWEEN A PERSONAL COMPUTER AND A USB MASS STORAGE, ASSOCIATED PERSONAL COMPUTER, AND STORAGE MEDIUM STORING AN ASSOCIATED USB MASS STORAGE DRIVER - A method for enhancing performance of data access between a personal computer and a USB Mass Storage is provided. The personal computer is equipped with a plurality of layers of drivers regarding USB data access, and a lower layer of the layers of the drivers includes a USB Bus Driver. The method includes: monitoring commands sent from an operating system (OS) file system to an upper layer; and when a command sent from the OS file system to the upper layer is utilized for accessing data of a data amount that is greater than a predetermined threshold value, omitting a portion of a plurality of IRPs, automatically generating a plurality of replies for replying to the omitted IRPs, and altering at least one IRP of remaining IRPs in order to correctly access the data with a lower IRP count, wherein the plurality of IRPs is associated with the command. | 03-10-2011 |
20110107000 | VOLTAGE INDICATOR SIGNAL GENERATION SYSTEM AND METHOD - The present invention provides for a system comprising a peripheral component interface (PCI) host bridge. The PCI host bridge is configured to be coupled to a PCI bus, and to receive a system reset signal, to generate a PCI bus reset signal based on the received system reset signal, to detect a PCI operational mode of the PCI bus, and to generate a voltage indicator signal based on the detected PCI operational mode. A voltage regulator is coupled to the PCI host bridge and configured to receive the voltage indicator signal and to regulate a signaling voltage for the PCI bus based on the voltage indicator signal. | 05-05-2011 |
20110131359 | PROGRAMMABLE BRIDGE HEADER STRUCTURES - A computer system includes compute nodes coupled through a switch to shared or non-shared I/O devices. The switch includes a pool of bridge headers and virtual bridges coupling a root port of a compute node to each of one or more shared or non-shared I/O devices. The switch is configured to associate each of the virtual bridges with a respective one of the fixed pool of bridge headers, receive a packet including data identifying the root port and a shared or non-shared I/O device, and route the packet in response to comparing data in the packet to data in the bridge headers associated with the virtual bridges. The virtual bridges comprise a hierarchy of virtual bridges in which one virtual bridge connects the root port to the remaining virtual bridges of the hierarchy. The switch may change the associations between virtual bridges and bridge headers. | 06-02-2011 |
20110153898 | VEHICLES INCLUDING BUS-COUPLED HUB UNIT AND POWERTRAIN ELECTRONIC CONTROL UNIT AND METHOD - A vehicle includes a body structure, a powertrain, a plurality of sensors, a hub unit, a plurality of leads, a powertrain electronic control unit, and a bus. The powertrain is supported by the body structure and includes an engine and a transmission. Each of the sensors is operable for detecting a respective parameter of the powertrain and for generating a corresponding sensor signal. The leads each couple a respective one of the sensors to the hub unit. The bus couples the hub unit to the powertrain electronic control unit. The hub unit is configured to receive the sensor signals from the sensors and, in response to the sensor signals, generate feedback signals and transmit the feedback signals over the bus to the powertrain electronic control unit. A method is also provided. | 06-23-2011 |
20110179211 | BIOS ARCHITECTURE - A BIOS architecture adapted in a computer system is provided. The BIOS architecture includes at least one BIOS, a programmable chip module, a baseboard management controller (BMC), a south bridge chip and a network interface controller (NIC). The NIC is connected to the south bridge chip and the BMC and is to receive a remote update data to determine the destination of the remote update data. When the destination of the remote update data is the south bridge chip, the south bridge chip updates the BIOS according to the remote update data. When the destination of the remote update data is the BMC, the NIC informs the BMC to receive the remote update data, such that the BMC controls the programmable chip module to update the BIOS according to the remote update data. | 07-21-2011 |
20110208890 | I/O SYSTEMS, METHODS AND DEVICES FOR INTERFACING A PUMP CONTROLLER - Embodiments of the present invention provide I/O systems, methods, and devices for interfacing pump controller(s) with control device(s) which may have different interfaces and/or signaling formats. In one embodiment, an I/O interface module comprises a processor, a memory, and at least two data communications interfaces for communicating with a pumping controller and a control device. The I/O interface module can receive discrete signals from the control device, interpret them accordingly and send the packets to the pump controller. The pump controller reads the packets and takes appropriate actions at the pump. The I/O interface module can interpret packets of data received from the pump controller and assert corresponding discrete signals to the control device. The I/O interface module is customizable and allows a variety of interfaces and control schemes to be implemented with a particular multiple stage pump without changing the hardware of the pump. | 08-25-2011 |
20110225337 | TRANSACTION PERFORMANCE MONITORING IN A PROCESSOR BUS BRIDGE - Described embodiments provide a system having a bridge for connecting two different processor buses. A process monitor within the bridge allows for measuring latency of commands issued on a first bus, passing through the bridge, and executed by clients coupled to the second bus. By using identification fields associated with the command, measuring the latency of each command begins with matching the identification field of the command to an integer. As the bridge passes acknowledgements back to the first bus, the monitoring of the command is stopped when an identification field associated with an acknowledgement matches the identification field of the command being monitored. Data collected include the minimum, maximum, total latency, and the number of commands monitored. From this data, the average latency can be easily calculated. | 09-15-2011 |
20110252174 | HIERARCHICAL TO PHYSICAL MEMORY MAPPED INPUT/OUTPUT TRANSLATION - In an embodiment, a translation of a hierarchical MMIO address range to a physical MMIO address range and an identifier of a bridge in a south chip are written to a north chip. A transaction is received that comprises a hierarchical MMIO address. The hierarchical MMIO address that is within the hierarchical MMIO address range is replaced in the transaction with the identifier of the bridge and with a physical MMIO address that is within the physical MMIO address range in the south chip. The transaction is sent to the device that is connected to the bridge in the south chip. The physical MMIO address range specifies a range of physical MMIO addresses in memory in the device. | 10-13-2011 |
20110252175 | INTEGRATED MEMORY CONTROL APPARATUS - An integrated memory control apparatus including a first interface decoder, a second interface decoder and an interface controller is provided. Wherein, the first interface decoder is coupled to a control chip through a first serial peripheral interface (SPI), the second interface decoder is coupled to a micro-processor unit through a general transmission interface, and the interface controller is coupled to a memory through a second SPI. When the interface controller receives the request signals from the control chip and the micro-processor unit, the control chip may correctly read data from the memory through the first and second SPI. On the other hand, the micro-processor unit may stop reading data from the memory through the general transmission interface. Therefore, the control chip and the micro-processor unit may share the same memory. | 10-13-2011 |
20110258359 | SYSTEMS AND METHODS FOR CONDUCTING COMMUNICATIONS AMONG COMPONENTS OF MULTIDOMAIN INDUSTRIAL AUTOMATION SYSTEM - An improved industrial automation system and communication system for implementation therein, and related methods of operation, are described herein. In at least some embodiments, the improved communication system allows communication in the form of messages between modules in different control or enterprise domains. Further, in at least some embodiments, such communications are achieved by providing a communication system including a manufacturing service bus having two internal service busses with a bridge between the internal busses. Also, in at least some embodiments, a methodology of synchronous messaging is employed. | 10-20-2011 |
20110320670 | CONNECTED INPUT/OUTPUT HUB MANAGEMENT - A method for implementing connected input/output (I/O) hub configuration and management includes configuring a first I/O hub in wrap mode with a second I/O hub. The hubs are communicatively coupled via a wrap cable. The method further includes generating data traffic on a computing subsystem that includes the hubs. Generating traffic includes: converting, via the first hub, a request to implement a transaction into an I/O device-readable request packet and transmitting the request packet over the wrap cable; converting, via the second hub, the I/O device-readable (IODR) request packet into a system readable request and transmitting the request over a system bus; converting, via the second hub, the response to an IODR response packet, and transmitting the response packet over the wrap cable; and converting, via the first hub, the IODR response packet into a system readable response packet, and transmitting the response packet over the system bus. | 12-29-2011 |
20110320671 | MOVING OWNERSHIP OF A DEVICE BETWEEN COMPUTE ELEMENTS - In an embodiment, a command is received that requests movement of ownership of a target device from an origin compute element to a destination compute element. From the origin compute element, a translation of a virtual bridge identifier to a first secondary bus identifier, a first subordinate bus identifier, and a first MMIO bus address range is removed. To the destination compute element, a translation of the target virtual bridge identifier to a second secondary bus identifier, a second subordinate bus identifier, and a second MMIO bus address range is added. From a south chip that comprises the target virtual bridge, a translation of the target virtual bridge identifier to an identifier of the origin compute element is removed. To the south chip, a translation of the target virtual bridge identifier to an identifier of the destination compute element is added. | 12-29-2011 |
20120047306 | Bus system and bridge circuit connecting bus system and connection apparatus - A bus system includes: a first connection apparatus and a second connection apparatus carrying-out an exchange in accordance with a predetermined protocol; a bus through which the first and second connection apparatuses are connected to each other; and a bridge inserted between the first connection apparatus and the bus, and carrying out an exchange with the second connection apparatus in accordance with the predetermined protocol instead of the first connection apparatus when receiving a disconnection instruction for the first connection apparatus. | 02-23-2012 |
20120066427 | INFORMATION BACKUP SYSTEM WITH STORING MECHANISM AND METHOD OF OPERATION THEREOF - A method of operation of an information backup system includes: supplying a power to a first communication port and a second communication port; electrically connecting a host microcontroller to the first communication port for connecting a handheld device; electrically connecting the host microcontroller to the second communication port for connecting a mass storage device, the host microcontroller is for functioning as a host to the second communication port and the first communication port; and transferring data between the first communication port and the second communication port. | 03-15-2012 |
20120072635 | RELAY DEVICE - A relay device includes: an input buffer for receiving data units, each of which includes a header, to which multiple pieces of destination information have been added, and data associated with the header; multiple virtual channels for storing data units, each of the multiple virtual channels storing a data unit in accordance with the destination information; a destination comparing section for determining the order of allocation of virtual channels at a relay device on the receiving end with respect to the data units that are stored on the multiple virtual channels by seeing if their destinations are the same; and an output section for outputting the stored data units preferentially through one of the virtual channels that has already allocated at the relay device on the receiving end. | 03-22-2012 |
20120079158 | SIGNAL SWITCH CONNECTOR SET APPLIED TO MOTHERBOARD OF COMPUTER SYSTEM - A signal switch connector set is disposed on a motherboard of a computer system. The signal switch connector set is capable of selectively connecting a USB 3.0 signal terminal of a south bridge chip to a USB 3.0 port located at the rear panel of a casing or connecting the USB 3.0 terminal of the south bridge chip to the USB 3.0 port located at the front panel of the casing. | 03-29-2012 |
20120096210 | STAR COUPLER FOR A BUS SYSTEM, BUS SYSTEM HAVING SUCH A STAR COUPLER AND METHOD FOR INTERCHANGING SIGNALS IN A BUS SYSTEM - A star coupler has the ability to distinguish signals arriving via connections according to the time slot in which they arrive and to forward these signals to at least one other connection on the basis of the connection via which the signals arrive and on the basis of the time slot. An assignment in which the star coupler once treats the bus system as a single bus system and virtually divides the bus system into two subsystems in another time slot is possible in particular. | 04-19-2012 |
20120117291 | COMPUTATIONALLY-NETWORKED UNIFIED DATA BUS - Embodiments of the present invention provide a computationally-networked unified data bus for a multi-processing domain architecture. Specifically, in a typical embodiment, a unified data bus is provided. A first data bus adapter (e.g., a node) is coupled to the unified data bus (e.g., a link), and a first processing domain is coupled to the first data bus adapter. In general, the first data bus adapter encapsulates, translates, and interprets data communicated between the unified data bus and the first processing domain. In addition, a second data bus adapter (e.g., a node) is coupled to the unified data bus and a second processing domain is coupled to the second data bus adapter. Similar to the first data bus adapter, the second data bus adapter encapsulates, translates, and interprets data communicated between the unified data bus and the second processing domain. Under these embodiments, the first processing domain and the second processing domain can each comprise at least one element selected from a group consisting of: memory input/outputs (I/Os), cache, heterogeneous data buses, and processors. Moreover, the first processing domain and the second processing domain can be selected from a group consisting of a heterogeneous processing domain and a hybrid processing domain. | 05-10-2012 |
20120131251 | FAST AND COMPACT CIRCUIT FOR BUS INVERSION - A processor based system with at least one processor, at least one memory controller and optionally other devices having bussed system with a fast and compact majority voter in the circuitry responsible for the bus inversion decision. The majority voter is implemented in analog circuitry having two branches. One branch sums the advantage of transmitting the bits without inversion, the other sums the advantage of transmitting the bits with inversion. The majority voter computes the bus inversion decision in slightly more than one gate delay by simultaneously comparing current drive in each branch. | 05-24-2012 |
20120137039 | INFORMATION PROCESSING APPARATUS - An information processing apparatus includes information holding circuits provided respectively for a plurality of transfer source bus control devices, an exclusive bus configured to be capable of mutually connecting the plurality of information holding circuits, and bus selection circuits provided respectively for the plurality of transfer source bus control devices and configured to select one of the exclusive bus and the hierarchical bus as a connection destination of each of the transfer source bus control devices. | 05-31-2012 |
20120159033 | MOTHERBOARD - A motherboard includes an I/O chip, a south bridge chip, and a delay circuit. The I/O chip detects a standby voltage on the motherboard and outputs an indicating signal that indicates whether the standby voltage is at high level. The south bridge chip is connected to the I/O chip to receive the indicating signal. The delay circuit is connected to the I/O chip and the south bridge chip. The delay circuit delays the indicating signal before sending the indicating signal to the south bridge chip. | 06-21-2012 |
20120166699 | METHOD AND APPARATUS TO PROVIDE A HIGH AVAILABILITY SOLID STATE DRIVE - A method and apparatus to use Solid State Drives (SSD) in a high availability enterprise system is provided. Concurrent redundant paths are provided to the SSD to at least two storage controllers via a serial system bus using a non-storage bus protocol. | 06-28-2012 |
20120185631 | OPERATION METHOD FOR A COMPUTER SYSTEM - A device receives a standard command. The device judges whether an address field and/or a data length field and/or a data field of the standard command includes at least one of a vendor command, a vendor data and a checkword. The device judges whether the address field and/or a data length field and/or the data field of the standard command matches a vendor predetermined pattern. If matched, the device performs a vendor operation based on the vendor command and/or the vendor data of the standard command. | 07-19-2012 |
20120221759 | SEMICONDUCTOR DEVICE - A semiconductor device includes: a first transistor; a second transistor; an interlayer insulating film covering the transistors; a rectangular-shaped first bus formed on the interlayer insulating film and connected to first source/drain regions; a rectangular-shaped second bus formed on the interlayer insulating film with spacing from the first bus and connected to third source/drain regions; an inter-bus interconnect formed between the first and second buses for connecting these buses; a first contact pad provided on the first bus, to which a wire is connected; and a second contact pad provided on the second bus, to which a wire is connected. The inter-bus interconnect is in contact with part of the side of the first bus facing the second bus and part of the side of the second bus facing the first bus. The first and second contact pads are respectively in contact with part of the first and second buses. | 08-30-2012 |
20120226847 | MULTI-PROCESSOR DEVICE - The present invention intends to provide a high-performance multi-processor device in which independent buses and external bus interfaces are provided for each group of processors of different architectures, if a single chip includes a plurality of multi-processor groups. A multi-processor device of the present invention comprises a plurality of processors including first and second groups of processors of different architectures such as CPUs, SIMD type super-parallel processors, and DSPs, a first bus which is a CPU bus to which the first processor group is coupled, a second bus which is an internal peripheral bus to which the second processor group is coupled, independent of the first bus, a first external bus interface to which the first bus is coupled, and a second external bus interface to which the second bus is coupled, over a single semiconductor chip. | 09-06-2012 |
20120233371 | Method and System for an Integrated Host PCI I/O Bridge and Dual Port Gigabit Ethernet Controller - Embodiments may include two gigabit Ethernet controllers integrated within a single chip and an I/O bridge coupled to the two gigabit Ethernet controllers and integrated within the single chip. The system may further include an I/O function coupled to the I/O bridge that is integrated within the single chip. The I/O function may include I/O logic and an I/O buffer integrated within the single chip and coupled to the I/O bridge and/or the two gigabit Ethernet controllers. A timing function or timing block may also be coupled to the I/O bridge and integrated within the single chip. A host system may be coupled to the I/O bridge. The I/O bridge may further include a primary bus controller, which may be a primary PCI bus controller. The controller or controller block may include control and status registers that may be coupled to the primary bus controller. | 09-13-2012 |
20120239847 | MULTI-CORE MICROPROCESSOR INTERNAL BYPASS BUS - Microprocessors with multi-core dies that include bypass buses are provided. Each microprocessor comprises a plurality of physical pins for coupling the microprocessor to a processor bus coupled to a chipset. The multi-core die has at least two complementary sets of one or more processing cores, each providing a bus interface coupling respective core inputs and outputs to corresponding processor bus lines. A bypass bus on the die enables cores of the complementary sets to bypass the processor bus and communicate directly with each other. The bypass bus does not carry signals off the die, drive signals on the processor bus to the chipset, or receive chipset-drive signals from the processor bus. Moreover, the microprocessor is operable to detect whether the chipset or a complementary core is driving the processor bus, and if the latter, to select the higher quality bypass bus signals over the corresponding processor bus signals. | 09-20-2012 |
20120271979 | SYSTEMS AND METHODS FOR ENABLING COMMUNICATION BETWEEN AN ACCESSORY CHARGER ADAPTER (ACA) AND AN ACA-AGNOSTIC UNIVERSAL SERIAL BUS CONTROLLER - A physical layer integrated circuit (PHY), including an accessory charger adapter (ACA) bridge circuit to communicate with an ACA via a universal serial bus (USB) cable having at least an ID pin and a VBUS pin. The PHY is also to communicate with an ACA-agnostic USB controller configured to act as an A-device or as a B-device. The ACA includes a USB accessory port. The ACA bridge circuit includes detection and control logic configured to detect, based on a resistance sensed on the ID pin, that a B-device is connected to the USB accessory port of the ACA and, as a result of such a detection, generate a signal to the USB controller that causes the USB controller to act as an A-device and ignore a VBUS drive signal from the USB controller. | 10-25-2012 |
20120284446 | ACCELERATOR ENGINE EMULATION OVER AN INTERCONNECT LINK - An apparatus and method of emulating a hardware accelerator engine over an interconnect link such as PCI Express (PCIe) link. In one embodiment, the accelerator emulation mechanism is implemented inside a PCIe Host Bridge which is integrated into a host IC or chipset. The accelerator emulation mechanism provides an interface compatible with other integrated accelerators thereby eliminating the overhead of maintaining different programming models for local and remote accelerators. Co-processor requests issued by threads requesting a service (client threads) targeting remote accelerator are queued and sent to a PCIe adapter and remote accelerator engine over a PCIe link. The remote accelerator engine performs the requested processing task, delivers results back to host memory and the PCIe Host Bridge performs co-processor request completion sequence (status update, write to flag, interrupt) include in the co-processor command. | 11-08-2012 |
20120284447 | CONSTITUTING A CONTROL SYSTEM WITH VIRTUAL AND PHYSICAL BACKPLANES AND MODULES AS BUILDING BLOCKS - A custom control system created based on combinations of software applications and hardware control and communication modules overlaid in a virtual backplane. The user can select the modules of interest and map them together without the loss of communications between the modules while the control system is configured and overlaid. The user can then archive the system design and implement the system with a greater level of confidence in the ability of the design to meet the requirements of the application while reducing the costs of the implementation. | 11-08-2012 |
20120303854 | MODULAR INTERFACE-INDEPENDENT STORAGE SOLUTION SYSTEM - A storage system provides a modular interface-independent architecture. The storage system includes multiple of storage devices removably coupled to a backplane. The backplane is configured to receive the signals from the storage devices, and separate the received signals into groups of power and data signals. The backplane is further configured to modify the second data signals to include information describing storage devices associated with the data signals, and convert the data signals into a predetermined interface technology signal format. The storage system also includes a bridge configured to modify the converted data signals to remove information describing storage devices associated with the data signals. The bridge is further configured to group the modified converted data signals into multiple data blocks and assign each of the plurality of data blocks to an output port of the bridge. | 11-29-2012 |
20120324137 | EXPANDER TO CONTROL MULTIPATHS IN A STORAGE NETWORK - A SAS expander forms a first path coupling the SAS initiator and a first port of a SAS target together. The first SAS expander notifies the SAS initiator of a virtual expander address instead of a SAS address of the first SAS expander. The first SAS expander notifies the SAS initiator of a virtual target port address, at least instead of a SAS address of the first port of the SAS target. A second SAS expander forms a second path coupling the SAS initiator and a second port of the SAS target together. The second SAS expander notifies the SAS initiator of the virtual expander address instead of a SAS address of the second SAS expander. The second SAS expander notifies the SAS initiator of the virtual target port address, at least instead of a SAS address of the second port of the SAS target. | 12-20-2012 |
20130024593 | SOURCE PACKET BRIDGE - A communication function between ports on a node that does not require a common time base to be distributed across the network is disclosed. A data stream received over a first port is placed on an interface between nodes using the time base of the first port; a second port samples the data stream on the interface and timestamps it using the time base of the second port. The data stream is timestamped by the second port and packetized before transmitted to the second node to another bridge or device. Alternatively, the first port extracts a time stamp from the data stream and calculates an offset using a cycle timer value from the bus connected to the first port. The offset is added to the cycle timer value on the bus connected to the second port and used to timestamp the data stream. | 01-24-2013 |
20130036248 | MONITOR WITH PERSONAL SYSTEM/2 KEYBOARD INTERFACE - A monitor for a computer includes a display screen, a frame fixing the display screen, a display circuit, a personal system (PS)/2 keyboard interface, a power circuit, and a monitor video interface. The PS/2 keyboard interface is disposed on the frame, and includes a data signal pin, a clock signal pin, a power pin, and a ground pin. The power circuit powers the display circuit and the PS/2 keyboard interface. The monitor video interface includes video pins, first and second idle pins. The video pins are connected to the display circuit. The first idle pin is connected to the data signal pin. The second idle pin is connected to the clock signal pin. | 02-07-2013 |
20130060986 | INTEGRATED LINK CALIBRATION AND MULTI-PROCESSOR TOPOLOGY DISCOVERY - Integrating link calibration and dynamic topology discovery in a multi-processor system establishes a first of a plurality of processors in the multi-processor system as a director of integrated link calibration and dynamic topology discovery. A plurality of high speed interconnects connects the plurality of processors with each other. The director processor directs calibration of each of the plurality of high speed interconnects via a shared hardware resource. The shared hardware resource is shared among the plurality of processors. Topology of the multi-processor system is incrementally discovered as each of the plurality of high speed interconnects is calibrated based on a result of each of the plurality of high speed interconnects being calibrated. | 03-07-2013 |
20130091314 | Field Bus Network Adapter and Field Bus Network Subscriber with Field Bus Connections - A field bus network adapter includes a first field bus connection configured to connect a first field bus cable, a second field bus connection configured to connect a second field bus cable, and N number of third field bus connections configured to connect a third cable each. The first field bus connection and the second field bus connection are connected to the N number of third field bus connections such that (i) data received at the first field bus connection are output at a first of the N number of third field bus connections, (ii) data received at an nth of the N number of third field bus connections are output at an (n+1)th of the N number of third field bus connections, and (iii) data received at an Nth of the N number of third field bus connections are output at the second field bus connection. | 04-11-2013 |
20130132633 | INTERFACE APPARATUS, CASCADING SYSTEM THEREOF AND CASCADING METHOD THEREOF - An interface apparatus, a cascading system thereof, and a cascading method thereof are provided. The cascading system includes a host, a first-type interface apparatus, and a second-type interface apparatus which are serially connected. The host provides data transmission of a first and a second channel by a first controller through a first interface port. In the first-type interface apparatus, data of the first channel is transmitted to a second controller through a second interface port and then to a third interface port, and data of the second channel is directly transmitted to the third interface port through the second interface port. In the second-type interface apparatus, the data of the second channel are transmitted to a third controller through a forth interface port and then to the fifth interface port, and the data of the first channel is directly transmitted to the fifth interface port through the forth interface port. | 05-23-2013 |
20130151746 | ELECTRONIC DEVICE WITH GENERAL PURPOSE INPUT OUTPUT EXPANDER AND SIGNAL DETECTION METHOD - An electronic device includes a general purpose input output (GPIO) expander and a baseboard management controller (BMC). The GPIO expander includes a number of GPIO interfaces and a gathering interface connected to the GPIO interfaces. The BMC includes a public interface and a scanning interface connected to the gathering interface. Each element is connected to the public interface and a different one of the GPIO interfaces. The BMC periodically detects whether there is a signal input from the public interface, scans the GPIO interfaces when there is a signal input from the public interface to determine a GPIO interface with a logic high level, an element connected to the GPIO interface, and a signal input from the element, and records an event including the GPIO interface, the element connected to the GPIO interface, and the signal, and stores the event. | 06-13-2013 |
20130159587 | Interconnect Redundancy for Multi-Interconnect Device - A multi-interconnect integrated circuit device includes an input/output (I/O) circuit for conveying a plurality of interleaved data channel groups by configuring the I/O circuit to convey a first data channel group over a default fixed interconnect signal paths if there are no connection failures in the default fixed interconnect signal paths, and to convey the first data channel group over a second plurality of default fixed interconnect signal paths if there is at least one connection failure in the first plurality of default fixed interconnect signal paths, where the second plurality of default fixed interconnect signal paths includes a redundant fixed interconnect signal path for replacing a failed interconnect signal path from the first plurality of default fixed interconnect signal paths. | 06-20-2013 |
20130159588 | COMPUTING DEVICE AND METHOD FOR TESTING SOL FUNCTION OF A MOTHERBOARD OF THE COMPUTING DEVICE - A method for testing a serial over local area network (SOL) function of a motherboard of a computing device. The method determines that the SOL function is normal if forward data can be transmitted from the serial port of the motherboard to a network interface controller (NIC) of the motherboard through a predefined path, and backward data can be transmitted from the NIC to the serial port through a predefined reverse path. The method determines that the SOL function is abnormal if the forward data cannot be transmitted from the serial port to the NIC through the predefined path, or the backward data cannot be transmitted from the NIC to the serial port through the predefined reverse path. | 06-20-2013 |
20130198432 | INTERRUPT HANDLING SYSTEMS AND METHODS FOR PCIE BRIDGES WITH MULTIPLE BUSES - A bridge includes buses, a memory, a component module, an interface and an interrupt module. The component module transfers data between a host control module and a network device via the memory and the buses. The interface is connected between the memory and the network device and transmits status information to the memory via one of the buses. The status information indicates completion of a last data transfer between the network device and the host control module. An interrupt module, subsequent to the status information being transmitted to the memory, detects a first interrupt generated by the network device, and transmits an interrupt message to the component module via the memory and the one of the buses. The component module then generates a second interrupt detectable by the host control module. The second interrupt indicates completion of data transfer between the network device and the host control module. | 08-01-2013 |
20130219100 | Staggered Island Structure In An Island-Based Network Flow Processor - An island-based network flow processor (IB-NFP) integrated circuit includes rectangular islands disposed in rows. In one example, the configurable mesh data bus is configurable to form a command/push/pull data bus over which multiple transactions can occur simultaneously on different parts of the integrated circuit. The rectangular islands of one row are oriented in staggered relation with respect to the rectangular islands of the next row. The left and right edges of islands in a row align with left and right edges of islands two rows down in the row structure. The data bus involves multiple meshes. In each mesh, the island has a centrally located crossbar switch and six radiating half links, and half links down to functional circuitry of the island. The staggered orientation of the islands, and the structure of the half links, allows half links of adjacent islands to align with one another. | 08-22-2013 |
20130246681 | POWER GATING FOR HIGH SPEED XBAR ARCHITECTURE - A low power interconnect allows client to client communication using an XBAR architecture. An XBAR compiler generates chip designs with XBAR data paths structured to reduce energy consumption and delay. Repeaters inserted into XBAR data paths reduce resistance capacitance (RC) delays so that a design can support desired frequency specifications along a path. Dynamic power consumption is reduced by inserting latch repeaters in the XBAR track. The latch repeaters each include a transmission gate and a latch. Select circuitry couples selected clients to a path. Enable circuitry opens the transmission gates located on the path between the selected clients. Latch repeaters that are not enabled on a given communication cycle gate off the unused portions of the path and maintain the data that was latched on a previous cycle. | 09-19-2013 |
20130268710 | METHOD FOR DATA THROUGHPUT IMPROVEMENT IN OPEN CORE PROTOCOL BASED INTERCONNECTION NETWORKS USING DYNAMICALLY SELECTABLE REDUNDANT SHARED LINK PHYSICAL PATHS - Methods and apparatus for facilitating data throughput improvements in interconnect fabrics employing point-to-point links using dynamically selectable routing. Initiators and targets are operatively coupled to first and second fabrics. The first and second fabrics include multiple point-to-point internal links and are communicatively coupled to one another via multiple fabric-to-fabric links, including first and second links from the first fabric to the second fabric. During operations, traffic on the first fabric-to-fabric link is detected to determine if it is busy, and depending on the determination, data transfers from an initiator coupled to the first fabric destined for a target coupled to the second fabric are selectively routed via either the first or second fabric-to-fabric links. | 10-10-2013 |
20130282946 | CONTROLLER AREA NETWORK BUS - The present disclosure describes a vehicle implementing a processing module for receiving data from a high-speed CAN bus and sending data to a low-speed CAN bus. The processing module shunts into the data from the high-speed CAN bus without affecting the self-contained data flow of the high-speed CAN bus. The processing module analyzes the received data and generates data (by forwarding or other means) to be sent to a low-speed CAN bus according to the received data. The processing module is designed to be replaceable and/or upgradable without affecting other components during the life-cycle of the vehicle. The processing module may further contain expansion modules that perform tasks in response to the received data. | 10-24-2013 |
20130282947 | INTERFACE SWITCHING CONTROL METHODS, AND PORTABLE TERMINALS AND PORTABLE MOBILE DEVICES USING THE SAME - An interface switching control method, a portable terminal and a portable mobile device using the method are disclosed. The method is applied in a portable terminal including a first device and a second device. The first device is connected to a shared device via a first interface, and the second device is connected to the shared device via a second interface. The portable terminal has a first state in which the first device and the second device are connected, and a second state in which the first device and the second device are disconnected. The method includes detecting a state of the portable terminal; and when the detection result indicates that the portable terminal is in the first state, controlling the first interface to be in an enabled state and controlling the second interface to be in a disabled state. The method achieves a real-time switching control over the interfaces for the shard device, and optimizes the interface control for the hybrid-system portable terminal. It is possible to meet various system performance requirements of different devices and reduce the system power consumption by enabling the interfaces required by the respective devices according to the different state of the portable terminal. | 10-24-2013 |
20130297845 | MECHANISM FOR FACILITATING CUSTOMIZATION OF MULTIPURPOSE INTERCONNECT AGENTS AT COMPUTING DEVICES - A mechanism is described for facilitating customization of multipurpose interconnect agents at computing devices according to one embodiment of the invention. A method of embodiments of the invention includes enhancing a multipurpose interconnect agent by associating a customization block to the multipurpose interconnect agent at a computing system. Enhancing may include customization of one or more functionalities of the multipurpose interconnect agent. The method may further include customizing, via the customization block, the one or more functionalities of the enhanced multipurpose interconnect agent, wherein customizing includes enabling integration of two or more processor interconnects carrying data packets. | 11-07-2013 |
20130318275 | OFFLOADING OF COMPUTATION FOR RACK LEVEL SERVERS AND CORRESPONDING METHODS AND SYSTEMS - A method is disclosed that includes writing data to predetermined physical addresses of a system memory, the data including metadata that identifies a processing type; configuring a processor module to include the predetermined physical addresses, the processor module being physically connected to the memory bus by a memory module connection; and processing the write data according to the processing type with an offload processor mounted on the processor module. | 11-28-2013 |
20130326106 | METHODS AND STRUCTURE FOR ACCOUNTING FOR CONNECTION RESETS BETWEEN PERIPHERAL COMPONENT INTERCONNECT EXPRESS BRIDGES AND HOST DEVICES - Methods and structure for accounting are provided for enhancing communications via a PCIE bridge. The bridge comprises a host interface that manages communications with a host device, and a PCIE interface that provides Memory Read Requests (MRds) to a PCIE device and receives Memory Read Completions (MRCs) from the PCIE device. The bridge also comprises a control unit that inserts tag information into the MRds. The control unit detects a reset of the host interface and revises the tag information inserted into the MRds responsive to detecting the reset. Additionally, the control unit analyzes tag information of received MRCs to determine whether it is the revised tag information or is old tag information, returns completion data from MRCs having the revised tag information to the host device, and discards completion data from received MRCs having the old tag information. | 12-05-2013 |
20130339565 | METHOD, DEVICE AND SYSTEM FOR AGGREGATION OF SHARED ADDRESS DEVICES - Techniques and mechanisms for managing resources of an aggregate device which spans multiple physical devices of a computer platform. In an embodiment, an aggregation device coupled to a host bus of the computer platform receives resource information generated by a pre-boot software process of the computer platform. In another embodiment, the aggregation device, based on the received resource information, represents a resource in a first input/output (I/O) device to a host operating system (OS) as residing in the aggregation device, the first I/O device coupled to the aggregation device via a host bus for exchanging communications referencing a shared address space. | 12-19-2013 |
20140019661 | System and Method for Providing Network Access for a Processing Node - A network interface controller includes a plurality of host interfaces configured to communicate with a plurality of processing nodes, a plurality of network interfaces configured to provide network communication for the processing nodes to a network, and a shared resource configured to provide link based services and stateless offload services for the processing nodes when communicating with the network. | 01-16-2014 |
20140019662 | SECURE PHYSICAL LAYER MANAGEMENT - One embodiment is directed to a communication media including one or more communication paths extending from a first end to a second end and a first connector assembly terminating the first end of the one or more communication paths. The first connector assembly includes a physical layer management (PLM) interface that is isolated from signals on the one or more communication paths. The first connector assembly also includes a programmable processor coupled to a storage device and coupled to the PLM interface. The programmable processor is configured to perform secure communications with another device coupled to the PLM interface to communicate physical layer information regarding the communication media to the other device. An aggregation point can associate a first port on the other device to which the first connector assembly is inserted with the first connector assembly or the communication media using the physical layer information. | 01-16-2014 |
20140040524 | RACK, SERVER AND ASSEMBLY COMPRISING SUCH A RACK AND AT LEAST ONE SERVER - A rack with a mounting bay to accommodate servers, wherein 1) the mounting bay defines two opposing internal areas disposed parallel to an insertion direction of the servers and divided into a multiplicity of slots, 2) one or more data lines for data connection of servers are configured in the rack, 3) the data lines include optical data lines, and 4) on at least one of the two internal areas of the mounting bay, an end section of a data line with a data interface is disposed on each slot such that a contactless optical data connection to a further data interface on a corresponding server is enabled. | 02-06-2014 |
20140047153 | COMPUTING APPARATUS WITH ENHANCED PARALLEL I/O FEATURES - Provided is a parallel I/O computing apparatus that includes a plurality of computing devices that may have different response characteristics depending on a number of parallel I/Os that are processed by the computing devices. The computing apparatus also includes an I/O dispatcher that distributes a different number of I/Os to one or more of the computing devices based on characteristics of the computing devices. | 02-13-2014 |
20140047154 | INTER-CHIP COMMUNICATIONS FOR IMPLANTABLE STIMULATING DEVICES - A device including a first integrated circuit (IC), a second IC configured to provide instructions to the first IC based on received data, wherein the first IC is a high-voltage IC and the second IC is a low-voltage IC, and a communication interface between the first and second ICs including a data bus of parallel data lines. The second IC is configured to select, based on the received data, one of a plurality of different communication modes for providing the instructions to the first IC via the communication interface, wherein each mode is defined by a quantity of address data and a quantity of configuration data used to provide the instructions to the first IC. | 02-13-2014 |
20140052885 | PARALLEL COMPUTER SYSTEM, DATA TRANSFER DEVICE, AND METHOD FOR CONTROLLING PARALLEL COMPUTER SYSTEM - A switch includes a plurality of ports and a combination determining unit that determines a central processing unit (CPU) to be paired with one of the ports. The port includes: an arbitration circuit that selects the CPU to be paired therewith when receiving an arbitration request from the CPU to be paired in a predetermined state, and selects one of the CPUs from which the arbitration request has been received in other cases to return transmission permission; and a data transfer unit that transfers the received data from the selected CPU to another CPU. The CPU includes: a request transmission unit that transmits the arbitration request to the ports; and a data transmission unit that transmits data to the paired port when the arbitration request is transmitted to the paired port in the predetermined state, and transmits data to the ports that have returned transmission permission in other cases. | 02-20-2014 |
20140068131 | LIMITING BANDWIDTH FOR WRITE TRANSACTIONS ACROSS NETWORKS OF COMPONENTS IN COMPUTER SYSTEMS - The disclosed embodiments provide a system that facilitates use of a network of components in a computer system. The system includes a bandwidth-allocation apparatus that provides a write transaction limit for a component on the network. The system also includes a transaction-management apparatus that compares the write transaction limit to a set of outstanding write transactions for the component upon detecting a write transaction from the component to the network. If the write transaction causes the set of outstanding write transactions to exceed the write transaction limit, the transaction-management apparatus restricts transmission of the write transaction over the network. | 03-06-2014 |
20140068132 | AUTOMATIC CONSTRUCTION OF DEADLOCK FREE INTERCONNECTS - Systems and methods for automatically building a deadlock free inter-communication network in a multi-core system are described. The example embodiments described herein involve deadlock detection during the mapping of user specified communication pattern amongst blocks of the system. Detected deadlocks are then avoided by re-allocation of channel resources. An example embodiment of the deadlock avoidance scheme is presented on Network-on-chip interconnects for large scale multi-core system-on-chips. | 03-06-2014 |
20140075078 | SYSTEM AND METHOD FOR SUPPORTING A SCALABLE MESSAGE BUS IN A DISTRIBUTED DATA GRID CLUSTER - A system and method can a scalable message bus in a distributed data grid. The system can provide a plurality of message buses in the distributed data grid, wherein the distributed data grid includes a plurality of cluster members and provides a plurality of services. Furthermore, the system can associate each said service in the distributed data grid with a said message bus, and use the plurality of message buses to support data transferring between different services on different cluster members in the distributed data grid. Additionally, the system can use a datagram layer to support clustering in the distributed data grid, and bypass the datagram layer in the distributed data grid for data transferring. | 03-13-2014 |
20140082248 | BUFFFERED CONDUITS FOR HIGH THROUGHPUT CHANNEL IMPLEMENTATION, CROSSTALK DE-SENSITIZATION AND LATE TIMING FIXES ON SKEW SENSITIVE BUSES - A method of manufacturing a system on a chip and a system on a chip including a set of pre-designed modules. These modules are place on a semiconductor and connecting by a set of busses formed according to a set of design rules specifying tracks having a minimum size of conductors and a minimum spacing between conductors. The busses are routed in a preferred direction. The busses include minimum size conductors at alternate tracks within a selected metal layer of the semiconductor and minimum size conductors at alternate tracks in a different metal layer. The conductors in the different metal layer are connected to corresponding connectors in the selected metal layer by vias. Shields of conductors not connected to the bus may be included in tracks not including bus conductors. | 03-20-2014 |
20140101353 | MULTI-PROCESSOR DEVICE - The present invention intends to provide a high-performance multi-processor device in which independent buses and external bus interfaces are provided for each group of processors of different architectures, if a single chip includes a plurality of multi-processor groups. A multi-processor device of the present invention comprises a plurality of processors including first and second groups of processors of different architectures such as CPUs, SIMD type super-parallel processors, and DSPs, a first bus which is a CPU bus to which the first processor group is coupled, a second bus which is an internal peripheral bus to which the second processor group is coupled, independent of the first bus, a first external bus interface to which the first bus is coupled, and a second external bus interface to which the second bus is coupled, over a single semiconductor chip. | 04-10-2014 |
20140115220 | SYNCHRONIZING BARRIER SUPPORT WITH ZERO PERFORMANCE IMPACT - The barrier-aware bridge tracks all outstanding transactions from the attached master. When a barrier transaction is sent from the master, it is tracked by the bridge, along with a snapshot of the current list of outstanding transactions, in a separate barrier tracking FIFO. Each barrier is separately tracked with whatever transactions that are outstanding at that time. As outstanding transaction responses are sent back to the master, their tracking information is simultaneously cleared from every barrier FIFO entry. | 04-24-2014 |
20140122764 | ADAPTIVE INTEGRATED CIRCUITRY WITH HETEROGENEOUS AND RECONFIGURABLE MATRICES OF DIVERSE AND ADAPTIVE COMPUTATIONAL UNITS HAVING FIXED, APPLICATION SPECIFIC COMPUTATIONAL ELEMENTS - The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications. | 05-01-2014 |
20140173161 | MULTIPROCESSOR SYSTEM WITH IMPROVED SECONDARY INTERCONNECTION NETWORK - Embodiments of a multiprocessor system are disclosed that may include a plurality of processors interspersed with a plurality of data memory routers, a plurality of bus interface units, a bus control circuit, and a processor interface circuit. The data memory routers may be coupled together to form a primary interconnection network. The bus interface units and the bus control circuit may be coupled together in a daisy-chain fashion to form a secondary interconnection network. Each of the bus interface units may be configured to read or write data or instructions to a respective one of the plurality of data memory routers and a respective processor. The bus control circuit coupled with the processor interface circuit may be configured to function as a bidirectional bridge between the primary and secondary networks. The bus control circuit may also couple to other interface circuits and arbitrate their access to the secondary network. | 06-19-2014 |
20140223066 | Multi-Node Management Mechanism - The described embodiments include a multi-node management mechanism for managing a plurality of server nodes. These embodiments further comprise a separate set of busses coupled between each of the server nodes and the multi-node management mechanism and a controller in the multi-node management mechanism, the controller being coupled to each bus in the sets of busses. In these embodiments, the controller is configured to handle communications on each bus so that the multi-node management mechanism appears to a corresponding server node to be a separate endpoint for the bus. | 08-07-2014 |
20140223067 | BUS SYSTEM - The invention relates to a bus system for transmitting data between data processing units ( | 08-07-2014 |
20140244885 | CONFIGURATION SNOOPING BRIDGE - Systems and methods for configuration snooping are provided. A bridge identifies an initialization message of a central processing unit (CPU) for a device that is downstream of a primary interface of the bridge. The bridge identifies a response to the initialization message. The bridge determines the address range for the device. The bridge stores the address range for the device in a list in the bridge. | 08-28-2014 |
20140244886 | CONTROLLER FOR FACILITATING OUT OF BAND MANAGEMENT OF RACK-MOUNTED FIELD REPLACEABLE UNITS - A system for the management of rack-mounted field replaceable units (FRUs) that affords the enhanced availability and serviceability of FRUs provided by blade-based systems but in a manner that accommodates different types of FRUs (e.g., in relation to form factors, functionality, power and cooling requirements, and/or the like) installed within a rack or cabinet. | 08-28-2014 |
20140289439 | METHOD OF HANDLING TRANSACTIONS, CORRESPONDING SYSTEM AND COMPUTER PROGRAM PRODUCT - A system, such as a System-on-Chip includes an interface component or PLUG which generates transactions over an IP block, such as an interconnect serving one or more clients via virtual channels. The client or clients are mapped onto the virtual channels via client/virtual channel mappings. The virtual channels are provided as a first set of virtual channels in the interface component which cooperate with a second set of virtual channels in the IP block. First and second client/virtual channel mappings for the first set of virtual channels and the second set of virtual channels are provided. The first and second client/virtual channel mappings are separately programmable and mutually decoupled from one another. | 09-25-2014 |
20140310442 | INTEGRATED CIRCUIT FOR VIDEO / AUDIO PROCESSING - An integrated circuit for video/audio processing in which design resources obtained by development of video/audio devices can also be used for other types of video/audio devices. The integrated circuit includes a microcomputer that includes a CPU, a stream input/output for inputting/outputting a video and audio stream to and from an external device, a media processor that executes the media processing including at least one of compressing and decompressing the video and audio stream inputted to the stream input/output, an AV input/output that converts the video and audio stream subjected to the media processing by the media processor into video and audio signals and outputting these signals to the external device. A memory interface controls a data transfer between the microcomputer, the stream input/output, the media processor and the AV input/output and an external memory. | 10-16-2014 |
20140317331 | EXTERNAL ELECTRONIC DEVICE AND INTERFACE CONTROLLER AND EXTERNAL ELECTRONIC DEVICE CONTROL METHOD - An interface controller, coupling a device main body of an external electronic device to a host, is disclosed, which transmits a termination-on signal to the host prior to a mechanically stable state of a device main body of the external electronic device. When the device main body has not reached the mechanically stable state yet, the interface controller responds to the host with default link information in a delayed manner. The default link information is contained in the interface controller. When the device main body reaches the mechanically stable state, the interface controller transmits specific link information retrieved from the device main body to the host. | 10-23-2014 |
20140330999 | COMPUTER SYSTEM AND A COMPUTER DEVICE - A computer system is provided. The computer system includes a hub board, a common bus, and a plurality of Sibling boards. The hub board has an I/O controller hub, which includes a main communication chipset. The plurality of Sibling boards is coupled to the hub board by the common bus. Each of the Sibling boards includes a memory and at least one CPU. The memory is operative to host a Sibling operating system. The CPU is coupled to the memory. The Southbridge type chipset which resides in the hub board is shared amongst the plurality of Sibling boards. At least one of the plurality of Sibling boards functions as a master processing unit of the system. Sibling boards offer processing flexibility through the means of how they are configured in the system. | 11-06-2014 |
20140351482 | Multi-processor with selectively interconnected memory units - A multi-processor having a plurality of data processing units and memory units has a bus system that selectively interconnects the processing units and the memory units. | 11-27-2014 |
20140359190 | OVER-CURRENT DETECTION FOR BUS LINE DRIVERS - An electrical circuit for driving a bus is described that includes at least one branch coupled to at least one signal line at a termination of the bus and a transmit data input configured to receive data that the electrical circuit drives across the bus. The electrical circuit also includes a current detection unit coupled to the at least one branch, which is configured to detect a current through the at least one branch. The electrical circuit also includes an over-current determination unit coupled to both the current detection unit and the transmit data input. The over-current determination unit is configured to determine an over-current condition at the at least one branch based on the current at the at least one branch and the data at the transmit data input. | 12-04-2014 |
20140365703 | BUS SYSTEM FOR SEMICONDUCTOR CIRCUIT - An exemplary semiconductor circuit bus system includes: a first bus comprised of distributed buses and having a first transfer rate; a second bus with a second transfer rate higher than the first transfer rate; a transmission node; a bus interface (IF) to connect the transmission node to the first bus; a router which connects the first and second buses; and a reception node connected to the second bus. The bus IF controls the flow rate of data flowing through the transmission routes of the first bus by reference to information about the amounts of transmissible data of the transmission routes. The router allocates the amounts of transmissible data to the transmission routes of the first bus and provides information about the amounts of transmissible data of the transmission routes for the bus IF and also controls the flow rate of the data flowing through the second bus. | 12-11-2014 |
20150074312 | MULTI-CHANNEL UNIVERSAL SERIAL BUS (USB) TO SUBRATE CHANNEL SYSTEMS AND METHODS - Multi-channel universal serial bus (USB) to subrate channel systems and methods are disclosed. According to an aspect, a system includes a USB interface configured to communicatively connect to a computing device. The system may also include a multi-channel interface configured to communicatively connect to multiple subrate channels. Further, the system may include a controller configured to communicatively connect the subrate channels with the computing device via the USB interface. The controller may also be configured to communicate, to the computing device, connection specifications for the subrate channels. | 03-12-2015 |
20150074313 | INTERNAL BUS ARCHITECTURE AND METHOD IN MULTI-PROCESSOR SYSTEMS - An internal bus architecture and method is described. Embodiments include a system with multiple bus endpoints coupled to a bus. In addition, the bus endpoints are directly coupled to each other. Embodiments are usable with known bus protocols. | 03-12-2015 |
20150089109 | DATA STORAGE SYSTEM WITH PRE-BOOT INTERFACE - A data storage system and associated method of using may generally have at least a data storage device that has independent first and second interfaces respectively connecting the data storage device to a host controller and an auxiliary controller. The auxiliary controller can be configured to provide system information to the data storage device prior to a synchronized connection being established between the data storage device and the host controller. | 03-26-2015 |
20150089110 | Providing A Consolidated Sideband Communication Channel Between Devices - In an embodiment, the present invention includes a protocol stack having a transaction layer and a link layer. In addition a first physical (PHY) unit is coupled to the protocol stack to provide communication between a processor and a device coupled to the processor via a physical link, where the first PHY unit is of a low power communication protocol and includes a first physical unit circuit. In turn, a second PHY unit is coupled to the protocol stack to provide communication between the processor and the device via a sideband channel coupled between the multicore processor and the device separate from the physical link, where the second PHY unit includes a second physical unit circuit. Other embodiments are described and claimed. | 03-26-2015 |
20150089111 | ACCESSING DATA STORED IN A COMMAND/ADDRESS REGISTER DEVICE - A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device. | 03-26-2015 |
20150113194 | Common Interface/Conditional Access Module and Method of Transmitting Data between Common Interface Card and Integrated Circuit Chip thereof - A common interface (CI)/conditional access (CA) module is used to transmit a conditional access data/command and a transport stream in an interleaving manner between a common interface card and an integrated circuit module having a conditional access module. With the aid of the CI/CA module, a same port can be shared for transmitting the conditional access data/command and the transport stream, instead of using two different and separated ports. | 04-23-2015 |
20150120982 | MULTI-CHANNEL UNIVERSAL SERIAL BUS (USB) TO SUBRATE CHANNEL SYSTEMS AND METHODS - Multi-channel universal serial bus (USB) to subrate channel methods are disclosed. According to an aspect, a method includes providing a system comprising a USB interface and a multi-channel interface configured to communicatively connect to a plurality of subrate channels. The method also includes communicatively connecting the subrate channels with a computing device via the USB interface. Further, the method includes communicating, to the computing device, connection specifications for the subrate channels. | 04-30-2015 |
20150127868 | INFORMATION PROCESSING DEVICE, CONTROL METHOD, AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM HAVING CONTROL PROGRAM RECORDED THEREON - An information processing device creates a management table of bridge addresses by allocating the bridge addresses to a plurality of bridges, respectively, and, when detecting one access to one device of a plurality of devices, refers to the management table, performs, based on the management table referred to, cancelling allocation of a bridge address of the bridge addresses and reallocating the bridge address to one or more of the plurality of bridges to enable execution of the one access, and updates the management table in regard to the bridge address cancelled and reallocated. Consequently, the information processing device can simultaneously use bridges the number of which exceeds a predetermined number even when the bridges the number of which exceeds the predetermined number are provided in the information processing device and therefore bridge addresses run out. | 05-07-2015 |
20150134870 | CLOCKING FOR PIPELINED ROUTING - An integrated circuit may have pipelined programmable interconnects that are configured to select between a routing signal stored in a register and the identical routing signal bypassing the register. The pipelined programmable interconnect may send the selected routing signal over a wire to the next pipelined programmable interconnect circuitry. The integrated circuit may also have clock routing circuitry to select respective clock signals for the registers in the different pipelined programmable interconnects. The clock routing circuitry may include first interconnects that convey region clocks, second interconnects that conveys routing clocks, a first selector circuit to select routing clocks among the region clocks, and a second selector circuit to select routing clocks for the respective registers. | 05-14-2015 |
20150143013 | INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND PROGRAM - An information processing apparatus including processing units and a connection control unit that controls the connections between the processing units, in which the connection control unit is provided with a table creation unit which, with respect to a first logical channel established with a processing unit, creates table information showing a correspondence between logical channels without designating a logical channel that corresponds to the first logical channel when there is no second logical channel established with another processing unit that corresponds to the first logical channel, a table storage unit that stores the table information created by the table creation unit, and a table update unit that updates the table information for the second logical channel that is stored in the table storage unit so as to configure the first logical channel as a logical channel that corresponds to the second logical channel when there is a second logical channel. | 05-21-2015 |
20150309957 | PROGRAMMABLE LOGIC UNIT - Programmable logic units are described. A described unit includes one or more input interfaces to receive one or more input signals; logic elements that are individually programmable; one or more output interfaces to provide one or more output signals; and a programmable interconnect array that is configured to selectively form one or more interconnections within the unit based on one or more programming settings. The programmable interconnect array can be programmable to route the one or more input signals from the one or more input interfaces to at least a portion of the logic elements, programmable to route one or more intermediate signals among at least a portion of the logic elements, and programmable to route one or more signals from at least a portion of the logic elements to produce the one or more output signals via the output interface. | 10-29-2015 |
20150317278 | DRIVER INTERFACE FUNCTIONS TO INTERFACE CLIENT FUNCTION DRIVERS - In embodiments of driver interface functions to interface client function drivers, a set of serial communication protocol driver interfaces are exposed by a core driver stack, and the serial communication protocol driver interfaces include driver interface functions to interface with client function drivers that correspond to client devices configured for data communication in accordance with the serial communication protocol. A client function driver can check for the availability of a driver interface function before interfacing with the core driver stack via the serial communication protocol driver interfaces. A contract version identifier can also be received from the client function driver via an extension of the driver interface functions, where the contract version identifier indicates a set of operation rules by which the client function driver interfaces with the core driver stack. | 11-05-2015 |
20150339251 | NETWORK RESOURCE MANAGEMENT SYSTEM UTILIZING PHYSICAL NETWORK IDENTIFICATION FOR BRIDGING OPERATIONS - The disclosed network resource management system employs a hardware configuration management (HCM) information handling system (IHS) that may couple to a single administered IHS or to multiple administered IHSs via an administrative network. An HCM tool in the HCM IHS may generate, modify and store hardware configuration information, including physical network identifications (PNet IDs), in an HCM database and share the HCM database with the administered IHSs. The administered IHS may be a bridging IHS. A bridging tool may extract hardware configuration information, including PNet IDs, from the HCM database. The bridging tool may utilize the hardware configuration information, including PNet IDs, to enable the bridging IHS to bridge networks internal to the bridging IHS with networks external to the bridging IHS. | 11-26-2015 |
20150347337 | Electronic Apparatus and Device Control Method - An electronic apparatus includes a holding unit that holds state information that indicates the interface that is set in a first device. If use of the interface that is set in a second device should be terminated, the second device sets itself to the interface that is indicated by the state information that is held in the holding unit. | 12-03-2015 |
20150347342 | TERMINAL BOARD ARCHITECTURE FOR UNIVERSAL I/O ALLOWING SIMPLEX OR REDUNDANT DEVICES - Provided is an interface architecture for an application specific integrated circuit (ASIC). The interface architecture includes a circuit board layout including slots for electrically coupling to (n) number of acquisition boards, each acquisition board being configured to accommodate (m) universal channels. The interface architecture is connectable to a plurality of terminal board types and can be configured to accommodate a predetermined multiple of (m) universal channels. | 12-03-2015 |
20150356053 | Virtual GPIO - A finite state machine is provided that both serializes virtual GPIO signals and deserializes virtual GPIO signals. The finite state machine frames the serialized virtual GPIO signals into frames each demarcated by a start bit and an end bit. | 12-10-2015 |
20160012002 | INTERCONNECTION NETWORK TOPOLOGY FOR LARGE SCALE HIGH PERFORMANCE COMPUTING (HPC) SYSTEMS | 01-14-2016 |
20160012004 | INTERCONNECTION NETWORK TOPOLOGY FOR LARGE SCALE HIGH PERFORMANCE COMPUTING (HPC) SYSTEMS | 01-14-2016 |
20160026592 | Unified Converged Network, Storage And Compute System - A unified converged network, storage and compute system (UCNSCS) converges functionalities of a network switch, a network router, a storage array, and a server in a single platform. The UCNSCS includes a system board, interface components free of a system on chip (SoC) such as a storage interface component and a network interface component operably connected to the system board, and a unified converged network, storage and compute application (UCNSCA). The storage interface component connects storage devices to the system board. The network interface component forms a network of UCNSCSs or connects to a network. The UCNSCA functions as a hypervisor that hosts virtual machines or as a virtual machine on a hypervisor and incorporates a storage module and a network module therewithin for controlling and managing operations of the UCNSCS and expanding functionality of the UCNSCS to operate as a converged network switch, network router, and storage array. | 01-28-2016 |
20160055112 | RETURN AVAILABLE PPI CREDITS COMMAND - In response to receiving a novel “Return Available PPI Credits” command from a credit-aware device, a packet engine sends a “Credit To Be Returned” (CTBR) value it maintains for that device back to the credit-aware device, and zeroes out its stored CTBR value. The credit-aware device adds the credits returned to a “Credits Available” value it maintains. The credit-aware device uses the “Credits Available” value to determine whether it can issue a PPI allocation request. The “Return Available PPI Credits” command does not result in any PPI allocation or de-allocation. In another novel aspect, the credit-aware device is permitted to issue one PPI allocation request to the packet engine when its recorded “Credits Available” value is zero or negative. If the PPI allocation request cannot be granted, then it is buffered in the packet engine, and is resubmitted within the packet engine, until the packet engine makes the PPI allocation. | 02-25-2016 |
20160062935 | USB TYPE C TO MHL M1 DEAD BATTERY CHARGING - Methods and apparatus, including computer program products, are provided for cable, connectors, and/or other devices. In one aspect there is provided an apparatus. The apparatus may include a first interface configured to enable coupling to a universal serial bus device; a controller circuitry configured to at least determine an amount of current and/or voltage available at a mobile high-definition link device when coupled and adjust, based on the determined amount, a value of pull up circuitry coupled to the first interface; and a second interface configured to enable coupling to Mobile High-definition link device. Related apparatus, systems, methods, and articles are also described. | 03-03-2016 |
20160077996 | Fibre Channel Storage Array Having Standby Controller With ALUA Standby Mode for Forwarding SCSI Commands - Storage arrays, systems and methods for processing commands to enable SCSI-level forwarding between an active controller and a standby controller are provided. In one example, the standby controller has ports that operate in an asymmetric logical unit access (ALUA) standby (SB) mode. One such method includes receiving a command by a port of the standby controller, wherein the port operates in the ALUA SB mode. The method includes identifying that the command is of a type that is predefined for forwarding, and forwarding the command from a SCSI layer of the standby controller to a SCSI layer of the active controller. The method further includes processing the command in a user space of the active controller to generate return data and forwarding the return data from the active controller to the standby controller. The method additionally includes sending the return data to the initiator, over the port of the standby controller. | 03-17-2016 |
20160085712 | MULTI-CHANNEL, SELECTABLE IDENTITY TAGGING DATA TRANSLATOR AND METHOD - A multi-channel, selectable identity tagging (MCSIT) data translator includes a word monitor port and a channel identifier (ID) tagger. The word monitor port is configured to receive a word generated by a specified one of a plurality of controllable components. The word includes no identifying information for the specified controllable component. The word monitor port is also configured to generate a channel ID corresponding to the specified controllable component and a word type corresponding to the word. The channel ID tagger is configured to determine whether to tag the word with the channel ID based on the word type and, based on the determination, to generate a processed word. | 03-24-2016 |
20160110304 | I/O MODULE, SETTING DEVICE, AND METHOD OF BUILDING PROCESS CONTROL SYSTEM - Provided is an I/O module including: a first interface including connectors each of which is connected to a field device; a second interface connected to a controller that controls the field device; a third interface connected to an external setting device that outputs a setting instruction; and a setting adjustor configured to set tag information, which identifies each of the connectors, to each of the connectors based on the setting instruction input from the setting device via the third interface. | 04-21-2016 |
20160124884 | REDUNDANCY FOR PORT EXTENDER CHAINS - Techniques implementing redundancy in an extended bridge comprising a controller bridge (CB) unit and a plurality of port extender (PE) units are provided. In one embodiment, the CB unit can receive join requests from the plurality of PE units and can determine, based on the join requests, whether the plurality of PE units are physically connected to the CB unit and/or other CB units in the extended bridge according to a ring topology. If the plurality of PE units are physically connected to the CB unit or the other CB units according to a ring topology, the CB unit can select a link in the ring topology as being a standby link. | 05-05-2016 |
20160147694 | CONNECTOR FOR A COMPUTING ASSEMBLY - Examples disclosed herein provide a computing assembly. The computing assembly includes a first CPU package mounted on a PCB, and a second CPU package mounted on the PCB. The computing assembly includes a connector to bridge a convection between a connection interface of the first CPU package and a connection interface of the second CPU package, wherein the connector comprises a plurality of signal paths for routing signals from the first and second CPU packages. The signals paths include a first signal path to route signals between the first and second CPU packages, and a second signal path to route signals between the first CPU package and another component. | 05-26-2016 |
20160147695 | FIELD BUS COUPLER FOR CONNECTING INPUT/OUTPUT MODULES TO A FIELD BUS, AND METHOD OF OPERATION FOR A FIELD BUS COUPLER - A method and apparatus for operating a field bus coupler in a normal operating mode to connect at least one input/output module with the control computer of an industrial automation system, including receiving from the control computer via a field bus a control output value that is transmitted via a sub-bus to the at least one input/output module, and receiving from the at least one input/output module via a sub-bus a control input value that is transmitted via the field bus to the control computer. During a diagnostic mode, the apparatus is operable to assign to the at least one input/output module via the sub-bus at least one desired diagnostic output value, and to assign to the control computer via the field bus at least one desired input value. | 05-26-2016 |
20160154758 | Array Processor Having a Segmented Bus System | 06-02-2016 |
20160179731 | DATA COMMUNICATIONS SYSTEM AND METHOD OF DATA TRANSMISSION | 06-23-2016 |