| Entries |
| Document | Title | Date |
|---|
| 20080201513 | Method and Device to Transfer Digital Data - Transfer digital data to and from a digital source from and to a digital storage device without using an intermediary media like a computer. Digital source includes digital storage devices and digital transmitting devices like televisions, videos and radios. Digital storage devices includes disc-on-keys, other portable hard disks, PDA's, MP3, MP4, digital cameras, and the like. Non-portable digital source examples are bank information booths and car park entry barriers. Screen to show memory content. Means to see contents of memory and move, copy, paste, delete files from and to the digital memory. Voice recognition operation. | 08-21-2008 |
| 20080222336 | DATA PROCESSING SYSTEM - To allow to use arithmetic circuits of sharable resources by priority with a simple procedure. In a data processing system including central processing units and a plurality of arithmetic circuits, wherein the central processing units are able to supply a command to one arithmetic circuit based on one fetched instruction and supply a command to other arithmetic circuit based on other fetched instruction, a memory circuit is provided which is used to store first information indicating which arithmetic circuit is executing a command, and second information indicating which central processing unit has reserved the arithmetic circuit for execution of the next command. When the arithmetic circuit is already executing a command, reservation of the arithmetic circuit for execution of the next command using the second information of the memory circuit, makes it possible, after the execution, to assign operation commands fast to the arithmetic circuits and cause them to execute the commands. | 09-11-2008 |
| 20080222337 | Pipeline accelerator having multiple pipeline units and related computing machine and method - A pipeline accelerator includes a bus and a plurality of pipeline units, each unit coupled to the bus and including at least one respective hardwired-pipeline circuit. By including a plurality of pipeline units in the pipeline accelerator, one can increase the accelerator's data-processing performance as compared to a single-pipeline-unit accelerator. Furthermore, by designing the pipeline units so that they communicate via a common bus, one can alter the number of pipeline units, and thus alter the configuration and functionality of the accelerator, by merely coupling or uncoupling pipeline units to or from the bus. This eliminates the need to design or redesign the pipeline-unit interfaces each time one alters one of the pipeline units or alters the number of pipeline units within the accelerator. | 09-11-2008 |
| 20080250182 | SIP (SYSTEM IN PACKAGE) DESIGN SYSTEMS AND METHODS - SiP design systems and methods. The system comprises a system partitioning module, a subsystem integration module, a physical design module, and an analysis module. The system partitioning module partitions a target system into subsystem partitions according to partition criteria. The subsystem integration module generates an architecture design and/or a cost estimation for the target system according to the subsystem partitions, at least one SiP platform, and IC geometry data. The physical design module generates a SiP physical design with physical routing for the target system according to the architecture design, the subsystem partitions, the SiP platform, and the IC geometry data. The analysis module performs a performance check within the subsystem partitions based on the SiP physical design and/or simulations of the target system. | 10-09-2008 |
| 20080250183 | STREAM UNDER-RUN/OVER-RUN RECOVERY - Machine-readable media, methods, and apparatus are described to recover from stream under-run and/or over-run conditions. In some embodiments, an audio controller may discard any partial sample block of the stream. | 10-09-2008 |
| 20080256281 | SYSTEM AND METHOD FOR PROVIDING AN ADAPTER FOR RE-USE OF LEGACY DIMMS IN A FULLY BUFFERED MEMORY ENVIRONMENT - A system and method for providing an adapter for re-use of legacy DIMMS in a fully buffered memory environment. The system includes a memory adapter card having two rows of contacts along a leading edge of a length of the card. The rows of contacts are adapted to be inserted into a socket that is connected to a daisy chain high-speed memory bus via a packetized multi-transfer interface. The memory adapter card also includes a socket installed on the trailing edge of the card. In addition, the memory adapter card includes a hub device for converting the packetized multi-transfer interface into a parallel interface having timings and interface levels that are operable with a memory module having a parallel interface that is inserted into the socket. In addition, the hub device converts the packetized multi-transfer interface into a parallel interface having timings and interface levels that are operable with a memory module having a parallel interface that is inserted into the socket. The hub device also converts the parallel interface into the packetized multi-transfer interface. | 10-16-2008 |
| 20080256282 | Calibration of Read/Write Memory Access via Advanced Memory Buffer - Methods and apparatuses to calibrate read/write memory accesses through data buses of different lengths via advanced memory buffers. One embodiment includes an advanced memory buffer (AMB) having: a plurality of ports to interface respectively with a plurality of data buses; a port to interface with a common clock bus for the plurality of data buses; and an adjustable circuit coupled with the plurality of ports to level delays on the plurality of data buses. In one embodiment, the data buses have different wire lengths between the dynamic random access memory (DRAM) memory chips and the advanced memory buffer (AMB). | 10-16-2008 |
| 20080270666 | Removable active communication bus - A removable active communication bus of an apparatus in one example comprises at least two blade communication interfaces that are configured to communicatively couple at least two blade components within at least one blade enclosure. | 10-30-2008 |
| 20080276029 | Method and System for Fast Flow Control - Flow of commands from logic under test, such as an FPGA, to a receiving component, such as a component in a PCIe hierarchy, is managed. A rate at which flow control signals are received by the logic under test from the receiving component is determined, the flow control signals indicating that there is space available in a buffer in the receiving component for receiving commands. The determined rate of receipt of the flow control signals is used for managing flow of commands from the logic under test to the receiving component without waiting for actual processing of flow control signals by the logic under test. | 11-06-2008 |
| 20080276030 | SRAM BUS ARCHITECTURE AND INTERCONNECT TO AN FPGA - An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connected in parallel with a tri-state buffer. The pass transistors and tri-state buffers are controlled by configuration SRAM bits. Some of the pass-through interconnect conductors are connected by programmable elements to the address, data and control signal lines of the SRAM blocks, while other pass through the SRAM blocks without being further connected to the SRAM bussing architecture. | 11-06-2008 |
| 20080282010 | Apparatus for digital/analog audio storage and playback - An audio data storage and playback apparatus is provided, including at least a USB hub or USB SIE, at least a storage media interface, and an audio codec. An upstream port of the USB hub or the USB SIE is connected to an electronic device with a USB interface. The storage media interface is connected to a downstream port of the USB hub or an endpoint of a USB SIE. The storage media interface can be connected to a portable storage media, such as flash memory, CD-R/W, DVD-R/W, and hard disk drive, to enable bi-directional data transmission and storage between the electronic device with a USB interface and the portable storage media connected to the storage media interface. The audio codec player forms a bi-directional data transmission connection with the storage media interface. The audio codec player is connected to at least an audio player and an audio input device. The audio data from the electronic device with a USB interface, the portable storage media connected to the storage media interface or the audio input device can be sent to the audio codec for encoding/decoding, and then stored or played back by the audio player or the electronic device with a USB interface to achieve the object of the present invention of multi-directional transmission, encoding/decoding, storage and playing back of audio data. | 11-13-2008 |
| 20080282011 | REMOTE CONTROL SYSTEM AND METHOD THEREOF - A remote control system and a method thereof are provided. The remote control system includes a first host, an adapter, and a peripheral device. The first host converts a first serial signal into a first network packet, and then outputs the first network packet through a network. The adapter is connected to the network to receive the first network packet, and then converts the first network packet into a second serial signal complying with a universal serial bus (USB) format. The peripheral device is coupled to the adapter through the USB, and receives the second serial signal, so that the user can control the peripheral device at a remote site through the network. | 11-13-2008 |
| 20080288703 | Method and Apparatus of Providing Power to an External Attachment Device via a Computing Device - A method and apparatus of providing power to an external Serial Advanced Technology Attachment (SATA) device via a computing device are described here. One embodiment includes, transmitting data to a plurality of devices via at least one port of a first type of a computing device, and providing power to the plurality of devices via at least one port of a second type of the computing device; wherein the plurality of devices comprises one or more of a disk controller and an external Serial Advanced Technology Attachment device. The at least one port of the first type of the computing device is an external Serial Advanced Technology Attachment port and the at least one port of the second type of the computing device is a Universal Serial Bus port. In one embodiment, the disk controller comprises at least one parallel advanced technology attachment port. | 11-20-2008 |
| 20080288704 | METHOD AND SYSTEM FOR UNIVERSAL SERIAL BUS (USB) OVER A/V BRIDGING AND A/V BRIDGING EXTENSIONS - Aspects of a system for universal serial bus (USB) over ANV bridging and ANV bridging extensions may include a LAN subsystem that enables reception of signals from a peripheral device coupled to a computing device via a USB interface. The LAN subsystem may enable the generation of payload data based on the received signals. The LAN subsystem may enable transmission of the generated payload data via a network based on a traffic class designation. The generated payload data may be encapsulated within an outgoing PDU, which may include an Ethernet frame and/or an IP packet. The outgoing encapsulating PDU may contain the traffic class designation. The LAN subsystem may also generate a time stamp for the encapsulating PDU. The LAN subsystem may enable indication that the outgoing encapsulating PDU encapsulates the generated payload data based on one or more data type identifiers, which include an EtherType and an EtherTypeSubType. | 11-20-2008 |
| 20080288705 | Wireless Peripheral Interconnect Bus - A wireless peripheral interconnect bus that enables the transferring of data at a high rate over wireless medium. The bus further enables the wireless connection of peripheral components to a computing device, thereby providing a distributed computing device. The bus implements a layered protocol to provide a reliable link over the wireless medium. The wireless peripheral interconnect bus may be implemented as at least one of a peripheral component interconnect PCI Express™ (PCIe) bus, a PCIe second generation, or a PCIe third generation. | 11-20-2008 |
| 20080288706 | MODULAR AUTOMATION DEVICE - The disclosure relates to a device, arrangement and method for communication between modular devices for measurement, closed-loop control and open-loop control, which are connected to one another via a backplane. It is proposed that two modules of the device in each case be connected to one another via a serial point-to-point connection. Modules with a coupling element are connected to a plurality of other modules. | 11-20-2008 |
| 20080301347 | USB2.0 BI DIRECTIONAL AMPLIFIER - A system for allowing a designer to implement Universal Serial Bus (USB) 2.0 in topologies not anticipated by a USB 2.0 specification and with reduced channel losses, the system comprising: a bus channel having a plurality of electrical elements; and a boost circuit connected at a predetermined location on the bus channel; a plurality of USB signals transmitted through the system; wherein edges of the plurality of USB signals are boosted without impacting the bi-directional nature of the bus channel. | 12-04-2008 |
| 20080301348 | DEVICE FOR CONTROLLING POINT-TO-POINT COMMUNICATION BETWEEN A MODULE AND TRANSMISSION BUS - The invention relates to a device for controlling point-to-point communication between a module ( | 12-04-2008 |
| 20080320198 | USB DEVICE COMMUNICATION APPARATUS, SYSTEMS, AND METHODS - Methods, systems and apparatus may operate to send and receive universal serial bus (USB) control endpoint standard device requests with embedded functional sub-requests. From the USB device perspective, such operations may comprise receiving a control endpoint standard device request from a host at the USB device, decoding the functional sub-request forming a first portion of the control endpoint standard device request, decoding data forming a second portion of the control endpoint standard device request, and executing the functional sub-request by the USB device. Other methods, systems, and apparatus are disclosed. | 12-25-2008 |
| 20080320199 | MEMORY AND CONTROL APPARATUS FOR DISPLAY DEVICE, AND MEMORY THEREFOR - A memory and control apparatus and a memory for a display device are provided. The memory and control apparatus includes a memory, a sense-latch circuit, and a timing and memory controlling apparatus. The memory is used for storing data. The memory has a display data bus and a general data bus. The sense-latch circuit is used for sensing and latching the data on the display data bus. The timing and memory controlling apparatus is used for controlling the memory, so as to make the display data represented on the display data bus, and to make the sense-latch circuit outputting the data on the display data bus. When the display device intends to store the data in the memory, the data on the general data bus is stored to the memory. | 12-25-2008 |
| 20080320200 | LED LIGHT DONGLE COMMUNICATION SYSTEM - A Universal Serial Bus (USB) dongle may include an optical transceiver having a USB inter face for engagement to an electronic device such as a laptop computer or other USB-configured device. The USB dongle may include a converter or buffering, isolation, modulation or amplification circuitry. The USB dongle sends and receives data signals which may be carried upon an optical transmission as generated by an LED light source which in turn is in communication with a host device such as a network processor. The USB dongle may also include operational amplifiers (op-amps) and transistor amplifiers. | 12-25-2008 |
| 20090006702 | SHARING UNIVERSAL SERIAL BUS ISOCHRONOUS BANDWIDTH BETWEEN MULTIPLE VIRTUAL MACHINES - A method and computer readable medium are disclosed. In one embodiment, the method includes enumerating multiple Universal Serial Bus (USB) devices on a computer platform running a multiple virtual machines (VMs). The method also includes assigning each of the USB devices to a VM, wherein each USB device may be assigned to a different VM. The method also includes making each USB device visible only to the VM it is assigned to. The method also includes limiting the bandwidth each of the VMs can schedule its assigned devices within a USB data transfer frame. This will allow all of the VMs to have access to the bandwidth of the frame by avoiding the problem of over-subscription when the schedule is merged. | 01-01-2009 |
| 20090006703 | INTERFACE FOR MULTIPLE MODEMS - Techniques are disclosed involving the exchange of information with multiple modems. For instance, an apparatus includes a host device, a plurality of modems, and a serial connection to transfer information between the host device and the plurality of modems. The information may include data associated with one or more user applications and commands for the plurality of modems. The serial connection may be a Universal Serial Bus (USB) connection. | 01-01-2009 |
| 20090006704 | Deferring Peripheral traffic with sideband control - In some embodiments, a system comprises a host system comprising an industry standard interface, a peripheral device coupled to the host device via the industry standard interface, and logic in the host system to confirm that the host device supports an enhanced feature, identify at least one pin on the industry standard interface on which the enhanced feature may be implemented, enable support for the enhanced feature on the at least one pin, and route communication traffic associated with the enhanced feature to the at least one pin. Other embodiments may be described. | 01-01-2009 |
| 20090019206 | Systems and Methods for Efficient Handling of Data Traffic and Processing Within a Processing Device - The present invention provides an improved platform hub that aims to, in some embodiments, optimize system resources to improve system performance and/or reduce consumption of power. | 01-15-2009 |
| 20090024780 | Universal Measurement or Protective Device - A measurement or protective device has an interface for establishing a connection to at least one measurement transducer and a further interface for connecting to a superordinate data bus. In order to allow the measurement or protective device to be used in a particularly universal manner and to make it possible for complex protective systems to be constructed in a particularly cost-effective manner, a communication unit is provided in the measurement or protective device. The communication unit is connected to both interfaces, can be directly connected to the measurement transducer via the interface, can be connected to the superordinate data bus via the further interface, forms messages and transmits them to the superordinate data bus. | 01-22-2009 |
| 20090024781 | Data Bus Interface With Interruptible Clock - In a data bus with asynchronous data transmission via a clock and a data line, the transmitted data are ascertained by sampling with a multiple of the data rate of the data bus. Sampling is done in this case with a clock which is not synchronous with the asynchronous clock of the data bus. For avoiding interferences which develop due to the unnecessary operation of the interface circuit with a high frequency clock when no data are currently transmitted, a control circuit is provided for detecting the beginning and the end of a data transmission. Only at the beginning of a data transmission, the interface circuit will be supplied with the required clock. After the end of the data transmission, the clock for the interface circuit will be switched off again. The control circuit is preferably designed as a state machine which reacts, without the need for clock signals, to the states on the data and clock line of the data bus. | 01-22-2009 |
| 20090043937 | Three-Dimensional Interconnection Architecture For Multiprocessor Computer - A three dimensional interconnection architecture is provided for a multiprocessor computer. The interconnection architecture includes multiple processor boards, one or more interconnection board and one or more edge board. The processor boards are configured parallel to each other, each having plural processors configured thereon. The interconnection board is connected with one side of each of the processor boards to allow one of the processors on one of the processor boards operatively connecting with another one of the processors on another one of the processor boards. The edge board is connected with another side of each of the processor boards to allow one of the processors on one of the processor boards operatively connecting with another one of the processors on another one of the processor boards. | 02-12-2009 |
| 20090043938 | SYSTEM FOR MEASURING AND OUTPUTTING AN ELECTRIC QUANTITY - A system is disclosed which communicates a quantity derived from measured time-dependent analog electric signals to an external bus or communication interface. The system includes a basic unit with a digitizer for converting the time-dependent analog signals into digital signal data, and at least one processor for computing the quantity from the digitized signals. A bus-specific adapter interfaces the digitized signals from the basic unit with the external bus. The adapter has an interface to the basic unit that is independent of the corresponding external bus and another interface to the external bus that is specific to the external bus. The adapter operates as a master and the basic unit operates as a slave. The adapter is advantageously implemented as a module separate from the basic unit, but which is easily attachable to the basic unit for easy exchange for configuring the system for different external buses. | 02-12-2009 |
| 20090043939 | Bus node - The present invention relates to an apparatus for connection to a communication bus, in particular an apparatus for encoding the status of several emergency devices for communication across an AS-interface. A data code indicative of a collective state of one or more subsets of the emergency devices is communicated during cyclic communication from the slave to the master whereas information indicative of the individual states of the emergency devices is communicated during acyclic communication from the slave to the master. | 02-12-2009 |
| 20090049223 | INTERFACE WITH MULTIPLE PACKET PREEMPTION BASED ON START INDICATORS OF DIFFERENT TYPES - Preemption techniques are disclosed which permit multiple high-priority packets to preempt a single low-priority packet. In one aspect, a first device is configured for communication with a second device via an interface bus. The first device comprises interface circuitry configured to receive from the second device a start indicator of a first type and a start indicator of a second type, and to allow at least one data segment associated with the start indicator of the second type to preempt at least one data segment associated with the start indicator of the first type. The start indicator of the second type may have a longer pulse width than that of the start indicator of the first type, such as a double-length pulse width. The first and second devices may comprise physical layer and link layer devices of a communication system. | 02-19-2009 |
| 20090049224 | System and Method for Distributed Partitioned Library Mapping - Embodiments of the present invention provide a system and method of media library access that eliminates, or at least substantially reduces, the shortcomings of prior art media library access systems and methods. More particularly, embodiments of the present invention provide systems and methods of distributed mapping of media library partitions. According to one embodiment, the present invention can include a first controller connected to a data transport element of a media library and a second controller connected to a media changer of the media library. The first controller can maintain a media library partition representing a portion of the media library, receive a command from a host application based on the media library partition and forward the command to the second controller. The first controller can further translate logical addresses referenced in the command to physical addresses before forwarding the command to the second controller. The second controller can receive the command from the first controller and forward the command to the media changer. The second controller, according to another embodiment of the present invention, can also prioritize the command on a FIFO basis or according to other prioritization scheme known in the art. | 02-19-2009 |
| 20090055568 | Non-blocking Address Switch with Shallow Per Agent Queues - In one embodiment, a switch is configured to be coupled to an interconnect. The switch comprises a plurality of storage locations and an arbiter control circuit coupled to the plurality of storage locations. The plurality of storage locations are configured to store a plurality of requests transmitted by a plurality of agents. The arbiter control circuit is configured to arbitrate among the plurality of requests stored in the plurality of storage locations. A selected request is the winner of the arbitration, and the switch is configured to transmit the selected request from one of the plurality of storage locations onto the interconnect. In another embodiment, a system comprises a plurality of agents, an interconnect, and the switch coupled to the plurality of agents and the interconnect. In another embodiment, a method is contemplated. | 02-26-2009 |
| 20090083468 | MANAGEMENT METHOD FOR UNIVERSAL SERIAL BUS (USB), BOOTING METHOD FOR COMPUTER DEVICE AND APPLIED MODULE THEREOF - A management method for a USB includes the step of detecting number of electronic devices connected to USB interfaces in a first group, and the USB interfaces in the first group are coupled to a first control terminal. Number of electronic devices connected to USB interfaces in a second group is detected, and the USB interfaces in the second group are coupled to a second control terminal. A third group is provided, and USB interfaces therein are switched to be coupled to the first or second control terminal. Number of electronic devices connected to the USB interfaces in the third group is further detected in the invention. The USB interfaces in the third group are determined to be coupled to the first or second control terminal according the numbers of the electronic devices connected to the first, second, and third groups. The working performance of the USB is improved. | 03-26-2009 |
| 20090083469 | INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD AND INFORMATION MANAGEMENT SYSTEM - An information processing device according the invention includes: a first interface used for communication via a network; a second interface used for communication with an information display device; an identifier acquisition unit that acquires an identifier specifying the information display device; an address storage unit that stores an address indicating location of a management device on the network; a mode information acquisition unit that acquires mode information indicating whether an operation mode of the information display device specified by the identifier acquired by the identifier acquisition unit is a server-linked mode or a stand-alone mode; a first transmission unit that transmits a request including a request to transmit management information specifying a content displayed in the information display device and the identifier, to the management device via the first interface when the mode information indicates the server-linked mode; a first receiving unit that receives the management information transmitted from the management device in response to the request transmitted by the first transmission unit, via the first interface; a second transmission unit that transmits a request to transmit the management information, to the information display device via the second interface when the mode information indicates the stand-alone mode; and a second receiving unit that receives the management information transmitted from the information display device in response to the request transmitted by the second transmission unit, via the second interface. | 03-26-2009 |
| 20090089475 | Low latency interface between device driver and network interface card - Methods and apparatus relating to a low latency interface between a device driver and a network interface device are described. In one embodiment, a network interface card (NIC) and a processor may be coupled through a coherent interconnection, e.g., to allow for coherent communication of data between buffers in the NIC and the processor. Other embodiments are also disclosed. | 04-02-2009 |
| 20090089476 | WIRELESS UNIVERSAL SERIAL BUS SYSTEM AND DRIVING METHOD THEREOF - A wireless universal serial bus system (WUSB) includes a device, a first host, and a second host. The first host communicates with the device through a first superframe according to a wireless USB protocol. The first host sets a host-adding bit in the first superframe when the second host transfers a second superframe to the first host according to the wireless USB protocol to enable communication between the second host and the device. | 04-02-2009 |
| 20090094397 | HOST CONTROLLER DEVICE AND DATA TRANSFER CONTROL METHOD - Data transfer efficiency has been unsatisfactorily decreased in host controller devices for USBs because of the fact that they must read out a loop of endpoint information including endpoint information that do not contribute to data transfer in a successive manner. In accordance with one embodiment of the present invention, a host controller device installed in a host device having a system memory | 04-09-2009 |
| 20090094398 | CENTRALIZED BUS INTERFACE WITH SINGLE WIRE SECONDARY DISTRIBUTION - A system for single wire secondary distribution comprising a spacecraft platform; a central bus interface unit coupled to the spacecraft platform; a payload unit coupled to the central bus interface unit; and a centralized power supply for powering the central bus interface unit and the payload unit; wherein the spacecraft platform provides a command to the central bus interface unit; wherein the central bus interface unit interrupts the power to the payload unit in a manner corresponding to the commands received by the central bus interface unit; wherein the payload unit decodes the interruption to the power and executes the command from the spacecraft platform. | 04-09-2009 |
| 20090106472 | Virtual SATA port multiplier, virtual SATA device, SATA system and data transfer method in a SATA system - A virtual SATA port multiplier and a virtual SATA device are provided for a SATA system. The virtual SATA port multiplier uses a SATA physical layer for data transfer between it and a SATA host, and a non-physical layer for direct data transfer between it and the virtual SATA device. Since the data transfer between the virtual SATA port multiplier and the virtual SATA device is not carried out by way of SATA physical layers, no physical layer circuits are required accordingly, thereby reducing the manufacturing cost, power consumption and hardware size of the SATA system. | 04-23-2009 |
| 20090113107 | DIFFERENTIAL TRANSMITTER CIRCUIT - A driver circuit is configured as a frequency compensated differential amplifier having one input coupled to a first data signal and a second input coupled to a second data signal. Each stage of the differential amplifier is biased with a current source. The driver circuit generates a first output signal coupled to the input of a first transmission line and a second output signal coupled to the input of a second transmission line. The first and second output signals are generated as the difference between the first and second data signals amplified by a compensated gain. A compensation network that attenuates the low frequency components of the input signals relative to the high frequency components is coupled between current sources biasing the differential amplifier. The outputs of the first and second transmission lines are coupled to the inputs of a differential receiver that may or may not be frequency compensated. | 04-30-2009 |
| 20090119437 | Method for Data Communication of Bus Users in an Open Automation System - A method for data communication of bus users of an open automation system such that any bus user with an individual and interactive communication may be connected, provides for a communication controller (KC) made up of at least one freely-programmable communication-ALU (RPA, TPA, PEA), with several commands being encoded on a command code for the communication-ALU optimized for particular communication functions, and logic function blocks (FI, Z, V, CRC) arranged in parallel in the communication ALU (RPA, TPA), which carry out particular communication functions, the communication functions not being definitively defined but rather being formed on the basis of the freely-programmable and communication function optimized communication ALUs (RPA, TPA, PEA), wherein several commands are carried out in a system cycle and transitions between various networks can be carried out. | 05-07-2009 |
| 20090125663 | Interface arrangement, especially for a system on a chip, and use thereof - An interface arrangement ( | 05-14-2009 |
| 20090125664 | SYSTEM CONTROLLER - A system LSI section | 05-14-2009 |
| 20090132747 | STRUCTURE FOR UNIVERSAL PERIPHERAL PROCESSOR SYSTEM FOR SOC ENVIRONMENTS ON AN INTEGRATED CIRCUIT - A design structure including universal peripheral processor architecture on an integrated circuit (IC) includes first and second data buses coupled to interface logic devices for enabling communication between the first and second data buses including enabling interface of multiple signaling protocols. One or more processors communicate with the first and second data buses to manage control functions on the IC. A data path enables transfer of data between the first and second data buses, and communicates with data storage devices. A data control path enables communication between the data storage devices and the processors. | 05-21-2009 |
| 20090144478 | PERFORMANCE BASED PACKET ORDERING IN A PCI EXPRESS BUS - A communications arrangement is implemented for packet data communications control. According to an example embodiment of the present invention, a communications arrangement ( | 06-04-2009 |
| 20090150591 | VIDEO COMMUNICATION NETWORK-COMPUTER INTERFACE DEVICE - The interface device is interposed between a switched-packet network and the bus of a computer. The interface device de-packets and de-compresses HD video data from the network, and places the de-packeted and de-compressed HD video data stream on the computer bus, ready for display. The interface device also compresses and packets HD video data from a video source and transmits the compressed and packetized HD video data to a packet network. The operations involving manipulation of the video data, including the packeting/de-packeting and compressing/de-compressing operations, are done, in the interface device, by hardware. The interface device enables an under-four GHz PC to carry out real-time two-way HD video communications. | 06-11-2009 |
| 20090157937 | Modular Data Transmission System with Separate Energy Supply for Each Connected Module - The invention pertains to a modular data transmission system ( | 06-18-2009 |
| 20090164689 | Early response indication for data retrieval in a multi-processor computing system - A data processing system is described that reduces read latency of requested memory data, thereby resulting in improved system performance. An exemplary system includes a bus, a processor, and a controller associated with the processor. The controller is configured to send a request for data to a memory storage unit, receive, from the memory storage unit, an early response indicating that the controller will later receive the requested data, and upon receipt of the early response indicator, start a timer to wait a period of time. The controller is further configured to, after expiration of the timer but prior to receipt of the requested data, send an arbitration request to initiate a transaction on the bus to communicate the requested data from the controller to the processor when the requested data is later received by the controller. | 06-25-2009 |
| 20090172237 | Scalable Distributed Routing Scheme for PCI Express Switches - A Peripheral Component Interconnect (PCI) Express switch is provided. The PCI Express switch includes a first routing information bus connected to the first port; a second routing information bus connected to the second port; a third routing information bus connected to the third port; two routing slaves in the first port, each dedicated to listening to one of the second and the third routing information buses; two routing slaves in the second port, each dedicated to listening to one of the first and the third routing information buses; and two routing slaves in the third port, each dedicated to listening to one of the first and the second routing information buses. | 07-02-2009 |
| 20090193169 | Interface adapter - Field devices for measuring a pressure or a fill level are connected, by way of a cable connection or a radio connection, to stationary evaluation- and display devices. A parameterization- and data recording system for a field device is stated, which system may make it possible to maintain fast and flexible communication between field devices and a mobile control device. The system comprises a connection box and an interface adapter, which converts a HART signal or an I | 07-30-2009 |
| 20090198856 | GATEWAY FOR A DATA BUS SYSTEM - The invention is related to a Gateway for a data bus system, especially a CAN-Bus-system, with at least two data bus source channels, the gateway being provided with—an interface for each data bus source channel, —a protocol core in each channel interface, —a channel message switch, whose inputs are coupled to the outputs of the protocol cores of the channel interfaces and whose output can be switched to one of its inputs, —a message handler coupled to the output of the channel message switch and being provided with a message filter for selecting messages and with a message buffer, —a channel interface with a protocol core coupled to a data bus target channel, —a control, that, in a diagnostic copy function, copies all the messages from a selectable source channel to the message handler by setting the channel message switch to the position assigned to the selected source channel and that causes the message filter to couple the filtered messages to the interface of the target channel. | 08-06-2009 |
| 20090210600 | MEMORY DEVICE WITH NETWORK ON CHIP METHODS, APPARATUS, AND SYSTEMS - Apparatus, method and systems are provided such as those that can include a processor module, an interface device disposed above or below the processor module, the interface device including a plurality of routing elements, at least one memory device disposed above or below the interface device and including a plurality of memory arrays, the plurality of memory arrays coupled to the interface device using a plurality of interconnects provided in vias provided in at least one of the memory device and the interface device. In addition, the interface device communicatively can couple the plurality of memory arrays to the processor module using the plurality of routing elements and the interconnects. | 08-20-2009 |
| 20090210601 | SYSTEMS AND METHODS FOR PROVIDING A VIRTUAL NETWORK INTERFACE CONNECTION ("NIC") WITH THE BASEBOARD MANAGEMENT CONTROLLER ("BMC") - Systems and methods for transferring Ethernet packets from an operating system to a baseboard management controller (“BMC”) have been provided. The operating system is typically stored in a memory. A method according to the invention may include tagging predetermined Ethernet packets for transfer from the operating system to the BMC. The method may also include transferring the tagged Ethernet packets from the operating system to a Local Area Network On Motherboard (LOM). The method may include transferring the tagged Ethernet packets from the LOM to the BMC. | 08-20-2009 |
| 20090210602 | MODIFYING PERIODIC SIGNALS PRODUCED BY MICROCONTROLLER - Multiple modules are connected to a signal output module via first and second busses. Different commands may be transmitted on the two busses. Both busses may be hierarchically constructed so that all units are connected one after the other in a chain like manner on the busses. The modules cooperate to transition an output signal between different duty cycles and activate and deactivate responsive to timer comparisons. | 08-20-2009 |
| 20090210603 | Flash memory circuit with combinational interface - A flash memory circuit has both SATA and USB interfaces. When the flash memory circuit is coupled to a computer, the flash memory circuit utilizes the transmitted power from the computer through the USB interface for operating, and communicates with the computer through the faster SATA interface for data accessing of the flash memory. | 08-20-2009 |
| 20090210604 | Memory Module Having Signal Lines Configured for Sequential Arrival of Signals at Synchronous Memory Devices - A memory module includes a first signal line to carry a first signal. The first signal line has (i) a first line segment disposed along a length of the memory module and coupled to a termination, and (ii) a second line segment disposed along a width of the memory module and coupled to an edge finger. The first line segment and the second line segment are coupled together at a turn. A first synchronous memory device and a second synchronous memory device are coupled to the first line segment. The first signal arrives at the first synchronous memory device and the second synchronous memory device in a sequential manner. The memory module includes a clock line routed alongside the first signal line. A clock signal arrives at the first synchronous memory device and the second synchronous memory device in sequence alongside the first signal traversing along the first signal line. | 08-20-2009 |
| 20090248940 | Information Handling System Including A Plurality Of Multiple Compute Element SMP Processors With Primary And Secondary Interconnect Trunks - An integrated circuit (IC) processor chip apparatus includes multiple processor chips on a substrate. At least one of the multiple processor chips includes a die with a primary interconnect trunk for communication of information between multiple compute elements situated along the primary interconnect trunk. That multiple processor chip includes a secondary interconnected trunk that may be oriented perpendicular with respect to the primary interconnect trunk. The secondary interconnect trunk communicates information off-chip via a number of I/O interfaces at the perimeter of that multiple processor chip. The I/O interfaces may be distributed uniformly along portions of the perimeter of that multiple processor chip. | 10-01-2009 |
| 20090254691 | MICROCONTROLLER WAVEFORM GENERATION - One embodiment of the present invention is a microcontroller ( | 10-08-2009 |
| 20090265498 | Multiphase Clocking Systems with Ring Bus Architecture - Systems and methods for transferring data using a ring bus architecture in a system that implements multi-phase clocking. In one embodiment, the system is a multiprocessor having multiple processor cores coupled to the ring bus. The bus may be a bidirectional bus having a first data path on which data is transferred in a clockwise direction and a second data path on which data is transferred in a counterclockwise direction. Controllers within the processor cores provide phase-shifted signals to the latches to clock data into them. Data transfers on the bus may be controlled by an arbiter which is coupled to the processor cores' controllers. The arbiter may schedule data transfers on the bus based on data transfer speeds associated with left-to-right and right-to-left data transfer directions. The arbiter may cause the phases of the clock signals to be selectively varied, or may cause the clock signals to be gated. | 10-22-2009 |
| 20090265499 | MULTI-PROTOCOL SERIAL INTERFACE SYSTEM - A multi-protocol serial interface system comprises a multi-protocol port pin array, a transport protocol change FPGA, a pull-up change FPGA and a memory. The multi-protocol port pin array comprises a plurality of port pins which interface with an external system for exchanging data with the external system. The transport protocol change FPGA determines roles of port pins of the multi-protocol port pin array depending on a variably changed protocol by selecting one of the plurality of programmed transport protocol circuits in response to code data. The pull-up change FPGA regulates pull-up load of the port pins corresponding to the roles of the port pins determined in the transport protocol change FPGA. The memory stores data processed in the transport protocol change FPGA unit and exchanged with the external system. | 10-22-2009 |
| 20090271553 | METHOD AND APPARATUS FOR OBTAINING TRACE INFORMATION OF MULTIPLE PROCESSORS ON AN SOC USING A SEGMENTED TRACE RING BUS TO ENABLE A FLEXIBLE TRACE OUTPUT CONFIGURATION - An integrated bus architecture for transmitting trace information from a plurality of processors included on an integrated chip having one or more peripheral I/O channels comprises a segmented bus having a plurality of segments arranged in a ring topology and configured to transmit trace information in a circular pathway from upstream segments to downstream segments, and one or more trace output circuits each connected to a respective segment and each including a switch configured to be dynamically toggled between enabled and disabled states. The plurality of segments includes a respective segment for each processor having a coupling unit connected to a trace port of the processor. The coupling unit is configured to receive trace information from the trace port, to receive trace information from the adjacent upstream segment, and to transmit items of trace information to the adjacent downstream segment. Each trace output circuit is configured to transmit trace information to a respective peripheral I/O channel when in the enabled state. Each trace output circuit is configured to transmit trace information to the adjacent downstream segment when in the disabled state. | 10-29-2009 |
| 20090271554 | Method and apparatus for data movement in a system on a chip - There is provided a system for comprising a plurality of blocks, each block comprising any hardware element and a plurality of segments for providing interconnection of the plurality of blocks. A segment comprises a connector between multiple blocks and other segments and segments are connected via the ports of blocks or other segments. Communications between blocks is packet based, each packet including at least a destination block. The packet includes at least one of data, packet/message identification and padding. Blocks have an associated address. A block has one or more input ports and one or more output ports. Segments include means for routing packets to destinations. Each block and segment includes properties. Properties include one or more of clocks, bandwidth, bit widths, and latencies. The plurality of segments for multiple packets to be active on different segments. A single segment includes a plurality of ports for multiple packets to be active on different ports of the segment. | 10-29-2009 |
| 20090276556 | MEMORY CONTROLLER AND METHOD FOR WRITING A DATA PACKET TO OR READING A DATA PACKET FROM A MEMORY - A memory controller and a method for data access are provided. The memory controller writes a data packet to or reads a data packet from a memory. The memory controller comprises a first register, a second register, a data packet adjuster, and a burst length determination unit. The first register stores a data bus width. The second register stores an operating frequency of the memory controller. The burst length determination unit determines a burst length according to the operating frequency. The data packet adjuster adjusts the data packet according to the data bus width and the burst length. | 11-05-2009 |
| 20090282181 | DATA PIPELINE MANAGEMENT SYSTEM AND METHOD FOR USING THE SYSTEM - The present invention relates to a data pipeline management system and more particularly to a minimum memory solution for unidirectional data pipeline management in a situation where both the Producer and Consumer need asynchronous access to the pipeline, data is non-atomic, and only the last complete (and validated) received message is relevant and once a data read from/write to the pipeline is initiated, that data must be completely processed. The data pipeline management system according to the invention can be implemented as a circular queue of as little as three entries and an additional handshake mechanism, implemented as a set of indices that can fit in a minimum of six bits (2×2+2×1). Both the Producer and Consumer will have a 2 bit index indicating where they are in the queue, and a 1 bit binary value indicating a special situation. Both parties can read all the indices but can only write their own, i.e. P and wrapP for the Producer and C and wrapC for the Consumer. For management of the handshakes a set of rules is provided. | 11-12-2009 |
| 20090300254 | Method for Connecting a Flexray user having a Microcontroller to a Flexray Communications line Via a Flexray Communications Control Device, and Flexray Communications Control Device, Flexray User, and Flexray Communications System for Realizing this Method - A method for connecting a FlexRay user having a microcontroller, which includes at least one serial interface, to a FlexRay communications link via a FlexRay communications control device having at least one serial hardware interface, the connection between the user and the communications control device being implemented via serial interfaces. To make it possible to connect the user to the communications controller via a serial interface without restricting its functionality, it is provided that at least one serial interface is emulated in the user, or that at least one additional serial interface is developed in the FlexRay communications control device. | 12-03-2009 |
| 20090300255 | SHIELDING OF DATALINES WITH PHYSICAL PLACEMENT BASED ON TIME STAGGERED ACCESS - A bus driver circuit divides an internal data bus for an integrated circuit memory into at least two groups, designated by speed. A faster group of data lines and a slower group of data lines are placed in an interleaved fashion in order to provide a two group shielding solution. At the earliest opportunity following the reception of a read command, the data from memory banks in the memory is sorted into these two groups. For a DDR3 memory, the sorting method is based on the A2 column address, known as C2. All of the data is brought out of the banks in parallel and sorted as it enters the main amplifiers. These main amplifiers are also divided into two groups, faster and slower. Each amplifier then connects to a data line (G-line) of the same group. The clock assigned to the fast group fires right away, thereby connecting the data associated with the fast amplifiers to the fast data group. This data group then proceeds to the output buffers through the entire data path as fast as possible. The second, slower data group is started with a delayed clock signal and proceeds through the data path to the output buffer maintaining a fixed delay. Since the first and second data groups are not switching at the same time they act as shields to one another. | 12-03-2009 |
| 20090307405 | Electropneumatic Module System Composed of Individual Modules Put in a Row - A modular system comprises a head module having at least one connection for an external bus signal on an external bus, at least one pneumatic supply connection, an electric supply connection and having a serial bus interface for an internal serial bus, an electric supply interface, a multipole interface and a pneumatic supply interface which are each led to the outside on the same side. The modular system further comprises at least one functional module having an internal serial bus line, electric supply lines, electric multipole lines and pneumatic supply lines which are each passed through from one side to the opposite side and which are each connected to a corresponding interface of the head module. The head module here converts serial bus signals into multipole signals and outputs these signals at the multipole interface. The functional module selectively branches at least one of the multipole lines and, with a signal carried thereon, executes a pneumatic or an electric or both a pneumatic and an electric function. | 12-10-2009 |
| 20090327562 | Implementing Bus Interface Calibration for Enhanced Bus Interface Initialization Time - A method and apparatus are provided for implementing bus interface calibration to improve bus interface initialization time in a system. Bus interface calibration is performed and average calibration values are saved. At bus interface initialization time, checking for saved calibration values is performed. The saved calibration values are used and tested. When the saved calibration values pass the test, then the saved calibration values are used for system operation without performing any training steps. | 12-31-2009 |
| 20090327563 | CONNECTING BETWEEN DATA-HANDLING CIRCUITS OF AN INTEGRATED CIRCUIT - Device, system and method of connecting between data-handling circuits of an integrated circuit. For example, an integrated circuit includes a plurality of data-handling circuits; and a circuit-interconnect topology including at least one store-and-forward circuit along at least one connection path between at least a first and a second of the plurality of data-handling circuits. Other embodiments are described and claimed. | 12-31-2009 |
| 20090327564 | Method and apparatus of implementing control and status registers using coherent system memory - In some embodiments control and status registers of a coherent Input/Output device coupled to a host system bus are mapped to a system memory. Direct memory access is provided to the memory mapped control and status registers in the system memory by a CPU that is coupled to the host system bus. Other embodiments are described and claimed. | 12-31-2009 |
| 20090327565 | BIMODAL MEMORY CONTROLLER - A memory controller has a communication path which is coupled to an external, wired electrical path. The memory controller includes at least two alternative interface circuits to communicate with the external, wired electrical path using signals having one of two different formats. Each of the alternative interface circuits is electrically coupled to a corresponding signal connector, and only one of these signal connectors, in turn, is electrically coupled to the external path via an I/O pin or printed-circuit board connection (depending upon implementation). The remaining signal connector may be left electrically uncoupled from the external, wired electrical path, and, if desired, the corresponding remaining interface circuit may be left unused during operation of the memory controller. | 12-31-2009 |
| 20090327566 | Storage Router and Method for Providing Virtual Local Storage - A storage router ( | 12-31-2009 |
| 20100011144 | DEVICE FOR DETECTING INTERRUPTIONS IN A RING BUS - A device for detecting interruptions in a ring bus has a first interface configured so that it permits connection of a first free end of a line of the ring bus so that the device transmits data to bus elements of the ring bus via the first interface, a second interface configured so that it permits connection of the second free end of the line of the ring bus, and the device detects a creeping interruption of the line of the ring bus. | 01-14-2010 |
| 20100030940 | DEVICE AND METHOD FOR SCHEDULING TRANSACTIONS OVER A DEEP PIPELINED COMPONENT - A device and a method, the device has transaction scheduling capabilities, and includes: (i) a memory unit adapted to output data at a first data rate, (ii) a data transaction initiator adapted to receive data at a second data rate that is lower than the first data rate; (iii) a deep pipelined crossbar characterized by a latency; and (iv) a data rate converter connected between the deep pipelined crossbar and the data transaction initiator; wherein the data rate converter is adapted to schedule a transaction of data unit from the memory unit in response to the latency of the deep pipelined crossbar, the first data rate, the second data rate, and size of an available storage space, within the data rate converter allocated for storing data from the memory unit. | 02-04-2010 |
| 20100036992 | USB and Ethernet Controller Combination Device - A USB-to-Ethernet controller with a USB hub may be integrated into a single integrated circuit (IC) USB-Ethernet Combination (UEC) device. The UEC may provide the end user with an Ethernet port, multiple downstream USB ports, and an upstream USB port for connecting to a USB host controller. One or more of the USB hub ports may be brought off the IC, enabling an end user to connect them to any arbitrary USB device(s). The third hub port may be an internal downstream port without a physical layer, and may be configured to connect to an Ethernet controller, which may comprise a USB device controller. The Ethernet controller may connect to the internal downstream port via a digital interface such as UTMI. The UEC device may appear to the host computer as two separate devices, an Ethernet controller and a USB hub. The Ethernet controller may appear as a permanently attached device on the internal downstream port. | 02-11-2010 |
| 20100049894 | DATA BACKUP TRANSMITTER - A data backup transmitter includes a body, a first connecting port and a second connecting port. The first and the second connecting ports are connected to the body. A data backup assembly is electrically connected between the first and the second connecting ports. The data backup assembly has a backup chip for controlling a backup process between the first and the second connecting ports. Thus, the first and second connecting ports are inserted into a computing device and a data-transmitting carrier respectively. A control button is used to control the backup chip to execute the signal transmission and data backup between the computing device and the data-transmitting carrier. | 02-25-2010 |
| 20100057970 | METHOD AND APPARATUS TO COMBINE POWER AND CONTROL SIGNALS IN A MOBILE COMPUTING DEVICE - A mobile computing device is described that includes multiple device components, a power supply and a power line connected to each device component. The power supply is operative to provide power signals to the device components over the power lines. The mobile computing device also includes a processor operative to generate a control signal for one or more device components. A power line communications control module is connected to the power supply and the processor, the power line communications control module is operative to receive a power signal and a control signal for a device component, combine the power signal and control data from the control signal to form a power data signal, and send the power data signal to the device component over a corresponding power line. Other embodiments are described and claimed. | 03-04-2010 |
| 20100057971 | Multi-Mode Bus Inversion Method and Apparatus - In one embodiment, an integrated circuit comprises circuitry for performing bus inversion. The circuitry is operable to configure the integrated circuit to implement one of a plurality of bus inversion schemes each of which the integrated circuit is capable of performing. The circuitry is also operable to process data input to and output from the integrated circuit based on the bus inversion scheme for which the integrated circuit is configured. | 03-04-2010 |
| 20100057972 | VIDEO DATA TRANSMISSION VIA USB INTERFACE - The invention relates to a method for the transmission of video data from a data source to a data sink, wherein the transmission is carried out via a USB interface, wherein the information transmitted via the USB interface represents the digital values of a YUV signal, wherein the digital values of the YUV signal are fed to a video encoder, particularly in the form of a video DAC, in the data sink. | 03-04-2010 |
| 20100064088 | HIGH SPEED TRANSIENT ACTIVE PULL-UP I2C | 03-11-2010 |
| 20100070671 | METHOD AND DEVICE FOR PROCESSING DATA - In a system including a multidimensional field of reconfigurable elements, and a method for operating said field of reconfigurable elements, one or more groups of said elements suitable for processing a predetermined task may be determined, a particular one of the one or more groups is selected, and the selected group is configured in a predetermined manner during runtime for processing the predetermined task, and in manufacturing of said system. | 03-18-2010 |
| 20100077123 | INTEGRATED TRANSMISSION CIRCUIT AND METHOD - An integrated transmission circuit and method for transmitting output data to a chipset via a transmission interface are provided. The integrated transmission circuit includes a first application circuit, a second application circuit, a media access control (MAC) circuit, and a physical layer (PHY) circuit. The first application circuit is used for receiving and processing first data to output first processed data. The second application circuit is used for receiving and processing second data to output second processed data. The MAC circuit is coupled to the first application circuit and the second application circuit, and used for encoding the first processed data and the second processed data so as to output encoded data. The PHY circuit is coupled to the MAC circuit to receive the encoded data so as to output the output data to the transmission interface. | 03-25-2010 |
| 20100077124 | METHOD AND CONTROL UNIT FOR ELECTRONIC CONTROL AND FEEDBACK CONTROL - The present invention relates to a method for electronic control and/or feedback control. In this system, the sequence for execution of a statement within a control unit is simplified, the flexibility and adaptability of the control unit are enhanced and the potential achievement of an enhanced computing speed is increased, by means of the provision that in this method a plurality of input registers ( | 03-25-2010 |
| 20100082869 | STACKABLE I/O MODULES APPEARING AS STANDARD USB MASS STORAGE DEVICES - An industrial automation device is provided that includes a universal serial bus interface and an I/O module coupled to the industrial automation device via the universal serial bus interface, wherein the I/O module is configured to connect as one of a plurality of universal serial bus device classes. An I/O module is provided that includes a plurality of inputs, a plurality of outputs, a universal serial bus connection configured to couple to the industrial automation device, a memory configured to store one of a plurality of universal serial bus device class information. A method for connecting the I/O module to the industrial automation device is also provided. | 04-01-2010 |
| 20100082870 | Tape-form communication sheet and information processing device using the tape-form - It is an object to provide a transmission system that is more suitable for transmission of a large volume of data than a cable or an optical fiber is and capable of coupling a transmission path and an electronic device easily without using a connector. A tape-form communication sheet is configured by a sheet body, plural coupling nodes regularly arranged in line and fitted in the sheet body, and a signal transmission wiring, wherein an interface of a computer having the interface similar to this coupling node is connected to the coupling node of the tape-form communication sheet for transmitting a signal. The coupling nodes are configured by an arrayed antenna and a communication circuit unit including a signal In/Out unit, a memory, a signal reception/output unit, and a CPU connected to the signal In/Out unit, the memory, and the signal reception/output unit, wherein the signal transmission wiring is connected to the signal In/Out unit of the respective coupling nodes. | 04-01-2010 |
| 20100082871 | Distributed Command and Address Bus Architecture - Distributed command and address bus architecture for memory modules and circuit boards is described. In one embodiment, a memory module includes a plurality of connector pins disposed on an edge of a circuit board, the plurality of connector pins comprising first pins coupled to a plurality of data bus lines, second pins coupled to a plurality of command and address bus lines, wherein the second pins are disposed in a first and a second region, wherein a portion of the first pins is disposed between the first and the second regions. | 04-01-2010 |
| 20100088451 | ARCHITECTURE VERIFYING APPARATUS, ARCHITECTURE VERIFYING METHOD, AND MEDIUM STORING ARCHITECTURE VERIFYING PROGRAM - An architecture verifying apparatus includes an inputting unit receiving limitation information, a bus monitor monitoring a bus transaction to obtain bus transaction information, a module monitor monitoring a reception transaction, processing, and a transmission transaction to obtain reception transaction information, processing information, and transmission transaction information, an architecture information generator associating the limitation information and the bus transaction information with the reception transaction information, the processing information, and the transmission transaction information to generate architecture information, and an outputting unit supplying the architecture information. | 04-08-2010 |
| 20100106879 | METHOD AND SYSTEM FOR CONTROLLING VIDEO SELECTION AND PLAYBACK IN A PORTABLE MEDIA PLAYER - A method and system in accordance with the present invention provides a system that allows a portable media player to control settings of portable media player when receiving video from an accessory, to control playback of the portable media player and to provide for navigation between video tracks in a hierarchical fashion. In so doing, a portable media player can then utilize this information to provide for the maximum functionality of the accessory when connected to the portable media player. | 04-29-2010 |
| 20100125693 | Memory module for improving signal integrity and computer system having the same - A memory module includes a plurality of buses and a plurality of memory chips arranged close to each other along each of the plurality of buses. An N-th memory chip, where N is an integer, of the plurality of memory chips is connected to any one of the plurality of buses, and each of the other memory chips of the plurality of memory chips, except for the N-th memory chip, is connected to the other one of the plurality of buses. | 05-20-2010 |
| 20100146182 | Field bus system - Field bus system, comprising (i) at least one field bus module with a connection unit for the connection to a network, wherein a control unit can be connected to the network and the at least one field bus module can be addressed in the network, and with a plurality of ports for the connection of field devices, in particular sensors and/or actuators, and (ii) at least one address connector which has a non-volatile memory for an address, wherein the at least one field bus module has an address port for the at least one address connector and the address of the at least one address connector in the network is communicated to the field bus module via its connection. | 06-10-2010 |
| 20100146183 | METHOD AND SYSTEM FOR ENHANCED INTERCONNECTIVITY IN VESSEL COMPUTERS - Apparatus and methods are provided for alleviating processing requirements of a central computer in a vessel. Each apparatus is placed in close proximity to one or more pieces of electronic equipment implementing a legacy interface. The apparatus processes data to and from the electronic equipment, including converting data to formats consistent with the formats used by the intended recipient. | 06-10-2010 |
| 20100146184 | CABIN TELECOMMUNICATION UNIT - A cabin telecommunications unit that provides combined telephone and entertainment/information services onboard an aircraft. The includes a central data bus for exchanging data between components of the cabin telecommunication unit; a first processor connected to said central data bus for processing a communication received by the cabin telecommunication unit and directing the communication to a destination point within the cabin; and a second processor connected to said central data bus for processing and responding to requests for data stored within said cabin telecommunications unit. | 06-10-2010 |
| 20100161866 | LOGIC CONTROLLER HAVING HARD-CODED CONTROL LOGIC AND PROGRAMMABLE OVERRIDE CONTROL STORE ENTRIES - Control logic of a node controller receives an input vector and produces an output vector. The control logic includes a plurality of tied control store entries including hard-coded logic to identify unique values of the input vector and to produce the output vector from a hard-coded output vector when the input vector is identified and when the tied control store is enabled. The control logic also includes a plurality of spare control store entries including programmable logic configurable to identify values of the input vector and to produce the output vector from a programmable output vector when the input vector is identified and when the spare control store is enabled. One of the spare control store entries that is configured to identify a value of the input vector that none of the tied control store entries that are enabled by the entry-enables register arc configured to identify is enabled. | 06-24-2010 |
| 20100161867 | SYSTEM AND METHOD FOR DISTRIBUTING SIGNAL WITH EFFICIENCY OVER MICROPROCESSOR - A system and associated method for distributing signals with efficiency over a microprocessor. A performance monitoring unit (PMU) sends configuration signals to a unit to monitor an event occurring on the unit. The unit is attached to a configuration bus and an event bus that are daisy-chained from PMU to other units in the microprocessor. The configuration bus transmits configuration signals from the PMU to the unit to set the unit to report the event. The unit sends event signals to the PMU through the event bus. The unit is configured upon receiving configuration signals comprising a base address of a bus ramp of the unit. A number of units and a number of events for monitoring is flexibly selected by adjusting a length of bit fields within configuration signals. | 06-24-2010 |
| 20100191890 | Globally Unique Transaction Identifiers - In one embodiment of the present invention, a method includes identifying a transaction from a first processor to a second processor of a system with a transaction identifier. The transaction identifier may have a value that is less than or equal to a maximum number of outstanding transactions between the two processors. In such manner, a transaction field for the transaction identifier may be limited to n bits, where the maximum number of outstanding transactions is less than or equal to 2 | 07-29-2010 |
| 20100199012 | System for connecting an external device to a serial flexray data bus - A system for connecting an external device to a serial FlexRay data bus using which data are transmitted over two data lines as a voltage difference signal, the external device being decoupled from the serial FlexRay data bus by an active star circuit to preserve the signal integrity of the voltage difference signal. | 08-05-2010 |
| 20100199013 | System and Method for Coupling a LTH HH Tape Device with a Serial Attached SCSI Connection to a SAS-Cable - A method, system and apparatus for efficiency coupling a LTO HH tape drive device having a Serial Attached SCSI connector to a SAS-Cable. The method for coupling a LTO HH tape drive device having a Serial Attached SCSI connector to a SAS-Cable includes employing an adapter having a structure featuring an offset between the centerlines of the LTO side and the SAS-Cable side. The method also includes reducing the overmold structure of the adapter on the SAS Cable Side of the adapter to prevent interference from excess structure contained on the connector during the insertion of the SAS Cable as well as enhancing the overmold structure of the adapter on the LTO drive side of the adapter to facilitate a secure grip on the adapter. The method further includes offsetting the centerlines of the LTO side and the SAS-Cable side to enhance the applicability of the adapter to a wide range of SAS-Cables and guiding the insertion of the adapter into a LTO drive via insertion guide pins to prevent the damage to the adapter pins on the LTO drive side of the adapter. | 08-05-2010 |
| 20100205343 | Generating interface adjustment signals in a device-to-device interconnection system - Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment circuits. | 08-12-2010 |
| 20100223413 | Data tranmission system and method - A system and method are provided for transmission of data bits across a data bus. To reduce power usage, noise, or some combination of the two, the data bus utilizes differential transmission using a three level signal in which a reference signal signifies no difference between input bits. Before the signals are transmitted an analysis is made to choose which one of a set of predetermined polarity reversal combinations is advantageous to encode the data bits. The data bits are so encoded and a formatting value F associated with the chosen polarity reversal is differentially transmitted with the encoded bits over the data bus. The three level differential signal is received at the far end of the bus, the encoded bits are recovered and decoded with use of F. The system and method achieves up to N bits transmitted per N data lines. | 09-02-2010 |
| 20100223414 | DATA TRANSFER COHERENCY DEVICE AND METHODS THEREOF - Methods and a device for performing coherent access requests are disclosed. The methods include receiving a first address associated with a first write or read request. During a write operation, if the first address is associated with a coherent access register, data to be written is stored at a data latch that is connected to a plurality of coherent data access registers. A second address and second data associated with a second write request are received. If the second address matches the first address, the second data and the latched first data are written to the coherent access register. By latching the first data and simultaneously writing the latched first data and the second data, overall coherency of the written data is maintained. | 09-02-2010 |
| 20100228901 | INPUT OUTPUT CONTROL APPARATUS WITH A PLURALITY OF PORTS AND SINGLE PROTOCOL PROCESSING CIRCUIT - The input output control device is provided with a plurality of fibre channel interface circuits and a protocol processing circuit capable of sequentially executing the protocol processing of each port, and is provided with a reception port identification register capable of identifying the port handling data to be received and a transmission port designation register designating the port handling data to be transmitted. In addition, it is possible to provide a controller using jointly the data buffers concerned with the plurality of ports. Control of a plurality of fibre channel interfaces with a low component count is possible, as is also the provision of an input output control device making an adequate capacity distribution with respect to the protocol processing between the plural fibre channel interfaces. | 09-09-2010 |
| 20100241780 | Spin-bus for information transfer in quantum computing - A spin bus quantum computing architecture includes a spin bus formed of multiple strongly coupled and always on qubits that define a string of spin qubits. A plurality of information bearing qubits are disposed adjacent a qubit of the spin bus. Electrodes are formed to the information bearing qubits and the spin bus qubits to allow control of the establishment and breaking of coupling between qubits to allow control of the establishment and breaking of coupling between each information bearing qubit and the spin bus qubit adjacent to it. The spin bus architecture allows rapid and reliable long-range coupling of qubits. | 09-23-2010 |
| 20100250819 | HIERARCHICAL MEMORY ARCHITECTURE USING A CONCENTRATOR DEVICE - A hierarchical memory storage using a concentrator device that is located between a processor and memory devices. The concentrator device includes a page buffer, a Phase-Change Memory (PCM) memory array, and a configurable Error-Correcting Code (ECC) engine to accommodate temporary storage for data transfers between the processor and the memory devices. | 09-30-2010 |
| 20100250820 | USB ISOLATOR WITH ADVANCED CONTROL FEATURES - A USB-based isolator system conveys USB signals between a pair of galvanically isolated circuit systems and supports controlled enumeration by a downstream device on upstream USB signal lines. The isolator system provides a multi-mode voltage regulator to support multiple voltage supply configurations. The isolator system further provides control systems for each of the isolated circuit systems and provides robust control in a variety of start up conditions. Additionally, the isolator system includes refresh timers and watchdog mechanisms to support persistent operation but manage possible communication errors that can arise between the isolated circuit systems. | 09-30-2010 |
| 20100262745 | USB Interface data transmission device and USB interface data communication system - The USB interface data transmission device comprises a USB interface controller unit, a dynamic data transmission unit, a central controller unit, a transmission mode configuration unit, a driver program memory and a data transmission interface. In them: The dynamic data transmission unit includes a data input node and a data output node, wherein the data input node supports the data downloading and the data output node support the data uploading, while when necessary the data input node and the data output node support each other's functions by changing their respective data uploading and downloading functions. In a download mode both the data input node and the data output node support the data downloading operation and in an upload mode both support the data uploading operation. | 10-14-2010 |
| 20100293315 | COMMUNICATION SYSTEM HAVING A CAN BUS AND A METHOD FOR OPERATING SUCH A COMMUNICATION SYSTEM - A communication system having one CAN bus and at least two devices interconnected by the CAN bus is described, at least one of the devices including: i) a CAN controller, which is suitable for transmitting CAN data frames over the CAN bus using a first physical protocol in a first operating mode; ii) an asynchronous serial communication interface unit, which is suitable for transmitting ASC data frames over the CAN bus using a second physical protocol in a second operating mode; iii) a first switching means, which is suitable for switching the first operating mode and the second operating mode depending on at least one agreement in effect between the device and at least one of the other devices; and iv) another switching means, which is suitable for switching the device to a third (restricted) operating mode, which differs from the first operating mode and the second operating mode, for powering up the device. | 11-18-2010 |
| 20100299473 | SERIAL PERIPHERAL INTERFACE AND METHOD FOR DATA TRANSMISSION - A serial peripheral interface of an integrated circuit including multiple pins and a clock pin is provided. The pins are coupled to the integrated circuit for transmitting an instruction, an address or a read out data. The clock pin is coupled to the integrated circuit for inputting multiple timing pulses. The plurality of pins transmit the instruction, the address or the read out data at rising edges, falling edges or both edges of the timing pulses. | 11-25-2010 |
| 20100306437 | METHOD AND APPARATUS TO SELECTIVELY EXTEND AN EMBEDDED MICROPROCESSOR BUS THROUGH A DIFFERENT EXTERNAL BUS - A method and apparatus to selectively extend an embedded microprocessor bus through a different external bus are generally presented. In this regard, an apparatus is introduced comprising a first high speed serializer/deserializer (SERDES) bus internal to an integrated circuit device to couple an embedded microprocessor with an embedded component, a second high speed SERDES bus different from the first bus to couple the embedded component with an external interface of the integrated circuit device, and extension circuitry to selectively bypass the embedded component and extend the first bus to function at the external interface over a physical layer of the second bus. Other embodiments are also described and claimed. | 12-02-2010 |
| 20100312939 | INTERCONNECTION NETWORK WITH DYNAMIC SUB-NETWORKS - An interconnection network with m first electronic circuits and n second electronic circuits, comprising m interconnection sub-networks, each comprising: | 12-09-2010 |
| 20100325332 | Systems And Methods Of Communicatively Coupling A Host Computing Device And A Peripheral Device - A method includes providing a bridge device ( | 12-23-2010 |
| 20100332712 | APPARATUSES FOR REGISTER FILE WITH NOVEL BIT CELL IMPLEMENTATION - Approaches to organizing/constructing a register file base cell in a way that reduces the number of signals which need to be routed to and through the bit base cell are disclosed. Base cells so constructed allow industry standard static timing approaches and tools to verify the timing of a register file comprised of such base cells as a whole and allow industry standard place-and-route (APR) tools to be used to implement the connections between the base cells and the other register file logic not directly included in the base cell. | 12-30-2010 |
| 20100332713 | Systems and Methods for Efficient Handling of Data Traffic and Processing Within a Processing Device - The present invention provides an improved platform hub that aims to, in some embodiments, optimize system resources to improve system performance and/or reduce consumption of power. | 12-30-2010 |
| 20110010479 | DATA PROCESSOR AND CONTROL SYSTEM - Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests. | 01-13-2011 |
| 20110022765 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR MAINTAINING A DIRECT CONNECTION BETWEEN AN INITIATOR AND A DRIVE - A system, method, and computer program product are provided for maintaining a direct connection between an initiator and a drive. In operation, a connection is established between an initiator and a drive. Additionally, the connection is determined to be a direct connection between the initiator and the drive. Further, the established direct connection is maintained between the initiator and the drive, such that the established direct connection remains open for information transfer. | 01-27-2011 |
| 20110022766 | Circuit Arrangement For A Motor Vehicle Data Bus - Transmission and/or reception circuit arrangement for the physical implementation of a motor vehicle data bus system and use thereof, wherein the circuit has a plurality of configurable modes of operation which are a different physical implementation of one or more logic states and also comprises electronic bit generation and/or bit reception circuit elements which are used in each mode of operation, wherein changeover and/or structure elements are present which can be used to change over the circuit arrangement between the modes of operation and/or to operate said circuit arrangement in different modes of operation. | 01-27-2011 |
| 20110029709 | Data Movement System and Method - Provided is a method of streaming transfer of data between a plurality of devices of a computer system. The method includes providing data to be sent from a source device to a target device and includes receiving, at the source device, one or more transfer credits from the target device. A transfer credit may be indicative of an amount of data that the target device is authorizing to be sent to the target device. The method also includes determining whether or not an accumulated transfer credit value satisfies a threshold value. If the accumulated transfer credit value satisfies the threshold value, the source device sends data to the target device and modifies the accumulated transfer credit value based on a quantity of data sent. If the accumulated transfer credit value does not satisfy the threshold value the source device does not send data to the target device. | 02-03-2011 |
| 20110040919 | IMAGE FORMING APPARATUS, IMAGE PROCESSING DEVICE, CONTROL DEVICE, AND CONNECTION DEVICE - A disclosed image forming apparatus includes an image processing device including plural image processing units; a control device configured to control the plural image processing units; and a connection unit configured to connect the image processing device to the control device. Each of the plural image processing units is connected to the control device by one of plural channels; the image processing device is connected to the control device by a first bus including the channels; and the connection unit is provided on the first bus so that the image processing device is connected to the control device by a single connection unit. | 02-17-2011 |
| 20110055448 | Method for Data Communication Between a Programmable Controller and a Data Processing Device and Interface Driver Program and Interface Hereto - A method for data communication between a programmable controller ( | 03-03-2011 |
| 20110072183 | INITIATOR AND TARGET FIREWALLS - A system comprising a first logic adapted to use qualifiers received from a component to determine which of a plurality of storages matches the qualifiers, the first logic generates a first signal indicative of a storage matching the qualifiers. The system also comprises a second logic coupled to the first logic and adapted to use a target address received from the component to determine which of the plurality of storages matches the target address, the second logic generates a second signal indicative of a storage matching the target address. Another logic is adapted to determine whether the storage associated with the first signal matches the storage associated with the second signal. The qualifiers indicate security mode attributes associated with the component. | 03-24-2011 |
| 20110078355 | Radio-Control Board For Software-Defined Radio Platform - A radio control board exchanges data with a radio frequency (RF) front end using a messaging protocol over an interface that includes separate data and control channels. Training data can also be passed over the interface for tuning the clock phase. | 03-31-2011 |
| 20110082960 | METHOD OF SERIAL BUS COMMUNICATION AND BUS INTERFACE DEVICE FOR THE SAME - There are provided a serial bus communication method and a bus interface device showing excellent performance when a medium with low conductivity is used. The serial bus communication method includes: retrieving available transmission rate to a destination node to which data will be transmitted from a transmission rate table whenever transmitting data through a bus; setting data rate for transmitting the data to the destination node by using the retrieved available transmission rate when the available transmission rate to the destination node is retrieved in the transmission rate table; and transmitting the data at the data rate. Accordingly, transmission performance is improved on a network using a medium with low conductivity. | 04-07-2011 |
| 20110087819 | Barrier transactions in interconnects - Interconnect circuitry for a data processing apparatus is disclosed. The interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device, said interconnect circuitry comprising: at least one input for receiving transaction requests from said at least one initiator device; at least one output for outputting transaction requests to said at least one recipient device; at least one path for transmitting said transaction requests between said at least one input and said at least one output; control circuitry for routing said received transaction requests from said at least one input to said at least one output; wherein said control circuitry is configured to respond to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths, by not allowing reordering of at least some transactions requests that occur before said barrier transaction request in said stream of transaction requests with respect to at least some transaction requests that occur after said bather transaction request in said stream of transaction requests; wherein said bather transaction request comprising an indicator indicating which of said transaction requests within said stream of transaction requests comprise said at least some transaction requests whose ordering is to be maintained. | 04-14-2011 |
| 20110106998 | Storage Router and Method for Providing Virtual Local Storage - A storage router and method for providing virtual local storage on remote storage devices to devices are provided. A plurality of devices, such as workstations, are connected to a first transport medium, and a plurality of storage devices are connected to a second transport medium. In one embodiment, the storage router maintains a map to allocate storage space on the remote storage devices to devices connected to the first transport medium by associating representations of the devices connected to the first transport medium with representations of storage space on the remote storage devices, wherein each representation of a device connected to the first transport medium is associated with one or more representations of storage space on the remote storage devices and receives and processes native low level block protocol requests from the devices connected to the first transport medium to access allocated storage. | 05-05-2011 |
| 20110106999 | ON-CHIP BUS - This disclosure involves an on-chip bus architecture involving an on-chip bus that includes a collector node and at least one device node. Each device node is in communication with an on-chip device. The collector node is capable of conducting multiple outstanding transactions with a plurality of on-chip devices over the on-chip bus wherein each on-chip device transmits all of its data signals across the on-chip bus in the form of packets. The on-chip bus includes at least one bus register, and each of the multiple on-chip devices includes at least one device register. The on-chip bus can provide top level register to register communications between the device register and the bus register. In one version, the on-chip bus is a distributed packet on-chip (DPO) bus. | 05-05-2011 |
| 20110119424 | SERVER MANAGEMENT SYSTEM - A server management system is provided. The server management system includes a plurality of motherboards, a baseboard, a bus, a first and a second sensor. The baseboard comprises a central control chip to generate a specific instruction. The bus is positioned on the baseboard. The motherboards are connected to the baseboard. Each of the motherboards includes a baseboard management controller (BMC) having an instruction-processing module used to receive the specific instruction through the bus and executes the specific instruction. The first sensor is connected to the central control chip and the second sensor is connected to the BMC. The instruction-processing module retrieves a first state of the first sensor from the central control chip to the BMC and retrieves a second state of the second sensor from the BMC to the central control chip according to the specific instruction. | 05-19-2011 |
| 20110138096 | Methods and Systems for Reliable Link Startup - Link startup systems, methods and devices associated with interconnects are described. Asymmetric lane connections are supported by, for example, independent renumbering of the connected lanes after an initial discovery process. Low-power, hibernating states of devices are supported by, for example, initialing alternating between transmission of startup and wakeup sequences over the interconnect between devices. | 06-09-2011 |
| 20110145467 | INTERCONNECTING COMPUTING MODULES TO FORM AN INTEGRATED SYSTEM - Systems, methods and portable devices are provided for interconnecting one or more computing modules within an enclosure together to form an integrated system. A portable device may include a communication interface configured to be removably coupled to each computing module for interconnecting them together to form the integrated system. A portable device may also include memory configured to store an integrated system personality that serves as a point of authority for each computing module of the integrated system. The integrated system personality may include an identifier of the integrated system. | 06-16-2011 |
| 20110153897 | SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM - The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register. The switching circuit switches between whether a parallel interface with the outside is to be used as a big endian or a little endian. A first register holds control data of the switching circuit. The switching circuit regards the parallel interface as the little endian when first predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register, and regards the parallel interface as the big endian when second predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register. Whatever the endian setting status, the control information can be correctly inputted without being influenced by the endian setting status. | 06-23-2011 |
| 20110161544 | LOW LATENCY SERIAL MEMORY INTERFACE - A device applies synchronous clocking across a first component and a second component of the device, and designates a particular serial link, from a group of serial links, as a master serial link. The device also designates the remaining serial links as slave serial links, provides, via the master serial link, an encoded data stream, and provides, via the slave serial links, un-encoded and scrambled data streams. | 06-30-2011 |
| 20110161545 | I2C/SPI CONTROL INTERFACE CIRCUITRY, INTEGRATED CIRCUIT STRUCTURE, AND BUS STRUCTURE THEREOF | 06-30-2011 |
| 20110167188 | SUBSCRIBER NODE OF A COMMUNICATION SYSTEM HAVING A FUNCTIONALLY SEPARATE TRANSMISSION EVENT MEMORY - A subscriber node of a communication system, a communication system and a method for transmitting a message in the communication system. The message is transmitted from a first subscriber node of the communication system via a data bus of the communication system to a second subscriber node of the communication system. An application program of the first subscriber node files the message, that is to be sent, in a message memory, from where it is retrieved by a communication controller, upon a sending command of the application program, and is transmitted via the data bus. In particular in the case of a cancellation of the transmission job, in order to be able to improve the capacity utilization and the efficiency of a host CPU, it is provided that a transmission event for the message, that is to be sent or that has been sent, is stored in at least one transmission event memory, that is functionally separate from the message memory, and that the application program is able to access the data stored in the event memory at any time. | 07-07-2011 |
| 20110173366 | DISTRIBUTED TRACE USING CENTRAL PERFORMANCE COUNTER MEMORY - A plurality of processing cores, are central storage unit having at least memory connected in a daisy chain manner, forming a daisy chain ring layout on an integrated chip. At least one of the plurality of processing cores places trace data on the daisy chain connection for transmitting the trace data to the central storage unit, and the central storage unit detects the trace data and stores the trace data in the memory co-located in with the central storage unit. | 07-14-2011 |
| 20110179210 | Semiconductor device and data processing system - A semiconductor device includes: first transmission wirings each transmitting a small-amplitude signal between one of a plurality of first drivers and one of a plurality of receivers; a second transmission wiring transmitting a reference signal connected to each of the plurality of receivers; and a second driver outputting the reference signal with an impedance higher than an impedance with which each of the first drivers outputs the small-amplitude signal. The second transmission wiring is arranged between first and second power supply wirings corresponding to first and second potentials of the small-amplitude signal. The first and second potentials are supplied to each of the first drivers. The plurality of first transmission wirings are arranged close to each other, without being sandwiched between the first and second power supply wirings. | 07-21-2011 |
| 20110185100 | Virtual Heterogeneous Channel For Message Passing - A technique includes using a virtual channel between a first process and a second process to communicate messages between the processes. Each message contains protocol data and user data. All of the protocol data is communicated over a first channel associated with the virtual channel, and the user data is selectively communicated over at least one other channel associated with the virtual channel. | 07-28-2011 |
| 20110191516 | Universal touch-screen remote controller - A remote controller has a control processor and a plurality of client device remote interfaces. A touchscreen display displays a rendering depicting a remote controller user interface having user operable control elements. The processor has associated storage that stores remote controller programs that configure the touchscreen according to a remote control configuration defined by a selected remote controller programs. The processor carries out functions defined in the selected one of the remote controller programs to transmit control commands from one of said client device remote interfaces to a client device upon receipt of input via the touchscreen user interface to implement the command to the client device. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract. | 08-04-2011 |
| 20110197009 | 12C-BUS INTERFACE WITH PARALLEL OPERATIONAL MODE - An electronic circuit has an interface for an I | 08-11-2011 |
| 20110202700 | DATA PROCESSING APPARATUS, METHOD OF CONTROLLING THE SAME, AND STORAGE MEDIUM STORING PROGRAM - A data processing apparatus which circulates a packet on a ring bus by connecting a plurality of communication modules to the ring bus and causing each communication module to send the packet to an adjacent communication module in synchronism with a predetermined periodical signal includes a plurality of data process modules each connected to a corresponding one of the plurality of communication modules to process data held in the packet, and an input/output module connected to at least one of the plurality of communication modules to receive/output data from/to the communication module. The number of circulations of data through the ring bus, which is input from the input/output module to one of the communication modules, until the data completes a predetermined processing and is received by the input/output module is acquired. The frequency of the periodical signal is changed in accordance with the number of circulations. | 08-18-2011 |
| 20110208889 | SATA/ESATA PORT CONFIGURATION - In one embodiment, a computer system comprises one or more processors, a circuit board assembly having at least one SATA port, a general purpose input/output port proximate the SATA port, signal generating logic to generate a signal when the general purpose input/output port is coupled to a connector, and a memory module communicatively connected to the one or more processors and comprising logic instructions stored in a computer readable medium which, when executed on the one or more processors, configure the one or more processors to configure the SATA port according to the signal generated by the signal generating circuitry. | 08-25-2011 |
| 20110213907 | SEMICONDUCTOR RESISTANCE ELEMENT, SEMICONDUCTOR MODULE INCLUDING THE SAME, AND PROCESSOR-BASED SYSTEM INCLUDING THE SEMICONDUCTOR MODULE - Provided may be a semiconductor resistance element including resistance patterns disposed on an insulating substrate. The substrate may have first and second planer surfaces disposed in a first direction, third and fourth planar surfaces at least between the first and second planar surfaces in a second direction and fifth and sixth planar surfaces at least between the first and second planar surfaces in a third direction. The semiconductor resistance element may include a first resistance pattern configured to cover a selected one of the first and second planar surfaces and a second resistance pattern on at least one of the third through sixth planar surfaces. | 09-01-2011 |
| 20110213908 | CONFIGURABLE INTERCONNECTION SYSTEM - An interconnection system, apparatus and method is described where the motherboard may be populated with less than all of the modules that it has been designed to accept while maintaining a configuration such that in the event of a module failure, a memory controller failure, or a combination thereof, the connectivity of the remaining modules is maintained. Where data is stored using a RAID organization of the memory on the modules, the data may be reconstructed to a spare module. The system also provides for the orderly incremental expansion of the memory by adding additional memory modules and memory controllers, while maintaining the connectivity properties. | 09-01-2011 |
| 20110219160 | FAST TWO WIRE INTERFACE AND PROTOCOL FOR TRANSFERRING DATA - An apparatus and method for exchanging data between devices. An interface between at least two devices features a serial clock line coupled to each device and a bidirectional serial data line coupled to each device. A delay relative to the clock signal is added to an edge of an output enable signal to prevent a collision between devices when control of the data line is switched. Multiple masters and slaves may be connected to the interface. | 09-08-2011 |
| 20110219161 | SYSTEM AND METHOD FOR PROVIDING ADDRESS DECODE AND VIRTUAL FUNCTION (VF) MIGRATION SUPPORT IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) MULTI-ROOT INPUT/OUTPUT VIRTUALIZATION (IOV) ENVIRONMENT - The present invention is a method for providing address decode and Virtual Function (VF) migration support in a Peripheral Component Interconnect Express (PCIE) multi-root Input/Output Virtualization (IOV) environment. The method may include receiving a Transaction Layer Packet (TLP) from the PCIE multi-root IOV environment. The method may further include comparing a destination address of the TLP with a plurality of base address values stored in a Content Addressable Memory (CAM), each base address value being associated with a Virtual Function (VF), each VF being associated with a Physical Function (PF). The method may further include when a base address value included in the plurality of base address values matches the destination address of the TLP, providing the matching base address value to the PCIE multi-root IOV environment by outputting from the CAM the matching base address value. The method may further include constructing a requestor ID for the VF associated with the matching base address value, the requestor ID being based upon the output matching base address value and a bus number for a PF which owns the CAM. | 09-08-2011 |
| 20110219162 | Adaptive-Allocation Of I/O Bandwidth Using A Configurable Interconnect Topology - Apparatus and methods allocate I/O bandwidth of an electrical component, such as an IC, by configuring an I/O interface into various types of interfaces. In an embodiment of the present invention, an I/O interface is configured into either a bi-directional contact, unidirectional contact (including either a dedicated transmit or dedicated receive contact) or a maintenance contact used in a maintenance or calibration mode of operation. The I/O interface is periodically reconfigured to optimally allocate I/O bandwidth responsive to system parameters, such as changing data workloads in the electronic components. System parameters include, but are not limited to, 1) number of transmit-receive bus turnarounds; 2) number of transmit and/or receive data packets; 3) user selectable setting 4) number of transmit and/or receive commands; 5) direct requests from one or more electronic components; 6) number of queued transactions in one or more electronic components; 7) transmit burst-length setting, 8) duration or cycle count of bus commands, and control strobes such as address/data strobe, write enable, chip select, data valid, data ready; 9) power and/or temperature of one or more electrical components; 10) information from executable instructions, such as a software application or operating system; 11) multiple statistics over respective periods of time to determine if using a different bandwidth allocation would result in better performance. The importance of a system parameter may be weighted over time in an embodiment of the present invention. | 09-08-2011 |
| 20110231592 | Mashup Infrastructure with Learning Mechanism - The present disclosure involves systems, software, and computer implemented methods for providing a mashup infrastructure with a learning mechanism. One process includes operations for receiving a request for connecting a first port of an application with a different port and identifying tagged parameters associated with the first port. A set of potential ports for connecting with the first port based at least in part on the tagged parameters is dynamically determined. A suggestion of potential ports for connecting with the first port, including at least a subset of potential ports selected from the set of potential ports, is presented. | 09-22-2011 |
| 20110238882 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 09-29-2011 |
| 20110252172 | SYSTEM AND METHOD FOR CONCURRENT OPERATION OF DUAL INTERFACES BETWEEN UICC AND MOBILE DEVICE - This invention relates to a process and system for operating a UICC with a terminal such as a cell phones or a PC, where there is an ISO 7816 channel and/or an IC-USB channel between the UICC and the terminal. The invention enables a Concurrent operation mode for simultaneously communicating data or ISO protocol commands over the ISO 7816 channel and communicating data or USB protocols over the IC-USB channel. The system dynamically enters and exits Concurrent mode when both the UICC and the terminal support it, and operates in standard operation modes when either of them does not support it. In one embodiment, on the terminal, the ISO interface is connected to the communication processor and the IC-USB interface is connected to the application processor through a USB bridge chip, and the UICC can be configured either as a host or a gadget. | 10-13-2011 |
| 20110252173 | TRANSLATING A REQUESTER IDENTIFIER TO A CHIP IDENTIFIER - In an embodiment a translation of RID (requester identifier) ranges to identifiers of north chips is stored into a south chip. A command that comprises a command RID is received at the south chip from a device. In response, a RID range is determined that encompasses the command RID, and a north chip identifier is found that is assigned a virtual function identified by the command RID. The command is sent from the south chip to the north chip identified by the north chip identifier. The translation comprises a RID compare value and a RID mask. A determination is made that the RID range encompasses the command RID by performing a logical-and operation on the command RID and the RID mask and comparing a result of the logical-and operation to the RID compare value. | 10-13-2011 |
| 20110258357 | SERIAL PORT CONNECTOR WITH POWER OUTPUT FUNCTION - A serial port connector with power output function includes a serial port having a plurality of pins. Under the existing EIA-RS-232, EIA-RS-422, and EIA-RS-485 standards for connectors, the definition of the pins of the serial port are altered, so that a pin that was originally defined as floating or for serial data communication signal is now changed to a power output specification. Thus, when the connector is connected via the same one cable to a serial port peripheral device, the connector can provide both functions of serial data communication signal transmission and power transmission to thereby largely increase the usability of the connector. | 10-20-2011 |
| 20110258358 | Device and Method for the Automated Detection of an Interface - In a device and a method for the automated detection of an interface between a position-measuring device and sequential electronics that are interconnected via a data-transmission channel, the position-measuring device includes an interface unit and a position-measuring unit. The interface unit is connected first of all to the data-transmission channel, and secondly to the position-measuring unit for the purpose of an internal data exchange. The interface to the sequential electronics is selectable in the interface unit from at least two interfaces. Also disposed in the position-measuring device is an interface-detection unit, which is supplied with at least one input signal that arrives from the sequential electronics via the data-transmission channel, and which includes a device for determining the time sequence of signal edges of the at least one input signal in conjunction with the signal status, as well as an evaluation unit in which the interface used to the sequential electronics is detectable by evaluating the time sequence determined, and is selectable in the interface unit. | 10-20-2011 |
| 20110271027 | Remote access of peripheral device connected to serial bus - A computing device includes a hardware network component, a hardware serial component, device drivers, a network driver, and a serial driver. The hardware network component connects the computing device to other computing devices. The hardware serial component connects the computing device to peripheral devices over a serial bus. Each device driver is for one of these peripheral devices or for a peripheral device connected to a serial bus of one of the other computing devices. The network driver is for the hardware network component, and the serial driver is for the hardware serial component. The serial, network, and device drivers interact to permit the computing device to communicate with the peripheral devices of the other computing devices over a network. The device drivers for the peripheral devices of the other computing devices are unaware that these peripheral devices are not connected to the serial bus of the computing device. | 11-03-2011 |
| 20110283034 | SEMICONDUCTOR CHIP, AND SEMICONDUCTOR PACKAGE AND SYSTEM EACH INCLUDING THE SEMICONDUCTOR CHIP - A semiconductor chip includes a redistribution interconnect that is implemented by shorting bumps, and a semiconductor package and a system each including the semiconductor chip. The semiconductor chip includes a semiconductor substrate, a passivation film disposed on the semiconductor substrate, and a plurality of pseudo bumps disposed on the passivation film. Each pseudo bump is directly connected to adjacent pseudo bumps to form at least one redistribution interconnect. | 11-17-2011 |
| 20110283035 | Hybrid Storage System With Control Module Embedded Solid-State Memory - A hybrid control module includes a host interface control module configured to transfer data to and from a host interface. A first embedded multi-media card (eMMC) interface is configured to (i) connect to a second eMMC interface of a control module embedded solid-state memory (SSM) and (ii) transfer the data between the hybrid control module and the control module embedded SSM. A buffer management module is (i) in communication with the host interface control module, the first eMMC interface and a disk access control module and (ii) configured to buffer the data in volatile memory. The data is received by the buffer management module and from at least one of the host interface control module, the first eMMC interface, or the disk access control module. | 11-17-2011 |
| 20110289252 | STORAGE ROUTER AND METHOD FOR PROVIDING VIRTUAL LOCAL STORAGE - A storage router and method for providing virtual local storage on remote storage devices to devices are provided. Devices are connected to a first transport medium, and a plurality of storage devices are connected to a second transport medium. In one embodiment, the storage router maintains a map to allocate storage space on the remote storage devices to devices connected to the first transport medium by associating representations of the devices connected to the first transport medium with representations of storage space on the remote storage devices, wherein each representation of a device connected to the first transport medium is associated with one or more representations of storage space on the remote storage devices and controls access from the devices connected to the first transport medium to the storage space on the remote storage devices in accordance with the map and using native low level block protocol. | 11-24-2011 |
| 20110320669 | COMMUNICATION SYSTEM AND METHOD - A communication system for transmitting data, for example, within a System-in-Package. The system includes a first circuit configured for: a) dividing the data into a plurality of packets having a determined size; and b) creating for each of the packets a transmission segment including a segment header and the respective packet as payload. The system also includes a second circuit configured for: a) separating the transmission segments into a plurality of physical units, where the physical units have a determined size; and b) transmitting the physical units over a physical communication channel. In particular, the segment header includes at least one field that identifies the number of physical units that are to be transmitted. | 12-29-2011 |
| 20120011294 | SYSTEM AND METHOD FOR SECURE AUTHENTICATION OF A "SMART" BATTERY BY A HOST - Systems and methods for providing a battery module | 01-12-2012 |
| 20120017021 | BUS TO BUS POWER INTERCONNECT - A bus interconnect in accordance with present embodiments includes a via block having first and second interfaces separated by a conductive body, wherein the via block is configured to communicatively couple with a first bus through the first interface and wherein the conductive body is configured to extend through an opening in a bus support panel. A first coupling section of the jumper includes a first attachment feature, wherein the first attachment feature is configured to facilitate attachment with the second interface of the via block. A neck section of the jumper extends perpendicularly from the first coupling section, and a second coupling section of the jumper extends perpendicularly from the neck section in parallel with the first coupling section. The second coupling section includes a second attachment feature configured to facilitate attachment with a second bus. The first coupling section and the second coupling section each extend away from the neck section in different directions. | 01-19-2012 |
| 20120023279 | INDICATOR CONTROL APPARATUS - An indicator control apparatus includes a bus connector, a signal converting unit, an address configuring unit, and an indicating unit. The signal converting unit receives bus signals from the bus connector. The address configuring unit sets an address of the signal converting unit. The signal converting unit converts the bus signals to digital input/output (I/O) signals in response to the address of the signal converting unit matching with the bus signals. The indicating unit is driven by the I/O signals and correspondingly displays information. | 01-26-2012 |
| 20120030394 | UNIVERSAL COMPUTER MANAGEMENT INTERFACE - An integrated computer management apparatus allowing a networked administrator to manage a computer via multiple connection types and protocols. A preferred embodiment of the device has a network connection for the administrative users, coupled via an internal Ethernet switch and a processor to keyboard-video-mouse, serial, and Ethernet computer connections. Depending on hardware characteristics, operational status, OS, and administrator preferences any of these may be used to provide remote computer system management functions. Software running on the processor can provide direct logical connection between the remote administrator and a management port; may serve web pages graphically interpreting data gleaned from one or more of the connections; can provide protocol translation or proxy services; or locally execute an intelligent management agent. The device can be physically small enough to be supported by its connecting cables, and receives power from the attached computer. | 02-02-2012 |
| 20120030395 | CIRCUIT CONFIGURATIONS AND METHOD FOR CONTROLLING A DATA EXCHANGE IN A CIRCUIT CONFIGURATION - In a method for controlling a data exchange between at least one set of data sinks and at least one set of data sources in circuit configurations and circuit sequences, which circuit configurations have at least one arbitration unit, the arbitration unit selects a first data sink (data sink arbitration) and a first data source (data source arbitration) according to a predefined sequence, and outputs an address of a first data source and a request signal and an address of a first data sink and a validity signal. Data of the first data source are stored in the first data sink. | 02-02-2012 |
| 20120042109 | CONNECTOR ELEMENT FOR A COMMUNICATION SYSTEM AND COMMUNICATION BUS SYSTEMS - A connector element for assembling a communication system, having a plurality of communication bus system contact elements for connecting to a communication bus system, a plurality of internal terminal elements and a configuration encoding unit. The connector element is designed for assembling the communication bus system. | 02-16-2012 |
| 20120042110 | BUS BANDWIDTH MONITORING DEVICE AND BUS BANDWIDTH MONITORING METHOD - A bus bandwidth monitoring device may include a buffer unit that is connected to a common bus, the buffer unit storing data that has been input via the common bus, a processing unit that performs predetermined processing based on the data stored in the buffer unit, and a detection unit that detects a bandwidth of data transmitted through the common bus based on a state of data transaction between the buffer unit and the processing unit. | 02-16-2012 |
| 20120042111 | BUS BANDWIDTH MONITORING DEVICE AND BUS BANDWIDTH MONITORING METHOD - A bus bandwidth monitoring device may include a buffer unit that is connected to a common bus, the buffer unit storing data that has been input via the common bus, a processing unit that performs predetermined processing based on the data stored in the buffer unit, and a detection unit that detects a bandwidth of the data of the common bus based on a state of storage of the data that is input to the buffer unit through the common bus. | 02-16-2012 |
| 20120047304 | APPARATUS AND METHOD FOR CONTROLLING EXTERNAL DEVICE - Provided is a terminal for controlling an external device, not equipped with its own memory or controller, connected to the terminal. The portable terminal, when being connected to at least one external device, changes its setting with an extracted setting data matching the connected external device. Accordingly, the connected external device in a connection state to the portable terminal performs corresponding operations under control of the portable terminal. | 02-23-2012 |
| 20120047305 | PACKET FORMAT FOR A DISTRIBUTED SYSTEM - A method is provided for transmitting a packet including information describing a bus transaction to be executed at a remote device. A bus transaction is detected on a first bus and a network packet is generated for transmission over a network. The network packet includes an opcode describing the type of bus transaction. One or more control signals of the bus transaction map directly to one or more bits of the opcode to simplify decoding or converting of the bus transaction to the opcode. The packet is transmitted to a remote device and the bus transaction is then replayed at a second bus. In addition, the packet includes a data field having a size that is a multiple of a cache line size. The packet includes separate CRCs for the data and header. The packet also includes a transaction ID to support split transactions over the network. Also, fields in the packet header are provided in a particular order to improve switching efficiency. | 02-23-2012 |
| 20120059965 | PRECISION SYNCHRONISATION ARCHITECTURE FOR SUPERSPEED UNIVERSAL SERIAL BUS DEVICES - A method of providing a synchronisation channel to a SuperSpeed USB device is provided. The method including a SuperSpeed communication channel connection to the SuperSpeed USB device with a USB cable that has USB 2.0 D+ and D− data signalling lines disabled or disconnected at an upstream connection point; multiplexing synchronization information onto the D+/D− data signalling lines at the upstream connection point; and demultiplexing the synchronization information from the D+/D− signalling lines at a downstream connection point of the cable; whereby the synchronisation channel is maintained across the D+/D− data signalling lines. | 03-08-2012 |
| 20120066426 | Method And Apparatus For Data Movement In A System On A Chip - There is provided a system for comprising a plurality of blocks, each block comprising any hardware element and a plurality of segments for providing interconnection of the plurality of blocks. A segment comprises a connector between multiple blocks and other segments and segments are connected via the ports of blocks or other segments. Communications between blocks is packet based, each packet including at least a destination block. The packet includes at least one of data, packet/message identification and padding. Blocks have an associated address. A block has one or more input ports and one or more output ports. Segments include means for routing packets to destinations. Each block and segment includes properties. Properties include one or more of clocks, bandwidth, bit widths, and latencies. The plurality of segments for multiple packets to be active on different segments. A single segment includes a plurality of ports for multiple packets to be active on different ports of the segment. | 03-15-2012 |
| 20120072634 | FULLY INTEGRATED, LOW AREA UNIVERSAL SERIAL BUS DEVICE TRANSCEIVER - A transceiver apparatus includes a process, a first type of transceiver circuit for data transmission, a second type of transceiver circuit for data transmission, and a communications interface for communicating between the first type of transceiver circuit and an external device. The first type of transceiver circuit is co-located with a physical layer associated with the first type of transceiver circuit. In some embodiments, the first type of transceiver circuit can be, for example, a USB 2.0 transceiver circuit, and the second type of transceiver circuit can be a USB 3.0 transceiver circuit. The aforementioned external device can be an external USB device. | 03-22-2012 |
| 20120079156 | IMPLEMENTING QUICKPATH INTERCONNECT PROTOCOL OVER A PCIe INTERFACE - Methods and apparatus for implementing the Intel QuickPath Interconnect® (QPI) protocol over a PCIe interface. The upper layers of the QPI protocol are implemented over a physical layer of the PCIe interface via use of QPI data bit mappings onto corresponding PCIe x16, x8, and x4 lane configurations. A QPI link layer to PCIe physical layer interface is employed to abstract the QPI link, routing, and protocol layers from the underlying PCIe physical layer (and corresponding PCIe interface circuitry), enabling QPI protocol messages to be employed over PCIe hardware. Thus, QPI functionality, such as support for coherent memory transactions, may be implemented over PCIe interface circuitry. | 03-29-2012 |
| 20120079157 | DEVELOPMENT OF FUNCTIONAL MODULES USING A MODULE BUS - Systems and methods are provided that facilitate development of a module for use in a control application by assembling one or more predefined aspects onto a module bus. The module bus acts as a virtual backplane that allows module functionality in the form of predefined bus-compliant aspects to be selected and added to the bus, thereby yielding a module having a desired set of functions. When an aspect is added to the module bus, the bus integrates the aspects into the module automatically without the need to modify the module's core code to interface the aspects with the module. The module bus also establishes the necessary interdependencies between aspects representing cross-cutting concerns without requiring new code to be writing to link the aspects. | 03-29-2012 |
| 20120084482 | SEMICONDUCTOR DATA PROCESSING DEVICE AND DATA PROCESSING SYSTEM - A communication control function is implemented with limited hardware resources without hampering the extensibility and degrading the processing performance. In an electric control unit coupled to a network bus comprises a reconfiguration module using for processing message received from the network bus. The reconfiguration module is made for configuring the processing circuit in accordance with the message transferred on the network bus to be processed. | 04-05-2012 |
| 20120084483 | DIE EXPANSION BUS - A die expansion bus efficiently couples a supplemental portion of a processing system to an original portion of the processing system on a die. The die expansion bus couples bus subsystems of the supplemental portion of the processing system to the bus subsystems of the original portion of the processing system. The original portion of the processing system is arranged to control the data resources of the supplemental portion of the processing system by accessing the memory endpoints associated with the bus subsystems of the supplemental portion of the processing system. | 04-05-2012 |
| 20120089762 | DELEGATING NETWORK PROCESSOR OPERATIONS TO STAR TOPOLOGY SERIAL BUS INTERFACES - An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner. | 04-12-2012 |
| 20120096209 | Multi peripheral accelerating apparatus - A multi peripheral accelerating apparatus includes a processor device disposed on a main board, a primary memory and a controller disposed on the main board and electrically connected to the processor device for exchanging information with the processor device, a secondary memory disposed on the main board and electrically connected to the controller, and one or more peripherals disposed on the main board and electrically connected to the controller for allowing the information to be transmitted or exchanged from the peripherals to the secondary memory when the processor device is transmitting or exchanging information with the primary memory. | 04-19-2012 |
| 20120102253 | DATA STORAGE DEVICE - A data storage device includes a number of storage units, a main universal serial bus (USB) interface connected to the storage units and cooperating with the storage units to form a main USB memory, and a number of branch USB interfaces corresponding to the storage units. Each branch USB interface is connected to a corresponding storage unit, and cooperates with the corresponding storage unit to form a branch USB memory. According to employing the branch USB interfaces and the storage units, the data storage device can function as several independent USB memories, to meet the need of using several USB memories at the same time. | 04-26-2012 |
| 20120110231 | HOME STORAGE SYSTEM - In general, embodiments of the present invention provide a home storage system and method of production. Specifically, in a typical embodiment, the home storage system includes a main controller that is coupled to a display controller, an external memory controller, an external interface, and a PCI-Express-based hybrid RAID controller. Further, a set of semiconductor storage device (SSD) memory units and a set of hard disk drive (HDD/Flash) memory units are coupled to the hybrid RAID controller. The external interface allows the storage system to establish network connectivity, while the external memory controller allows the storage device to be coupled to different types of external memory devices. | 05-03-2012 |
| 20120124266 | HYBRID STORAGE DEVICE AND ELECTRONIC SYSTEM USING THE SAME - A hybrid storage device is provided. The hybrid storage device includes a first storage part that comprises an interface device based on a first standard, a second storage part that comprises an interface device based on a second standard, and a connector for interface devices that is shared by the first storage part and the second storage part and comprises a plurality of pins. | 05-17-2012 |
| 20120144084 | DATA MANAGEMENT DEVICE AND METHOD THEREOF - A data management device used to manage (that is, exchange data, upgrade programs, and other tasks) a communication device includes a microprocessor unit (MPU), a communication module, a storage module, a display module, and an input/output module. The communication module, the storage module, the display module, and an input/output module are connected to the MPU. The communication module establishes communication between the MPU and the communication device. The storage module stores driver and application programs for the MPU. The display module displays communication states between the MPU and the communication device. Management information can be input into the MPU by the input/output module and transmitted to the communication device by the communication module. | 06-07-2012 |
| 20120144085 | Memory Module Having Signal Lines Configured for Sequential Arrival of Signals at a Plurality of Memory Devices - A memory module includes a substrate, a plurality of signal lines, a clock line and a plurality of memory devices. The plurality of signal lines including first and second signal lines routed alongside one another where, for each of the first and second signal lines, a respective signal, starting at a corresponding first edge finger, traverses in sequence, a respective first segment of a respective signal line, a respective turn portion of the respective signal line, and a respective second segment of the respective signal line. The clock line is to provide a clock signal that traverses in sequence, a second edge finger, the first segment of the clock line, the turn portion of the clock line, and the second segment of the clock line. The respective signals traverse and the clock signal line arrive at the plurality of memory devices in sequence. | 06-07-2012 |
| 20120151113 | BUS SYSTEMS AND METHODS FOR CONTROLLING DATA FLOW IN A FIELD OF PROCESSING ELEMENTS - A bus system for a configurable architecture and methods therefor are provided in which optimization of the configuration efficiency and reconfiguration efficiency are taken into account separately. A system and method may include controlling data transmission by: transmitting, by a first hardware element and to a second hardware element, a data packet conditional upon and/or responsive to the second hardware element's assignment of a signal to a connecting bus via which the data packet is transmitted, where the signal indicates that no incoming data packet can be lost. A system and method may include controlling data transmission by: transmitting, by a first hardware element and to a second hardware element, a first data packet and subsequently a second data packet; and receiving, by the first hardware element and from the second hardware element, an acknowledgement of the first data packet subsequent to the transmittal of the second data packet. | 06-14-2012 |
| 20120159031 | Device and Method for Enabling Multi-Value Digital Computation - A row driver is configured to activate a row line responsive to a signal having one of multiple possible values. A column driver is configured to activate a column line responsive to a signal having one of multiple possible values. The row and column drivers comprise sets of sense amps and decoders. One of a plurality of lines is operably connected to and input/output line responsive to the active row line and column line. The use of sense amps in the row and column drivers enables this flow control circuit to operate with low power consumption and allows the flow control circuit to act as a register. | 06-21-2012 |
| 20120159032 | ELECTRONIC DEVICE AND PROGRAM - An electronic device provided with a multimedia interface having a cross-device control function and a general-purpose serial bus interface is provided with a control unit that prohibits the use of the cross-device control function whenever an external device is connected via the general-purpose serial bus interface during a state permitting control by the cross-device control function from an image display device connected via the multimedia interface. | 06-21-2012 |
| 20120166698 | UNIFIED INFORMATION BUS - Systems, methods, and other embodiments associated with unified information bus are described. One example method includes receiving a unified information object that includes data and associated meta-data; identifying an object type for the unified information object, selecting one or more data transfer components that perform operations on the identified object type and transferring the unified information object to the one or more selected data transfer components. | 06-28-2012 |
| 20120198117 | System and Method for Improving Throughput of Data Transfers Using a Shared Non-Deterministic Bus - System and method for facilitating data transfer between logic systems and a memory according to various conditions. Embodiments include systems and methods for facilitating and improving throughput of data transfers using a shared non-deterministic bus, a system and method for managing a memory as a circular buffer, and a system and method for facilitating data transfer between a first clock domain and a second clock domain. Embodiments may be implemented individually or in combination. | 08-02-2012 |
| 20120210035 | DEVICE FOR A MULTI-BOOT SYSTEM WITH NETWORK SWITCHES - A device for a multi-boot system with network switches has a box, a selection module and a bridge connecting card. The box has an operation panel mounted with multiple switches. The selection module is mounted in the box and has a hard disk selector and a network selector. The hard disk selector has a power input port, multiple power output ports connected to the power input port via part of the switches. The network selector has a network input port and a network output port connected to the network input port via the other switches and is connected to a network cable. The bridge connecting card is mounted outside of the box. The multiple switches can form multiple combinations. Each combination corresponds to one operating system for booting and the communicating status with Internet. | 08-16-2012 |
| 20120210036 | NON MAIN CPU/OS BASED OPERATIONAL ENVIRONMENT - A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state. | 08-16-2012 |
| 20120210037 | Electrical Device - An electrical device, which is assembled from modules or includes assembled modules, the modules each including an electronic circuit mounted on a respective heat sink, the modules being configured as nodes of a system bus that also leads to an electronic circuit designed as a node of the system bus, the electronic circuit being configured in a lower part that is configured in a recess of the housing of the electrical device; an upper part being detachably connectable to the lower part; a memory element being configured in the upper part; and data lines for reading out the memory element via the electronic circuit being routed via a plug connection to the electronic circuit. | 08-16-2012 |
| 20120226846 | HDMI DEVICE AND ASSOCIATED POWER MANAGEMENT METHOD - An HDMI device and an associated power management method are provided for use in the case with an HDMI Ethernet Channel implemented. The HDMI device can acquire an external power source by connecting to another HDMI device through an HDMI interface. Thus, when the internal power source of the HDMI device is disabled, the external power source can be used as a backup power source for the internal Ethernet circuit of the HDMI device. | 09-06-2012 |
| 20120233370 | PROCESS CONTROL ASSEMBLY FOR A PROCESS AND/OR AUTOMATION TECHNOLOGY APPARATUS - A process control arrangement (PKA), having a number of fieldbus systems (DP | 09-13-2012 |
| 20120239846 | MULTI-RATE, MULTI-PORT, GIGABIT SERDES TRANSCEIVER - A multi-port SERDES transceiver includes multiple parallel ports and serial ports, and includes the flexibility to connect any one of the parallel ports to another parallel port or to a serial port, or both. Furthermore, the multi-port transceiver chip can connect any one of serial ports to another serial port or to one of the parallel ports. The substrate layout of the multi-port SERDES transceiver chip is configured so that the parallel ports and the serial ports are on the outer perimeter of the substrate. A logic core is at the center of the substrate, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the data ports. | 09-20-2012 |
| 20120246376 | METHOD FOR OPERATING A FIELDBUS INTERFACE - A method for operating a fieldbus interface, which is connected to a fieldbus of process automation technology. The method includes the steps as continuous monitoring of data traffic on the fieldbus by the fieldbus interface; need-dependent performing of active communication by the fieldbus interface in parallel with the monitoring of the data traffic; and registering by the fieldbus interface of monitored information concerning network management of the fieldbus. | 09-27-2012 |
| 20120260016 | MULTI-USE PHYSICAL ARCHITECTURE - A multi-use physical (PHY) architecture that includes a PHY connection that includes one or more bit lines and that is communicatively coupled to a first processor. The PHY connection is configurable to carry signals between the first processor and a second processor, or between the first processor and a memory. The one or more bit lines are configured to carry signals bi-directionally at a first voltage when the PHY connection is configured to carry signals between the first processor and the memory. The one or more bit lines are configured to carry signals uni-directionally at a second voltage when the PHY connection is configured to carry signals between the first processor and the second processor. The second voltage is different than the first voltage. | 10-11-2012 |
| 20120265914 | ADAPTIVE INTEGRATED CIRCUITRY WITH HETEROGENOUS AND RECONFIGURABLE MATRICES OF DIVERSE AND ADAPTIVE COMPUTATIONAL UNITS HAVING FIXED, APPLICATION SPECIFIC COMPUTATIONAL ELEMENTS - The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications. | 10-18-2012 |
| 20120265915 | DISTRIBUTED COMPUTING SYSTEM ARCHITECTURE - A computing system architecture is based upon a peer-to-peer, asynchronous model. The architecture specifies a set of infrastructure facilities that comprise an inter-prise operating system. The inter-prise operating system provides all the facilities that make application coding as easy in the peer-to-peer asynchronous model as it is in a hierarchical, synchronous model. Services, which reside in containers, are linked asynchronously by an inter-prise bus and use data from a virtual data store. | 10-18-2012 |
| 20120284445 | Redundant Electrical Network Between Remote Electrical Systems and a Method of Operating Same - A redundant electrical connection network may include a first electronic system having a first processor, a second, remote electric system having a second processor, a first communication link coupled between the first and second processors, and a second communication link coupled between the first and second processors. The second communication link may be separate and isolated from the first communication link, and the first and second processors may be configured to normally conduct data communications solely via one of the first and second communication links, and at least one of the first and second processors may be configured to monitor the one of the first and second communication links and re-route the data communications solely to the other of the first and second communication links upon detection of loss of the one of the first and second communication links. | 11-08-2012 |
| 20120290761 | USB Converter and Related Method - A Universal Serial Bus (USB) converter used in a USB system comprises at least one USB package processing unit and a processor. Each USB package processing unit is for receiving input packets from a corresponding first USB device according to a first protocol, converting the input packets into output packets of a second protocol, and outputting the output packets to a second USB device according to the second protocol. The processor is for selectively placing each USB package processing unit of the at least one USB package processing unit in a standby mode according to a corresponding detection signal indicating detected electrical state of a corresponding pin of the USB system connected to the corresponding first USB device. | 11-15-2012 |
| 20120290762 | ROUTE LOOKUP METHOD FOR REDUCING OVERALL CONNECTION LATENCIES IN SAS EXPANDERS - A system and method for reducing overall connection latencies in a SAS expander is disclosed. The SAS expander includes a plurality of ports and a route lookup table configured for providing a central resource for routing information for the ports. The SAS expander also includes a plurality of connection history caches (CHCs) associated with the ports, each CHC is configured for storing at least one successfully established connection record. Upon receiving a connection request at a particular port, that particular port may determine whether a matching connection record for the connection request is stored in its corresponding CHC. If the matching connection record is stored in its corresponding CHC, a connection may be established in response to the connection request based on the matching connection record. However, if no matching connection record is found in its corresponding CHC, the connection may be established utilizing the route lookup table. | 11-15-2012 |
| 20120297103 | FABRIC INTERCONNECT FOR DISTRIBUTED FABRIC ARCHITECTURE - A system includes scaled-out fabric coupler (SFC) boxes and distributed line card (DLC) boxes. Each SFC box has fabric ports and a cell-based switch fabric for switching cells. Each DLC box is in communication with every SFC box. Each DLC box has network ports receiving packets and network processors. Each processor has a fabric interface that provides SerDes channels. The processors divide each packet received over the network ports into cells and distribute the cells of each packet across the SerDes channels. Each DLC box further comprises DLC fabric ports through which the DLC is in communication with the SFCs. Each DLC fabric port includes a pluggable interface with a given number of lanes over which to transmit and receive cells. Each lane is mapped to one of the SerDes channels such that an equal number of SerDes channels of each fabric interface is mapped to each DLC fabric port. | 11-22-2012 |
| 20120297104 | CONTROLLED INTERMEDIATE BUS ARCHITECTURE OPTIMIZATION - An intermediate bus architecture power system includes a bus converter that converts an input voltage into a bus voltage on an intermediate bus and a point-of-load converter that supplies an output voltage from the bus voltage on the intermediate bus. Additionally, the intermediate bus architecture power system includes a decision engine optimizing controller that controls a system variable to improve an overall system performance based on a monitored system variable or a system constraint. In another aspect, a method of operating an intermediate bus architecture power system includes converting an input voltage into a bus voltage on an intermediate bus and converting the bus voltage on the intermediate bus into an output voltage. The method also includes controlling a system variable to improve overall system performance based on a monitored system variable or a system constraint. | 11-22-2012 |
| 20120297105 | PATTERN DETECTION FOR PARTIAL NETWORKING - A pattern detector for a bus node for a system bus having a plurality of stations that are coupled together by means of an arrangement of bus lines, the bus node comprising: decoding circuitry configured for an analysis of sub-patterns in a stream of data on at least one bus line, and analysing circuitry configured to determine a series of digital relative length information of said sub-patterns, wherein said relative length information is generated by comparison of an actual sub-pattern with a preceding sub-pattern in the stream of data on said at least one bus line. A corresponding method of encoding digital bus message information on a bus system in which the digital bus message comprises at least one part that is by means of sub-patterns to be transmitted in a stream of data on at least one bus line, wherein the method comprises: encoding a series of digital relative information by means of the sub-patterns in the stream of data, wherein said relative information is generated by adapting each sub-pattern carrying one bit of the bus message information with respect to an preceding sub-pattern. A corresponding digital bus messages may be encoded in accordance with the method, which bus messages are of particular use in a bus system, in which communication takes place on arbitrarily manner. | 11-22-2012 |
| 20120303853 | ENGINEERING OF A DATA COMMUNICATION - In a method for communication between function modules in the field of automation systems, a first function module has a first communication interface, and a second function module has a second communication interface. The first communication interface is assigned to the second communication interface, and the assignment is stored. | 11-29-2012 |
| 20120311217 | FACILITATING PROCESSING OF OUT-OF-ORDER DATA TRANSFERS - Processing of out-of-order data transfers is facilitated in computing environments that enable data to be directly transferred between a host bus adapter (or other adapter) and a system without first staging the data in hardware disposed between the host bus adapter and the system. An address to be used in the data transfer is determined, in real-time, by efficiently locating an entry in an address data structure that includes the address to be used in the data transfer. | 12-06-2012 |
| 20120311218 | FACILITATING PROCESSING OF OUT-OF-ORDER DATA TRANSFERS - Processing of out-of-order data transfers is facilitated in computing environments that enable data to be directly transferred between a host bus adapter (or other adapter) and a system without first staging the data in hardware disposed between the host bus adapter and the system. An address to be used in the data transfer is determined, in real-time, by efficiently locating an entry in an address data structure that includes the address to be used in the data transfer. | 12-06-2012 |
| 20120324136 | REPRESENTATION OF DATA RELATIVE TO VARYING THRESHOLDS - An apparatus having first and second circuits is disclosed. The first circuit may be disposed on a first side of a bus and configured to store thresholds in a first memory. Each threshold generally represents a respective one of a plurality of regular bit patterns in first data. The first circuit may also be configured to generate second data by representing each respective first data as (i) an index to one of the thresholds and (ii) a difference between the one threshold and the respective first data. A width of the bus may be narrower than the respective first data. The second circuit may be disposed on a second side of the bus and configured to (i) store the thresholds and a plurality of items in a second memory and (ii) reconstruct the first data by adding the respective thresholds to the second data in response to the items. | 12-20-2012 |
| 20130007330 | CO-DESIGN OF A TESTBENCH AND DRIVER OF A DEVICE - This disclosure concerns the co-design of a testbench ( | 01-03-2013 |
| 20130013837 | UNDERLAYING DEVICE FOR A COMPUTER DEVICE - An underlaying device includes a main signal port, an expanding signal port, a signal process component, and a power connector. The main signal port is receiving and sending a communication signal from/to the computer device by means of a main signal wire. The expanding signal port is receiving and sending the communication signal from/to an external expanding device. The signal process component is coupled between the main signal port and the expanding signal port for transforming the communication signal into a signal which is able to be received and sent between the main signal port and the expanding signal port. The power connector is supplying power by means of a power wire. The underlaying device is suitable for various computer devices and is able to integrate the functionality of connection ports. | 01-10-2013 |
| 20130013838 | INFORMATION PROCESSING APPARATUS, METHOD THEREOF, AND STORAGE MEDIUM - An information processing apparatus includes a plurality of modules connected in a ring shape via a bus, and each module processes a packet flowing in a single direction on the ring in a predetermined order. The module includes a communication unit for transmitting a packet received from a first direction in the ring via the bus to a second direction, a discrimination unit for discriminating a packet from among the packets received from the first direction as a processing packet to be processed by the module, and a processing unit which is connected with the communication unit one by one and configured to process the processing packet. The communication unit transmits the packet processed by the processing unit at an interval equivalent to processing time or more for a processing packet processed by a module in a latter stage in the predetermined order among packets transmitted by the communication unit to the second direction. | 01-10-2013 |
| 20130013839 | MULTI-CORE IMAGE PROCESSOR FOR PORTABLE DEVICE - A portable handheld device including a CPU for processing a script; a multi-core processor for processing an image; an input buffer for receiving data for processing by the multi-core processor, the input buffer being provided under the control of the multi-core processor to send data thereto; and an output buffer for receiving data processed by the multi-core processor, the output buffer being provided under the control of the multi-core processor to receive data therefrom. The multi-core processor comprises a plurality of micro-coded processing units. The CPU is configured with authority to clear and query the input and output buffers. | 01-10-2013 |
| 20130019043 | Vehicle Communications Interface and Method of Operations Thereof - A vehicle communication interface (VCI) that allows for a single communications protocol to be used between a software application and a plurality of software drivers that are connected to physical interfaces of the VCI. Also, a method of communicating with a vehicle using a host system such as a personal computer. The method also makes use of a single communications protocol between a software application that processes information received from a vehicle and a plurality of software drivers. | 01-17-2013 |
| 20130036247 | I2C ISOLATED, BIDIRECTIONAL COMMUNICATION SYSTEM WITH ISOLATED DOMAIN CURRENT SOURCE PULL-UPS - This disclosure describes a circuit implementation providing the functions necessary to implement an isolated I | 02-07-2013 |
| 20130046912 | METHODS OF MONITORING OPERATION OF PROGRAMMABLE LOGIC - Disclosed is a method of monitoring operation of programmable logic for a streaming processor, the method comprising: generating a graph representing the programmable logic to be implemented in hardware, the graph comprising nodes and edges connecting nodes in the graph; inserting, on each edge, monitoring hardware to monitor flow of data along the edge. Also disclosed is a method of monitoring operation of programmable logic for a streaming processor, the method comprising: generating a graph representing the programmable logic to be implemented in hardware, the graph comprising nodes and edges connecting the nodes in the graph; inserting, on at least one edge, data-generating hardware arranged to receive data from an upstream node and generate data at known values having the same flow control pattern as the received data for onward transmission to a connected node. | 02-21-2013 |
| 20130060984 | Administering Computing System Resources In A Computing System - Administering computing system resources in a computing system, the computing system comprising at least one slot adapted to receive an electrical component having a set of pins, the slot configured to couple pins of the electrical component to the computing system, installed within the slot a presence detectable baffle, the presence detectable baffle comprising a passive chassis having a form factor consistent with the electrical component and a presence detectable pin set connected to the passive chassis, the pin set consistent with the electrical component, including: identifying, by a system manager, the presence detectable baffle; and managing, by the system manager, computing system operating attributes in dependence upon presence detectable baffle attributes. | 03-07-2013 |
| 20130060985 | DEVICE CAPABLE OF ADOPTING AN EXTERNAL MEMORY - A device includes a memory controller, a memory bus coupled to the memory controller, an internal memory and an external memory connection unit. The internal memory may be directly connected to the memory controller through the memory bus. The external memory connection unit may connect an external memory directly to the memory controller through a portion of signal lines in the memory bus, and may generate a flag signal indicating whether the external memory is connected to the external memory connection unit. | 03-07-2013 |
| 20130067134 | PSEUDO MULTI-MASTER I2C OPERATION IN A BLADE SERVER CHASSIS - A system and method are directed towards a pseudo multi-master operation on a serial bus. The pseudo multi-master operation allows multiple devices without standard multi-master functionality to operate on the serial bus as masters. In a disclosed example, the serial bus is an Inter-Integrated Circuit (I2C) bus, which is isolated when an adapter card requires access to the I2C bus, such as to update vital product data (VPD) to a memory device, and to cache the updated VPD to a chassis management module. | 03-14-2013 |
| 20130073771 | ASYNCHRONOUS PROTOCOL CONVERTER - An asynchronous protocol converter, which is capable of flexibly carrying out communications between tens of IP cores in an asynchronous protocol Network-on-Chip system, and which is multiple input multiple output is provided. In an LSI ( | 03-21-2013 |
| 20130086294 | Serial Peripheral Interface and Method for Data Transmission - A serial peripheral interface of an integrated circuit including multiple pins and a clock pin is provided. The pins are coupled to the integrated circuit for transmitting an instruction, an address or a read out data. The clock pin is coupled to the integrated circuit for inputting multiple timing pulses. The plurality of pins transmit the instruction, the address or the read out data at rising edges, falling edges or both edges of the timing pulses. | 04-04-2013 |
| 20130103874 | UPGRADE SYSTEM FOR POWER SUPPLY UNIT - An upgrade system for a power supply unit. The power supply unit includes a master interface for outputting power. The upgrade system includes a test board with a slave interface and an upgrade interface, and an upgrade device. Each of the master interface and the slave interface includes four reserved pins. The four reserved pins of the master interface are correspondingly connected to the four reserved pins of the slave interface. The four reserved pins of the slave interface are further connected to the upgrade interface. The upgrade device communicates with the power supply unit through the upgrade interface and the reserved pins of the master interface and the slave interface. | 04-25-2013 |
| 20130111098 | POWER SUPPLY UNIT AND POWER SUPPLY SYSTEM FOR SERVERS | 05-02-2013 |
| 20130132629 | APPARATUS OF STORAGE MEDIUM FOR INTERFACING BOTH HOST AND MOBILE DEVICE - An apparatus of storage medium for interface both USB host and USB OTG device is provided, including a USB module, a micro USB module, a control module, a storage module, where the control module is connected to the USB module, the micro USB module and the storage module, and provides signals to determine and control the data flow among the above modules. The apparatus can be connected to a USB host via the USB module and/or a USB OTG device via the micro USB module to access data in the storage module. The storage module can be realized as, for example, a pendrive module, a memory card reader with memory card, or a pendrive module plus a memory card reader with memory card. When connected to both a USB host and a USB OTG device simultaneously, the apparatus of the present invention can function as a USB cable. | 05-23-2013 |
| 20130132630 | SYSTEM AND METHOD FOR VIDEO ROUTING AND DISPLAY - A system and a method for video routing and display are provided. The system comprises a host, a video output apparatus and a graphic processing apparatus. The video output apparatus is connected to the host through a first transmission interface for respectively receives a video data and a video streaming through a first channel and a second channel of the first transmission interface. The graphic processing apparatus is connected to the video output apparatus through a second transmission interface, by which a third channel and a fourth channel of the second transmission interface are respectively connected to the first channel and the second channel of the first transmission interface. The graphic processing apparatus receives the video data in the first channel through the third channel, processes the video data, and transmits the processed video data to the video output apparatus through the fourth channel for outputting the processed video data. | 05-23-2013 |
| 20130132631 | SIGNAL COLLECTION SYSTEM AND METHOD WITH SIGNAL DELAY - An exemplary signal collection system includes a signal transmitting module, a computer, and a data collection card interconnecting the signal transmitting module and the computer. The signal transmitting module includes a signal source and a delay chip connected to the signal source. The delay chip receives a first path high-speed signal output from the signal source and transmits the first path high-speed signal to the data collection card in real time. The delay chip also generates a second path high-speed signal by delaying the first path high-speed signal and transmitting the second path high-speed signal to the data collection card. The data collection card transmits the high-speed signals output from the delay chip to the computer. A signal collection method based upon the signal collection system is also provided. | 05-23-2013 |
| 20130132632 | OPTICAL TRANSCEIVER HAVING RESET SEQUENCE - An electronic apparatus is disclosed where the apparatus provides the I2C bus and enables to resume the I2C bus even after the apparatus receives external RESET independent of the status of the I2C communication. A circuit unit communicating with the controller by the I2C bus, which is necessary to be reset, is further coupled with the controller by an internal RESET. The controller, receiving the external RESET, first completes the communication on the I2C bus, then sends the internal RESET to the circuit unit, finally resets itself. | 05-23-2013 |
| 20130138857 | Extensive Battery management system - Disclosed is an extensive battery management system for a second-used application automobile use batteries. The extensive battery management system includes a process unit, a record unit, an input interface and an output interface. The record unit is connected to the process unit so that the former stores data from the latter. The input interface is connected to the process unit. The output interface is connected to the process unit. | 05-30-2013 |
| 20130138858 | Providing A Sideband Message Interface For System On A Chip (SoC) - According to one embodiment, a system on a chip includes multiple agents each corresponding to an intellectual property (IP) logic and a fabric to couple the agents. The fabric can include a primary message interface and a sideband message interface. The fabric further includes one or more routers to provide out-of-band communications between the agents via this sideband message interface. To effect such communication, the router can perform a subset of ordering rules of a personal computer (PC)-based specification for sideband messages. Other embodiments are described and claimed. | 05-30-2013 |
| 20130138859 | SYSTEMS AND METHODS FOR INTEGRATING UNIVERSAL SERIAL BUS DEVICES - A mechanism for integrating Universal Serial Bus (USB) devices is disclosed. A method of the invention includes retrieving an identifier of the USB device connected to a computer system, matching the identifier with a device identification stored in a systems library of the computer system. The systems library includes an application identifier corresponding to the device identification and an attribute corresponding to the application identifier. The method also includes executing instructions associated with attribute corresponding to the application identifier associated with the device identification matched to the identifier. | 05-30-2013 |
| 20130145068 | UNIVERSAL SERIAL BUS DEVICE FOR HIGH-EFFICIENT TRANSMISSION - The present invention discloses a Universal Serial Bus (“USB”) device that includes an Ethernet port configured to receive a first Ethernet packet, and an input control circuit including a data register memory, a header register memory and an input data control circuit. The input data control circuit, upon receiving a first Ethernet packet, stores first packet data of the first Ethernet packet in the data register memory, transmits the first packet data to a USB host, and, in response to the transmission of the first packet data, stores first header data of the first Ethernet packet in the header register memory. | 06-06-2013 |
| 20130145069 | HARDWARE CONTROL INTERFACE FOR IEEE STANDARD 802.11 - A standardized 802.11 hardware control interface may be provided such that a driver may communicate with any one or more of a variety of network adapters. | 06-06-2013 |
| 20130145070 | METHOD OF DEBUGGING CONTROL FLOW IN A STREAM PROCESSOR - Disclosed is a method of monitoring operation of programmable logic for a streaming processor, the method comprising: generating a graph representing the programmable logic to be implemented in hardware, the graph comprising nodes and edges connecting nodes in the graph; inserting, on each edge, monitoring hardware to monitor flow of data along the edge. Also disclosed is a method of monitoring operation of programmable logic for a streaming processor, the method comprising: generating a graph representing the programmable logic to be implemented in hardware, the graph comprising nodes and edges connecting the nodes in the graph; inserting, on at least one edge, data-generating hardware arranged to receive data from an upstream node and generate data at known values having the same flow control pattern as the received data for onward transmission to a connected node. | 06-06-2013 |
| 20130159584 | DATA BUS INVERSION CODING - Techniques are disclosed relating to data inversion encoding. In one embodiment, an apparatus includes an interface circuit. The interface circuit is configured to perform first and second data bursts that include respective pluralities of data transmissions encoded using an inversion coding scheme. In such an embodiment, the initial data transmission of the second data burst is encoded using the final data transmission of the first data burst. In some embodiments, the first and second data bursts correspond to successive write operations or successive read operations to a memory module from a memory PHY. | 06-20-2013 |
| 20130159585 | CONTROL SYSTEM AND RELAY APPARATUS - A bus interface receives, via a bus, a control signal for controlling an electronic circuit, and outputs a signal corresponding to the received control signal to the electronic circuit. A signal maintaining circuit maintains the value of the signal to be output from the bus interface to the electronic circuit in accordance with an instruction from a reset control circuit. When the bus becomes unusable due to termination of operations of the control device or the like, the reset control circuit causes the signal maintaining circuit to maintain the value of the output signal to the electronic circuit, and subsequently resets the bus interface so as to restore the bus. | 06-20-2013 |
| 20130159586 | MOTOR VEHICLE CONTROL SYSTEM WITH SIMPLIFIED INFORMATION EXCHANGE - A control system includes a gateway controller and a remote controller. The gateway controller is configured to embed an HTTP request in a CAN bus-compatible message and transmit the CAN bus-compatible message onto a CAN bus. The remote controller is configured to receive the CAN bus-compatible message from the CAN bus, extract the HTTP request from the CAN bus-compatible message, and create an HTTP response to the HTTP request. | 06-20-2013 |
| 20130166809 | DRIVE CIRCUIT FOR PERIPHERAL COMPONENT INTERCONNECT-EXPRESS (PCIE) SLOTS - A drive circuit is used in an electronic device comprising multiple peripheral component interconnect-express (PCIE) slots. The drive circuit includes a motherboard, a first signal generation circuit, a second signal generation circuit, and a first delay circuit. The motherboard provides a control signal to the first signal generation circuit and the first delay circuit. The first signal generation circuit outputs immediate drive signals to first multiple PCIE slots. The first delay circuit outputs a first delay control signal to the second signal generation circuit after a predetermined time. The second signal generation circuit outputs drive signals to drive second multiple PCIE slots. | 06-27-2013 |
| 20130179619 | TWO PIN SERIAL BUS COMMUNICATION INTERFACE AND PROCESS - A two pin communication interface bus and control circuits are used with circuit boards, integrated circuits, or embedded cores within integrated circuits. One pin carries data bi-directionally and address and instruction information from a controller to a selected port. The other pin carries a clock signal from the controller to a target port or ports in or on the desired circuit or circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is minimal. The bus is used for communication, such as serial communication related to the functional operation of an IC or core design, or serial communication related to test, emulation, debug, and/or trace operations of an IC or core design. | 07-11-2013 |
| 20130191576 | COMPUTER SYSTEM AND METHOD FOR CONTROLLING ADDITIONAL CHASSIS ADDED TO COMPUTER SYSTEM - Regarding an additional storage chassis used by being connected to a basic chassis equipped with a storage controller, provided is a computer system capable of changing or updating a firmware environment of the additional storage chassis so that normal operation of the additional storage chassis can be secured on the user side even if the operation different from the operation, which was guaranteed at the time of factory shipment, is executed on the user. | 07-25-2013 |
| 20130198431 | DATA PROCESSING APPARATUS, INPUT CONTROL APPARATUS, AND CONTROL METHOD - An input control apparatus, which accepts input of data from the outside and inputs the data to a bus in a data processing system in which a plurality of communication units are connected by the bus in a ring shape and data processed by processing units are delivered via the bus, controls acceptance of data based on the number of data items which should be output outside, are suspended from output, and remain on the bus. | 08-01-2013 |
| 20130212312 | System Comprising a Bus, and Method to Transmit Data Over a Bus System - A system including a bus, and a method to transmit data over a bus system are disclosed. According to an embodiment, a method to transmit data over a bus system includes deliberately delaying the transmission of data. The deliberate delay caused by deliberately delaying the transmission of data may be chosen to predominate stochastic delay differences. | 08-15-2013 |
| 20130227189 | ELECTRONIC DEVICE WITH BUS SHARING FUNCTION - A electronic device includes a bus, two electronic elements connected to the bus, and a controller. Each of the two electronic element is designated a logic unit number (LUN) and a first temporary buffer identified by the LUN for storing messages transmitted from or to the corresponding electronic element by the bus. The controller for obtaining the LUN of the message transmitted from/to the at least two electronic element, determining the temporary buffer which the message is stored according to the obtained LUN, storing the message to the determined temporary buffer, and transmitting the message stored in the temporary buffer to the corresponding electronic element or processing the message stored in the temporary buffer. | 08-29-2013 |
| 20130238830 | BUS EXTENSION FRAMEWORK SYSTEM - A control system having a bus extension framework. The system may have a flexible and reuseable block mechanism which may integrate with block control structures, and yet provide connections over a low cost two-wire communications bus. A function block engine may extend to multiple devices such as sensors, actuators, In/output devices, wall modules, graphical displays, network storage mechanisms, and so on. The system may integrate with other graphical function block systems and extend with a simple connection to and from additional bus resources. A connection scheme may hide the complexity of the underlying communications and still permit multiple address devices to communicate to each other among function block host devices. Complexity of the underlying communications may be revealed graphically to a system operator in an under-the-hood view. A main host controller may have a proxy file that holds a data file on virtually all of the devices in the system. | 09-12-2013 |
| 20130254447 | AUTOMATION CONTROL COMPONENT - Embodiments of the present disclosure are directed toward an automation control device including a base having a module slot, a functional module including communication and control circuitry configured to communicatively couple with the base via the module slot, a terminal block configured to communicatively couple the base and the first functional module with field wiring, a first power bus configured to transmit a first power to the functional module, and a second power bus configured to transmit a second power to the functional module. | 09-26-2013 |
| 20130254448 | MICRO-LINK HIGH-BANDWIDTH CHIP-TO-CHIP BUS - A chip package includes a micro-link between components disposed on a substrate. The micro-link may be an ultra-short multi-conductor transmission line with shared reference planes that results in a distribution of impedance values. Furthermore, the composite signal traces in the transmission line each can support communication of one symbol at a time by ensuring that multiple reflections reach a substantial fraction of a steady-state value within a symbol time. In this way, the micro-link may facilitate continued scaling of the communication bandwidth between the components with low latency to increase the performance of computer systems that include the chip package. | 09-26-2013 |
| 20130262731 | SUPERSPEED INTER-CHIP COMMUNICATIONS - An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB 3.0 system interface and an M-PHY interface. | 10-03-2013 |
| 20130275644 | Method and Terminal for Starting Universal Serial USB State Machine - A method and terminal for starting a USB state machine are provided in the present document. The method includes: connecting a USB voltage bus pin to a logic level; if detecting that a voltage of a charging voltage pin is greater than a threshold limit value, starting a charging state machine and the USB state machine. In the present document, the USB state machine is started through a signal for detecting plug-in and pull-out of a charger, which can not only trigger the start-up of the USB state machine, but also possess a function of satisfying overvoltage protection, thereby the charger and the USB are enabled to share one physical interface with the simplest and securest method under the premise of guaranteeing the reliability. | 10-17-2013 |
| 20130275645 | ELECTRONIC DEVICE AND DATA TRANSMISSION METHOD - Embodiments of the present invention relate to electronic devices and data transmission methods. The electronic device includes: a first part including a first main board, a first processor connected to the first main board, at least one sharable hardware component and a first connector; and a second part including a second main board, a second processor connected to the second main board and a second connector corresponding to the first connector. The first part and the second part are connectable to each other via the first connector and the second connector. The first connector is configured to receive, from a first driving module of the hardware component, a first data sent from the hardware component via a first connector driving module, and transmit the first data to the second connector such that a second connector driving module can provide the first data from the second connector to a first application running in the second part via a second driving module of the hardware component. The present invention realizes simple and effective sharing of hardware component. | 10-17-2013 |
| 20130282944 | SAS INTEGRATION WITH TRAY AND MIDPLANE SERVER ARCHITECTURE - In computing scenarios involving multiple computational units, an enclosure (e.g., a rack or server cabinet) may store the units and provide resources such as shared power and network connectivity. Additionally, the components of the units may communicate through a Serial Attached SCSI (SAS) bus, but many such enclosures provide little or no integration with the SAS buses, thus entailing extensive SCSI cabling. Presented herein are architectures for enclosures presenting a set of slots for trays storing respective computing blades, where such trays include SAS connectors that connect directly (i.e., without cabling) with connectors on a midplane that interconnects the blades into a SAS bus featuring at least one integrated SAS expander. Additional architectural variations involve providing SAS expander on one or both of the midplane and the blades; grouping blades into subsets having distinct SAS buses; and interconnecting the SAS buses and expanders of multiple midplanes in the enclosure. | 10-24-2013 |
| 20130282945 | APPARATUS AND METHOD EMULATING A PARALLEL INTERFACE TO EFFECT PARALLEL DATA TRANSFER FROM SERIAL FLASH MEMORY - Apparatus and method emulating a parallel interface to effect parallel data transfer from serial flash memory are provided. A field-programmable gate array (FPGA) may be coupled to a processor via a data bus. A serial flash memory may be coupled to the FPGA via a serial interface. The FPGA may be programmed to emulate a parallel interface by converting a serial data stream of boot code or operating software received from the serial flash memory to a parallel data stream to effect parallel data transfer over the data bus to the processor. The FPGA may be responsive to respective logic signals set by the processor to start access to the serial flash memory by pointing to at least one predefined location corresponding to at least one starting address of data to be transferred to the processor without using a plurality of address lines to access the serial flash memory. | 10-24-2013 |
| 20130290593 | Interfacing a Switch Array - An interface circuit for a switch array having an array of switches, each closeable to couple a row conductor of a plurality of row conductors to a column conductor of one or more column conductors, comprises a current generator and a current detector. The current generator has a plurality of row interface ports for coupling to different ones of the row conductors and is arranged to generate a switch array current for coupling to the row interface ports, the switch array current having a different one of a plurality of different switch array current magnitudes for different ones of the row interface ports, and generate one or more reference currents each having a different reference current magnitude. The current detector has one or more column interface ports for coupling to the one or more column conductors and is arranged to detect the switch array current flowing at any one of the one or more column interface ports, and generate a row indication indicative of which of the row conductors a closed one of the switches is coupled to by determining which one of the switch array current magnitudes the detected switch array current has by comparing the detected switch array current with the one or more reference currents. | 10-31-2013 |
| 20130304960 | Apparatus, System and Method For Configuration of Adaptive Integrated Circuitry Having Fixed, Application Specific Computational Elements - The present invention concerns configuration of a new category of integrated circuitry for adaptive or reconfigurable computing. The preferred adaptive computing engine (ACE) IC includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, controller operations, memory operations, and bit-level manipulations. The preferred system embodiment includes an ACE integrated circuit coupled with the configuration information needed to provide an operating mode. Preferred methodologies include various means to generate and provide configuration information for various operating modes. | 11-14-2013 |
| 20130318273 | Wireless Communication Device and Method for Manufacturing Wireless Communication Device - The present invention provides a wireless communication device and a method for manufacturing a wireless communication device. The wireless communication device includes: an antenna; a main board, including a ground part, where the ground part is connected to the antenna; at least one matching network, connected to the ground part; a USB connector, including a shell and at least one first pin extending from the shell, where the at least one first pin is connected to the at least one matching network, and at least one first pin is one-to-one corresponding to at least one matching network. According to the present invention, a matching network may be connected between a pin of the USB connector of the wireless communication device and the ground part of the main board, and is configured to control wireless performance of an antenna radiation system of the wireless communication device. | 11-28-2013 |
| 20130318274 | Scalable Portable-Computer System - A scalable portable-computer system is disclosed. A novel portable-computer comprises a cluster connectivity bus, hard-wired to the central and graphics processing units (CPU and GPU, respectively) of said portable computer. | 11-28-2013 |
| 20130326105 | PROCESSOR WITH REAL-TIME SIGNAL TRANSMISSION AND STORAGE - A processor with real-time signal transmission and storage comprises a motherboard and a display. The motherboard has a power input end, a processing core, a signal input end, a storage device and an image output end. The power input end has one conducting wire to connect to the power source to provide power to the motherboard and a display; the processing core has a processing program inside and connect to the signal input end and the storage device; the signal input end provides a transmission line to connect an input end of a working unit; and the storage device provides space to save signals complied and organized by the processing core. The display has a signal connector to connect to the image output end of the motherboard. | 12-05-2013 |
| 20130339564 | Function Approximation Circuitry - Function approximation circuitry approximates an arbitrary function F over discrete inputs. Discrete values of the function F are stored in a lookup table (LUT) component for various inputs. An addressing module generates an address from an input. An interpolation factor module generates an interpolation factor from the input. An interpolation module generates an output, which is an approximate value of the function F for the input, from the interpolation factor, and from outputs of the LUT component when the LUT component is addressed by the address. | 12-19-2013 |
| 20130346663 | Generating Interface Adjustment Signals in a Device-To-Device Interconnection System - Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment circuits. | 12-26-2013 |
| 20130346664 | NON MAIN CPU/OS BASED OPERATIONAL ENVIRONMENT - A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based operational state. The computing system also includes a controller that operates functional tasks while the computing system is within the non main CPU/OS based operational state. The computing system also includes an I/O unit coupled to the main system bus that remains active while the computing system operates within the non main CPU/OS based operational state. | 12-26-2013 |
| 20140006670 | Controlling A Physical Link Of A First Protocol Using An Extended Capability Structure Of A Second Protocol | 01-02-2014 |
| 20140006671 | Location of Computing Assets within an Organization | 01-02-2014 |
| 20140006672 | Location of Computing Assets within an Organization | 01-02-2014 |
| 20140025858 | Recursive Lookup with a Hardware Trie Structure that has no Sequential Logic Elements - A hardware trie structure includes a tree of internal node circuits and leaf node circuits. Each internal node is configured by a corresponding multi-bit node control value (NCV). Each leaf node can output a corresponding result value (RV). An input value (IV) supplied onto input leads of the trie causes signals to propagate through the trie such that one of the leaf nodes outputs one of the RVs onto output leads of the trie. In a transactional memory, a memory stores a set of NCVs and RVs. In response to a lookup command, the NCVs and RVs are read out of memory and are used to configure the trie. The IV of the lookup is supplied to the input leads, and the trie looks up an RV. A non-final RV initiates another lookup in a recursive fashion, whereas a final RV is returned as the result of the lookup command. | 01-23-2014 |
| 20140032807 | METHOD AND SYSTEM FOR MULTIPLE SERVERS TO SHARE A POSTAL SECURITY DEVICE - Systems and methods that allow a PSD to be physically shared by multiple servers such that if a server fails, another server can be utilized as a backup server for the PSD without any manual intervention or moving of the PSD and without risking loss of data from the PSD. A PSD is interfaced by an interface device to a system level bus that allows for multiple initiators. An initiator is any server that can access and issue commands over the system level bus to access the PSD. When one of the servers fails, the functionality of the server can be rolled to a backup server which will be able to access the PSD over the bus. | 01-30-2014 |
| 20140040523 | MINIMIZING THE AMOUNT OF TIME STAMP INFORMATION REPORTED WITH INSTRUMENTATION DATA - This invention is time stamping subsystem of an electronic apparatus. A time stamp generator generates a multibit time stamp value including a predetermined number of least significant bits overlapping a predetermined number of most significant bits. Each client receives the least significant bits. Each client associates captured data with a corresponding set of the least significant bits in a message. A central scheduling unit associates most significant bits of the time stamp value with the least significant bits of the message. This associating compares overlap bits of the most significant bits and least significant bits. The most significant bits are decremented until the overlap bits are equal. | 02-06-2014 |
| 20140047152 | Data communication interface for an agricultural utility vehicle - A data communication interface for an agricultural utility vehicle, particularly an agricultural tractor, having an interface connector that can be connected either to a first data communication network or to a second data communication network by means of an electrically operatable changeover device, wherein the first data communication network is terminated at a line end associated with the interface connector by means of a disconnectable terminating resistor, and having a control unit that connects the interface connector to the first data communication network by means of appropriate operating of the changeover device exclusively when it infers the presence of a control signal that is provided for disconnecting the terminating resistor. | 02-13-2014 |
| 20140068130 | INFORMATION PROCESSING APPARATUS AND CONTROLLING METHOD - A control circuit performs control to initialize a plurality of interface circuits connected to a communication circuit and each connected to each of a plurality of communication lines, and detects whether or not initialization of each of the interface circuits has been completed. When the control circuit detects that initialization of all of the interface circuits has been completed, the control circuit controls the communication circuit so as to start data communication via the interface circuits. | 03-06-2014 |
| 20140075076 | Overclocked Line Rate for Communication with PHY Interfaces - A system side interface of a PHY chip used in conjunction with a 100GBASE backplane, sends and receives data using an NRZ signal format, but at a data rate of between about 26.5 Gbps/per lane to 27.2 Gbps/per lane, which is consistent with the PAM 4 signaling protocol. Thus, chip-to-chip communications between a PHY chip and a switch or controller chip can use an “overclocked” NRZ signaling format, reducing the amount of logic needed, which in turn can reduce signal latency, and reduce the chip area and power consumption required to implement the logic. | 03-13-2014 |
| 20140075077 | Bus Node and Control System for Controlling a Work Machine - A bus node for an electric coupling of a bus system to a functional module arrangement, having an electronic circuit for converting electrical signals between a bus protocol provided by the bus system and an internal communications protocol provided by the functional module arrangement, and having a first coupling means for electrically connecting the electronic circuit to the functional module arrangement, and having a second coupling means for electrically connecting the electronic circuit to the bus system, wherein the first coupling means comprises a first contact means that is configured for a direct electrical contact with a ground connection of the functional module arrangement. | 03-13-2014 |
| 20140089548 | Systems, Methods, and Articles of Manufacture To Stream Data - Systems and methods for streaming data. Systems allow read/write across multiple or N device modules. Device modules on a bus ring configure at power up (during initialization process); this process informs each device module of its associated address values. Each ringed device module analyzes an address indicator word, which identifies an address at which a read/write operation is intended for, and compares the address designated by the address indicator word to its assigned addresses; when the address designated by the address indicator word is an address associated with the device module, the device module read/writes from/to the address designated by the address indicator word. Memory controller (ring controller or master bus) is not required to ‘know’ which memory chip/device module in a daisy chain the address command word is intended for. Therefore, system embodiments allow streaming without consideration of a number of memory chips/device modules on bus. The bus isolates modules like object oriented programming. | 03-27-2014 |
| 20140089549 | NON-LINEAR TERMINATION FOR AN ON-PACKAGE INPUT/OUTPUT ARCHITECTURE - An on-package interface. A first set of single-ended transmitter circuits on a first die. A first set of single-ended receiver circuits on a second die. The receiver circuits have a termination circuit comprising an inverter and a resistive feedback element. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines arc matched. | 03-27-2014 |
| 20140095756 | HIGH-SPEED DATA TRANSMISSION INTERFACE CIRCUIT AND DESIGN METHOD OF THE SAME - A high-speed data transmission interface circuit used in a network switch device is provided. The high-speed data transmission interface circuit comprises a main circuit hoard, a connector and a daughter circuit board. The main circuit board comprises a transmission port interface module and a first wire. The transmission port interface module comprises a reduced pin extended attachment unit interface (RXAUI). The first wire connects the connector and the main circuit board. The daughter circuit board comprises a high definition multimedia interface (HDMI) module and a second wire. The HDMI module is connected to an external network device through a HDMI signal wire. The second wire connects the connector and the HDMI module. The transmission port interface module communicates with the external network device through the connector and the daughter board. | 04-03-2014 |
| 20140095757 | MICROCONTROLLER PROGRAMMABLE SYSTEM ON A CHIP WITH PROGRAMMABLE INTERCONNECT - Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks. | 04-03-2014 |
| 20140108695 | INTERFACE LOGIC FOR A MULTI-CORE SYSTEM-ON-A-CHIP (SOC) - In one embodiment, the present invention includes a system-on-a-chip (SoC) with first and second cores, interface logic coupled to the cores, chipset logic coupled to the interface logic, and a virtual firewall logic coupled between the chipset logic and the second core. The interface logic may include a firewall logic, a bus logic, and a test logic, and the chipset logic may include a memory controller to provide for communication with a memory coupled to the SoC. In some system implementations, both during test operations and functional operations, the second core can be disabled during normal operation to provide for a single core SoC, enabling greater flexibility of use of the SoC in many different implementations. Other embodiments are described and claimed. | 04-17-2014 |
| 20140115218 | ASYMMETRIC MESH NoC TOPOLOGIES - A method of interconnecting blocks of heterogeneous dimensions using a NoC interconnect with sparse mesh topology includes determining a size of a mesh reference grid based on dimensions of the chip, dimensions of the blocks of heterogeneous dimensions, relative placement of the blocks and a number of host ports required for each of the blocks of heterogeneous dimensions, overlaying the blocks of heterogeneous dimensions on the mesh reference grid based on based on a guidance floor plan for placement of the blocks of heterogeneous dimensions, removing ones of a plurality of nodes and corresponding ones of links to the ones of the plurality of nodes which are blocked by the overlaid blocks of heterogeneous dimensions, based on porosity information of the blocks of heterogeneous dimensions, and mapping inter-block communication of the network-on-chip architecture over remaining ones of the nodes and corresponding remaining ones of the links. | 04-24-2014 |
| 20140115219 | GENERAL INPUT/OUTPUT ARCHITECTURE, PROTOCOL AND RELATED METHODS TO IMPLEMENT FLOW CONTROL - An enhanced general input/output communication architecture, protocol and related methods are presented. | 04-24-2014 |
| 20140122762 | APPLICATION MERGING SYSTEM FOR MULTIPLE PLATFORMS FPGA OF A SAME SERIES - Provided is a Field Programmable Gate Array (FPGA) application merging system for multiple platforms of a same series, which is used in a testing or manufacturing system comprising an adapter and at least two platforms. The FPGA application merging system comprises: at least two functional modules corresponding to the at least two platforms respectively; an IO selector connected to the at least two functional modules respectively, configured to select one of the at least two functional modules adaptively; and an IO attribute controller connected to the IO selector, configured to select an attribute in accordance with the selected functional module, wherein each IO has a three-state logic attribute. The FPGA application merging system may significantly reduce the cost of the FPGA version in later development, maintenance, storage, upgrading and so on, mitigate the difficulty of storage, loading and other operations on the board, and significantly increase the operation efficiency. | 05-01-2014 |
| 20140122763 | TWO PIN SERIAL BUS COMMUNICATION INTERFACE AND PROCESS - A two pin communication interface bus and control circuits are used with circuit boards, integrated circuits, or embedded cores within integrated circuits. One pin carries data bi-directionally and address and instruction information from a controller to a selected port. The other pin carries a clock signal from the controller to a target port or ports in or on the desired circuit or circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is minimal. The bus is used for communication, such as serial communication related to the functional operation of an IC or core design, or serial communication related to test, emulation, debug, and/or trace operations of an IC or core design. | 05-01-2014 |
| 20140129755 | EXTERNAL BOOST OF PROCESSING THROUGH A DATA PROCESSING DEVICE - A method includes providing a non-motherboard level Input/Output (I/O) interface in a data processing device including a processor communicatively coupled to a memory, and providing a driver component of an external processor in the memory of the data processing device and/or a memory associated with the external processor. The method also includes installing the driver component in the data processing device to render the data processing device compatible with the external processor, and coupling the external processor to the data processing device through the non-motherboard level I/O interface to provide boosting of processing through the data processing device, thereby dispensing with a need to make a motherboard level modification in the data processing device therefore. | 05-08-2014 |
| 20140136747 | ELECTRONIC DEVICE AND DEVICE ACCESS METHOD - An electronic device includes a device connected to a bus controller, a memory that stores a program, and a processing unit that executes access to the device through the bus controller according to the program. The processing unit generates a prediction value of executing access to the device based on the result of executing access in the past in parallel with the access to the device, and executes, prior to completing access to the device, using the prediction value of the execution of the access to the device, post-processing of the access to the device using the result of executing access to the device when a number of times which the result of executing access in the past matches a prediction value of execution of access in the past reaches a specified number of times. | 05-15-2014 |
| 20140149624 | Method for Determining a Serial Attached Small Computer System Interface Topology - A method for determining a topology based on input/output criteria includes selecting a predefined topology, measuring the fitness of the topology, and breeding individuals from the topology by combining elements from the fittest individuals. The topology is then updated with the new individuals and the fitness of the new topology is measured. Iterations continue similarly until certain criteria are met. | 05-29-2014 |
| 20140156899 | BROADCAST SERIAL BUS TERMINATION - A subsea broadcast serial bus system includes a broadcast serial bus having a first signal line and a second signal line. One or more nodes are connected in parallel to the first signal line and the second signal line of the broadcast serial bus. Each node connects the first signal line to the second signal line via a node impedance. A subsea node connected to the broadcast serial bus includes an adjustable impedance that may be adjusted based on the number of nodes connected to the broadcast serial bus. | 06-05-2014 |
| 20140156900 | MODULAR CONTROL APPARATUS - A control apparatus has a number of modules arranged next to one another in a longitudinal direction. The modules each comprise at least one module part having a housing. Furthermore, the module part comprises a first electrical bus connector on a first side of the housing for electrical connection to a first neighboring module part adjacent in the longitudinal direction, and a second electrical bus connector on a second side, opposite the first side, of the housing for electrical connection to a second neighboring module part adjacent in the longitudinal direction. The module part further comprises at least one movable element, movable between a first position and a second position. In the first position, the movable element provides an electrical connection between the first bus connector and the second bus connector and, in the second position, provides an insulation point between the first bus connector and the second bus connector. | 06-05-2014 |
| 20140156901 | COMPUTING DEVICE, A SYSTEM AND A METHOD FOR PARALLEL PROCESSING OF DATA STREAMS - An apparatus for identification of an input data against one or more learned signals is provided. The apparatus comprising a number of computational cores, each core comprises properties having at least some statistical independency from other of the computational, the properties being set independently of each other core, each core being able to independently produce an output indicating recognition of a previously learned signal, the apparatus being further configured to process the produced outputs from the number of computational cores and determining an identification of the input data based the produced outputs. | 06-05-2014 |
| 20140164664 | ORTHOGONAL LAYOUT GENERATION - An orthogonal layout generation method can include receiving, in a computer system, data related to a plurality of devices for a schematic layout, generating, in the computer system, a node for each of the plurality of devices, hereby generating a plurality of nodes, generating, in the computer system, a link for each of the plurality of nodes, thereby generating a plurality of links, orthogonalizing, in the computer system, the plurality of nodes, initializing, in the computer system, a route for each of the plurality of links, thereby generating a plurality of routes, orthogonalizing, in the computer system, the routes and selecting, in the computer system, a direction for each of the plurality of routes. | 06-12-2014 |
| 20140164665 | DEVICE FOR EXCHANGING DATA BETWEEN AT LEAST TWO APPLICATIONS - A device for exchanging data between at least two data consuming and/or emitting applications, has two modules with input/outputs connected to a corresponding application each including two internal communication submodules respectively for emission and for reception; a control module; a synchronization clock; and a closed-loop transmission line, each submodule for emission including an emission FSM circuit with an emission request output connected to the module, an emission authorization request input connected to an output of the module, and an output interface for data attached to the application A | 06-12-2014 |
| 20140173156 | CABLE ADAPTER CORRELATION IN A CLUSTER - A verified cluster configuration is collected and stored by a central management entity. Servers within the cluster are connected to network cables, where each of the servers has at least one network port and memory storing a port identification code for each network port, and where each network cable has memory storing a cable identification code. For each verified connection between a network cable and a network port, the port identification code is stored in the memory of the network cable and the cable identification code is stored in the memory of the corresponding server. The data identifying each connection is stored by the central management entity and includes the port identification code for a particular network port in association with the network cable identification code for the corresponding network cable. Any miswiring of the configuration is identified by the central management entity and easily corrected by the administrator. | 06-19-2014 |
| 20140173157 | COMPUTING ENCLOSURE BACKPLANE WITH FLEXIBLE NETWORK SUPPORT - Computing unit enclosures are often configured to connect units (e.g., server racks or trays) with a wired network. Because the network type may vary (e.g., Ethernet, InfiniBand, and Fibre Channel), such enclosures often provide network resources connecting each unit with each supported network type. However, such architectures may present inefficiencies such as unused network resources, and may constrain network support for the units to a small set of supported network types. Presented herein are enclosure architectures enabling flexible and efficient network support by including a backplane comprising a backplane bus that exchanges data between the units and a network adapter using an expansion bus protocol, such as PCI-Express. By shifting the point of network specialization from the enclosure to the network adapter, such architectures may be compatible with network adapters of any network type that communicate with the units according to a widely supported and network-type-independent expansion bus protocol. | 06-19-2014 |
| 20140173158 | Rate of Transfer of Data Within A Plasma System - A bus interconnect interfaces a host system to a radio frequency (RF) generator that is coupled to a plasma chamber. The bus interconnect includes a first set of host ports, which are used to provide a power component setting and a frequency component setting to the RF generator. The ports of the first set of host ports are used to receive distinct variables that change over time. The bus interconnect further includes a second set of generator ports used to send a power read back value and a frequency read back value to the host system. The bus interconnect includes a sampler circuit integrated with the host system. The sampler circuit is configured to sample signals at the ports of the first set at selected clock edges to capture operating state data of the plasma chamber and the RF generator. | 06-19-2014 |
| 20140173159 | EXPRESSCARD ADAPTER AND ELECTRONIC DEVICE - An ExpressCard adapter able to accept a PCI-E-type or a USB-type ExpressCard in a single ExpressCard slot includes the ExpressCard slot, a PCI-E port, a data conversion unit, a switch unit, and a detection unit. The data conversion unit is connected to the PCI-E port, and converts between USB data and PCI-E data. The switch unit connects the ExpressCard slot to the PCI-E port or to the data conversion unit. The detection unit detects the type of ExpressCard which is inserted and controls the switch unit to connect the ExpressCard slot either to the PCI-E port or to the data conversion unit as required. | 06-19-2014 |
| 20140173160 | Innovative Structure for the Register Group - A processing circuit comprises a plurality of modules connected in series to form a module pipeline. Each module comprises one or more registers having corresponding addresses within an address range for the module. A register request, including a target register address, is passed from one module to succeeding modules down the module pipeline until the register request is received at the module containing the targeted register. Data is written into or read out from the targeted register. | 06-19-2014 |
| 20140181348 | CROSSTALK AWARE DECODING FOR A DATA BUS - Techniques for decoding encoded data are described herein. An example of a device in accordance with the present techniques includes a receiving signaling module coupled to a plurality of signal lines. The signaling module includes a receiver to receive a plurality of encoded line voltages or currents on the plurality of signal lines of a bus, wherein each one of the plurality of encoded line voltages corresponds to a weighted sum of data. The signaling module includes a comparator to determine the voltage level of each line at a unit interval and convert the voltage level to a digital value. The signaling module includes a lookup table correlating the digital value with a digital bit stream. | 06-26-2014 |
| 20140215115 | Device for Distributing Data About a Vehicle - A device for distributing data about a vehicle, has a first sensor data reception interface for receiving first sensor data from a first sensor, a second sensor data reception interface for receiving second sensor data from a second sensor, and a transmission interface for transmitting the data about the vehicle on the basis of the first sensor data and the second sensor data to a receiver. A vehicle and an on-board system which incorporate the devise are also encompassed herein. | 07-31-2014 |
| 20140244883 | SYSTEMS AND METHODS FOR IMPEDANCE MATCHING FOR MULTI-DROP TOPOLOGIES - In accordance with embodiments of the present disclosure, a system may include a driver, a plurality of drops, and a plurality of transmission lines, including one transmission line between the driver and one of the plurality of drops and one transmission line between successive adjacent drops. Each particular transmission line of the plurality of transmission lines may be manufactured to have a desired impedance based on a corresponding effective impedance as seen at a drop located on an end of the particular transmission line furthest from the driver in a direction away from the driver. | 08-28-2014 |
| 20140244884 | Multi-slot multi-point audio interface - An apparatus includes multiple media processing modules and a control unit. The media processing modules are configured to exchange digital media signals over a shared bus. The control unit is configured to determine a desired connectivity scheme among the media processing modules, to adaptively define, based on the desired connectivity scheme, connections that transfer the media signals among the media processing modules over the shared bus, and to instruct the media processing modules to establish the connections, by communicating with the media processing modules over a control interface that is independent of the shared bus. | 08-28-2014 |
| 20140281097 | SEMICONDUCTOR DEVICE AND MEMORY SYSTEM - A semiconductor device capable of communicating with a host apparatus includes a symbol generation unit, a coding unit, and a transmission unit. The symbol generation unit includes a random number generation circuit and generates a symbol according to a random number generated by the random number generation circuit. The coding unit performs 8b/10b coding for the symbol. The transmission unit transmits the symbol coded by the 8b/10b coding unit to the host apparatus. | 09-18-2014 |
| 20140304448 | GENERAL INPUT/OUTPUT ARCHITECTURE, PROTOCOL AND RELATED METHODS TO IMPLEMENT FLOW CONTROL - An enhanced general input/output communication architecture, protocol and related methods are presented. | 10-09-2014 |
| 20140317330 | TWO WIRE SERIAL VOLTAGE IDENTIFICATION PROTOCOL - In one embodiment a system comprises an integrated circuit, a plurality of voltage regulators; and a data bus coupled to the integrated circuit and the plurality of voltage regulators. In some embodiments the integrated circuit comprises logic to embed a timing signal on the data bus. Other embodiments may be described. | 10-23-2014 |
| 20140344496 | SYSTEMS AND METHODS FOR DATA COMMUNICATION - A data communication system is provided. The data communication system includes a data bus, and a line replacement unit including a terminal controller, and a plastic optical fiber serial interface module (POFSIM) coupled between the terminal controller and the data bus. The POFSIM is configured to transmit digital optical signals to the data bus based on electrical signals received from the terminal controller, and transmit electrical signals to the terminal controller based on digital optical signals received from the data bus. | 11-20-2014 |
| 20140344497 | ENABLING ARRANGEMENT FOR AN ELECTRONIC DEVICE WITH HOUSING-INTEGRATED FUNCTIONALITIES AND METHOD THEREFOR - An electronic device includes a housing, or a ‘cover’, the housing material molded into a desired target shape and to at least partially embed a plurality of functional elements and an enabling arrangement, optionally at least partially embedded in the housing, the enabling arrangement including: a first connector with a first plurality of connecting elements to establish a connection between the plurality of functional elements and the enabling arrangement, a second connector with one or more second connecting elements to be connected a host device utilizing the functionalities associated with the functional elements, a memory for storing and retrieval of instructions, and processing elements capable of transforming signals from a one known format to another predetermined format according to stored instructions. A corresponding method is presented. | 11-20-2014 |
| 20140351481 | OFFLOADING OF COMPUTATION FOR RACK LEVEL SERVERS AND CORRESPONDING METHODS AND SYSTEMS - A distributed server system is disclosed that can handle multiple networked applications. A system can include at least one main processor; a plurality of offload processors connected to a memory bus; and a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, with the virtual switch configured to receive memory read/write data over the memory bus. | 11-27-2014 |
| 20140359189 | SYSTEMS AND METHODS FOR PROVIDING CONNECTIONS TO AN INFORMATION HANDLING SYSTEM - In accordance with embodiments of the present disclosure, an interface for an information handling system comprising a connector, wherein the connector comprises a legacy portion and an expanded portion. The legacy portion may comprise a plurality of signal pins defining a first set of lanes of communication between the information handling system and an information handling resource coupled to the connector. The expanded portion comprising a plurality of signal pins defining a second set of lanes of communication between the information handling system and an information handling resource coupled to the expanded portion. | 12-04-2014 |
| 20140365702 | SENSOR NETWORK USING PULSE WIDTH MODULATED SIGNALS - A device includes a bus interface to couple to a shared bus of a sensor network. The device also includes a sensor interface to couple to a sensor of the sensor network. The device further includes a gated pulse width modulation circuit coupled to the bus interface and to the sensor interface. The gated pulse width modulation circuit is configured to transmit, during a time slot determined based on a timing signal received via the shared bus, an analog pulse width modulated representation of a signal received from the sensor. | 12-11-2014 |
| 20140372653 | Storage Device with Multiple Interfaces and Multiple Levels of Data Protection and Related Method Thereof - A storage device with multiple interfaces and multiple levels of data protection includes a first memory area and a second memory area utilizing data protection for protecting second data stored in the second memory area, the second memory area being distinct from the first memory area. The storage device also includes a first interface through which the storage device writes first data into the first memory area or reads first data stored in the first memory area and a second interface through which the storage device writes second data into the second memory area or reads second data stored in the second memory area, the second interface being distinct from the first interface. A controller controls access to the first memory area and the second memory area, and the second memory area is inaccessible through the first interface. | 12-18-2014 |
| 20140372654 | BRIDGE CIRCUITRY FOR COMMUNICATIONS WITH DYNAMICALLY RECONFIGURABLE CIRCUITS - A bridge circuit may be used to interface between dynamically reconfigurable circuitry and dedicated circuitry or other circuitry having static configurations during normal operation of the device. The bridge circuit may include interface circuitry coupled between first and second interfaces that communicate with the dynamically reconfigurable circuitry and the dedicated circuitry. Control circuitry may control the interface circuitry based on variable communications requirements of the second interface without interrupting communications with the dedicated circuitry at the first interface. The variable communications requirements may be dependent on which configuration of the dynamically reconfigurable circuitry is currently implemented. | 12-18-2014 |
| 20150026379 | GENERIC METHOD TO BUILD VIRTUAL PCI DEVICE AND VIRTUAL MMIO DEVICE - A technology for implementing a method to build a virtual device as at least one of a virtual Peripheral Controller Interconnect (PCI) device or a virtual Input/Output (I/O) device is disclosed. A method of the disclosure includes receiving a request for a PCI compatible device. The method further includes building a virtual device based on the request for the PCI compatible device, where the virtual device is built as at least one of a virtual PCI device or a virtual I/O device. | 01-22-2015 |
| 20150032929 | CIRCUITRY FOR A COMPUTING SYSTEM, LSU ARRANGEMENT AND MEMORY ARRANGEMENT AS WELL AS COMPUTING SYSTEM - A circuitry for a computing system comprising a first load/store unit, LSU, and a second LSU as well as a memory arrangement. The first LSU is connected to the memory arrangement via a first bus arrangement comprising a first write bus and a first read bus. The second LSU is connected to the memory arrangement via a second bus arrangement comprising a second write bus and a second read bus. The computing system is arranged to carry out a multiple load instruction to read data via the first read bus and the second read bus and/or to carry out a multiple store instruction to write data via the first write bus and the second write bus. | 01-29-2015 |
| 20150032930 | Hardware abstract data structure, data processing method and system - A Hardware Abstract Data Structure (HADS) includes a General Interface (GI), a Coherence Interface (CI), a Control and Configuration Logic (CCL), an Intelligence Logic (IL) and a Memory Pool (MP), wherein the GI is arranged to implement intercommunion between the HADS and a processor; the CI is arranged to implement coherence storage between multiple processors; the CCL is arranged to, in response to a command received by the GI, configure a hardware data structure for the MP; the IL is arranged to complete a large amount of simple and frequent data processing; and the MP is arranged to store data. Correspondingly, a method and data processing system are also disclosed. Through the disclosure, the HADS which is dynamically configurable, flexible, efficient, universal in interface and good in interconnectivity can be implemented to improve the data processing efficiency. | 01-29-2015 |
| 20150039801 | LIN Bus Module - One aspect of the invention relates to a network node for connecting to a Local Interconnect Network (LIN). In accordance with one example of the present invention, the network node includes a bus terminal which is operably coupled to a data line for receiving a data signal, which represents serial data, via that data line. The data signal is a binary signal having high and low signal levels. The network node further includes a receiver circuit which employs a comparator to compare the data signal with a reference signal. The comparator generates a binary output signal representing the result of the comparison. The network node also includes a measurement circuit that receives the data signal and provides a first voltage signal such that it represents the high signal level of the data signal. | 02-05-2015 |
| 20150089107 | Providing A Serial Protocol For A Bidirectional Serial Interconnect - In one embodiment, the present invention includes a host controller with transmit logic to prepare data into a packet for communication along an interconnect and to transmit the packet. This packet may include a preamble portion having a first predetermined value, a content portion including the data and having a plurality of symbols each including a start bit separate from the data, an error detection portion including an inverted version of the content portion, and a postamble portion having a second predetermined value. Other embodiments are described and claimed. | 03-26-2015 |
| 20150089108 | CLOCK SIGNALS FOR DYNAMIC RECONFIGURATION OF COMMUNICATION LINK BUNDLES - In at least some embodiments, an electronic device includes a processor and a memory coupled to the processor. The electronic device also includes a serial communication link controller coupled to the processor, the serial communication link controller supporting dynamic reconfiguration of a plurality of communication link bundles. The serial communication link controller receives an input clock and generates first and second clock signals based on the input clock, the first and second clock signals having different clock rates and being provided to each of a plurality of communication link bundles. | 03-26-2015 |
| 20150095541 | METHOD AND SYSTEM FOR ENUMERATING DIGITAL CIRCUITS IN A SYSTEM-ON-A-CHIP (SOC) - Methods and systems for enumerating digital circuits in a system-on-a-chip (SOC) are disclosed. The method includes incrementing an enumeration value received from a previous enumerable instance to uniquely identify an immediately adjacent enumerable instance of a plurality of enumerable instances in a daisy chain configuration. | 04-02-2015 |
| 20150095542 | COLLECTIVE COMMUNICATIONS APPARATUS AND METHOD FOR PARALLEL SYSTEMS - A collective communication apparatus and method for parallel computing systems. For example, one embodiment of an apparatus comprises a plurality of processor elements (PEs); collective interconnect logic to dynamically form a virtual collective interconnect (VCI) between the PEs at runtime without global communication among all of the PEs, the VCI defining a logical topology between the PEs in which each PE is directly communicatively coupled to a only a subset of the remaining PEs; and execution logic to execute collective operations across the PEs, wherein one or more of the PEs receive first results from a first portion of the subset of the remaining PEs, perform a portion of the collective operations, and provide second results to a second portion of the subset of the remaining PEs. | 04-02-2015 |
| 20150120981 | Data Interface for Point-to-Point Communications Between Devices - A data interface is provided for point-to-point communications between two devices, such as a read channel and a disk controller in an HDD system. An interface for communications from a transmitting device to a receiving device comprises a data bus configured to communicate m bits of data and a corresponding n bit data tag, wherein a given n bit data tag identifies a data type of a corresponding m bits of data on the data bus. An acknowledge signal from the receiving device optionally indicates that data on the data bus has been received and that the data on the data bus can be changed to a new value. A valid flag optionally indicates when a new predefined m-bit data value and corresponding n-bit tag value are on the data bus. | 04-30-2015 |
| 20150301973 | VARIABLE INTERCONNECT PITCH FOR IMPROVED PERFORMANCE - A method of designing conductive interconnects includes determining a residual spacing value based at least in part on an integer multiple of a interconnect trace pitch and a designated cell height. The method also includes allocating the residual spacing to at least one interconnect trace width or interconnect trace space within the interconnect trace pitch. | 10-22-2015 |
| 20150317270 | SEMICONDUCTOR DEVICE AND MEMORY SYSTEM - A semiconductor device capable of communicating with a host apparatus includes a symbol generation unit, a coding unit, and a transmission unit. The symbol generation unit includes a random number generation circuit and generates a symbol according to a random number generated by the random number generation circuit. The coding unit performs 8b/10b coding for the symbol. The transmission unit transmits the symbol coded by the 8b/10b coding unit to the host apparatus. | 11-05-2015 |
| 20150331820 | N-FACTORIAL VOLTAGE MODE DRIVER - System, methods and apparatus are described that provide an N-factorial (N!) voltage-mode driver. A method communicating on an N! interface includes encoding data in a symbol to be transmitted over the N wires of the interface, and for each wire of the N wires, calculating a resultant current for the wire by summing current flows defined for two or more two-wire combinations that include the wire, and coupling a switchable voltage source to the each wire. Each bit in the symbol defines a current flow between a pair of the N wires that is one of a plurality of possible two-wire combinations of the N wires. The switchable voltage source may be selected from a plurality of switchable voltage sources in order to provide a current in the each wire that is proportionate to the resultant current | 11-19-2015 |
| 20160070667 | SYSTEM FOR DESIGNING NETWORK ON CHIP INTERCONNECT ARRANGEMENTS - A system for designing Network-on-Chip interconnect arrangements includes a Network-on-Chip backbone with a plurality of backbone ports and a set of functional clusters of aggregated IPs providing respective sets of System-on-Chip functions. The functional clusters include respective sub-networks attachable to any of the backbone ports and to any other functional cluster in the set of functional clusters independently of the source map of the Network-on-Chip backbone. | 03-10-2016 |
| 20160132439 | EXPANDABLE ASYMMETRIC-CHANNEL MEMORY SYSTEM - An expandable memory system that enables a fixed signaling bandwidth to be configurably re-allocated among dedicated memory channels. Memory channels having progressively reduced widths are dedicated to respective memory sockets, thus enabling point-to-point signaling with respect to each memory socket without signal-compromising traversal of unloaded sockets or costly replication of a full-width memory channel for each socket. | 05-12-2016 |
| 20160149723 | SIGNALING CONTROL AMONG MULTIPLE COMMUNICATION INTERFACES OF AN ELECTRONIC DEVICE BASED ON SIGNAL PRIORITY - The present disclosure provides signaling control among multiple communication interfaces of an electronic device based on signal priority. According to an aspect, an electronic device includes multiple communication interfaces. The electronic device also includes a communication controller configured to determine priority of signals to be communicated on different communication interfaces among the plurality of communication interfaces. Further, the communication controller is configured to determine an order of communication of the signals among the different communication interfaces based on the priority of the signals to be communicated. The communication controller is also configured to control communication of the signals among the different communication interfaces based on the determined order of communication. | 05-26-2016 |
| 20160161980 | PERIPHERAL INTERFACE CIRCUIT AT HOST SIDE AND ELECTRONIC SYSTEM USING THE SAME - A peripheral interface circuit at host side and an electronic system using the same is disclosed. The peripheral interface circuit has a bus clock signal generator and a data register. The bus clock signal generator outputs a bus clock signal based on a host clock signal to be conveyed to a peripheral device via an interface bus as a reference for the peripheral device to output data. The data register receives the data output from the peripheral device and retrieved at the host side in accordance with the host clock signal. The bus clock signal generator adjusts the bus clock signal based on how the host clock signal is phase-asynchronous to the data output from the peripheral device and retrieved at the host side in accordance with the host clock signal. | 06-09-2016 |
| 20160162423 | N-PHASE SIGNAL TRANSITION ALIGNMENT - System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Information is transmitted in N-phase polarity encoded symbols. Drivers may be adapted or configured to align state transitions on two or more connectors in order to minimize a transition period between consecutive symbols. The drivers may include circuits that advance or delay certain transitions. The drivers may include pre-emphasis circuits that operate to drive the state of a connector for a portion of the transition period, even when the connector is transitioned to an undriven state. | 06-09-2016 |
| 20160170922 | AUTOMATION DEVICE AND METHOD FOR OPERATING THE SAME | 06-16-2016 |
| 20160170924 | Memory with Alternative Command Interfaces | 06-16-2016 |
| 20160170925 | Multi-processor with selectively interconnected memory units | 06-16-2016 |
| 20160188498 | Memory System Topologies Including A Buffer Device And An Integrated Circuit Memory Device - Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization. | 06-30-2016 |
| 20160253283 | MULTI-FUNCTION PORTS ON A COMPUTING DEVICE | 09-01-2016 |
