Entries |
Document | Title | Date |
20080215789 | Data transfer control device and electronic instrument - A data transfer control device includes a PATA I/F connected to a PATA bus, a SATA I/F connected to a SATA bus, and a sequence controller that controls a transfer sequence. The PATA I/F includes a task file register that is a pseudo register provided to implement a PATA/SATA bus bridge, and the SATA I/F includes a shadow task file register, a register value being transferred between the shadow task file register and the task file register. | 09-04-2008 |
20080215790 | Memory systems for automated computing machinery - Design structures embodied in machine readable medium are provided. Embodiments of the design structure include a memory system comprising: a memory controller; a memory bus terminator; a high speed memory bus that interconnects the memory controller, the memory bus terminator, and at least one memory module; and the at least one memory module, the memory module comprising at least one memory hub device, high speed random access memory served by the memory hub device, two bus signal ports, and a segment of the high speed memory bus fabricated on the memory module so as to interconnect the bus signal ports and the memory hub device, the high speed memory bus connected to the memory hub device by a negligible electrical stub. | 09-04-2008 |
20080228984 | Single-Chip Multi-Media Card/Secure Digital (MMC/SD) Controller Reading Power-On Boot Code from Integrated Flash Memory for User Storage - A Multi-Media Card/Secure Digital (MMC/SD) single-chip flash device contains a MMC/SD flash microcontroller and flash mass storage blocks containing flash memory arrays that are block-addressable rather than randomly-addressable. MMC/SD transactions from a host MMC/SD bus are read by a bus transceiver on the MMC/SD flash microcontroller. Various routines that execute on a CPU in the MMC/SD flash microcontroller are activated in response to commands in the MMC/SD transactions. A flash-memory controller in the MMC/SD flash microcontroller transfers data from the bus transceiver to the flash mass storage blocks for storage. Rather than boot from an internal ROM coupled to the CPU, a boot loader is transferred by DMA from the first page of the flash mass storage block to an internal RAM. The flash memory is automatically read from the first page at power-on. The CPU then executes the boot loader from the internal RAM to load the control program. | 09-18-2008 |
20080263253 | APPARATUS AND METHOD FOR A TEST AND MEASUREMENT INSTRUMENT - The apparatus for a test and measurement instrument consists of multiple integrated circuits with each integrated circuit being connected to its own memory controller. At least one of the integrated circuits is a specialized integrated circuit, which may be a graphics processing unit, a digital signal processor, or a field-programmable gate array. Each memory controller is connected to its own memory. The integrated circuits are connected in a circular arrangement by multiple high-speed interconnects. A bridge is connected to at least the first and last integrated circuits. A system bus connects the bridge to an acquisition module. The acquisition module has a signal bus interface with the system bus being connected to the acquisition module and having its own acquisition hardware. The acquisition hardware is a direct memory access machine that can transfer data to any portion of the memory. There is a signal source connected to the signal bus interface. | 10-23-2008 |
20080270668 | Method to Hide or Reduce Access Latency of a Slow Peripheral in a Pipelined Direct Memory Access System - A bus bridge between a high speed DMA bus and a lower speed peripheral bus sets a threshold for minimum available buffer space to send a read request dependent upon a frequency ratio and the DMA read latency. Similarly, a threshold for minimum available data for a write request depends on the frequency ratio and the DMA write latency. The bus bridge can store programmable values for the DMA read latency and write latency. | 10-30-2008 |
20080320201 | CENTRAL PROCESSING APPARATUS, CONTROL METHOD THEREFOR AND INFORMATION PROCESSING SYSTEM - A plurality of system controllers | 12-25-2008 |
20090049225 | Information processing apparatus, information processing method, program for executing the information processing method, storage medium storing the program, DMA controller, DMA transfer method, program for executing the DMA transfer method, and storage medium storing the program - Disclosed herein is an information processing apparatus that transfers information, using direct memory access (DMA), between a first storage section in an information processing system and a second storage section in an information transfer system. The information processing system includes the first storage section for storing the information, and a control section. The information transfer system includes: the second storage section for storing descriptor information indicating the location at which the information is stored in the first storage section and the size of the information; and a DMA transfer section for DMA transferring the information between the first storage section and the second storage section based on the descriptor information. The DMA transfer section DMA transfers the descriptor information concerning the DMA transferred information from the second storage section to the first storage section. The control section loads the descriptor information from the first storage section. | 02-19-2009 |
20090070513 | Method and Apparatus for Distributed Direct Memory Access for Systems on Chip - A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory. | 03-12-2009 |
20090138645 | SOC SYSTEM - Provided is a System on Chip (SoC) system for a multimedia system enabling high-speed transfer of a large amount of multimedia data and a processor to rapidly control a peripheral device. The SoC system includes a processor; a plurality of peripheral devices; a plurality of physically divided memories; a control bus for transferring a control signal from the processor to the peripheral devices and the memories; a data bus for transferring data between the processor, the peripheral devices and the memories; a bridge for coupling the control bus and the data bus to the processor; a plurality of memory controllers coupled to the control bus and controlling each of the memories; a Direct Memory Access (DMA) controller coupled to the data bus and the control bus and controlling data transfer between the peripheral devices and the memories; and a matrix switch coupled between the DMA controller and the memory controllers and enabling simultaneous multiple memory access. | 05-28-2009 |
20090138646 | METHOD AND APPARATUS FOR SIGNALING BETWEEN DEVICES OF A MEMORY SYSTEM - A method and apparatus for signaling between devices of a memory system is provided. In accordance with an embodiment of the invention, one or more of several capabilities are implemented to provide heretofore unattainable levels of important system metrics, for example, high performance and/or low cost. These capabilities relate to timing adjustment capabilities, bit time adjustment capabilities, cycle time selection, use of differential and/or non-differential signaling for bus signals and/or clock signals, use of termination structures on a bus, including integrated termination structures, and active control circuitry to allow adjustment to different characteristic bus impedances and power-state control, including a calibration process to optimize the termination value, use of slew rate control circuitry and transfer characteristic control circuitry in the predriver and driver of transmitter blocks to allow adjustment to different characteristic bus impedances and to allow adjustment for other bus properties, including a calibration process to optimize the such circuitry, and/or provision of a memory component designed to prefetch (preaccess) words that are wider than the width of the data bus so that the memory access bandwidth approximately matches the transfer bandwidth, and memory component able to adjust the size of the prefetch (preaccess) word to accommodate connection to data buses of different width. | 05-28-2009 |
20090172238 | BRIDGE CIRCUIT - A bridge circuit includes a bus, a memory interface module, a memory control module, and an external storage control module. The memory interface module receives a memory address from a processor via a memory interface and outputs the memory address to the bus. The memory address corresponds to one of a plurality of address regions of an address space of the processor. The memory control module receives the memory address via the bus and communicates with a memory when the memory address corresponds to a first one of the plurality of address regions. The external storage control module receives the memory address via the bus and communicates with an external storage device when the memory address corresponds to a second one of the plurality of address regions. | 07-02-2009 |
20090216932 | DATA PROCESSING APPARATUS - A data processing apparatus includes: a system bus; a processor connected to the system bus in slave connection, the processor having a command register configured to retain a DMA request command corresponding to a resource on the system bus and be accessed through the system bus; and a DMA controller connected to the system bus in bus-mastering connection, the DMA controller being configured to read out the DMA request command retained in the command register and control DMA transfer between the resource on the system bus and the processor based on the DMA request command. | 08-27-2009 |
20090222610 | BRIDGE, INFORMATION PROCESSING DEVICE , AND ACCESS CONTROL METHOD - A downstream port | 09-03-2009 |
20090248941 | Peer-To-Peer Special Purpose Processor Architecture and Method - A peer-to-peer special purpose processor architecture and method is described. Embodiments include a plurality of special purpose processors coupled to a central processing unit via a host bridge bus, a direct bus directly coupling each of the plurality of special purpose processors to at least one other of the plurality of special purpose processors and a memory controller coupled to the plurality of special purpose processors, wherein the at least one memory controller determines whether to transmit data via the host bus or the direct bus, and whether to receive data via the host bus or the direct bus. | 10-01-2009 |
20090259789 | MULTI-PROCESSOR, DIRECT MEMORY ACCESS CONTROLLER, AND SERIAL DATA TRANSMITTING/RECEIVING APPARATUS | 10-15-2009 |
20090265500 | Information Processing Apparatus, Information Processing Method, and Computer Program - An information processing apparatus including a plurality of nodes, each node connecting at least a memory and a processor to a system bus; an interconnection bus that interconnects the nodes; a device that is connected to a system bus on any of the plurality of nodes and performs data processing; and a memory selecting unit that selects a memory connected to the system bus to which the device is connected as a memory to be accessed by the device. | 10-22-2009 |
20090271555 | ACCESSING DATA - A method of accessing data in a device comprising: a first integrated circuit having a processor, a memory connected to the processor and a direct memory access engine operatively coupled to the memory and to the microprocessor; a second integrated circuit comprising storage means for holding data values in respective locations, the second integrated circuit being connected to the first integrated circuit via a serial link, the method comprising: the processor generating a plurality of memory access requests independent from one another and supplying a bundle of said independent memory access requests to the direct memory access engine, each memory access request comprising an address of a storage location in the storage means; the direct memory access engine sequentially supplying the memory access requests via the serial link to the second integrated circuit; the second integrated circuit returning a data value responsive to each memory access request and appending to the data value said address of the location where the data value was stored in the storage means; and storing in the memory of the first integrated circuit the returned data value and its appended address. | 10-29-2009 |
20090276557 | BUS SYSTEM FOR USE WITH INFORMATION PROCESSING APPARATUS - A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on t | 11-05-2009 |
20090287871 | UNIVERSAL SERIAL BUS HOST CONTROLLER AND CONTROL METHODS THEREOF - The present invention provides a USB host controller and control method thereof. The USB host controller comprises a first controller, a second controller and a first memory. The first controller controls first transfer between a host and a USB device. The second controller controls second transfer between the host and the USB device. The first memory is coupled to the first controller and the second controller and is configured to temporarily store data transferred between the host and the USB device. The first controller accesses the first memory during the first transfer, and the second controller accesses the first memory during the second transfer. | 11-19-2009 |
20090300256 | SELF-SYNCHRONIZING DATA STREAMING BETWEEN ADDRESS-BASED PRODUCER AND CONSUMER CIRCUITS - A circuit arrangement and method facilitate the direct streaming of data between producer and consumer circuits ( | 12-03-2009 |
20090319714 | SYSTEM AND METHOD FOR TRANSMITTING DATA PACKETS IN A COMPUTER SYSTEM HAVING A MEMORY HUB ARCHITECTURE - A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled to an upstream link. The upstream reception port receives the data packets from downstream memory hubs. The system further includes a bypass bus coupled to the upstream reception port. The bypass bus transports the data packets from the upstream reception port. The system further includes a temporary storage coupled to the upstream reception port and configured to receive the data packets from the upstream reception port. The system further includes a bypass multiplexer for selectively coupling an upstream transmission port to either one of a core logic circuit, the temporary storage, or the bypass bus. The system further includes a breakpoint logic circuit coupled to the bypass multiplexer and configured to switch the bypass multiplexer to selectively connect the upstream transmission port to either one of the core logic circuit, the bypass bus, or the temporary storage. The system further includes a local memory coupled to the core logic circuit and operable to receive and send the data packets to the core logic circuit. | 12-24-2009 |
20100005212 | PROVIDING A VARIABLE FRAME FORMAT PROTOCOL IN A CASCADE INTERCONNECTED MEMORY SYSTEM - Systems and methods for providing a variable frame format protocol in a cascade interconnected memory system. The systems include a memory hub device that utilizes a first bus interface to communicate on a high-speed bus. The hub device also includes frame decode logic for translating variable format frames received via the first bus interface into memory device commands and data. The translating includes identifying write data headers and associated write data for self-registering write to data buffer commands. | 01-07-2010 |
20100049895 | Providing a Connection Between a Memory Medium of a Mobile Device and an External Device - System and method for providing a high speed connection to a memory medium of a mobile device. The mobile device may be a mobile phone or other type of portable electronic device. The memory medium may be removable and/or may be flash memory, as desired. The mobile device may include a USB hub that provides a direct high speed connection between an external device and a memory medium of the mobile device. The USB hub may also provide a connection (possibly high speed) between the external device and the processor of the mobile device. The mobile device may also include a high speed connection between the processor of the mobile device and the memory medium. | 02-25-2010 |
20100049896 | PEER-TO-PEER NETWORK COMMUNICATIONS USING SATA/SAS TECHNOLOGY - A conventional serial communications protocol that is limited to supporting only host-to-slave communications, such as SATA or SAS, is extended to support peer-to-peer communications, e.g., by adding a memory-map layer into the conventional protocol stack between the link layer and the protocol layer. The addition of the memory-map layer enables two (or more) non-host devices (i.e., peer devices) to communicate with one another without using a host computer and without relying on conventional protocol-bridging techniques. | 02-25-2010 |
20100095044 | MOTHERBOARD SYSTEM, STORAGE DEVICE FOR BOOTING UP THEREOF AND CONNECTOR - A motherboard system is provided. The motherboard system includes a central processing unit (CPU), a control unit and an interface connector. The control unit is electrically connected to the CPU. The interface connector is electrically connected to the control unit and has a boot loader interface unit and a peripheral storage device interface unit, wherein the boot loader interface unit is electrically connected to the control unit and is configured for electrically connecting a system read only memory. When the power of the motherboard system is turned on, the CPU sends a read only memory fetch cycle to the control unit and fetches a booting program from the system read only memory configured in an external device via the boot loader interface unit. Accordingly, the system read only memory can be conveniently updated and maintained. | 04-15-2010 |
20100106880 | MANAGING MISALIGNED DMA ADDRESSES - A system and method operable to manage misaligned direct memory access (DMA) data transfers is provided. This method involves determining a delta between N bytes of data to be copied from within a local side buffer (source location) to a remote buffer (destination location). After the delta is determined a tail of the same length is copied to temporary storage. Then the N bytes of data on the local side buffer minus the tail will be shifted to align the N bytes of data to be copied from within the local side buffer to the starting address of the destination location in the remote buffer. The pre-shifted N bytes of data within the local side buffer may be DMA transferred to the remote buffer. The tail transferred to temporary storage may then be copied from temporary storage to the remote buffer | 04-29-2010 |
20100115170 | CHIP COMBINED WITH PROCESSOR CORES AND DATA PROCESSING METHOD THEREOF - A chip having integrated multiple processor cores and a data processing method are disclosed. The processor chip includes an MP core (main processor core), an AP core (application processor core) which performs a processing function designated by a control of the MP core, a first SM controller which sets a path such that the MP core is coupled with a shared memory, and a second SM controller which sets a path such that the AP core is coupled with the shared memory. By virtue of the present invention, the number of chips installed can be minimized, to allow efficient utilization of PCB space and enable a compact size for a portable terminal. | 05-06-2010 |
20100153610 | BUS ARBITER AND BUS SYSTEM - A bus interface unit receives first and second data sent out to a data bus and observes address values indicated on an address bus. The first and second data are written into first and second registers respectively. First and second address detection unit receive the address values observed by the bus interface respectively. The first address detection unit outputs a first detection signal when it detects an address value which corresponds with the value of the first data. The second address detection unit outputs a second detection signal, when it detects an address value having an increment from the first data, which corresponds with the value of the second data. A control unit raises the priority of one of the bus masters given a bus utilization right, during the period from a start of outputting the first detection signal to an end of outputting the second detection signal. | 06-17-2010 |
20100161868 | DATA TRANSFER APPARATUS AND DATA TRANSFER METHOD - A data transfer apparatus performing data communication by transmitting a bus use request to an arbiter between a plurality of nodes coupled in a tree shape through a bus is provided. The data transfer apparatus includes a request generation circuit which generates a highest priority request indicating that a priority level for using the bus is the highest, a determination circuit which determines the priority level of the highest priority request, and a priority level setting circuit which determines the highest priority request which takes priority based on a result of the determination circuit when a plurality of highest priority requests conflicts in a node. | 06-24-2010 |
20100169532 | SYSTEM LSI HAVING PLURAL BUSES - A system LSI includes first and second memories, first and second buses, a bus bridge that performs signal transfer between the first and second buses, a first bus system connecting to the first bus and accessing the first or second memory, a second bus system connecting to the second bus and accessing the first or second memory, a memory access circuit having first and second bus-side input/output terminals that perform signal transfer to/from the first and second buses and first and second memory-side input/output terminals that perform signal transfer to/from the first and second memories. | 07-01-2010 |
20100174843 | SYSTEM AND METHOD FOR OPERATING A BUS SYSTEM - A bus system for the real-time communication of a superordinate unit with one or more subordinate units is used for exchanging address and data information via a bus. For the rapid exchange of messages, further fields are provided between the fields for the address and data information. | 07-08-2010 |
20100223415 | REMOTE MEMORY ACCESS USING REVERSIBLE HOST/CLIENT INTERFACE - Accessing memory on a first device from a second device is supported by reversible host/client interfacing between the devices. The reversible interfacing permits the first and second devices to be configured respectively as host and client, or respectively as client and host. | 09-02-2010 |
20100262746 | METHOD OF INTEGRATING A PERSONAL COMPUTING SYSTEM AND APPARATUS THEREOF - An integrated circuit also referred to as an integrated computing system has a single substrate that has either deposited thereon or etched thereon, a central processing unit, a north bridge, a south bridge, and a graphics controller. An internal bus is coupled between the north bridge and the central processing unit. The central processing unit and north bridge do not require interfaces to perform bus protocol conversions. | 10-14-2010 |
20100281201 | PROTOCOL TRANSLATION IN A DATA STORAGE SYSTEM - A data storage system includes an input/output server and a storage unit. The input/output server includes a processor, memory, and a host channel adapter. The storage unit includes a processor, memory, and a storage module. The storage module includes a storage controller, and an interface block for connecting the storage module to a corresponding memory-mapped interface. The storage unit further includes a host channel adaptor. The storage unit host channel adapter is connected to a corresponding memory-mapped interface. The storage unit host channel adapter is capable of remote direct memory access to the input/output server. Protocol translation logic is configured to intercept a memory access request from the storage controller, and initiate a corresponding remote direct memory access to the input/output server through the storage unit host channel adapter and the input/output server host channel adapter. | 11-04-2010 |
20100306438 | BUS SYSTEM FOR USE WITH INFORMATION PROCESSING APPARATUS - A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal. | 12-02-2010 |
20100312940 | DMA TRANSFER CONTROL DEVICE - A DMA transfer control device comprises: a DMA arbiter that performs DMA transfer for each DMA channel formed by a combination of a memory and a plurality of input/output devices and DMA controller circuits that control the DMA arbiter; a judgment unit and a transfer time calculation unit that calculates a next DMA transfer scheduled time based on the DMA transfer size for a DMA transfer request and a judgment time. A timer counter that times the judgment time at a unit time interval, and a comparator that compares the judgment time at which a DMA transfer request arrives with the DMA transfer scheduled time are also provided, and the judgment unit sends the DMA transfer permission to the DMA arbiter when an output of the comparator indicates that the judgment time is not earlier than the DMA transfer scheduled time. The efficiency of data transfer by dynamically controlling DMA transfer is performed. | 12-09-2010 |
20100318711 | SIMULTANEOUS INTERMEDIATE PROXY DIRECT MEMORY ACCESS - Disclosed is a method that simultaneously transfers DMA data from a peripheral device to a hardware assist function and processor memory. A first DMA transfer is configured to transfer data from the peripheral to a peripheral DMA engine. While receiving the data, the DMA engine simultaneously transfers this data to processor memory. The DMA engine also transfers a copy of the data to a hardware assist function. The DMA engine may also simultaneously transfer data from processor memory to a peripheral device while transferring a copy to a hardware assist function. | 12-16-2010 |
20100318712 | SYSTEM AND METHOD FOR DISTRIBUTED PERSISTENT COMPUTING PLATFORM - Example embodiments of the invention are disclosed for an adaptive computing platform wherein a reader/writer device uses distributed, external memory resources as non-volatile memory blocks to provide distributed execution-in-place capability for the reader/writer device, such as a mobile phone, to enhance the processing power of the device. The execution architecture of the reader/writer device is scalable and adaptive to accommodate variations in the speed, size, and other characteristics of different external memory blocks it uses as it moves from one external memory block to another. | 12-16-2010 |
20100318713 | Flow Control Mechanisms for Avoidance of Retries and/or Deadlocks in an Interconnect - Flow control mechanisms avoid or eliminate retries of transactions in a coherency interconnect. A class of transaction (CoT) framework is defined whereby individual transactions are associated with CoT labels consistent with chains of dependencies that exist between transactions initiated by any of the cooperating devices that participate in a given operation. In general, coherency protocols create dependencies that, when mapped to physical resources, can result in cycles in a graph of dependencies and deadlock. To support architectural mechanisms for deadlock avoidance, CoT labels are applied to individual transactions consistent with a precedence order of those transactions both (i) with respect to the operations of which such transactions are constituent parts and (ii) as amongst the set of such operations supported in the coherency interconnect. CoT labels applied to respective transactions constitute a CoT framework that may be used by coherency managers to efficiently support concurrent in-flight transactions without retry. | 12-16-2010 |
20100318714 | METHOD AND APPARATUS TRANSFERRING DATA VIA UNIVERSAL SERIAL BUS - A method of communicating data between an external storage device and a USB host via a USB device is disclosed. The method includes receiving data from the USB host; and either (1) directly communicating the received data to the external storage device via an exclusive bus, or (2) indirectly communicating the received data to the external storage device via a USB bus, separate from the exclusive bus. | 12-16-2010 |
20100325334 | HARDWARE ASSISTED INTER-PROCESSOR COMMUNICATION - An external memory based FIFO (xFIFO) apparatus coupled to an external memory and a register bus is disclosed. The xFIFO apparatus includes an xFIFO engine, a wDMA engine, an rDMA engine, a first virtual FIFO, and a second virtual FIFO. The xFIFO engine receives a FIFO command from the register bus and generates a writing DMA command and a reading DMA command. The wDMA engine receives the writing DMA command from the xFIFO engine and forwards an incoming data to the external memory. The rDMA engine receives the reading DMA command from the xFIFO engine and pre-fetches a FIFO data from the external memory. The wDMA engine and the rDMA engine synchronize with each other via the first virtual FIFO and the second virtual FIFO. | 12-23-2010 |
20110010480 | METHOD FOR EFFICIENT I/O CONTROLLER PROCESSOR INTERCONNECT COUPLING SUPPORTING PUSH-PULL DMA READ OPERATIONS - A system for I/O controller-processor interconnect coupling supporting a push-pull DMA read operation, in one aspect, may comprise a processor interconnect comprising a plurality of caches and memory subsystems and an I/O controller coupled with the processor interconnect. The I/O controller may comprise a plurality of DMA read request queues, a DMA read slot pool comprising a plurality of DMA read slots, and an expander logic determining a priority of requests in said request queues. | 01-13-2011 |
20110016250 | SYSTEM AND METHOD UTILIZING DISTRIBUTED BYTE-WISE BUFFERS ON A MEMORY MODULE - A memory system and method utilizing one or more memory modules is provided. The memory module includes a plurality of memory devices and a controller configured to receive control information from a system memory controller and to produce module control signals. The memory module further includes a plurality of circuits, for example byte-wise buffers, which are configured to selectively isolate the plurality of memory devices from the system memory controller. The circuits are operable, in response to the module control signals, to drive write data from the system memory controller to the plurality of memory devices and to merge read data from the plurality of memory devices to the system memory controller. The circuits are distributed at corresponding positions separate from one another. | 01-20-2011 |
20110022767 | DMA CONTROLLER WITH INTERRUPT CONTROL PROCESSOR - Provided is a direct memory access (DMA) controller having an interrupt control processor that can process DMA transmission-related interrupts according to a control program modifiable by a user. The DMA controller includes the interrupt control processor that can process a DMA transmission-related interrupt and a DMA request interrupt transmitted from peripheral devices and control the DMA channel through the control program that can be modified by the user, so that DMA channel control and relevant interrupt processing loads caused by a plurality of DMA data transmissions are reduced, and the flexibility of DMA channel control and interrupt processing in control of the DMA controller is provided to the user. | 01-27-2011 |
20110047311 | MULTI-PORT MEMORY AND OPERATION - Multi-port memory having an additional control bus for passing commands between ports have individual ports that can be configured to respond to a command received from an external control bus or to a command received from the additional control bus. This facilitates various combinations of ports to vary the bandwidth or latency of the memory to facilitate tailoring performance characteristics to differing applications. | 02-24-2011 |
20110072184 | DATA PROCESSING DEVICE AND DATA PROCESSING SYSTEM - To provide a data processing device in which a plurality of CPUs can individually and independently communicate with different functions of a USB device using a single communication path. The data processing device is configured so that a USB host module to be coupled to a plurality of central processing units has a plurality of pipes to communicate with an arbitrary end point of a USB device coupled from the outside of the data processing device, the data processing device also includes an access control register to specify which central processing unit should have a right to control the pipe and specify to which extent a range of the content of setting of a function for the pipe should be allowed, and a USB host interface is controlled in accordance with the content of setting of the access control register. | 03-24-2011 |
20110107001 | Performing data operations using non-volatile third dimension memory - Performing data operations using non-volatile third dimension memory is described, including a storage system having a non-volatile third dimension memory array configured to store data, the data including an address indicating a file location on a disk drive, and a controller configured to process an access request associated with the disk drive, the access request being routed to the non-volatile third dimension memory array to perform a data operation, wherein data from the data operation is used to create a map of the disk drive. In some examples, an address in the non-volatile third dimension memory array provides an alias for another address in a disk drive. | 05-05-2011 |
20110125949 | Routing packet from first virtual machine to second virtual machine of a computing device - A networking packet is to be sent from a first virtual machine of a computing device to a second virtual machine of the computing device. A hardware network interface controller (NIC) of the computing device is to determine whether the networking packet is to be routed from the first virtual machine to the second virtual machine in accordance with a first approach or a second approach, based upon one or more considerations regarding a state of the computing device. The hardware NIC is then to control routing of the networking packet in accordance with the first approach or the second approach. | 05-26-2011 |
20110131360 | Context Execution in a Media Controller Architecture - Described embodiments provide a media controller for processing one or more data transfer requests received from at least one host device. The media controller includes a buffer to receive data of a data transfer request from a communication link and a command parser to generate one or more contexts corresponding to the data transfer request. The one or more contexts are stored in the buffer. At least one queue of the media controller includes a regular context queue for queuing regular-priority contexts, and a high-priority context queue for queuing high-priority contexts. A context manager coordinates processing of regular-priority contexts and high-priority contexts of the at least one queue based on context boundaries, wherein, when a context is processed at a context boundary, data corresponding to the processed context is data is transferred between the communication link and at least one of the buffer and the at least one storage media. | 06-02-2011 |
20110167189 | STORAGE APPARATUS AND ITS DATA TRANSFER METHOD - By writing a command for transferring data from a first cluster to a second cluster and the second cluster writing data that was requested from the first cluster based on the command into the first cluster, data can be transferred in real time from the second cluster to the first cluster without having to issue a read request from the first cluster to the second cluster. | 07-07-2011 |
20110185101 | SCALABLE DISTRIBUTED MEMORY AND I/O MULTIPROCESSOR SYSTEM - A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact. | 07-28-2011 |
20110191517 | SYSTEM AND METHOD FOR TRANSMITTING DATA PACKETS IN A COMPUTER SYSTEM HAVING A MEMORY HUB ARCHITECTURE - A system and method for transmitting data packets from a memory hub to a memory controller is disclosed. The system includes an upstream reception port coupled to an upstream link. The upstream reception port receives the data packets from downstream memory hubs. The system further includes a bypass bus coupled to the upstream reception port. The bypass bus transports the data packets from the upstream reception port. The system further includes a temporary storage coupled to the upstream reception port and configured to receive the data packets from the upstream reception port. The system further includes a bypass multiplexer for selectively coupling an upstream transmission port to either one of a core logic circuit, the temporary storage, or the bypass bus. The system further includes a breakpoint logic circuit coupled to the bypass multiplexer and configured to switch the bypass multiplexer to selectively connect the upstream transmission port to either one of the core logic circuit, the bypass bus, or the temporary storage. The system further includes a local memory coupled to the core logic circuit and operable to receive and send the data packets to the core logic circuit. | 08-04-2011 |
20110202701 | UNIFIED SYSTEM AREA NETWORK AND SWITCH - A network switch, based on the PCI Express protocol, is disclosed. The switch includes a processor, local memory and a plurality of non-transparent bridges. By configuring the non-transparent bridges appropriately, the network switch can facilitate a number of different communication mechanisms, including TCP/IP communication between servers, server clusters, and virtualized I/O device utilization. For example, the network switch may configure the non-transparent bridges so as to have access to the physical memory of every server attached to it. It can then move data from the memory of any server to the memory of any other server. In another embodiment, the network switch is connected to an I/O device, and multiple servers are given access to that I/O device via virtualized connections. | 08-18-2011 |
20110271028 | MODULAR INTEGRATED CIRCUIT WITH COMMON INTERFACE - A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The plurality of hub interfaces provide a plurality of signal interfaces between the hub module and each of the plurality of spoke modules, wherein each of the plurality of signal interfaces is isolated from each of the other signal interfaces of the plurality of signals interface, and wherein each of the plurality of signal interfaces operates in accordance with a common signaling format. | 11-03-2011 |
20110283036 | Multi-Pass System and Method Supporting Multiple Streams of Video - Systems and methods are disclosed for performing multiple processing of data in a network. In one embodiment, the network comprises a first display pipeline that is formed in real time from a plurality of possible display pipelines and that performs at least a first processing step on received data. A buffer stores the processed data and a second display pipeline that is formed in real time from a plurality of possible display pipelines performs at least a second processing step on stored data. | 11-17-2011 |
20110314199 | APPARATUS AND METHOD FOR DIRECT MEMORY ACCESS IN A HUB-BASED MEMORY SYSTEM - A memory hub for a memory module having a DMA engine for performing DMA operations in system memory. The memory hub includes a link interface for receiving memory requests for access at least one of the memory devices of the system memory, and further including a memory device interface for coupling to the memory devices, the memory device interface coupling memory requests to the memory devices for access to at least one of the memory devices. A switch for selectively coupling the link interface and the memory device interface is further included in the memory hub. Additionally, a direct memory access (DMA) engine is coupled through the switch to the memory device interface to generate memory requests for access to at least one of the memory devices to perform DMA operations. | 12-22-2011 |
20110320672 | METHOD AND APPARATUS FOR DISTRIBUTED DIRECT MEMORY ACCESS FOR SYSTEMS ON CHIP - A distributed direct memory access (DMA) method, apparatus, and system is provided within a system on chip (SOC). DMA controller units are distributed to various functional modules desiring direct memory access. The functional modules interface to a systems bus over which the direct memory access occurs. A global buffer memory, to which the direct memory access is desired, is coupled to the system bus. Bus arbitrators are utilized to arbitrate which functional modules have access to the system bus to perform the direct memory access. Once a functional module is selected by the bus arbitrator to have access to the system bus, it can establish a DMA routine with the global buffer memory. | 12-29-2011 |
20120011295 | METHOD AND APPARATUS FOR WIRELESS BROADBAND SYSTEMS DIRECT DATA TRANSFER - Apparatus and method for direct data transfer in a wireless broadband system having an operating system, the apparatus including a central processing unit (CPU), at least one dedicated Direct Memory Access unit (DMA) local to the CPU, coupled directly to the CPU, and a commands FIFO (First In First Out) receiving commands from the CPU and automatically transferring the commands in sequence to the DMA for implementation by the DMA, in the absence of intervention by the operating system. | 01-12-2012 |
20120023280 | Atomic Operations with Page Migration in PCIe - A method and data processing system enables scheduling of atomic operations within a Peripheral Component Interconnect Express (PCIe) architecture during page migration. In at least one embodiment, firmware detects the activation of a page migration operation. The firmware notifies the I/O host bridge, which responds by setting an atomic operation stall (AOS) bit to a pre-established value that indicates that there is an ongoing migration within the memory subsystem of a memory page that is mapped to that I/O host bridge. When the AOS bit is set to the pre-established value, the I/O host bridge prevents/stalls any received atomic operations from completing. The I/O host bridge responds to receipt of receipt of an atomic operation by preventing the atomic operation from being initiated within the memory subsystem, when the AOS bit is set to the pre-established value. The AOS bit is reset when the migration operation has completed. | 01-26-2012 |
20120030396 | Decoupled Memory Modules: Building High-Bandwidth Memory Systems from Low-Speed Dynamic Random Access Memory Devices - Apparatus and methods related to exemplary memory system are disclosed. The exemplary memory systems use a synchronization device to increase channel bus data rates while using relatively-slower memory devices operating at device bus data rates that differ from channel bus data rates. | 02-02-2012 |
20120030397 | INFORMATION PROCESSING SYSTEM AND METHOD FOR CONTROLLING INFORMATION PROCESSING SYSTEM - An information processing system includes a memory, a controller that reads data from a device coupled thereto and writes the data on the memory, a bridge that couples a system bus and an input output bus, the system bus being coupled to the memory and the processor, the input output bus being coupled to the controller, a check code generator that generates a check code from the data read from the device, and a determining unit that determines whether a second check code generated from the data read from the memory corresponds with the first check code. | 02-02-2012 |
20120030398 | Combination Non-Volatile Memory and Input-Output Card with Direct Memory Access - A removable electronic circuit card having both a memory module with a non-volatile mass storage memory and a separate input-output module so that data transfers may be made through the input-output module directly to and from the mass storage memory in a direct memory access (DMA) type transfer when the card is inserted into the host system but without having to pass the data through the host system. Once the host gives a DMA command, the data transfer is accomplished independently of the host system, except for the host supplying power and possibly a clock signal and other like support, during such a data transfer directly with card. The data for the transfer can be communicated between the input-output module and the exterior device through either wireless or an electrical connection means. | 02-02-2012 |
20120036301 | PROCESSOR SUPPORT FOR FILLING MEMORY REGIONS - Techniques are disclosed relating to distributing workloads between processors and/or processing elements. A computer system having at least first and second processing elements may cause a request to initialize one or more memory regions to be handled by the second processing element. Initialization may be accomplished by the second processing element directly accessing a memory that includes the specified memory region to be initialized. Thus, while the second processing element is causing the memory region to be initialized, the first processing element is free to perform other computational tasks. A cache associated with the first processing element may be undisturbed as a result of the second processing element performing the initialization, which may avoid displacement of data from the cache. | 02-09-2012 |
20120036302 | DETERMINATION OF ONE OR MORE PARTITIONABLE ENDPOINTS AFFECTED BY AN I/O MESSAGE - A data processing system includes a processor core, a system memory including a first data structure including a plurality of entries mapping requester identifiers (IDs) to partitionable endpoint (PE) numbers, and an input/output (I/O) subsystem including a plurality of PEs each having an associated PE number, where each of the plurality of PEs including one or more requesters each having a respective requester ID. An I/O host bridge, responsive to receiving an I/O message including a requester ID and an address, determines a PE number by reference to a first entry from the first data structure, and responsive to determining the PE number, accesses a second entry of the second data structure utilizing the PE number as an index and validates the address by reference to the accessed entry in the second data structure. The I/O host bridge, responsive to successful validation, provides a service indicated by the I/O message. | 02-09-2012 |
20120036303 | APPARATUS AND METHODS FOR OPTICALLY-COUPLED MEMORY SYSTEMS - Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier substrate and operable to transmit and receive optical signals, and first and second memory modules. The module substrate of the first memory module has an aperture formed therein, the aperture being operable to provide an optical path for optical signals between the controller and an optical transmitter/receiver unit of the second memory module. | 02-09-2012 |
20120072636 | POWER-OPTIMIZED FRAME SYNCHRONIZATION FOR MULTIPLE USB CONTROLLERS WITH NON-UNIFORM FRAME RATES - A method, apparatus, and system to synchronize multiple host controllers with non-uniform frame rates. The apparatus includes a first host controller, a second host controller, and logic. The first host controller is configured to access memory at a first frame rate. The second host controller is configured to access the memory at a second frame rate which is different from the first frame rate. The logic is coupled to the first and second host controllers to synchronize the memory accesses of the first and second host controllers at a common frame rate. Other embodiments are described. | 03-22-2012 |
20120084484 | SELECTIVELY COMBINING COMMANDS FOR A SYSTEM HAVING NON-VOLATILE MEMORY - Systems and methods are disclosed for selectively combining commands for a system having non-volatile memory (“NVM”). In some embodiments, a command dispatcher of a system can receive multiple commands to access a NVM for a period of time. After receiving the multiple commands, the command dispatcher can determine a set of commands that are naturally combinable. In some embodiments, the command dispatcher can select commands that are fairly distributed across different chip enables (“CEs”) and/or buses. After selecting the set of commands, the command dispatcher can combine the set of commands into a multi-access command. Finally, the command dispatcher can dispatch the multi-access command to the NVM. | 04-05-2012 |
20120110232 | MULTI-DESTINATION DIRECT MEMORY ACCESS TRANSFER - An apparatus generally including an internal memory and a direct memory access controller is disclosed. The direct memory access controller may be configured to (i) read first information from an external memory across an external bus, (ii) generate second information by processing the first information, (iii) write the first information across an internal bus to a first location in the internal memory during a direct memory access transfer and (iv) write the second information across the internal bus to a second location in the internal memory during the direct memory access transfer. The second location may be different from the first location. | 05-03-2012 |
20120131252 | INTELLIGENT PCI-EXPRESS TRANSACTION TAGGING - Systems and methods of routing data units such as data packets or data frames that provide improved system performance and more efficient use of system resources. The disclosed systems and methods employ memory mapping approaches in conjunction with transaction ID tag fields from the respective data units to assign each tag value, or at least one range of tag values, to a specified address, or at least one range of specified addresses, for locations in internal memory that store corresponding transaction parameters. The disclosed systems and methods can also apply selected bits from the transaction ID tag fields to selector inputs of one or more multiplexor components for selecting corresponding transaction parameters at data inputs to the multiplexor components. The disclosed systems and methods may be employed in memory-read data transfer transactions to recover the transaction parameters necessary to determine destination addresses for memory locations where the memory-read data are to be transmitted. | 05-24-2012 |
20120131253 | PCIE NVRAM CARD BASED ON NVDIMM - A memory system controller includes one or more sockets for accommodating NVDIMM cards produced by different NVDIMM providers; a PCIe interface for coupling the memory system controller to a host; and a controller coupled to the PCIe interface over a PCIe-compliant connection and to the one or more sockets over respective DDR2 connections. The controller is configured to manage data transfers between the host and a specified one of the NVDIMM sockets in which an NVDIMM card is accommodated as DMA reads and writes, format data received from the PCIe interface for transmission to the specified NVDIMM socket over the corresponding one or more DDR2 interfaces, and initiate save and restore operations on the NVDIMM card accommodated within the specified NVDIMM socket in response to power failure and power restoration indications. | 05-24-2012 |
20120137040 | MULTI CHANNEL SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME - Disclosed is a semiconductor memory device that includes a plurality of channel memories mounted within a package and is capable of minimizing or reducing the number of through-silicon vias. With the semiconductor memory device, a row command or a row address on two or more channels is applied through a shared bus. The semiconductor memory device is capable of reducing an overhead of a die size by reducing the number of through-silicon vias. A method of driving a multi-channel semiconductor memory device including a plurality of memories, using a shared bus, is also provided. | 05-31-2012 |
20120166700 | SPECIALIZED UNIVERSAL SERIAL BUS CONTROLLER - An apparatus comprises a memory device to store a pre-generated Universal Serial Bus (USB) command before a USB peripheral device is coupled to a USB. The apparatus also includes a processing device to retrieve the pre-generated USB command from the memory device and transmit the pre-generated USB command to the USB peripheral device over the USB. A method comprises identifying a Universal Serial Bus (USB) peripheral device is coupled to a USB. The USB peripheral device is coupled to the universal serial bus after a pre-generated USB command is stored in a memory device. The method further includes transmitting the pre-generated USB command to the USB peripheral device over the USB in response to identifying the USB peripheral device is coupled to the USB. | 06-28-2012 |
20120173786 | METHOD AND SYSTEM FOR PERFORMING DMA IN A MULTI-CORE SYSTEM-ON-CHIP USING DEADLINE-BASED SCHEDULING - A direct memory access (DMA) engine schedules data transfer requests of a data processing system according to both an assigned transfer priority and the deadline for completing a transfer. | 07-05-2012 |
20120185632 | IMPLEMENTING PCI-EXPRESS MEMORY DOMAINS FOR SINGLE ROOT VIRTUALIZED DEVICES - A method, system and computer program product are provided for implementing PCI-Express memory domains for single root virtualized devices. A PCI host bridge (PHB) includes a memory mapped IO (MMIO) domain descriptor (MDD) and an MMIO Domain Table (MDT) are used to associate MMIO domains with PCI memory VF BAR spaces. One MDD is provided for each unique VF BAR space size per bus segment connecting a single root IO virtualization (SRIOV) device to the PCI host bridge (PHB). The MDT used with the MDD includes having a number of entries limited to a predefined total number of SRIOV VFs to be configured. A VF BAR Stride, which may be further implemented as a VF BAR Stride Capability Structure, is provided to reduce the number of MDDs required to map SRIOV VF BAR spaces. A particular definition of the MDD is provided to reduce the number of MDDs required to at most one per SRIOV bus segment below a PHB. | 07-19-2012 |
20120198118 | USING DMA FOR COPYING PERFORMANCE COUNTER DATA TO MEMORY - A device for copying performance counter data includes hardware path that connects a direct memory access (DMA) unit to a plurality of hardware performance counters and a memory device. Software prepares an injection packet for the DMA unit to perform copying, while the software can perform other tasks. In one aspect, the software that prepares the injection packet runs on a processing core other than the core that gathers the hardware performance counter data. | 08-02-2012 |
20120233372 | DATA TRANSFER CONTROL DEVICE, INTEGRATED CIRCUIT OF SAME, DATA TRANSFER CONTROL METHOD OF SAME, DATA TRANSFER COMPLETION NOTIFICATION DEVICE, INTEGRATED CIRCUIT OF SAME, DATA TRANSFER COMPLETION NOTIFICATION METHOD OF SAME, AND DATA TRANSFER CONTROL SYSTEM - A data transfer control device | 09-13-2012 |
20120239848 | MITIGATION OF EMBEDDED CONTROLLER STARVATION IN REAL-TIME SHARED SPI FLASH ARCHITECTURE - An embedded controller includes a microcontroller core, a first bus interface that does not support bus arbitration, a second bus interface and memory control circuitry. The first bus interface is configured to receive and transmit memory transactions from and to a Central Processing Unit (CPU) chipset. The second bus interface is configured to communicate with a memory and to transfer the memory transactions of the CPU chipset to and from the memory. The memory control circuitry is configured to evaluate a starvation condition that identifies an inability of the microcontroller core to access the memory via the second bus interface due to the memory transactions transferred between the CPU chipset and the memory via the first and second bus interfaces, and to invoke a predefined corrective action when the starvation condition is met. | 09-20-2012 |
20120260017 | COMPUTER, COMPUTER SYSTEM, AND DATA COMMUNICATION METHOD - A computer includes first and second processors, first and second I/O devices, a shared memory, and an interrupt controller. The first processor issues a control command for causing the first I/O device to read target data from the first apparatus and store the target data in the shared memory. The first I/O device reads the target data from the first apparatus and, transfers the target data to the shared memory, and generates an I/O complete interrupt. The interrupt controller delivers the generated I/O complete interrupt to the second processor. When the second processor receives the I/O complete interrupt, the second processor issues a control command for causing the second I/O device to read the target data from the shared memory and send the target data to the second apparatus. The second I/O device reads the target data from the shared memory and sends the target data to the second apparatus. | 10-11-2012 |
20120265916 | DYNAMIC ALLOCATION OF A DIRECT MEMORY ADDRESS WINDOW - A computer-implemented method may include determining that a slot coupled to a peripheral component interconnect host bridge is occupied by an input/output adapter. The computer-implemented method may include determining one or more characteristics of the input/output adapter and determining whether the input/output adapter is capable of using additional memory based on the one or more characteristics of the input/output adapter. The computer-implemented method may also include allocating the additional memory for the input/output adapter in response to determining that the input/output adapter is capable of using the additional memory. | 10-18-2012 |
20120265917 | DATA TRANSFERRING DEVICE - A data transfer device for transferring data on a platform, in particular for transferring simultaneous data between different components of the platform, is disclosed. In one aspect, the data transfer device is adapted for simultaneous transfer of data between at least 3 ports of which at least one is an input port and at least one is an output port. The data transfer device has at least two controllers for executing instructions that transfer data between an input port and an output port. The controllers are adapted for receiving a synchronization instruction for synchronizing between the controllers and/or a synchronization instruction for synchronizing input ports and output ports. | 10-18-2012 |
20120278522 | USING DIRECT MEMORY ACCESS TO INITIALIZE A PROGRAMMABLE LOGIC DEVICE - An embodiment includes using direct memory access (DMA) to initialize a programmable logic device (PLD). An aspect of the invention includes manipulating a control line of the PLD to configure the PLD in a programming mode. PLD programming data is received at a PLD interface from a DMA control at a DMA speed. The PLD interface controls access of a processor and the DMA control to a programming port on the PLD. The PLD interface includes a data buffer and pacing logic. The PLD programming data is written to the data buffer and read from the data buffer. The PLD programming data transmitted to the programming port on the PLD at a PLD programming speed. The pacing logic of the PLD interface controls the data transmission at the PLD programming speed, and the DMA control is configured to transform the PLD programming data while the processor performs other processing tasks. | 11-01-2012 |
20120290763 | Method and system of complete mutual access of multiple-processors - The present disclosure discloses a method of complete mutual access of multiple-processors. The method comprises: a separate boot memory and a separate address mapping module are allocated for each processor; the processors perform the mutual access in the multiple-processors through the address mapping module after the processors are booted. The present disclosure also discloses a system for enabling complete mutual access of the multiple-processors. The method and the system creates the advantage of allowing complete mutual access of the multiple-processors, thereby sharing address space in the multiple-processors, sharing the peripheral controller and memory, improving expansibility and performance of the system. | 11-15-2012 |
20120303855 | IMPLEMENTING STORAGE ADAPTER PERFORMANCE OPTIMIZATION WITH HARDWARE ACCELERATORS OFFLOADING FIRMWARE FOR BUFFER ALLOCATION AND AUTOMATICALLY DMA - A method and controller for implementing storage adapter performance optimization with automatic chained hardware operations eliminating firmware operations, and a design structure on which the subject controller circuit resides are provided. The controller includes a plurality of hardware engines and a control store configured to store a plurality of control blocks. Each control block is designed to control a hardware operation in one of the plurality of hardware engines. A plurality of the control blocks is selectively arranged in a respective predefined chain to define sequences of hardware operations. An automatic hardware structure is configured to build the respective predefined chain controlling the hardware operations for a predefined hardware function. The predefined hardware function includes buffer allocation and automatic DMA data from a host system to the controller for write operations, eliminating firmware operations. | 11-29-2012 |
20120303856 | SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING THE SAME - A microcomputer includes a CPU (Central Processing Unit), a DMA (Direct Memory Access) processing unit, and a control unit. The control unit controls a processing speed of the CPU to be faster as the number of holding transfers increases, in which the number of holding transfers is the number of DMA transfers held to the DMA processing unit. | 11-29-2012 |
20120317328 | SCALABLE DISTRIBUTED MEMORY AND I/O MULTIPROCESSOR SYSTEM - A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact. | 12-13-2012 |
20120324138 | DISTRIBUTED TRACE USING CENTRAL PERFORMANCE COUNTER MEMORY - A plurality of processing cores, are central storage unit having at least memory connected in a daisy chain manner, forming a daisy chain ring layout on an integrated chip. At least one of the plurality of processing cores places trace data on the daisy chain connection for transmitting the trace data to the central storage unit, and the central storage unit detects the trace data and stores the trace data in the memory co-located in with the central storage unit. | 12-20-2012 |
20130007331 | System Core for Transferring Data Between an External Device and Memory - Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this approach include the regularity of the syntax, the relative ease with which the instruction set can be represented in database form, the ready ability with which tools can be created, the ready generation of self-checking codes and parameterized test cases. Parameterizations can be fairly easily mapped and system maintenance is significantly simplified. | 01-03-2013 |
20130013840 | SINGLE PIPE NON-BLOCKING ARCHITECTURE - A method for processing an incoming command destined for a target is provided, comprising: determining if the incoming command is a data command or a management command; forwarding the incoming command to a storage management component of the target when the incoming command is a management command; when the incoming command is a data command: determining if a disk command queue on the target is full; sending the incoming command to the disk command queue when the disk command queue is not full; when the disk command queue is full: starting a timer, the timer having a predetermined length; sending the incoming command to the disk command queue when the disk command queue becomes not full prior to the expiration of the timer; and sending a rejection of the incoming command to the host only if, upon expiration of the timer, if the disk command queue is still full. | 01-10-2013 |
20130024594 | SEMICONDUCTOR STORAGE DEVICE-BASED DATA RESTORATION - Embodiments of the invention provide a device and method for warm booting whereby data restoration occurs at the powering-on of the host, and can therefore be performed by the boot disk. Specifically, when the system is powered on, a backup controller will send a notification to a DMA controller indicating the data restoration is needed. The backup controller will automatically resorts contents of a backup storage device to main memory. During the process, when the host requests data, the DMA controller reads the data from the backup storage unit and sends it to the host. Then, once data restoration is complete, normal operations can commence. | 01-24-2013 |
20130024595 | PCI EXPRESS SWITCH WITH LOGICAL DEVICE CAPABILITY - A PCIe switch implements a logical device for use by connected host systems. The logical device is created by logical device enabling software running on a host management system. The logical device is able to consolidate one or more physical devices or may be entirely software-based. Commands from the connected host are processed in the command and response queues in the host and are also reflected in shadow queues stored in the management system. A DMA engine associated with the connected host is set up to automatically trigger on queues in the connected (local) host. Commands are sent to the physical devices to complete the work and a completion signal is sent to the management software and a response to the work is sent directly to the connected host, which is not aware that the logical device is non-existent and is implemented by software in the management system. | 01-24-2013 |
20130042043 | Method and Apparatus for Dynamic Channel Access and Loading in Multichannel DMA - An arbiter detects waiting states of N buffers holding direct memory access (DMA) requests, and detects an availability of R core channels of a core R-channel DMA memory. The arbiter, based on the detection, dynamically grants up to R of the N buffers access to the R core channels. An N-to-R controller communicates DMA requests from the N buffers to currently granted ones of the R core channels, and maintains a location record of different data from each of the N buffers being written into different ones of the R core channels. | 02-14-2013 |
20130073772 | SOLID-STATE DISK, AND USER SYSTEM COMPRISING SAME - The inventive concept relates to a user system including a solid state disk. The user system may include a main memory for storing data processed by a central processing unit; and a solid state disk for storing the selected data among data stored in the main memory. The main memory and the solid state disk form a single memory hierarchy. Thus, the user system of the inventive concept can rapidly process data. | 03-21-2013 |
20130091316 | MODULAR INTEGRATED CIRCUIT WITH COMMON INTERFACE - A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The plurality of hub interfaces provide a plurality of signal interfaces between the hub module and each of the plurality of spoke modules, wherein each of the plurality of signal interfaces is isolated from each of the other signal interfaces of the plurality of signals interface, and wherein each of the plurality of signal interfaces operates in accordance with a common signaling format. | 04-11-2013 |
20130132634 | ROUTING SWITCH APPARATUS, NETWORK SWITCH SYSTEM, AND ROUTING SWITCHING METHOD - The present disclosure relates to a routing switch apparatus, a network switch system, and a routing switch method. The routing switch apparatus includes one or more direct memory access modules and at least two protocol conversion interfaces. The direct memory access module is configured to generate a continuous access request of a cross network node, and control data transmission in the at least two protocol conversion interfaces; each protocol conversion interface is configured to convert a communication protocol of data transmitted inside and outside the routing switch apparatus and connect the routing switch module and an external network node. The routing switch apparatus may be introduced to replace a network switch, so that cross-node memory access and IO space access can be performed directly rather than through a proxy, thereby reducing delay of the cross-node memory access and IO space access and improving overall performance of a system. | 05-23-2013 |
20130159590 | LOW LATENCY, HIGH BANDWIDTH DATA COMMUNICATIONS BETWEEN COMPUTE NODES IN A PARALLEL COMPUTER - Methods, systems, and products are disclosed for data transfers between nodes in a parallel computer that include: receiving, by an origin DMA on an origin node, a buffer identifier for a buffer containing data for transfer to a target node; sending, by the origin DMA to the target node, a RTS message; transferring, by the origin DMA, a data portion to the target node using a memory FIFO operation that specifies one end of the buffer from which to begin transferring the data; receiving, by the origin DMA, an acknowledgement of the RTS message from the target node; and transferring, by the origin DMA in response to receiving the acknowledgement, any remaining data portion to the target node using a direct put operation that specifies the other end of the buffer from which to begin transferring the data, including initiating the direct put operation without invoking an origin processing core. | 06-20-2013 |
20130166810 | APPARATUS FOR PROCESSING REGISTER WINDOW OVERFLOW AND UNDERFLOW - An apparatus for processing a register window overflow and underflow includes register windows each configured to include local registers and incoming registers, dedicated internal memories configured to store contents of the local registers and the incoming registers for each word, dedicated data buses configured to connect the local registers and the incoming registers and the respective dedicated internal memories, a memory word counter configured to perform counting in order to determine whether or not there is a storage space of a word unit in the dedicated internal memories, and a logic block configured to control an operation of the dedicated data buses when one of a window overflow and a window underflow is generated based on the count value of the memory word counter. | 06-27-2013 |
20130173834 | METHODS AND APPARATUS FOR INJECTING PCI EXPRESS TRAFFIC INTO HOST CACHE MEMORY USING A BIT MASK IN THE TRANSACTION LAYER STEERING TAG - Methods and apparatus are provided for implementing transaction layer processing (TLP) hint (TPH) protocols in the context of the peripheral component interconnect express (PCIe) base specification. The method allows an endpoint function associated with a PCI Express device to configure a steering tag header in the open systems interconnect (OSI) transaction layer to identify a particular processing resource that the requester desires to target, such as a specific processor or cache location within the execution core. A bit mask may be implemented by the hardware or operating system, for example, by embedding the bit mask in the steering tag header. The bit mask provides administrative oversight of the steering tag header configuration, to thereby mitigate unintended denial of service attacks or cache misses occasioned by aggressive steering tag configuration strategies employed by endpoint functions. | 07-04-2013 |
20130179620 | Administering Connection Identifiers For Collective Operations In A Parallel Computer - Administering connection identifiers for collective operations in a parallel computer, including prior to calling a collective operation, determining, by a first compute node of a communicator to receive an instruction to execute the collective operation, whether a value stored in a global connection identifier utilization buffer exceeds a predetermined threshold; if the value stored in the global ConnID utilization buffer does not exceed the predetermined threshold: calling the collective operation with a next available ConnID including retrieving, from an element of a ConnID buffer, the next available ConnID and locking the element of the ConnID buffer from access by other compute nodes; and if the value stored in the global ConnID utilization buffer exceeds the predetermined threshold: repeatedly determining whether the value stored in the global ConnID utilization buffer exceeds the predetermined threshold until the value stored in the global ConnID utilization buffer does not exceed the predetermined threshold. | 07-11-2013 |
20130198433 | METHODS AND SYSTEMS FOR DEVICES WITH SELF-SELECTING BUS DECODER - Disclosed are methods and devices, among which is a device including a self-selecting bus decoder. In some embodiments, the device may be coupled to a microcontroller, and the self-selecting bus decoder may determine a response of the peripheral device to requests from the microcontroller. In another embodiment, the device may include a bus translator and a self-selecting bus decoder. The bus translator may be configured to translate between signals from a selected one of a plurality of different types of buses. A microcontroller may be coupled to a selected one of the plurality of different types of buses of the bus translator. | 08-01-2013 |
20130227190 | High Data-Rate Processing System - A data processing system includes a hub processing portion, and a first plurality of processing resources communicatively connected to define a first ring, wherein each processing resource of the first plurality of processing resources is communicatively connected to the hub processing portion. | 08-29-2013 |
20130254449 | COLLABORATIVE BUS ARBITRATION MULTIPLEX ARCHITECTURE AND METHOD OF ARBITRATION OF DATA ACCESS BASED ON THE ARCHITECTURE - A collaborative bus arbitration multiplex architecture includes of a main memory, a bus, a plurality of BMPDs, and a BAM. Arbitration can be done according to the following steps of awaiting whether any of the BMPDs renders any request for access; B) identifying whether the access authority of the bus is being fetched by any other BMPDs; C) identifying whether the main memory to which the request for access corresponds have any record that the corresponding BMPD needs special treatment; D) identifying whether all of the BMPDs have rendered the requests for access; E) according to a generic arbitration principle, identifying whether the corresponding BMPDs indicated in the steps C) and D) win the access authority; F) yielding the access authority of the bus to the BMPDs winning the access authority as indicated in the step E); and G) accessing the main memory. | 09-26-2013 |
20130262732 | SEMICONDUCTOR INTEGRATED CIRCUIT AND DMA CONTROL METHOD OF THE SAME - A semiconductor integrated circuit includes a bus, a memory connected to the bus, an arithmetic processing unit connected to the bus, a first DMA controller connected to the bus, and at least one functional block connected to the bus. The functional block includes a functional macro which is configured to perform a process that realizes a given function, a second DMA controller which is configured to control data transfer between the memory and the functional macro, and an access condition setting unit which is configured to set an access condition regarding the DMA transfer between the memory and the functional macro. | 10-03-2013 |
20130268711 | RAW MEMORY TRANSACTION SUPPORT - Methods, systems, and apparatus for implementing raw memory transactions. An SoC is configured with a plurality of nodes coupled together forming a ring interconnect. Processing cores and memory cache components are operatively coupled to and co-located at respective nodes. The memory cache components include a plurality of last level caches (LLC's) operating as a distributed LLC and a plurality of home agents and caching agents employed for supporting coherent memory transactions. Route-back tables are used to encode memory transactions requests with embedded routing data that is implemented by agents that facilitate data transfers between link interface nodes and memory controllers. Accordingly, memory request data corresponding to raw memory transactions may be routed back to requesting entities using headerless packets. | 10-10-2013 |
20130282948 | System and method for system wide self-managing storage operations - The present invention presents a system and method to provide a storage system wide approach to better manage IO requests and better manage the prefetch transfers of data to and from the drives. | 10-24-2013 |
20130318276 | OFFLOADING OF COMPUTATION FOR RACK LEVEL SERVERS AND CORRESPONDING METHODS AND SYSTEMS - A system is disclosed that can include at least one processor module connectable to a memory bus. The processor module can include at least one memory, at least one offload processor mounted on the processor module, and configured to execute operations on data received over the memory bus, and to output context data to the memory and read context data from the memory, and a hardware scheduling logic mounted on the module and configured to control operations of the at least one processor. | 11-28-2013 |
20130318277 | PROCESSING STRUCTURED AND UNSTRUCTURED DATA USING OFFLOAD PROCESSORS - A structured data processing system is disclosed that can include a plurality of XIMM modules connected to a memory bus in a first server, with the XIMM modules each respectively having a DMA slave module connected to the memory bus and an arbiter for scheduling tasks, with the XIMM modules providing an in-memory database; and a central processing unit (CPU) in the first server connected to the XIMM modules by the memory bus, with the CPU arranged to process and direct structured queries to the plurality of XIMM modules. | 11-28-2013 |
20130326107 | Hardware Apparatus for a System, System and Memory Access Method - A hardware apparatus for a system comprises an interface and a direct memory access device. The interface is configured to connect the hardware apparatus to a system bus, which the hardware apparatus can use to communicate with a central control unit in the system and/or with another hardware apparatus in the system. The direct memory access device is configured to directly access a main memory of the central control unit, and to set an identifier for data flow control in the main memory of the central control unit when the direct memory access device has terminated direct access to a main memory of the system. | 12-05-2013 |
20140013022 | UNIVERSAL DIGITAL BLOCK INTERCONNECTION AND CHANNEL ROUTING - A programmable routing scheme provides improved connectivity both between Universal Digital Blocks (UDBs) and between the UDBs and other micro-controller elements, peripherals and external Inputs and Outputs (I/Os) in the same Integrated Circuit (IC). The routing scheme increases the number of functions, flexibility, and the overall routing efficiency for programmable architectures. The UDBs can be grouped in pairs and share associated horizontal routing channels. Bidirectional horizontal and vertical segmentation elements extend routing both horizontally and vertically between different UDB pairs and to the other peripherals and I/O. | 01-09-2014 |
20140019663 | CONTROLLER - A controller as an embodiment of the present disclosure controls a timing of transmitting an access request that has been received from an initiator (or its transmission interval). The controller includes: transmitting and receiving circuitry configured to receive an access request related to burst accesses from a first initiator that is connected via a first bus to, and adjacent to, the transmitting and receiving circuitry and configured to transmit the access request to a second bus implemented as a network; and a transmission interval controller configured to control the timing of transmitting the access request that has been received from the first initiator according to density of the burst accesses during a period in which the burst accesses continue and an access load on the second bus. | 01-16-2014 |
20140019664 | METHOD AND SYSTEM FOR PERFORMING DMA IN A MULTI-CORE SYSTEM-ON-CHIP USING DEADLINE-BASED SCHEDULING - A direct memory access (DMA) engine schedules data transfer requests of a data processing system according to both an assigned transfer priority and the deadline for completing a transfer. | 01-16-2014 |
20140025859 | INPUT/OUTPUT PROCESSING - The present disclosure provides a computer system that includes a processor coupled to a host memory through a memory controller. The computer system also includes an upper device communicatively coupled to the memory controller, the upper device configured to process local input/output received from or sent to a lower device. The computer system also includes a memory comprising a data flow identifier used to associate a data flow resource of the upper device with an external data flow resource corresponding to the lower device. A data packet received by the upper device from the lower device includes the data flow identifier. | 01-23-2014 |
20140052886 | All-to-All Comparisons on Architectures Having Limited Storage Space - Mechanisms for performing all-to-all comparisons on architectures having limited storage space are provided. The mechanisms determine a number of data elements to be included in each set of data elements to be sent to each processing element of a data processing system, and perform a comparison operation on at least one set of data elements. The comparison operation comprises sending a first request to main memory for transfer of a first set of data elements into a local memory associated with the processing element and sending a second request to main memory for transfer of a second set of data elements into the local memory. A pair wise comparison computation of the all-to-all comparison of data elements operation is performed at approximately a same time as the second set of data elements is being transferred from main memory to the local memory. | 02-20-2014 |
20140052887 | APPARATUSES FOR OPERATING, DURING RESPECTIVE POWER MODES, TRANSISTORS OF MULTIPLE PROCESSORS AT CORRESPONDING DUTY CYCLES - A device includes a first processor and a second processor. The first processor is configured to operate in accordance with a first power mode. The first processor includes a first transistor. The first processor is configured to, while operating in accordance with the first power mode, switch the first transistor at a first duty cycle. The second processor is configured to operate in accordance with a second power mode. The second processor includes a second transistor. The second processor is configured to, while operating in accordance with the second power mode, switch the second transistor at a second duty cycle. The second duty cycle is greater than the first duty cycle. The second processor consumes less power while operating in accordance with the second power mode than the first processor consumes while operating in accordance with the first power mode. | 02-20-2014 |
20140068133 | VIRTUALIZED LOCAL STORAGE - Embodiments of electronic circuits, computer systems, and associated methods include a module that accesses memory using virtual addressing, the memory including local memory that is local to the module and nonlocal memory that is accessible via a system bus coupled to the module, the module including logic coupled to the local memory via a local bus. The logic is configured to receive a memory access specified to a virtual address, determine whether the virtual address is within the local memory, and direct the memory access either to the local memory via the local bus or to the nonlocal memory via the system bus based on the determination. | 03-06-2014 |
20140068134 | DATA TRANSMISSION APPARATUS, SYSTEM, AND METHOD - Embodiments of the present invention provide a data transmission apparatus, system, and method. The apparatus includes: a data transit module, configured to read configuration information of a first sending buffer of a first processor core, and when the configuration information indicates that the first sending buffer stores data to be transmitted to a receiving buffer of a second processor core, control a DMA module to transmit the data from the first sending buffer to the receiving buffer, and set interrupt information; and an interrupt management module, configured to read the interrupt information, and when the interrupt information indicates that an interrupt needs to be triggered to the second processor core, control a multi-core interrupt controller to trigger the interrupt to the second processor core, to enable the second processor core to process the data in the receiving buffer. | 03-06-2014 |
20140075079 | DATA STORAGE DEVICE CONNECTED TO A HOST SYSTEM VIA A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) INTERFACE - An apparatus of a data storage device is provided. The data storage device is connected to a host system via a peripheral component interconnect express (PCIe) interface. The host system includes a first memory having a plurality of first memory space addresses. The data storage device comprises a second memory, a non-transparent bridge (NTB) and a processor. The NTB is coupled to the host system, and having a first portion and a second portion. The processor coupled between the NTB and the second memory, wherein the first portion of the NTB and the plurality of first memory space addresses have a first mapping relationship therebetween, and the processor writes a first datum in the first memory into the second memory via the first mapping relationship according to a command from the host system. | 03-13-2014 |
20140075080 | Accumulation of Waveform Data using Alternating Memory Banks - System and method for hardware implemented accumulation of waveform data. A digitizer is provided that includes: a circuit, and first and second memory banks, coupled to the circuit. The circuit may be configured to: store a first subset of the waveforms in the first memory bank, accumulate each waveform in a chunk-wise manner, where each chunk has a specified size, thereby generating a first bank sum including a first partial accumulation of the set of waveforms, store a second subset of waveforms in the second memory bank concurrently with the accumulation, and accumulate each waveform of the second subset of waveforms in a chunk-wise manner, thereby generating a second bank sum including a second partial accumulation of the set of waveforms, where the first and second partial accumulations of the set of waveforms are useable to generate an accumulated record of the set of waveforms. | 03-13-2014 |
20140075081 | Methods and Apparatus for Providing Bit-Reversal and Multicast Functions Utilizing DMA Controller - Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an array processor. Improved data transfer control within a data processing system provides support for radix 2, 4 and 8 fast Fourier transform (FFT) algorithms through data reordering or bit-reversed addressing across multiple PEs, carried out concurrently with FFT computation on a digital signal processor (DSP) array by a DMA unit. Parallel data distribution and collection through forms of multicast and packet-gather operations are also supported. | 03-13-2014 |
20140082249 | REQUEST SENT TO STORAGE DEVICE BASED ON MOVING AVERAGE - Embodiments herein relate to sending a request to a storage device based on a moving average. A threshold is determined based on a storage device type and a bandwidth of a cache bus connecting a cache to a controller. The moving average of throughput is measured between the storage device and a host. The request of the host to access the storage device is sent directly to the storage device, if the moving average is equal to the threshold. | 03-20-2014 |
20140082250 | EMBEDDED MULTIMEDIA CARD (eMMC), HOST FOR CONTROLLING eMMC, AND METHOD OPERATION FOR eMMC SYSTEM - An eMMC includes flash memory including an extended card specific data (CSD) register (“EXT_CSD register”), and an eMMC controller that controls operation of the flash memory. The eMMC controller is receives a clock from a host via a clock line, receives a SEND_EXT_CSD command from the host via a command line, and provides the host with eMMC information stored in the EXT_CSD register via a data bus in response to the SEND_EXT_CSD command, the eMMC information including maximum operating frequency information for the eMMC. | 03-20-2014 |
20140089550 | Low Power Signaling for Data Transfer - Methods, systems and computer readable storage medium embodiments for communicating over a data bus include, determining a number of changes in bit value in respective bit positions between a previous bit string and a current bit string, transmitting either the current bit string in an inverted form over the data bus if the determined number of changes in bit value exceeds a threshold or the current bit string in non-inverted form if the determined number of changes in bit value does not exceed a threshold, and transmitting an additional at least one bit along with the current bit string having a logic value that indicates whether the current bit string is in an inverted form or non-inverted form. Methods, systems, and computer readable storage medium embodiments for receiving bit strings over a bus are also disclosed. | 03-27-2014 |
20140095758 | STORAGE ARCHITECTURE FOR SERVER FLASH AND STORAGE ARRAY OPERATION - A storage architecture of a storage system environment has a storage connector interface configured to exchange data directly between flash storage devices on a server and a storage array of the environment so as to bypass main memory and a system bus of the server. According to one or more embodiments, the storage connnector interface includes control logic configured to implement the data exchange in accordance with one of a plurality of operational modes that deploy and synchronize the data on the flash storage devices and the storage array. Advantageously, the storage connector interface obviates latencies and bandwidth consumption associated with prior data exchanges over the main memory and bus, thereby enhancing storage architecture performance. | 04-03-2014 |
20140095759 | REPLICATED STATELESS COPY ENGINE - Techniques are disclosed for performing an auxiliary operation via a compute engine associated with a host computing device. The method includes determining that the auxiliary operation is directed to the compute engine, and determining that the auxiliary operation is associated with a first context comprising a first set of state parameters. The method further includes determining a first subset of state parameters related to the auxiliary operation based on the first set of state parameters. The method further includes transmitting the first subset of state parameters to the compute engine, and transmitting the auxiliary operation to the compute engine. One advantage of the disclosed technique is that surface area and power consumption are reduced within the processor by utilizing copy engines that have no context switching capability. | 04-03-2014 |
20140101354 | MEMORY ACCESS CONTROL MODULE AND ASSOCIATED METHODS - First and second data interfaces provide data transfer to and from a plurality of memory banks. The first data interface uses a first bus size and a first clock frequency. The second data interface uses a second bus size and a second clock frequency. The second bus size is an integer multiple of the first bus size. The first clock frequency is an integer multiple of the second clock frequency. A channelizer module segments data from the second data interface into data segments of the first bus size and transmits them to addressed ones of the plurality of memory banks using the first clock frequency. The channelizer module also receives data in accordance with the first bus size and first clock frequency from the plurality of memory banks, combines this data into the second bus size, and transmits the data to the second data interface using the second clock frequency. | 04-10-2014 |
20140108696 | LOW SPEED ACCESS TO DRAM - Embodiments provide access to a memory over a high speed serial link at slower speeds than the high speed serial links regular operation. An embodiment may comprise a memory apparatus with a differential receiver coupled to a protocol recognition circuit, a low speed receiving circuit that has a first receiver coupled with a first input of the differential receiver and a second receiver coupled with a second input of the differential receiver, wherein the low speed receiving circuit is coupled with the protocol recognition circuit, allowing the first and second receivers to access the protocol recognition block at a different frequency than the differential receiver. | 04-17-2014 |
20140122765 | METHOD AND APPARATUS FOR SECURING AND SEGREGATING HOST TO HOST MESSAGING ON PCIE FABRIC - A PCIe fabric includes at least one PCIe switch. The fabric may be used to connect multiple hosts. The PCIe switch implements security and segregation measures for host-to-host message communication. A management entity defines a Virtual PCIe Fabric ID (VPFID). The VPFID is used to enforce security and segregation. The fabric ID may be extended to be used in switch fabrics with other point-to-point protocols. | 05-01-2014 |
20140136748 | SYSTEM AND METHOD FOR PERFORMANCE OPTIMIZATION IN USB OPERATIONS - An apparatus may include a processor and first logic operable on the processor to output a direct memory access (DMA) activity indicator to indicate a current state of activity of direct memory access data transfer operations. The apparatus may further include second logic operable on the processor to determine scheduled DMA activity to be performed; and third logic operable on the processor to output a pre-wake indicator to a controller before the scheduled DMA activity is to be performed, to satisfy both Quality of Service (QOS) and Power saving needs. Other embodiments are disclosed and claimed. | 05-15-2014 |
20140143470 | Processing System With Interspersed Processors DMA-FIFO - Embodiments of a multi-processor array are disclosed that may include a plurality of processors, local memories, configurable communication elements, and direct memory access (DMA) engines, and a DMA controller. Each processor may be coupled to one of the local memories, and the plurality of processors, local memories, and configurable communication elements may be coupled together in an interspersed arrangement. The DMA controller may be configured to control the operation of the plurality of DMA engines. | 05-22-2014 |
20140149625 | METHOD AND APPARATUS FOR DMA TRANSFER WITH SYNCHRONIZATION OPTIMIZATION - A DMA optimization circuit transfers data from a single source device to a plurality of destination devices on a computer bus. A first DMA control circuit is configured to transfer a payload of data from the source device to a first destination device where the payload of data divided into a plurality of chunks of data. A second DMA control circuit is configured to transfer the payload of data from the source device to a second destination device, and is further configured to perform a logical operation on the data transferred to the second destination device. A synchronization controller is configured to control each DMA control circuit to independently transfer the chunk of data, and receives a signal indicating that both DMA control circuits have finished transferring the corresponding chunk of data. The synchronization controller then transfers of a next chunk of data only when both DMA control circuits have finished transferring the corresponding chunk of data. | 05-29-2014 |
20140149626 | RECEIVER AND METHOD FOR DATA PROCESSING - The present invention discloses a receiver and a method for data processing. The receiver includes a system on chip and a memory, where the system on chip is connected to the memory through an external buffer bus; the system on chip includes an LLR subsystem, a controller, a rate matching module, an incremental redundancy IR reconstructing module, and a combiner, where the LLR subsystem is connected to the controller and the rate matching module respectively; the controller is connected to the IR reconstructing module, and the rate matching module and the IR reconstructing module are connected to the combiner respectively; and the controller stores LLR data currently corresponding to a data block demodulated by the LLR subsystem into a memory, and read LLR data historically corresponding to the data block and stored in the memory into the IR reconstructing module when the data block is a retransmitted data block. | 05-29-2014 |
20140156902 | LINE CODING FOR LOW-RADIO NOISE MEMORY INTERFACES - According to some embodiments, a method and apparatus are provided to receive a first data burst associated with a first data line and a second data burst associated with a second data line, determine a first one or more stuff bits to be transmitted after the first data burst and a second one or more stuff bits to be transmitted after the second data burst, and output data comprising the first data burst and the first one or more stuff bits and the second data burst and the second one or more stuff bits. | 06-05-2014 |
20140156903 | SCALABLE STORAGE SYSTEM HAVING MULTIPLE STORAGE CHANNELS - Techniques are generally described related to a scalable storage system. One example scalable storage system may include a first storage channel including a first storage node, a second storage node, and a first serial link. The first storage node is coupled with the second storage node via the first serial link. The scalable storage system may include a multi-channel interface including a first input-channel coupled with the first storage node and a first output-channel coupled with the second storage node. For a first request transmitted from a computer system and received by the multi-channel interface, the multi-channel interface is configured to direct the first request via the first input-channel to the first storage node of the first storage channel. The first storage node is configured to process the first request. Upon determining that a request segment in the first request is directed to the second storage node, the first serial link is configured to transmit the request segment from the first storage node to the second storage node, allowing the second storage node to process the request segment. | 06-05-2014 |
20140164666 | SERVER AND METHOD FOR SHARING PERIPHERAL COMPONENT INTERCONNECT EXPRESS INTERFACE - A server provides a sharing method for a peripheral component interconnect express (PCIe) interface to one or more servers. The server receives an accessing request from a virtual machine to access a sharing unit, and transmits a model number of the sharing unit with the PCIe interface and a memory address of a PCIe base address register (BAR). The server establishes a first window in a storage device of the virtual machine, and maps the first window to a memory of the PCIe BAR of the sharing unit. The server further establishes a second window in a storage device of the server, and maps the second window to the storage device of the virtual machine. | 06-12-2014 |
20140164667 | FLEXIBLE AND EXPANDABLE MEMORY ARCHITECTURES - Memory system architectures, memory modules, processing systems and methods are disclosed. In various embodiments, a memory system architecture includes a source configured to communicate signals to a memory device. At least one memory cube may coupled to the source by a communications link having more than one communications path. The memory cube may include a memory device operably coupled to a routing switch that selectively communicates the signals between the source and the memory device. | 06-12-2014 |
20140189186 | MEMORY BUS ATTACHED INPUT/OUTPUT ('I/O') SUBSYSTEM MANAGEMENT IN A COMPUTING SYSTEM - Memory bus attached Input/Output (‘I/O’) subsystem management in a computing system, the computing system including an I/O subsystem communicatively coupled to a memory bus, including: detecting, by an I/O subsystem device driver, a hibernation request; setting, by the I/O subsystem device driver, a predetermined memory address to a value indicating that the I/O subsystem is not to service system requests; detecting, by the I/O subsystem device driver, that the I/O subsystem device driver has been restarted; and setting, by the I/O subsystem device driver, the predetermined memory address to a value indicating that the I/O subsystem can resume servicing system requests. | 07-03-2014 |
20140201416 | OFFLOAD PROCESSOR MODULES FOR CONNECTION TO SYSTEM MEMORY, AND CORRESPONDING METHODS AND SYSTEMS - A method can include receiving write data over a system memory bus via an in-line module connector, the write data including a metadata portion identifying a processing to be performed on at least a portion of the write data; performing the processing on at least a portion of the write data with at least one offload processor mounted on a module having the in-line module connector to generate processed data; and transmitting the processed data over the system memory bus; wherein the system memory bus is further connected to at least one processor connector configured to receive at least one host processor different from the at least one offload processor. | 07-17-2014 |
20140201417 | OFFLOAD PROCESSOR MODULES FOR CONNECTION TO SYSTEM MEMORY, AND CORRESPONDING METHODS AND SYSTEMS - A system can include a host processor connected to memory via a system memory bus; and at least one offload processor module, including at least one offload processor mounted on the offload processor module, and configured to execute operations on data received over the system memory bus, and to output context data to memory, and read context data from the memory, and hardware scheduling logic mounted on the module and configured to control operations of the at least one offload processor. | 07-17-2014 |
20140207991 | HARDWARE ACCELERATED COMMUNICATIONS OVER A CHIP-TO-CHIP INTERFACE - A device and method for communicating, via a memory-mapped communication path, between a host processor and a cellular-communication modem are disclosed. The method includes providing logical channels over the memory-mapped communication path and transporting data organized according to one or more cellular communication protocols over at least one of the logical channels. In addition, the method includes acknowledging when data transfer occurs between the host processor and the cellular-communication modem, issuing commands between the host processor and the cellular-communication modem, and communicating and managing a power state via one or more of the logical channels. | 07-24-2014 |
20140207992 | PROCESSOR WITH TIGHTLY COUPLED SMART MEMORY UNIT - An information processor includes a central processing unit core and a direct memory access unit connected to the central processing unit core. The information processor further includes at least one tightly coupled smart memory unit connected to the central processing unit core. The at least one tightly coupled smart memory unit includes a memory unit, and a local processing unit adapted to process data stored in the memory unit, wherein the memory unit is adapted to be accessed by the central processing unit core and the local processing unit, and the local processing unit is separate from the central processing unit core and the direct memory access unit. | 07-24-2014 |
20140207993 | APPARATUS AND METHOD FOR DATA BYPASS FOR A BI-DIRECTIONAL DATA BUS IN A HUB-BASED MEMORY SUB-SYSTEM - A memory hub includes first and second link interfaces for coupling to respective data busses, a data path coupled to the first and second link interfaces and through which data is transferred between the first and second link interfaces, and further includes a write bypass circuit coupled to the data path to couple write data on the data path and temporarily store the write data to allow read data to be transferred through the data path while the write data is temporarily stored. A method for writing data to a memory location in a memory system is provided which includes accessing read data in the memory system, providing write data to the memory system, and coupling the write data to a register for temporary storage. The write data is recoupled to the memory bus and written to the memory location following provision of the read data. | 07-24-2014 |
20140223068 | Memory System Topologies Including A Buffer Device And An Integrated Circuit Memory Device - Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization. | 08-07-2014 |
20140223069 | DATA TRANSFER MANAGEMENT - Methods, controllers, and systems for managing data transfer, such as those in solid state drives (SSDs), are described. In some embodiments, the data transfer between a host and a memory is monitored and then assessed to provide an assessment result. A number of storage units of the memory allocated to service another data transfer is adjusted based on the assessment result. Additional methods and systems are also described. | 08-07-2014 |
20140281098 | CONDITIONAL LINKS FOR DIRECT MEMORY ACCESS CONTROLLERS - Some embodiments relate to a Direct Memory Access (DMA) controller. The DMA controller includes a bus controller having a system bus interface and configured to read a pattern from a memory location via the system bus interface. Pattern comparison logic compares the read pattern to at least one predetermined pattern. Control logic induces the bus controller to process a first conditional link over the system bus interface if the read pattern differs from the predetermined pattern, and induces the bus controller to process a second conditional link over the system bus interface if the read pattern differs from the predetermined pattern. | 09-18-2014 |
20140281099 | METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR CONTROLLING FLOW OF PCIe TRANSPORT LAYER PACKETS - This application relates to systems and methods for controlling the flow of transport layer packets (TLP) in a peripheral component interconnect express (PCIe)-based environment. In an exemplary embodiment, an arbiter in a PCIe device determines the amount of data, if any, that should be expected in response to transmission of a particular TLP. If a receive buffer of the PCIe device has enough available space for storing the expected data, the arbiter permits transmission of the particular TLP. If the receive buffer does not have enough available space for storing the expected data, the arbiter suppresses transmission of the particular TLP until the receive buffer has enough available space. The exemplary embodiment may improve data flow through the PCIe environment by reducing fragmented transfers of data. | 09-18-2014 |
20140281100 | LOCAL BYPASS FOR IN MEMORY COMPUTING - Embodiments include a method for bypassing data in an active memory device. The method includes a requestor determining a number of transfers to a grantor that have not been communicated to the grantor, requesting to the interconnect network that the bypass path be used for the transfers based on the number of transfers meeting a threshold and communicating the transfers via the bypass path to the grantor based on the request, the interconnect network granting control of the grantor in response to the request. The method also includes the interconnect network requesting control of the grantor based on an event and communicating delayed transfers via the interconnect network from other requestors, the delayed transfers being delayed due to the grantor being previously controlled by the requestor, the communicating based on the control of the grantor being changed back to the interconnect network. | 09-18-2014 |
20140281101 | INCOMING BUS TRAFFIC STORAGE SYSTEM - In managing incoming bus traffic storage for store cell memory (SCM) in a sequential-write, random-read system, a priority encoder system can be used to find a next empty cell in the sequential-write step. Each cell in the SCM has a bit that indicates whether the cell is full or empty. The priority encoder encodes the next empty cell using these bits and the current write pointer. The priority encoder can also find next group of empty cells by being coupled to AND operators that are coupled to each group of cells. Further, a cell locator selector selects a next empty cell location among priority encoders for cell groups of various sizes according to an opcode by appending ‘0’s to cell locations outputs from priority encoders that are smaller than the size of the SCM. | 09-18-2014 |
20140289441 | Multilevel Memory Bus System - The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus. This multilevel memory bus system may be disposed to support: an n-bit wide bus width, such as nibble-wide or byte-wide bus widths; a selectable data sampling rate, such as a single or double sampling rate, on the intermediate bus; a configurable bus data rate, such as a single, double, quad, or octal data sampling rate; CRC protection; an exclusive busy mechanism; dedicated busy lines; or any combination of these. | 09-25-2014 |
20140297914 | CHIP INCLUDING MEMORY ELEMENT STORING HIGHER LEVEL MEMORY DATA ON A PAGE BY PAGE BASIS - A bus system for transferring data between parts of a multiprocessor system. The bus system is divided into a plurality of segments. Each segment is controlled by a table providing routing information. The bus system establishes communication between a sender and a receiver according to data where the data includes an identifier that identifying the source of the data transfer and/or the target of the data transfer. | 10-02-2014 |
20140304449 | Multi-core processor having disabled cores - A multi-core processor having a cache, an interconnect system selectively connecting the cache to individual cores, and a interconnect control whereby selected cores are disabled. | 10-09-2014 |
20140310443 | Shims for Processor Interface - An interface unit configured to perform transfers between a processor and one or more peripheral devices is disclosed. A system includes a processor, a number of devices (e.g., peripheral devices), and an interface unit coupled therebetween. The interface unit includes FIFOs for storing data transmitted to or received from the devices by the processor. The interface unit may access data from a device responsive to a request from the processor. The data may be loaded into a FIFO according to transfer parameters controlled by the device. After the data has been received by the FIFO, the interface unit may generate an interrupt to the processor. Data may then be transferred from the interface unit to the processor according to transfer parameters controlled by the processor. The interface unit may thus homogenize a processor interface to a number of different devices. | 10-16-2014 |
20140317332 | SEMICONDUCTOR DEVICE FOR PERFORMING TEST AND REPAIR OPERATIONS - A semiconductor device may include: a storage unit configured to store program codes provided through control of a processor core; and a control unit configured to perform a control operation on a semiconductor memory device according to the program codes. | 10-23-2014 |
20140317333 | Direct Memory Access Controller with Hybrid Scatter-Gather Functionality - A direct memory access (DMA) controller stores a set of DMA instructions in a list, where each entry in the list includes a bit field that identifies the type of the entry. Based on the bit field, the DMA controller determines whether each DMA instruction is a buffer pointer or a jump pointer. If a DMA instruction is identified as a buffer pointer, the DMA controller transfers data to or from the location specified by the buffer pointer. If a DMA instruction is identified as a jump pointer, the DMA controller jumps to the location in the list specified by the jump pointer. A subset of the list of DMA instructions may be cached, and the DMA controller executes the cache entries sequentially. If a jump pointer is encountered in the cache, the DMA controller flushes the cache and reloads it from main memory based on the jump pointer. | 10-23-2014 |
20140325114 | MULTI-CHANNEL DIRECT MEMORY ACCESS CONTROLLER AND CONTROL METHOD THEREOF - Disclosed herein is a multi-channel direct memory access (DMA) controller. The DMA controller includes: a register which stores control information and an operation state of each of a plurality of direct memory access (DMA) channels; a transmission processor which controls flow of transmission and reception of data such that all of the DMA channels requesting DMA transmission cyclically repeat unit transmission with reference to the register; and a transmission sequence control unit which controls the transmission processor such that the transmission sequence of each of the DMA channels is determined in a circulation cycle of unit transmission by reflecting priority information of the respective DMA channels stored in the register. | 10-30-2014 |
20140331000 | Computer System, Method for Accessing Peripheral Component Interconnect Express Endpoint Device, and Apparatus - A computer system and a method are provided for accessing a peripheral component interconnect express (PCIe) endpoint device. The computer system includes: a processor, a PCIe bus, and an access proxy. The access proxy connects to the processor and the PCIe endpoint device; the processor acquires an operation instruction, where the operation instruction instructs the processor to access the PCIe endpoint device through the access proxy, and send an access request to the access proxy according to the operation instruction; and the access proxy sends a response message of the access request to the processor after receiving the access request sent by the processor. Because the processor does not directly access the PCIe endpoint device to be accessed but completes access through the access proxy, thereby avoiding an MCE reset for the processor. | 11-06-2014 |
20140337557 | MINIMIZING MICRO-INTERRUPTIONS IN HIGH-PERFORMANCE COMPUTING - Data storage systems and methods for storing data in computing nodes of a super computer or compute cluster are described herein. The super computer storage may be coupled with a primary storage system. In addition to a CPU and memory, non-volatile memory is included with the computing nodes as local storage. The super computer includes a plurality of computing groups, each including a plurality of computing nodes. There is one burst buffer fabric per group and one input/output node per group. When data bursts occur, data may be stored by a first computing node on the local storage of a second computing node in the computing group through the burst buffer fabric without interrupting the CPU in the second computing node. Further, the local storage of other computing nodes may be used to store redundant copies of data from a first computing node to make the super computer data resilient. | 11-13-2014 |
20140344498 | Use of Host System Resources by Memory Controller - A method for data storage includes, in a system that includes a host having a host memory and a memory controller that is separate from the host and stores data for the host in a non-volatile memory including multiple analog memory cells, storing in the host memory information items relating to respective groups of the analog memory cells of the non-volatile memory. A command that causes the memory controller to access a given group of the analog memory cells is received from the host. In response to the command, a respective information item relating to the given group of the analog memory cells is retrieved from the host memory by the memory controller, and the given group of the analog memory cells is accessed using the retrieved information item. | 11-20-2014 |
20140359191 | ADC SEQUENCING - A device comprises a central processing unit (CPU) and a memory configured for storing memory descriptors. The device also includes an analog-to-digital converter controller (ADC controller) configured for managing an analog-to-digital converter (ADC) using the memory descriptors. In addition, the device includes a direct memory access system (DMA system) configured for autonomously sequencing conversion operations performed by the ADC without CPU intervention by transferring the memory descriptors directly between the memory and the ADC controller for controlling the conversion operations performed by the ADC. | 12-04-2014 |
20140359192 | APPARATUS INCLUDING BUFFER ALLOCATION MANAGEMENT AND RELATED METHODS - Memory system controllers can include hardware masters, first buffers, and a switch coupled to the hardware masters and to the first buffers. The switch can include second buffers and a buffer allocation management (BAM) circuit. The BAM circuit can include a buffer tag pool. The buffer tag pool can include tags, each identifying a respective first buffer or a respective second buffer. The BAM circuit can be configured to allocate a tag to a hardware master in response to an allocation request from the hardware masters. The BAM circuit can be configured to prioritize allocation of a tag identifying a second buffer over a tag identifying a first buffer. | 12-04-2014 |
20140365704 | USING DUAL PHYS TO SUPPORT MULTIPLE PCIE LINK WIDTHS - Systems described herein enable PCIe device components to be used with multiple PCIe topologies and with host systems of varying configurations. In some cases, a number of varying PHYs and PCIe cores are utilized to increase the number of applications and/or specifications that may be satisfied with a host interface design. Further, some systems described herein may include a number of synchronizers, clock multiplier units, and selectors to create a host interface that can be configured for a number of applications. Despite increasing the flexibility of the usage of systems disclosed herein, costs can be reduced by using the systems of the present disclosure for PCIe based devices. | 12-11-2014 |
20140365705 | DATA PROCESSING DEVICE AND DATA TRANFER CONTROL DEVICE - A data processing device includes: a processing block which is connected to a common bus and which processes a plurality of data, which is inputted simultaneously, in parallel; a memory which is consisted of address space which has a plurality of banks; and a common bus arbitration unit which arbitrates a request for access to the memory outputted from the processing block, and controls exchange of data via the common bus between the processing block whose access request has been accepted and the memory. The processing block includes a data transfer control device which changes an order of access to the bank of the memory corresponding to the respective data, unifies the respective data into an exchange data, and exchanges the exchange data with the memory when the processing block performs exchanging of the data to be processed in parallel with the memory via the common bus. | 12-11-2014 |
20140365706 | DATA-PROCESSING APPARATUS AND DATA TRANSFER CONTROL DEVICE - A data-processing apparatus includes: a plurality of processing blocks which is connected to a common bus; a memory which includes an address space having a plurality of banks; and a common bus arbitrating section which arbitrates an access request to access the memory, and controls data delivery through the common bus that receives the access request and is provided between the plurality of processing blocks and the memory. At least one processing block among the plural processing blocks is an exchange-processing block that performs exchange of an access order to access the banks in the memory when the communication of the data is performed between the memory and the processing block through the common bus. The exchange-processing block includes a data transfer control device that performs the exchange of the access order to access the banks by controlling the order of the data. | 12-11-2014 |
20140365707 | MEMORY DEVICE WITH VOLATILE AND NON-VOLATILE MEDIA - Apparatuses, systems, methods, and computer program products are disclosed for providing a memory device with volatile and non-volatile media. A volatile memory medium is on a circuit board configured to be installed on a memory bus of a processor. A non-volatile memory medium is on the same circuit board. A mapping module is configured to selectively store data in either the volatile memory medium or the non-volatile memory medium. The data is provided by way of one or more commands from the processor. | 12-11-2014 |
20140372655 | System and Method for Symmetrical Direct Memory Access (SDMA) - This invention defines a System and Method for optimized Data Transfers between two Processing entities, (typically done with DMA technology). We will call this invention and method, Symmetrical DMA, or SDMA. | 12-18-2014 |
20140379953 | CONTINUOUS IN-MEMORY ACCUMULATION OF HARDWARE PERFORMANCE COUNTER DATA - In-memory accumulation of hardware counts in a computer system is carried out by continuously sending count values from full-speed hardware counter units to a memory controller. A sending unit periodically samples performance data from the hardware counter units, and transmits count values to a bus interface for an interconnection bus which communicates with the memory controller. The memory controller responsively updates an accumulated count value stored in system memory using the current count value, e.g., incrementing the accumulated count value. A count value can be sent with a pointer to a memory location and an instruction on how the location is to be updated. The instruction may be an atomic read-modify-write operation, and the memory controller can include a dedicated arithmetic logic unit to carry out that operation. A data harvester can then be used to harvest accumulated count values by reading them from a table in system memory. | 12-25-2014 |
20150019786 | METHOD AND SYSTEM FOR SYNCHRONIZING ADDRESS AND CONTROL SIGNALS IN THREADED MEMORY MODULES - A memory system includes a memory module which further includes a set of memory devices. The set of memory devices includes a first subset of memory devices and a second subset of memory devices. An address bus is disposed on the memory module, wherein the address bus includes a first segment coupled to the first subset and a second segment coupled to the second subset. An address signal traverses the set of memory devices in sequence. The memory system also includes a memory controller which is coupled to the memory module. The memory controller includes a first circuit to output a first control signal that controls the first subset, such that the first control signal and the address signal arrive at a memory device in the first subset at substantially the same time. The memory controller additionally includes a second circuit to output a second control signal that controls the second subset, such that the second control signal and the address signal arrive at a memory device in the second subset at substantially the same time. | 01-15-2015 |
20150019787 | DATA INTERLEAVING MODULE - The present disclosure includes apparatuses and methods related to a data interleaving module. A number of methods can include interleaving data received from a bus among modules according to a selected one of a plurality of data densities per memory cell supported by an apparatus and transferring the interleaved data from the modules to a register. | 01-15-2015 |
20150026380 | Scalable Direct Inter-Node Communication Over Peripheral Component Interconnect-Express (PCIe) - A method of communicating data over a Peripheral Component Interconnect Express (PCIe) Non-Transparent Bridge (NTB) comprising transmitting a first posted write message to a remote processor via the NTB, wherein the first posted write message indicates an intent to transfer data to the remote processor, and receiving a second posted write message in response to the first posted write message, wherein the second posted write message indicates a destination address list for the data. Also disclosed is a method of communicating data over a PCIe NTB comprising transmitting a first posted write message to a remote processor via the NTB, wherein the first posted write message comprises a request to read data, and receiving a data transfer message comprising at least some of the data requested by the first posted write message. | 01-22-2015 |
20150026381 | REMOTE TERMINAL DEVICE AND METHOD OF OPERATING THE SAME - Provided is a remote terminal device having an industrial versa module eurocard bus (VMEbus) structure and including a main module that receives control logic information of a field device from an input/output module, and a programmable logic controller (PLC) function module that receives the control logic information from the main module, performs a logic corresponding to the control logic information, and outputs a result of the performed logic. The PLC function module includes a dual port RAM including a plurality of memory areas, and a PLC chip that reads the control logic information written on one of the plurality of memory areas, performs the logic corresponding to the read control logic information, and outputs the result of the performed logic to another one of the plurality of memory areas. | 01-22-2015 |
20150026382 | MEMORY AND PROCESS SHARING VIA INPUT/OUTPUT WITH VIRTUALIZATION - Embodiments of the present invention provide an approach for memory and process sharing via input/output (I/O) with virtualization. Specifically, embodiments of the present invention provide a circuit design/system in which multiple chipsets are present that communicate with one another via a communications channel. Each chipset generally comprises a processor coupled to a memory unit. Moreover, each component has its own distinct/separate power supply. Pursuant to a communication and/or command exchange with a main controller, a processor of a particular chipset may disengage a memory unit coupled thereto, and then access a memory unit of another chipset (e.g., coupled to another processer in the system). Among other things, such an inventive configuration reduces memory leakage and enhances overall performance and/or efficiency of the system. | 01-22-2015 |
20150026383 | DIRECT MEMORY ACCESS CONTROLLER - Systems and methods for direct memory access are described. One example system includes a memory module that includes a first memory portion that maintains transfer descriptors of direct memory access (DMA) channels, and a second memory portion that maintains transfer descriptors of enabled DMA channels. The system includes a controller coupled to the memory module, the controller includes one or more DMA channels coupled to a system bus, a channel arbiter that selects one of the enabled DMA channels as an active DMA channel for data transfer including re-arbitrating after each burst or beat in a given transfer, and an active channel buffer that receives a transfer descriptor of the active DMA channel from the second memory portion. The controller is configured to write back the transfer descriptor of the active DMA channel into the second memory portion when the active DMA channel loses arbitration. | 01-22-2015 |
20150032932 | Storage Expansion Apparatus and Server - A storage expansion apparatus and a server, where the storage expansion apparatus includes a quick path interconnect (QPI) interface module, which communicates with a central processing unit (CPU) through a QPI bus; a peripheral component interconnect express (PCIe) interface module, which communicates with the CPU through a PCIe bus; an interface selecting module, connected to the QPI interface module and the PCIe interface module separately; a home agent (HA) module, connected to the interface selecting module; and a memory controller engine (MCEng) module, connected to the HA module and the interface selecting module separately. The storage expansion apparatus may serve as a CPU memory capacity expansion device, and may also serve as storage expansion hardware of storage input and output (TO). | 01-29-2015 |
20150039802 | SERIAL-PARALLEL INTERFACE CIRCUIT WITH NONVOLATILE MEMORY - A serial-parallel interface circuit with nonvolatile memories is provided. A control module generates a plurality of control signals, wherein the control signals include readout and write-in control signals and memory programming control signals. An input terminal receives a plurality of digital data from external. The digital data are transmitted to the input terminal serially. Memory modules are coupled to the input terminal and receive the control signals from the control module. The input terminal transmits the digital data to the memory modules. One of the memory modules includes a memory unit, and the memory unit stores or transmits one bit of the digital data based on a high voltage control signal and a memory control signal. A plurality of output signal lines are respectively coupled to the memory modules. The memory unit transmits the one bit of the digital data to one of the output signal lines. | 02-05-2015 |
20150039803 | DATA TRANSFER APPARATUS, DATA TRANSFER METHOD, AND DATA TRANSFER PROGRAM - An object of the present invention is to prevent occurrence of data destruction when a transfer source region and a transfer destination region of data overlap with each other and even when transfer is performed using a burst transfer function. The data read from the transfer source region is temporarily written into a ring buffer, and then the data written into the ring buffer is written into the transfer source region. In this case, reading of the data from the ring buffer is controlled, based on a magnitude relation between the number of times of wrap-arounds caused by writing of the data into the ring buffer and the number of times of wrap-arounds caused by reading of the data from the ring buffer. | 02-05-2015 |
20150039804 | PCI Express Data Transmission - PCIe devices and corresponding methods are provided wherein a length of data to be transferred is aligned to a multiple of a double word length. | 02-05-2015 |
20150046625 | SOLID STATE DRIVE ARCHITECTURES - A solid state drive includes DRAM logical flash and flash memory, in which system processor reads and writes only to the DRAM logical flash which minimizes writes to the flash memory. A method for operation of a solid state flash device includes writing, by a CPU, to a solid state drive by sending commands and data to DRAM logical flash using flash commands and formatting. | 02-12-2015 |
20150052279 | FUNCTION TRANSFER USING VIRTUALIZED MAPPING - The present disclosure includes a method for migration of a first virtual function of a first device located on a PCI bus and accessible by a device driver using a virtual address. A second virtual function is created on a second device. A base address is determined for the second virtual function as a function of a logical location of the second device within the PCI structure. An offset is determined for the second virtual function as a function of the base address and the virtual address. The device driver is notified that the first virtual function is on hold. The offset is stored in a translation table. The device driver is notified that the hold has been lifted. Accesses to the virtual address and by the device driver to memory of the second virtual function are routed based upon the offset in the translation table. | 02-19-2015 |
20150052280 | METHOD AND SYSTEM FOR COMMUNICATIONS-STACK OFFLOAD TO A HARDWARE CONTROLLER - The current document is directed to offloading communications processing from server computers to hardware controllers, including network interface controllers. In one implementation, the transport channel and zero, one, or more protocol channels immediately overlying the transport channel of a Windows Communication Foundation communications stack are offloaded to a network interface controller. The offloading of communications processing carried out by the methods and systems to which the current document is directed involves minimal supporting development and is configurable, during service-application initialization, by exchange of relatively small amounts of information between an enhanced NIC and the communications stack. | 02-19-2015 |
20150052281 | FUNCTION TRANSFER USING VIRTUALIZED MAPPING - The present disclosure includes a method for migration of a first virtual function of a first device located on a PCI bus and accessible by a device driver using a virtual address. A second virtual function is created on a second device. A base address is determined for the second virtual function as a function of a logical location of the second device within the PCI structure. An offset is determined for the second virtual function as a function of the base address and the virtual address. The device driver is notified that the first virtual function is on hold. The offset is stored in a translation table. The device driver is notified that the hold has been lifted. Accesses to the virtual address and by the device driver to memory of the second virtual function are routed based upon the offset in the translation table. | 02-19-2015 |
20150052282 | System and Method for Virtual Machine Live Migration - A system for virtual machine live migration includes a management node, a source server, a destination server, a peripheral component interconnect express (PCIe) switch, and an single root input/output virtualization (SR-IOV) network adapter, where the source server includes a virtual machine (VM) before live migration; the destination server includes a VM after live migration; the management node is adapted to configure, using the PCIe switch, a connection relationship between a virtual function (VF) module used by the VM before live migration and the source server as a connection relationship between the VF module and the destination server; and the destination server, using the PCIe switch and according to the connection relationship with the VF module configured by the management node, uses the VF module to complete virtual machine live migration. By switching the connection relationships, the system ensures that a data packet receiving and sending service is not uninterrupted. | 02-19-2015 |
20150058512 | DYNAMICALLY RESIZING DIRECT MEMORY ACCESS (DMA) WINDOWS - A dynamic DMA window mechanism can resize DMA windows dynamically by increasing one DMA window at the expense of reducing a neighboring DMA window. The dynamic DMA window mechanism can decide to dynamically resize DMA windows based on a request from a system administrator, based on a request by an operating system device driver for an I/O adapter, or based on a performance monitor determining such a resizing would benefit system performance. Once one DMA window has been increased by allocating a portion of a donor DMA window, device drivers for the I/O devices corresponding to the two windows are updated to reflect the new DMA window sizes. | 02-26-2015 |
20150058513 | DYNAMICALLY RESIZING DIRECT MEMORY ACCESS (DMA) WINDOWS - A dynamic DMA window mechanism can resize DMA windows dynamically by increasing one DMA window at the expense of reducing a neighboring DMA window. The dynamic DMA window mechanism can decide to dynamically resize DMA windows based on a request from a system administrator, based on a request by an operating system device driver for an I/O adapter, or based on a performance monitor determining such a resizing would benefit system performance. Once one DMA window has been increased by allocating a portion of a donor DMA window, device drivers for the I/O devices corresponding to the two windows are updated to reflect the new DMA window sizes. | 02-26-2015 |
20150058514 | STORAGE DEVICE AND INFORMATION PROCESSING SYSTEM - A storage device able to make a redundant write operation of unselected data unnecessary and able to optimize an arrangement of pages to a state having a high efficiency for rewriting, wherein the storage device has a first memory unit, a second memory unit having a different access speed from the first memory, and a control circuit, wherein the control circuit has a function of timely moving the stored data in two ways between the first memory unit and the second memory unit having different access speeds in reading or rewriting. | 02-26-2015 |
20150067224 | DIRECT MEMORY ACCESS (DMA) ADDRESS TRANSLATION WITH A CONSECUTIVE COUNT FIELD - DMA translation table entries include a consecutive count (CC) field that indicates how many subsequent translation table entries point to successive real page numbers. A DMA address translation mechanism stores a value in the CC field when a translation table entry is stored, and updates the CC field in other affected translation table entries as well. When a translation table entry is read, and the CC field is non-zero, the DMA controller can use multiple RPNs from the access to the single translation table entry. Thus, if a translation table entry has a value of 2 in the CC field, the DMA address translation mechanism knows it can access the real page number (RPN) corresponding to the translation table entry, and also knows it can access the two subsequent RPNs without the need of reading the next two subsequent translation table entries. | 03-05-2015 |
20150067225 | AUTOMATIC COMMUNICATION AND OPTIMIZATION OF MULTI-DIMENSIONAL ARRAYS FOR MANY-CORE COPROCESSOR USING STATIC COMPILER ANALYSIS - There are provided source-to-source transformation methods for a multi-dimensional array and/or a multi-level pointer for a computer program. A method includes minimizing a number of holes for variable length elements for a given dimension of the array and/or pointer using at least two stride values included in stride buckets. The minimizing step includes modifying memory allocation sites, for the array and/or pointer, to allocate memory based on the stride values. The minimizing step further includes modifying a multi-dimensional memory access, for accessing the array and/or pointer, into a single dimensional memory access using the stride values. The minimizing step also includes inserting offload pragma for a data transfer of the array and/or pointer prior as at least one of a single-dimensional array and a single-level pointer. The data transfer is from a central processing unit to a coprocessor over peripheral component interconnect express. | 03-05-2015 |
20150074315 | MEMORY TRANSACTION ORDERING - Embodiments are disclosed relating to methods of ordering transactions across a bus of a computing device. One embodiment of a method includes determining a current target memory channel for an incoming transaction request, and passing the incoming transaction request downstream if the current target memory channel matches an outstanding target memory channel indicated by a direction bit of a counter or the counter equals zero. The method further includes holding the incoming transaction request if the counter is greater than zero and the current target memory channel does not match the outstanding target memory channel. | 03-12-2015 |
20150074316 | REFLECTIVE MEMORY BRIDGE FOR EXTERNAL COMPUTING NODES - In at least some examples, a computing node includes a processor and a local memory coupled to the processor. The computing node also includes a reflective memory bridge coupled to the processor. The reflective memory bridge maps to an incoming region of the local memory assigned to at least one external computing node and maps to an outgoing region of the local memory assigned to at least one external computing node. | 03-12-2015 |
20150074317 | ELECTRONIC SYSTEM WITH DIAGNOSTIC INTERFACE MECHANISM AND METHOD OF OPERATION THEREOF - A electronic system includes: an integrated circuit including: an internal data path, configured to drive a functional output, a universal streaming and logging interface, coupled to the internal data path, to generate a trace data bus, and a direct memory access (DMA) controller, coupled to the universal streaming and logging interface, to manage the storage of the trace data bus; a support circuit, coupled to the integrated circuit, configured to receive the trace data bus; and a support processor chip, coupled to the support circuit, configured to analyze the trace data bus for identifying a failure mode of the integrated circuit. | 03-12-2015 |
20150074318 | METHODS AND SYSTEMS FOR MULTIMEDIA DATA PROCESSING - In certain embodiments, methods and systems for multimedia data processing are provided. In an embodiment, a method for processing multimedia data includes defining one or more pixel block regions in a first cache so as to cache a plurality of reference pixel blocks corresponding to reference data. A reference pixel block from among the plurality of reference pixel blocks is assigned to a pixel block region from among the one or more pixel block regions based on a predetermined criterion. The reference pixel block is associated with a tag based on the pixel block region so as to facilitate a search of the reference data in order to process a plurality of pixel blocks associated with a multimedia frame of the multimedia data. | 03-12-2015 |
20150100716 | SYSTEMS AND METHODS OF USING AN SPI CONTROLLER - A system for managing internal-computer system communications including a processor, an SPI controller, an interconnector, and an SPI cluster containing multiple SPI interfaces, with the SPI interfaces being connected to one or more devices in the computer system or environment. The SPI cluster includes SPI interfaces that can convert communications to/from a plurality of device's formats to serialized digital formats suitable for ingest and actuation for the SPI controllers. The interconnector may use a differentially, optically, galvanometrically, inductively coupled driven wire and to enable communications between the SPI cluster constituents and the SPI controller. The SPI controller manages communications to the SPI interfaces that act as coordinated intermediates for device control and communications, thus insulating the computer system's processor from the increased workload of managing all internal system communications. | 04-09-2015 |
20150113195 | ELECTRONIC DEVICE - An electronic device includes: a communication module; an input module; a display; an interface; at least one sensor; a memory; and a processor module. The processor module includes at least one of: at least one dummy chip including at least one Through Silicon Via (TSV); at least one memory bridge including at least one TSV; at least one memory connected to the at least one dummy chip and the at least one memory bridge and that can exchange an electric signal through the at least one dummy chip and the at least one memory bridge; or at least one processor. The at least one processor may be configured to exchange an electric signal through the at least one memory bridge, and to transmit an electric signal to at least one of the communication module, input module, display, interface, at least one sensor, or first memory. The at least one processor may exchange information via a circuit path that includes at least one of the memory bridge and a portion of the at least one memory, when transmitting the electric signal. | 04-23-2015 |
20150120983 | DIRECT MEMORY ACCESS CONTROLLER, CONTROL METHOD THEREOF, AND INFORMATION PROCESSING SYSTEM - Two channels of a main CPU channel and a sub CPU channel each including a reception channel and a transmission channel, and performing a data transfer by a DMA in accordance with a descriptor are provided, a channel switching part selects the main CPU channel or the sub CPU channel in accordance with information set at a mode setting register, and performs a switching of channels at a boundary of a packet to be transferred to thereby enable the switching of channels without interrupting a DMA operation. | 04-30-2015 |
20150120984 | MEMORY SYSTEM HAVING HIGH DATA TRANSFER EFFICIENCY AND HOST CONTROLLER - According to one embodiment, the host controller includes a register set to issue command, and a direct memory access (DMA) unit and accesses a system memory and a device. First, second, third and fourth descriptors are stored in the system memory. The first descriptor includes a set of a plurality of pointers indicating a plurality of second descriptors. Each of the second descriptors comprises the third descriptor and fourth descriptor. The third descriptor includes a command number, etc. The fourth descriptor includes information indicating addresses and sizes of a plurality of data arranged in the system memory. The DMA unit sets, in the register set, the contents of the third descriptor forming the second descriptor, from the head of the first descriptor as a start point, and transfers data between the system memory and the host controller in accordance with the contents of the fourth descriptor. | 04-30-2015 |
20150127869 | SYSTEM AND METHOD FOR SUPPORTING AN EFFICIENT PACKET PROCESSING MODEL IN A NETWORK ENVIRONMENT - A system and method can support efficient packet processing in a network environment. The system can comprise a thread scheduling engine that operates to assign a thread key to each software thread in a plurality of software threads. Furthermore, the system can comprise a pool of direct memory access (DMA) resources that can be used to process packets in the network environment. Additionally, each said software thread operates to request access to a DMA resource in the pool of DMA resources by presenting an assigned thread key, and a single software thread is allowed to access multiple DMA resources using the same thread key. | 05-07-2015 |
20150127870 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a first global line suitable for inputting/outputting data from/to a first bank, a second global line suitable for inputting/outputting data from/to a second bank, a multi-purpose register (MPR) suitable for loading data having a predetermined value on the first global line in a training mode, a first data input/output (I/O) unit suitable for inputting/outputting data between one of the first and second global lines and a first data pad and selectively transferring data loaded on the first global line to the second global line in response to a bandwidth option in the training mode, and a second data I/O unit enabled in response to the bandwidth option, suitable for inputting/outputting data between the second global line and a second data pad. | 05-07-2015 |
20150127871 | UPDATED IO MEMORY MANAGEMENT UNIT IDENTITY SETTINGS FOR DMA REMAPPING - Disclosed is a system and method for updating IOMMU (Input Output Memory Management Unit) tables for remapping DMA (Direct Memory Access) range for a requested bus device when the device is active. | 05-07-2015 |
20150127872 | COMPUTER SYSTEM, SERVER MODULE, AND STORAGE MODULE - An exemplary computer system includes a server module including a first processor and first memory, a storage module including a second processor, a second memory and a storage device, and a transfer module. The transfer module retrieves a first transfer list including an address of a first storage area, which is set on the first memory for a read command, from the server module. The transfer module retrieves a second transfer list including an address of a second storage area in the second memory, in which data corresponding to the read command read from the storage device is stored temporarily, from the storage module. The transfer module sends the data corresponding to the read command in the second storage area to the first storage area by controlling the data transfer between the second storage area and the first storage area based on the first and second transfer lists. | 05-07-2015 |
20150134871 | REDUCED HOST DATA COMMAND PROCESSING - Methods and systems are provided that execute reduced host data commands. A reduced host data command may be a write command that includes or is received with an indication of host data instead of the host data. The reduced host data command may be executed with a Direct Memory Access (DMA) circuit independently of a processor that executes administrative commands. In the execution of the reduced host data command, host data may be generated, metadata may be generated, and the generated host data and/or metadata may be copied into backend memory with the DMA circuit independently of the processor. | 05-14-2015 |
20150134872 | BUS SUBSCRIBER FOR A BUS SYSTEM, BUS SYSTEM FOR A MOTOR VEHICLE, AND METHOD FOR ALLOCATING ADDRESSES IN A BUS SYSTEM - A bus system that has at least two lines. A bus subscriber has at least one connection element that has at least two contacts that can each be connected to one of the lines. An address allocation device can be used to ascertain an address for the bus subscriber in the bus system on the basis of a respective connection state of the contacts with respect to the lines. Also, a method allocates addresses in the bus system. | 05-14-2015 |
20150143014 | SUPPORT FOR IOAPIC INTERRUPTS IN AMBA-BASED DEVICES - One disclosed computing system comprises a x86 processor, memory, a PCIe root complex (RC), a PCIe bus, and an interconnect chip having a PCIe endpoint (EP) that is connected to the PCIe RC through a PCIe link, the PCIe EP being connected to an AMBA® bus. The interconnect chip may communicate with the IO device via the AMBA® bus in an AMBA® compliant manner and communicate with the host system in a PCIe compliant manner. This communication may include receiving a command from the processor, sending the command to the IO device over the AMBA® bus, receiving a response from the IO device over the AMBA® bus, and sending over the AMBA® bus and the PCIe link one or more DMA operations to the memory. Further communication may include sending an IOAPIC interrupt to the processor of the host system according to PCIe ordering rules. | 05-21-2015 |
20150143015 | DMA CONTROLLER AND DATA READOUT DEVICE - A DMA controller ( | 05-21-2015 |
20150149680 | INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD - An information processing apparatus having first and second buses, includes: a read/write command unit transmitting a read command or a write command to the first bus; a read command unit receiving a read command from the second bus; a write command unit receiving a write command from the second bus; and a command unit transmit the read command and the write command to the read/write command unit based on the read and write commands received by the read command unit and the write command unit. | 05-28-2015 |
20150149681 | METHODS FOR SHARING BANDWIDTH ACROSS A PACKETIZED BUS AND SYSTEMS THEREOF - A system, method, and computer readable medium for sharing bandwidth among executing application programs across a packetized bus for packets from multiple DMA channels includes receiving at a network traffic management device first and second network packets from respective first and second DMA channels. The received packets are segmented into respective one or more constituent CPU bus packets. The segmented constituent CPU bus packets are interleaved for transmission across a packetized CPU bus. | 05-28-2015 |
20150149682 | IN-VEHICLE SENSOR, IN-VEHICLE SENSOR SYSTEM, AND METHOD OF SETTING IDENTIFIERS OF IN-VEHICLE SENSORS IN IN-VEHICLE SENSOR SYSTEM - An in-vehicle sensor ( | 05-28-2015 |
20150293863 | BROADCAST AND UNICAST COMMUNICATION BETWEEN NON-COHERENT PROCESSORS USING COHERENT ADDRESS OPERATIONS - Non-address data is received that is to be transmitted on a non-transitory communication medium communicably coupling a plurality of devices, wherein the communication medium includes an address component and a data transport component separate from the address component. At least a portion of the non-address data is inserted into a portion of an address command. An indicator is set in the address command to notify a receiver that the information received in the address command over the address component is not associated with a memory address. The address command containing the non-address data is then sent over the address component of the communication medium. | 10-15-2015 |
20150293865 | Restore PCIe Transaction ID On The Fly - Restoring retired transaction identifiers (TID) associated with Direct Memory Access (DMA) commands without waiting for all DMA traffic to terminate is disclosed. A scoreboard is used to track retired TIDs and selectively restore retired TIDs on the fly. DMA engines fetch a TID, and use it to tag every DMA request. If the request is completed, the TID can be recycled to be used to tag a subsequent request. However, if a request is not completed, the TID is retired. Retired TIDs can be restored without having to wait for DMA traffic to end. Any retired TID value may be mapped to a bit location inside a scoreboard. All processors in the system may have access to read and clear the scoreboard. Clearing the TID scoreboard may trigger a DMA engine to restore the TID mapped to that location, and the TID may be used again. | 10-15-2015 |
20150293880 | SERIAL BUS INTERFACE TO ENABLE HIGH-PERFORMANCE AND ENERGY-EFFICIENT DATA LOGGING - A new serial bus interface module that enables constrained sensor systems to better match flash-based storage devices' (SD card) read and write performance. The serial bus interface module augments existing flash-based storage with non-volatile random-access memory to form a hybrid storage system using the most popularly used master-slave bus architecture. Together with PSC-like features, the serial bus interface module not only enables slave-to-slave transfer (therefore eliminating the double-transaction problem) but also reads caching (one source to multi-sink) and buffering while flushing. These transaction types enable multi-sector write for significantly faster speed and lower energy overhead, while the use of non-volatile memory for metadata caching means low risk of file-system corruption in the event of power failure. The serial bus interface also enables the direct data transfer from sensors to storage or communication modules without requiring the microprocessor's intervention. | 10-15-2015 |
20150295010 | ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME - This technology provides an electronic device and a method of fabricating the same. An electronic device in accordance with an implementation of this document includes a transistor comprising a semiconductor substrate including an active region defined by an isolation layer; and a gate which is formed over the active region and the isolation layer and extends in a first direction to cross the active region, wherein the active region includes a head portion towering over the isolation layer, a body portion disposed under the head portion, and a neck portion which is disposed between the head portion and the body portion and is recessed compared to the head portion and the body portion in the first direction, in a region where the gate and the active region overlap with each other. | 10-15-2015 |
20150301745 | COMPUTER REALIZING HIGH-SPEED ACCESS AND DATA PROTECTION OF STORAGE DEVICE, COMPUTER SYSTEM, AND I/O REQUEST PROCESSING METHOD - In a computer, a logical partition for calculation in which an OS and an application operate and a logical partition for storage for providing a storage function are constructed. In the logical partition for calculation, a device corresponding to a storage device is provided, while the logical partition for storage provides a volume. A memory space that can be shared by the both logical partitions is prepared, and management information describing a sorting destination or a sorting method of an I/O request issued by an application is provided in the memory. If the logical partition for calculation receives an I/O request from the application, the partition refers to the management information and sorts the I/O request to the storage device or the logical partition for storage. The logical partition for storage processes the received I/O request by the storage function and transmits the result to the storage device. | 10-22-2015 |
20150301964 | METHODS AND SYSTEMS OF MULTI-MEMORY, CONTROL AND DATA PLANE ARCHITECTURE - In one exemplary embodiment, a data-plane architecture includes a set of one or more memories that store a data and a metadata. Each memory of the set of one or more memories is split into an independent memory system. The data-planes architectures includes a storage device. A network adapter transfers data to the set of one or more memories. A set of one or mote processing pipelines transform and process the data from the set of one or more memories; wherein the the one or more processing pipelines are coupled with the one or more memories, the storage device, and wherein each of the set of one or more processing pipelines comprise a programmable block for local data processing. | 10-22-2015 |
20150301965 | INTERFACE UNIT - An interface unit is provided for the arrangement between a bus system, to which a processor unit and a data memory are connectable, and a data transporting unit, in particular a network processor, are described. The interface unit carries out a direct memory access to the data memory as a function of an identifier (chid) previously agreed upon between an application and the data transporting unit. | 10-22-2015 |
20150309839 | Virtual Machine Live Migration Method, Virtual Machine Memory Data Processing Method, Server, and Virtual Machine System - A virtual machine live migration method and a server, to resolve a problem that live migration of a virtual machine cannot be implemented in an SR-IOV technology scenario. According to the virtual machine live migration method and the server in the embodiments of the present invention, by setting a dirty write flag, a virtual PCIE device of a to-be-migrated virtual machine performs at least one read and write operation on received data; a virtual machine manager of the to-be-migrated virtual machine can identify a change in the data and migrate changed data to a destination virtual machine, thereby resolving a problem in the prior art that data cannot be migrated during a virtual machine live migration process because the data passes through the virtual PCIE device but the virtual machine manager cannot perceive the data. | 10-29-2015 |
20150309943 | MEMORY CONTROL UNIT AND DATA STORAGE DEVICE INCLUDING THE SAME - A data storage device includes a storage memory device, a control unit suitable for generating a descriptor, which describes a work for controlling the storage memory device, and storing the descriptor in a working memory, and a memory control unit suitable for generating control signals for the storage memory device by fetching an instruction set from an instruction memory based on the descriptor. | 10-29-2015 |
20150309947 | TRACKING STATISTICS CORRESPONDING TO DATA ACCESS IN A COMPUTER SYSTEM - Embodiments of the present invention disclose a method, computer program product, and system for determining statistics corresponding to data transfer operations. In one embodiment, the computer implemented method includes the steps of receiving a request from an input/output (I/O) device to perform a data transfer operation between the I/O device and a memory, generating an entry in an input/output memory management unit (IOMMU) corresponding to the data transfer operation, wherein the entry in the IOMMU includes at least an indication of a processor chip that corresponds to the memory of the data transfer operation, monitoring the data transfer operation between the I/O device and the memory, determining statistics corresponding to the monitored data transfer operation, wherein the determined statistics include at least: the I/O device that performed the data transfer operation, the processor chip that corresponds to the memory of the data transfer operation, and an amount of data transferred. | 10-29-2015 |
20150309948 | TRACKING STATISTICS CORRESPONDING TO DATA ACCESS IN A COMPUTER SYSTEM - Embodiments of the present invention disclose a method, computer program product, and system for determining statistics corresponding to data transfer operations. In one embodiment, the computer implemented method includes the steps of receiving a request from an input/output (I/O) device to perform a data transfer operation between the I/O device and a memory, generating an entry in an input/output memory management unit (IOMMU) corresponding to the data transfer operation, wherein the entry in the IOMMU includes at least an indication of a processor chip that corresponds to the memory of the data transfer operation, monitoring the data transfer operation between the I/O device and the memory, determining statistics corresponding to the monitored data transfer operation, wherein the determined statistics include at least: the I/O device that performed the data transfer operation, the processor chip that corresponds to the memory of the data transfer operation, and an amount of data transferred. | 10-29-2015 |
20150316978 | MULTIMEDIA PROCESSING SYSTEM AND METHOD OF OPERATING THE SAME - The multimedia processing system includes a plurality of first units including a CPU and a top domain; a storage domain configured to store a plurality of multimedia data; a multimedia codec domain configured to decode segments of target multimedia data received from the storage domain and to output decoded segments according to control of the CPU or the top domain; a system bus configured to connect the plurality of first units, the storage domain, and the multimedia codec domain with one another; and an alive domain configured to control power supply to the plurality of first units, the storage domain, the multimedia codec domain, and the system bus and to receive a signal from a user. | 11-05-2015 |
20150317269 | SWITCHING A COMPUTER SYSTEM FROM A HIGH PERFORMANCE MODE TO A LOW POWER MODE - A computer system includes a first processor, a second processor, and a common memory connected to the second processor. The computer system is switched from a high performance mode, in which at least a portion of the first processor and at least a portion of components on the second processor are active, to a low power mode, in which at least a portion of the first processor is active and the components on the second processor are inactive. All central processing unit (CPU) cores on the second processor are quiesced. Traffic from the second processor to the common memory is quiesced. Paths used by the first processor to access the common memory are switched from a first path across the second processor to a second path across the second processor. | 11-05-2015 |
20150317274 | IMPLEMENTING COHERENT ACCELERATOR FUNCTION ISOLATION FOR VIRTUALIZATION - A method, system and computer program product are provided for implementing coherent accelerator function isolation for virtualization in an input/output (IO) adapter in a computer system. A coherent accelerator provides accelerator function units (AFUs), each AFU is adapted to operate independently of the other AFUs to perform a computing task that can be implemented within application software on a processor. The AFU has access to system memory bound to the application software and is adapted to make copies of that memory within AFU memory-cache in the AFU. As part of this memory coherency domain, each of the AFU memory-cache and processor memory-cache is adapted to be aware of changes to data commonly in either cache as well as data changed in memory of which the respective cache contains a copy. | 11-05-2015 |
20150323975 | SYNCHRONIZATION OF ACTIVITY OF MULTIPLE SUBSYSTEMS IN A SoC TO SAVE STATIC POWER - The present disclosure relates to synchronization and parallel operation of two or more cores within a multi-core computing system so as to reduce an amount of time that all cores are operating during a processing period and thereby increase an amount of idle time per processing period. In this way deeper sleep and/or idle states for the cores and the system can be entered. | 11-12-2015 |
20150324306 | FLOW PINNING IN A SERVER ON A CHIP - Various embodiments provide for a system on a chip or a server on a chip that performs flow pinning, where packets or streams of packets are enqueued to specific queues, wherein each queue is associated with a respective core in a multiprocessor/multi-core system or server on a chip. With each stream of packets, or flow, assigned to a particular processor, the server on a chip can process and intake packets from multiple queues from multiple streams from the same single Ethernet interface in parallel. Each of the queues can issue interrupts to their assigned processors, allowing each of the processors to receive packets from their respective queues at the same time. Packet processing speed is therefore increased by receiving and processing packets in parallel for different streams. | 11-12-2015 |
20150324307 | INPUT/OUTPUT DEVICE TRANSFERRING AND/OR RECEIVING DATA TO AND/OR FROM A CONTROL DEVICE - The invention relates to a input/output device transferring and/or receiving data to and/or from a control device, wherein the input/output device transfers the data to the control device over a physical connection of the Ethernet type according to a UDP/IP protocol, the input/output device being connected to a plurality of data processing or acquisition devices by means of at least one connection different from the Ethernet physical connection and in that the input/output device includes means for connecting at least one other input/output device to the Ethernet connection and for managing the transmission over the Ethernet connection of the data transmitted by the input/output devices to the control device. | 11-12-2015 |
20150324308 | SOLID STATE DRIVE CONTROLLING CIRCUIT AND RELATED SOLID STATE DRIVE DEVICE AND SOLID STATE DRIVE ACCESS SYSTEM - A solid state drive (SSD) controlling circuit and related SSD device and SSD access system are disclosed. The SSD controlling circuit includes: an AHCI (advance host controller interface) controlling circuit for coupling with a PCIe (peripheral component interconnect express) interface; and a flash memory controlling circuit coupled with the AHCI controlling circuit and configured to operably control accessing operations of one or multiple flash memory arrays of a solid state drive. The AHCI controlling circuit transmits an indication message to a host device through the PCIe interface. The indication message is configured to declare that the AHCI controlling circuit is currently coupled with M solid state drives, wherein M is an integer greater than 1 and less than 32. | 11-12-2015 |
20150324309 | COMMUNICATION VIA A MEMORY INTERFACE - A memory space of a module connected to a memory controller via a memory interface may be used as a command buffer. Commands received by the module via the command buffer are executed by the module. The memory controller may write to the command buffer out-of-order. The memory controller may delay or eliminate writes to the command buffer. Tags associated with commands are used to specify the order commands are executed. A status buffer in the memory space of the module is used to communicate whether commands have been received or executed. Information received via the status buffer can be used as a basis for a determination to re-send commands to the command buffer. | 11-12-2015 |
20150324314 | STORAGE DEVICE WITH EXPANSION SLOT - Provided is an apparatus including a first storage device. The apparatus also includes an expansion slot configured to receive a removable card with a second storage device. The removable card with the second storage device is configured to provide faster read/write times to the second storage device than read/write times of the first storage device. The first and second storage devices are seen as a single storage device by a host computing device. | 11-12-2015 |
20150331638 | EFFICIENT ENFORCEMENT OF COMMAND EXECUTION ORDER IN SOLID STATE DRIVES - A method in a storage device includes receiving from a host storage commands for execution in a non-volatile memory of the storage device. At least a subset of the storage commands are to be executed in accordance with an order-of-arrival in which the storage commands in the subset are received. The received storage commands are executed in the non-volatile memory in accordance with internal scheduling criteria of the storage device, which permit deviations from the order-of-arrival, but such that execution of the storage commands in the subset reflects the order-of-arrival to the host. | 11-19-2015 |
20150331817 | Memory Rank and ODT Configuration in a Memory System - A memory system includes a two memory modules and a memory controller. The memory modules each include at least a first memory package corresponding to a first number of memory ranks (e.g. one memory rank) and a second memory package corresponding to a second number of memory ranks (e.g. two memory ranks) that is greater than the first number of memory ranks For each module, the memory packages may be asymmetrically staggered such that one memory package is further from the memory controller than the other memory package. The memory controller is coupled to the memory packages of both modules via a common data line and generates control information for controlling the on-die termination (ODT) of the memory packages. | 11-19-2015 |
20150339224 | SYSTEM AND METHOD FOR HOST-PROCESSOR COMMUNICATION OVER A BUS - A system, method and computer program product for communications between computer devices, including a mobile device having a mobile application running thereon; a specialized memory device having a memory device application running thereon and further having one of a memory device processor and a memory device controller; and a bus for providing communication between the mobile device and the specialized memory device. An unmodified file system and/or driver for the specialized memory device is employed on the mobile device. The specialized memory device processor or the specialized memory device controller need not employ file system awareness. | 11-26-2015 |
20150339239 | PROVIDING MEMORY BANDWIDTH COMPRESSION USING COMPRESSED MEMORY CONTROLLERS (CMCs) IN A CENTRAL PROCESSING UNIT (CPU)-BASED SYSTEM - Providing memory bandwidth compression using compressed memory controllers (CMCs) in a central processing unit (CPU)-based system is disclosed. In this regard, in some aspects, a CMC is configured to receive a memory read request to a physical address in a system memory, and read a compression indicator (CI) for the physical address from a master directory and/or from error correcting code (ECC) bits of the physical address. Based on the CI, the CMC determines a number of memory blocks to be read for the memory read request, and reads the determined number of memory blocks. In some aspects, a CMC is configured to receive a memory write request to a physical address in the system memory, and generate a CI for write data based on a compression pattern of the write data. The CMC updates the master directory and/or the ECC bits of the physical address with the generated CI. | 11-26-2015 |
20150339246 | INFORMATION PROCESSING APPARATUS AND BUS CONTROL METHOD - An information processing apparatus includes: a plurality of memories; a plurality of buses each connected to each of the memories; an input/output device configured to make access to the plurality of memories; a processing unit configured to alter a mapping of a logical address and a physical address of a memory area used by the input/output device; and a switch configured to transfer access from the input/output device to any one of the plurality of buses based on the mapping, whereby the performance deterioration due to bus conflict is suppressed. | 11-26-2015 |
20150339247 | SYSTEM-ON-CHIP DESIGN STRUCTURE - Aspects may include a method of designing a system-on-chip. The method may include receiving multiple processing modules, each representing in software one of multiple processing units of a system-on-chip. The method may further include modeling communications from one or more of the multiple processing modules as accesses to memory. The method may further include generating a coherent memory module associated with the multiple processing modules based on modeling the communications from the one or more of the multiple processing modules as accesses to memory. The coherent memory module may represent in software a coherent memory associated with the multiple processing units. | 11-26-2015 |
20150347331 | MEMORY SYSTEM, MEMORY INTERFACING DEVICE, AND INTERFACING METHOD PERFORMED IN THE MEMORY SYSTEM - A method of interfacing a memory controller and a memory device in a memory system includes transmitting a control signal between the memory controller and the memory device using a time division multiplexing (TDM) communication process, and transmitting data between the memory controller and the memory device using a serializer/deserializer (SERDES) communication process. Data communication in the memory system is performed via a physical channel and a plurality of virtual channels corresponding to the physical channel. | 12-03-2015 |
20150347332 | A COMMON PUBLIC RADIO INTERFACE LANE CONTROLLER - A Common Public Radio Interface, CPRI, lane controller of a processor, in a Time Division Duplex, TDD, system, said CPRI lane controller comprising: a Direct Memory Access (or more than one), DMA, controller connected to a memory through a switch fabric to perform read or/and write memory access transactions via an internal system bus of said processor, wherein said DMA controller is adapted to generate a RX/TX transaction interrupt(s) for each completed memory access RX/TX transaction counted by a corresponding transaction counter(s) which provides a TDD slot awareness interrupt(s) when a RX/TX TDD slot has terminated, wherein said DMA controller has a steering control(s) adapted to steer the memory access transactions either to said memory or to be legitimately blocked by said switch fabric in response to said TDD slot awareness interrupt(s) to save bandwidth, BW, of the internal system bus of said processor. | 12-03-2015 |
20150347339 | System and Method for Extended Peripheral Component Interconnect Express Fabrics - An exemplary embodiment extended peripheral component interconnect express (PCIe) device includes a host PCIe fabric comprising a host root complex. The host PCIe fabric has a first set of bus numbers and a first memory mapped input/output (MMIO) space on a host CPU. An extended PCIe fabric includes a root complex endpoint (RCEP) as part of an endpoint of the host PCIe fabric. The extended PCIe fabric has a second set of bus numbers and a second MMIO space separate from the first set of bus numbers and the first MMIO space, respectively. | 12-03-2015 |
20150347349 | DIRECT ACCESS TO LOCAL MEMORY IN A PCI-E DEVICE - A method includes communicating between at least first and second devices over a bus in accordance with a bus address space, including providing direct access over the bus to a local address space of the first device by mapping at least some of the addresses of the local address space to the bus address space. In response to indicating, by the first device or the second device, that the second device requires to access a local address in the local address space that is not currently mapped to the bus address space, the local address is mapped to the bus address space, and the local address is accessed directly, by the second device, using the mapping. | 12-03-2015 |
20150356027 | CIRCUITS FOR AND METHODS OF ENABLING THE ACCESS TO DATA - A circuit for enabling access to data is described. The circuit comprises a memory device storing data blocks having a first predetermined size; and a direct memory access circuit coupled to the memory device, the direct memory circuit accessing a data payload having a second predetermined size which is greater than the first predetermined size; wherein the direct memory access circuit accesses the data payload in response to a descriptor having a plurality of addresses corresponding to a predetermined number of the data blocks stored in the memory device. A method of enabling the access to data is also disclosed. | 12-10-2015 |
20150356034 | EMBEDDED MICROCONTROLLER AND BUSES - A system can include a power supply unit; a processor; memory operatively coupled to the processor; a chipset operatively coupled to the processor; diagnostic information memory; and a microcontroller operatively coupled to the chipset via a first diagnostic data transfer bus and the microcontroller operatively coupled to the power supply unit and to the diagnostic information memory via a second diagnostic data transfer bus. | 12-10-2015 |
20150356044 | HIGH-SPEED MEMORY SYSTEM - The disclosed embodiments relate to a Flash-based memory module having high-speed serial communication. The Flash-based memory module comprises, among other things, a plurality of I/O modules, each configured to communicate with an external device over one or more external communication links, a plurality of Flash-based memory cards, each comprising a plurality of Flash memory devices, and a plurality of crossbar switching elements, each being connected to a respective one of the Flash-based memory cards and configured to allow each one of the I/O modules to communicate with the respective one of the Flash-based memory cards. Each I/O module is connected to each crossbar switching element by a high-speed serial communication link, and each crossbar switching element is connected to the respective one of the Flash-based memory cards by a plurality of parallel communication links. | 12-10-2015 |
20150356048 | METHOD AND APPARATUS FOR CONTROLLING ACCESS TO A COMMON BUS BY MULTIPLE COMPONENTS - Apparatuses and methods for controlling access to a common bus including a plurality of memory devices coupled to a common bus, wherein individual ones of the plurality of memory devices are configured to access the common bus responsive to a strobe signal, and a strobe line driver programmed with a first delay associated with a combination of a first command type and a first one of the plurality of memory devices to provide a first strobe signal to the first one of the plurality of memory devices, and further programmed with a second delay associated with a combination of a second command type and a second one of the plurality of memory devices to provide a second strobe signal to the second one of the plurality of memory devices. | 12-10-2015 |
20150363347 | PORTABLE USB MASS STORAGE DEVICE - A new type of portable USB mass storage gadget is disclosed which provides the user with upgradeable high speed mass storage and processing for use with portable computer appliances such as smart phones and tablets as well as standard desk top computers and laptops. Various modifications to the embodiment referred to as a UDRIVE are disclosed including a battery option, wireless connectivity, security, and additional internal electronics and external interfaces that allow processing of the data stored or sent to the portable gadget. | 12-17-2015 |
20150370586 | LOCAL SERVICE CHAINING WITH VIRTUAL MACHINES AND VIRTUALIZED CONTAINERS IN SOFTWARE DEFINED NETWORKING - Methods, software, and apparatus for implementing local service chaining (LSC) with virtual machines (VMs) or virtualized containers in Software Defined Networking (SDN). In one aspect a method is implemented on a compute platform including a plurality of VMs or containers, each including a virtual network interface controller (vNIC) communicatively coupled to a virtual switch in an SDN. LSCs are implemented via a plurality of virtual network appliances hosted by the plurality of VMs or containers. Each LCS comprises a sequence (chain) of services performed by virtual network appliances defined for the LSC. In connection with performing the chain of services, packet data is forwarded between VMs or containers using a cut-through mechanisms under which packet data is directly written to receive (Rx) buffers on the vNICs in a manner that bypasses the virtual switch. LSC indicia (e.g., through LSC tags) and flow tables are used to inform each virtual network appliance and/or or its host VM or container of the next vNIC Rx buffer or Rx port to which packet data is to be written. | 12-24-2015 |
20150370610 | FLEXIBLE DEPLOYMENT AND MIGRATION OF VIRTUAL MACHINES - Virtual machines in a computer system cluster, or cloud environment, require access to their assigned storage resources connected to the virtual machines via storage area networks (SAN). Such virtual machines may be independent from associated physical servers in the computer system cluster on which they are deployed. These virtual machines may dynamically migrate among assigned physical servers while maintaining access to their connected storage resources both from the source physical server and the target physical server during the migration. | 12-24-2015 |
20150370750 | MEMORY DEVICE FOR A HIERARCHICAL MEMORY ARCHITECTURE - A hierarchical memory device having multiple interfaces with different memory formats includes a Phase Change Memory (PCM). An input port and an output port connect the hierarchical memory device in a daisy-chain hierarchy or a hierarchical tree structure with other memories. Standard non-hierarchical memory devices can also attach to the output port of the hierarchical memory device. | 12-24-2015 |
20150378921 | SYSTEMS AND METHODS FOR STORAGE SERVICE AUTOMATION - A cache automation module detects the deployment of storage resources in a virtual computing environment and, in response, automatically configures cache services for the detected storage resources. The automation module may detect new storage resources by monitoring storage operations and/or requests, by use of an interface provided by virtualization infrastructure, and/or the like. The cache automation module may deterministically identify storage resources that are to be cached and automatically caching services for the identified storage resources. | 12-31-2015 |
20150378946 | HIGH THROUGHPUT REGISTER FILE MEMORY - Pipelining is included inside a register file memory. A register file memory device includes a static bitcell, and pipelined combinational logic. The combinational logic pipeline couples the I/O (input/output) node to the static bitcell. The pipeline includes multiple stages, where each stage includes a static logic element and a register element, where the operation of each stage transfers data through to a subsequent stage. The number of stages can be different for a read than a write. The multiple stages perform the operations to execute the read or write request. | 12-31-2015 |
20150378947 | CACHE LOAD BALANCING IN STORAGE CONTROLLERS - Methods and structure are provided for cache load balancing in storage controllers that utilize Solid State Drive (SSD) caches. One embodiment is a storage controller of a storage system. The storage controller includes a host interface operable to receive Input and Output (I/O) operations from a host computer. The storage controller also includes a cache memory that includes an SSD. Further, the storage controller includes a cache manager that is distinct from the cache memory. The cache manager is able to determine physical locations in the multiple SSDs that are unused, to identify an unused location that was written to a longer period of time ago than other unused locations, and to store a received I/O operation in the identified physical location. Further, the cache manager is able to trigger transmission of the stored I/O operations to storage devices of the storage system for processing. | 12-31-2015 |
20150378948 | Auxiliary Interface for Non-Volatile Memory System - A non-volatile memory system is formed a plurality of memory banks and a controller, where the controller has an auxiliary memory interface for use with an additionally non-volatile memory bank, where the additional memory bank and interface are used for metadata, such as logical to physical translation data. The other banks are used for user data. In an exemplary embodiment, a non-volatile memory could include a controller and (N+1) NAND flash memories, where N of these memories would store user data, but the remaining memory with its own controller interface would be dedicated to the storage of metadata. This allows for the metadata to be kept in non-volatile memory, but still quite readily accessible relative to the typical paging/overlay arrangement for metadata that is typically used in many non-volatile memory system. | 12-31-2015 |
20150378956 | MEMORY PHYSICAL LAYER INTERFACE LOGIC FOR GENERATING DYNAMIC RANDOM ACCESS MEMORY (DRAM) COMMANDS WITH PROGRAMMABLE DELAYS - A plurality of registers implemented in association with a memory physical layer interface (PHY) can be used to store one or more instruction words that indicate one or more commands and one or more delays. A training engine implemented in the memory PHY can generate at-speed programmable sequences of commands for delivery to an external memory and to delay the commands based on the one or more delays. The at-speed programmable sequences of commands can be generated based on the one or more instruction words. | 12-31-2015 |
20160004653 | CACHING SYSTEMS AND METHODS WITH SIMULATED NVDRAM - Systems and methods presented herein provide for simulated NVDRAM operations. In a host system, a host memory is sectioned into pages. An HBA in the host system comprises a DRAM and an SSD for cache operations. The DRAM and the SSD are sectioned into pages and mapped to pages of the host memory. The SSD is further sectioned into regions comprising one or more pages of the SSD. The HBA is operable to load a page of data from the SSD into a page of the DRAM when directed by a host processor, to determine that the page of the DRAM is occupied with other data, to determine a priority of the region of the page of other data occupying the page of the DRAM, and to flush the other data from the DRAM to the SSD based on the determined priority. | 01-07-2016 |
20160004654 | SYSTEM FOR MIGRATING STASH TRANSACTIONS - A system for migrating stash transactions includes first and second cores, an input/output memory management unit (IOMMU), an IOMMU mapping table, an input/output (I/O) device, a stash transaction migration management unit (STMMU), a queue manager and an operating system (OS) scheduler. The I/O device generates a first stash transaction request for a first data frame. The queue manager stores the first stash transaction request. When the first core executes a first thread, the queue manager stashes the first data frame to the first core by way of the IOMMU. The OS scheduler migrates the first thread from the first core to the second core and generates pre-empt notifiers. The STMMU uses the pre-empt notifiers to update the IOMMU mapping table and generate a stash replay command. The queue manager receives the stash replay command and stashes the first data frame to the second core. | 01-07-2016 |
20160004655 | COMPUTING SYSTEM AND OPERATING METHOD OF THE SAME - A computing system includes a first unified module including a first storage device and a second storage device that are different from each other, and a unified module interface configured to provide a direct memory access (DMA) request signal to control a first DMA with respect to the first storage device and to perform a second DMA on the second storage device. An application processor is configured to receive the DMA request signal from the unified module interface, and provide a DMA request response signal to the unified module interface and control the second DMA with respect to the second storage device. | 01-07-2016 |
20160004660 | MEMORY SYSTEM AND DATA STORAGE DEVICE - A memory system includes a first memory device and a second memory device suitable for outputting and receiving signals through first and second sub input/output lines, respectively, a controller suitable for outputting and receiving signals to and from the first memory device and the second memory device, through a main input/output line and a selection unit suitable for electrically coupling the main input/output line with one of the first and the second sub input/output lines, through which an activated one of the first memory and the second memory devices outputs and receives signals. | 01-07-2016 |
20160011987 | EFFICIENT SEARCH KEY CONTROLLER WITH STANDARD BUS INTERFACE, EXTERNAL MEMORY INTERFACE, AND INTERLAKEN LOOKASIDE INTERFACE | 01-14-2016 |
20160011994 | MULTI-PROCESSOR WITH EFFICIENT SEARCH KEY PROCESSING | 01-14-2016 |
20160011995 | ISLAND-BASED NETWORK FLOW PROCESSOR WITH EFFICIENT SEARCH KEY PROCESSING | 01-14-2016 |
20160011996 | MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER | 01-14-2016 |
20160011998 | DIRECT MEMORY ACCESS CONTROLLER | 01-14-2016 |
20160012003 | INPUT/OUTPUT ACCELERATION IN VIRTUALIZED INFORMATION HANDLING SYSTEMS | 01-14-2016 |
20160012005 | CACHED PHY REGISTER DATA ACCESS | 01-14-2016 |
20160019079 | SYSTEM AND METHOD FOR INPUT/OUTPUT ACCELERATION DEVICE HAVING STORAGE VIRTUAL APPLIANCE (SVA) USING ROOT OF PCI-E ENDPOINT - Methods and systems for I/O acceleration using an I/O accelerator device on a virtualized information handling system include pre-boot configuration of first and second device endpoints that appear as independent devices. After loading a storage virtual appliance that has exclusive access to the second device endpoint, a hypervisor may detect and load drivers for the first device endpoint. The storage virtual appliance may then initiate data transfer I/O operations using the I/O accelerator device. The data transfer operations may be read or write operations to a storage device that the storage virtual appliance provides access to. The I/O accelerator device may use direct memory access (DMA). | 01-21-2016 |
20160019178 | MEMORY MAPPING IN A PROCESSOR HAVING MULTIPLE PROGRAMMABLE UNITS - The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units. | 01-21-2016 |
20160026494 | MID-THREAD PRE-EMPTION WITH SOFTWARE ASSISTED CONTEXT SWITCH - Methods and apparatus relating to mid-thread pre-emption with software assisted context switch are described. In an embodiment, one or more threads executing on a Graphics Processing Unit (GPU) are stopped at an instruction level granularity in response to a request to pre-empt the one or more threads. The context data of the one or more threads is copied to memory in response to completion of the one or more threads at the instruction level granularity and/or one or more instructions. Other embodiments are also disclosed and claimed. | 01-28-2016 |
20160034405 | HETEROGENEOUS MEMORY SYSTEM AND DATA COMMUNICATION METHOD IN THE SAME - Provided are a heterogeneous memory system and a data communication method in the same. The heterogeneous memory system includes a plurality of different kinds of memory cells, and a central processing unit (CPU) configured to communicate with each of the plurality of memory cells using a high-speed serial link technique. The CPU includes a CPU protocol engine that generates and packetizes command data to be transmitted to at least one of the plurality of memory cells, and each of the plurality of memory cells include a memory protocol engine configured to analyze the command data received from the CPU, and a memory controller configured to perform the corresponding operation according to the analysis result in the memory protocol engine. | 02-04-2016 |
20160034408 | MEMORY MODULE WITH DISTRIBUTED DATA BUFFERS AND METHOD OF OPERATION - A memory module is operatable in a memory system with a memory controller. The memory module comprises a module control device to receive command signals from the memory controller and to output module command signals and module control signals. The module command signals are provided to memory devices organized in groups, each group including at least one memory device, while the module control signals are provided to a plurality of buffer circuits to control data paths in the buffer circuits. The plurality of buffer circuits are associated with respective groups of memory devices and are distributed across a surface of the memory module such that each module control signal arrives at the plurality of buffer circuits at different points in time. The plurality of buffer circuits are configured to align read data signals received from the memory devices such that the read data signals are transmitted to the memory controller from the memory module substantially aligned with each other and in accordance with a read latency parameter of the memory system. | 02-04-2016 |
20160041932 | MEMORY STORAGE WITH BATTERY AND SOLAR CELLS - A portable storage device can include a memory and one or more connectors for connecting to other devices. During use, a user can connect a remote device such as a smartphone, tablet, or the like to the portable storage device in order to transfer data from the remote device to the memory of the portable storage device. The portable storage device can include a rechargeable power source configured to provide the necessary electrical current for establishing communication between the remote device and the memory of the portable storage device. The portable storage device can further include one or more photovoltaic devices for generating electrical energy and recharging the rechargeable power source of the portable storage device. | 02-11-2016 |
20160048455 | Memory Data Transfer Method and System - A method and apparatus are disclosed for providing a DMA process. Accordingly, a DMA process is initiated for moving data from contiguous first locations to contiguous second locations and to a third location or third locations. Within the DMA process the data from each of the contiguous first locations is retrieved and stored in a corresponding one of the contiguous second locations and in the third location or corresponding one of the third locations. The DMA process is performed absent retrieving the same data a second other time prior to storing of same within the corresponding one of the contiguous second locations and in the third location or corresponding one of the third locations. | 02-18-2016 |
20160048466 | CONFIGURABLE MEMORY CIRCUIT SYSTEM AND METHOD - A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.). | 02-18-2016 |
20160048467 | USB DEVICE WITH DYNAMICALLY CONFIGURABLE ENDPOINT ALLOCATION - A compound USB device has a controller and a N+1 component USB devices. Each component USB device C | 02-18-2016 |
20160048468 | RESOURCE ALLOCATION BY VIRTUAL CHANNEL MANAGEMENT AND BUS MULTIPLEXING - According to embodiments of the invention, methods, computer system, and apparatus for virtual channel management and bus multiplexing are disclosed. The method may include establishing a virtual channel from a first device to a second device via a bus, the bus having a first bus capacity and a second bus capacity, the second bus capacity having greater capacity than the first bus capacity, determining whether a store command is issued for the first bus capacity, determining whether the first bus capacity is available, and allocating the second bus capacity and marking the second bus capacity as unavailable in response to the store command if the first bus capacity is unavailable. | 02-18-2016 |
20160055096 | Multi-Processor, Multi-Domain, Multi-Protocol Cache Coherent Speculation Aware Shared Memory Controller and Interconnect - This invention combines a multicore shared memory controller and an asynchronous protocol converting bridge to create a very efficient heterogeneous multi-processor system. After traversing the protocol converting bridge the commands travel through the regular processor port. This allows the interconnect to remain unchanged while having any combination of different processors connected. This invention tightly integrates all of the processors into the same memory controller/interconnect. | 02-25-2016 |
20160055107 | DATA PROCESSING APPARATUS AND METHOD - A data processing apparatus is provided, which includes: a plurality of processor cores; a shared processor cache, the shared processor cache being connected to each of the processor cores and to a main memory; a bus controller, the bus controller being connected to the shared processor cache and performing, in response to receiving a descriptor sent by one of the processor cores, a transfer of requested data indicated by the descriptor from the shared processor cache to an input/output (I/O) device; a bus unit, the bus unit being connected to the bus controller and transferring data to/from the I/O device; wherein the shared processor cache includes means for prefetching the requested data from the shared processor cache or main memory by performing a direct memory access in response to receiving a descriptor from the one of the processor cores. | 02-25-2016 |
20160055113 | Redundant System Boot Code in a Secondary Non-Volatile Memory - A controller determines whether system boot code stored in a first non-volatile memory is compromised and non-recoverable. In response to determining that the system boot code is compromised and non-recoverable, switch logic is activated to connect a second non-volatile memory to the shared bus and to disconnect the first non-volatile memory from the shared bus. | 02-25-2016 |
20160056246 | ELECTRONIC DEVICE - An electronic device includes a transistor. The transistor includes a body including a metal oxide; a gate electrode; and a gate insulating layer interposed between the body and the gate electrode, wherein the transistor is turned on or turned off by movement of oxygen vacancies in the body according to voltages applied to the gate electrode and the body. | 02-25-2016 |
20160062653 | MEMORY CARD - The memory card includes a non-volatile memory, an internal memory, a bus converter, and a media controller. The non-volatile memory is rewritable. The internal memory is configured to divide data transferred from a host into M (M is an integer of 2 or more) segments each of which including N (N is a natural number) times a minimum transfer unit of the non-volatile memory as a unit to record. The bus converter is configured to output 1/M of the minimum transfer unit of data in parallel from each of the M segments recorded in the internal memory. The media controller is configured to integrate 1/M of data belonging to each of different segments input in parallel from the bus converter as one minimum transfer unit of data to record in the non-volatile memory. | 03-03-2016 |
20160062729 | MULTI-CHANNEL AUDIO COMMUNICATION IN A SERIAL LOW-POWER INTER-CHIP MEDIA BUS (SLIMBUS) SYSTEM - Multi-channel audio communication in a Serial Low-power Inter-chip Media Bus (SLIMbus) system is disclosed. In this regard, in one aspect, a multi-channel output port is provided in a SLIMbus system. The multi-channel output port receives an audio stream from an audio source (e.g., a storage medium) via a direct memory access (DMA) pipe and distributes the audio stream to multiple receiving ports (e.g., speakers) over multiple data channels, all connected to the single multi-channel output port. In another aspect, a multi-channel input port is provided in a SLIMbus system. The multi-channel input port connects to multiple data channels from multiple distributing ports (e.g., microphones). By providing the multi-channel output port and/or the multi-channel input port in a SLIMbus system, it is possible to support multiple data channels with a single DMA pipe, thus improving implementation flexibilities and efficiencies of the SLIMbus system. | 03-03-2016 |
20160062911 | ROUTING DIRECT MEMORY ACCESS REQUESTS IN A VIRTUALIZED COMPUTING ENVIRONMENT - A device may receive a direct memory access request that identifies a virtual address. The device may determine whether the virtual address is within a particular range of virtual addresses. The device may selectively perform a first action or a second action based on determining whether the virtual address is within the particular range of virtual addresses. The first action may include causing a first address translation algorithm to be performed to translate the virtual address to a physical address associated with a memory device when the virtual address is not within the particular range of virtual addresses. The second action may include causing a second address translation algorithm to be performed to translate the virtual address to the physical address when the virtual address is within the particular range of virtual addresses. The second address translation algorithm may be different from the first address translation algorithm. | 03-03-2016 |
20160062926 | STORAGE CONTROL DEVICES AND METHOD THEREFOR TO INVOKE ADDRESS THEREOF - A storage control device comprises storage control and memory modules coupled with each other. The memory module keeps a first Serial Attached SCSI (SAS) address. In one embodiment the memory module further keeps a firmware which the storage control module executes to invoke the first SAS address to facilitate data communication. To invoke the first SAS address, in one embodiment the storage control module fetches a bit string from the memory module. The bit string is written into a data structure that is returned to the storage control module when it is determined that the bit string is a SAS address. In one embodiment the memory module further keeps a configuration file which the storage control module invokes to operate. The configuration file comprises a second SAS address, which is not invoked by the storage control module unless the bit string is not a SAS address. | 03-03-2016 |
20160062927 | DATA TRANSFER CONTROL APPARATUS - A data transfer control apparatus controls data transfers between different modules, and includes a module DMA controller configured for a predetermined module, a function DMA controller that provides a function absent in the module DMA controller, and a temporary memory coupled to the module DMA controller and the function DMA controller. When the temporary memory is input with data acquired by the module DMA controller from the predetermined module in order of acquisition, the temporary memory outputs the acquired data to the function DMA controller in order of input. When the temporary memory is input with data to be transferred to the predetermined module from the function DMA controller, the temporary memory outputs the data to be transferred to the module DMA controller in order of input. | 03-03-2016 |
20160062928 | INFORMATION PROCESSOR WITH TIGHTLY COUPLED SMART MEMORY UNIT - An information processor includes a plurality of first processing units; and a direct memory access unit coupled to at least one first processing unit. The information processor includes at least one first memory unit coupled to the direct memory access unit. The first memory unit includes a second memory unit. The first memory unit includes a second processing unit for processing data stored in the second memory unit. The second memory unit is adapted to be accessed by at least one first processing unit through the direct memory access unit, and the second processing unit is separate from the plurality of first processing units and the direct memory access unit. The first memory unit includes at least one register to be accessed by the at least one first processing unit and the second processing unit. The second processing unit is for receiving operation instructions from the at least one register. | 03-03-2016 |
20160070665 | PORTABLE ELECTRONIC DEVICE AND USER DATA ACCESS METHOD THEREFOR - A portable electronic device with user data access method. The disclosed portable electronic device includes a first non-volatile memory, a central processing unit, an interface and a connector. The first non-volatile memory is configured to store first data. The central processing unit is powered with an operating voltage and is configured to run an operating system. The interface controller is electrically coupled to the first non-volatile memory. The connector is electrically coupled to the interface controller and configured to connect with a host device. When the central processing unit crashes or is not powered with the operating voltage, the interface controller is configured to read the first data stored in the first non-volatile memory and transmit the first data to the host device via the connector. | 03-10-2016 |
20160077988 | EFFICIENT DATA MOVEMENT WITHIN FILE SYSTEM VOLUMES - Embodiments are directed to efficiently managing data storage and efficiently storing data. In one scenario, a computer system receives a write request addressed to one portion of data storage within a data store. The computer system redirects the received write request to another portion of data storage which includes storage containers, each of which is a logically specified portion of the data store. The computer system determines which storage container the write request is to write to, and identifies a storage container that is to be de-staged from the second portion of data storage to the first portion of data storage. The computer system then de-stages the identified storage containers to the first portion of data storage, the data of the de-staged container being stored on the first portion of data storage in the same order in which the data was stored in the identified storage container prior to de-staging. | 03-17-2016 |
20160077989 | METHODS AND APPARATUS FOR AGGREGATING PACKET TRANSFER OVER A VIRTUAL BUS INTERFACE - Methods and apparatus for data aggregation and multiplexing of one or more virtual bus interfaces via a physical bus interface. Various disclosed embodiments are configured to: (i) multiplex multiple logical interfaces over a single physical interface, (ii) exchange session management and logical interface control, (iii) manage flow control, (iv) provide “hints” about the data (e.g., metadata), and/or (v) pad data packets. In one particular implementation, the methods and apparatus are configured for use within a wirless-enabled portable electronic device, such as for example a cellular-enabled smartphone, and make use of one or more features of a high-speed serialized physical bus interface. | 03-17-2016 |
20160085689 | MEMORY TRANSFER OF OBJECTS IN A DATA STORAGE DEVICE - Herein are data storage devices to transfer a data object between memory regions during a storage operation. These data storage devices include a host controller configured to identify an object stored in a host region of a memory system for writing to a storage media controlled by a drive controller. The host controller initiates a memory transfer operation to transfer an object from the host region of the memory system to a drive region of the memory system. The host controller transfers a storage command to the drive controller to write the object to the storage media. The drive controller may be configured to transfer an object from the drive region to the host region when reading the object. | 03-24-2016 |
20160085701 | CHAINED CPP COMMAND - A chained Command/Push/Pull (CPP) bus command is output by a first device and is sent from a CPP bus master interface across a set of command conductors of a CPP bus to a second device. The chained CPP command includes a reference value. The second device decodes the command, in response determines a plurality of CPP commands, and outputs the plurality of CPP commands onto the CPP bus. The second device detects when the plurality of CPP commands have been completed, and in response returns the reference value back to the CPP bus master interface of the first device via a set of data conductors of the CPP bus. The reference value indicates to the first device that an overall operation of the chained CPP command has been completed. | 03-24-2016 |
20160085702 | HIERARCHICAL IN-MEMORY SORT ENGINE - A local sorting module includes a set of storage elements storing binary vectors configured in a one-dimensional (1D) or two-dimensional (2D) array structure and separated by respective comparators configured to conditionally compare and sort the binary vectors. The comparators may perform a sort using a compare-and-flip or a compare-and-swap operation. Local sorting modules may be coupled with a global sorting module for enabling a tournament sort algorithm to output values stored in storage elements one at a time until all data is outputted in a predetermined sorting order. | 03-24-2016 |
20160092362 | MEMORY NETWORK TO ROUTE MEMORY TRAFFIC AND I/O TRAFFIC - According to an example, memory traffic including memory access commands is routed between compute nodes and memory nodes in a memory network. Other traffic is also routed in the memory network. The other traffic may include input/output traffic between the compute nodes and peripherals connected to the memory network. | 03-31-2016 |
20160092383 | COMMON DIE IMPLEMENTATION FOR MEMORY DEVICES - A memory device and a memory controller can interface over a system data bus that has a narrower bandwidth than a data bus internal to the memory device. The memory device and memory controller transfer data over the system data bus on all transfer periods of a burst length, but send fewer bits than would be needed for the exchange to transfer all bits that can be read or written on the internal data bus of the memory device. The memory device can have different operating modes to allow for a common memory device to be used in different system configurations based on the ability to interface with the narrower bandwidth system data bus. | 03-31-2016 |
20160098367 | LOGICAL-TO-PHYSICAL BLOCK MAPPING INSIDE THE DISK CONTROLLER: ACCESSING DATA OBJECTS WITHOUT OPERATING SYSTEM INTERVENTION - Data access in a storage device managed by a storage controller is carried out by receiving in the storage controller offsets in objects directly from a plurality of requesting entities of a computer system. The computer controls a mapping mechanism operated by the storage controller, wherein the mapping mechanism relates the offsets in the objects into physical addresses of the data on the storage device, and wherein the data is accessed at the physical addresses. | 04-07-2016 |
20160110303 | ELECTRONIC DEVICE AND SYSTEM FOR SHARING THE EDID OF A DISPLAY AMONG MULTIPLE HOSTS - The present disclosure provides an electronic device that comprises a memory and a controller. The memory includes a first memory location and a second memory location, which are configured to store data in an alternate manner The controller is configured to write, when connection of a display to the electronic device is detected, extended display identification data (EDID) of the display through a first channel to one of the first and second memory locations, and to enable the EDID of the display to be accessible to hosts through second channels. | 04-21-2016 |
20160124876 | METHODS AND SYSTEMS FOR NOTICING COMPLETION OF READ REQUESTS IN SOLID STATE DRIVES - The present disclosure relates to methods and systems for performing operations in a communications protocol. An example method can include submitting a request for a queue entry representing a command from a host comprising a request for data stored at a storage location; receiving the command from the host; and executing the command. The method can include providing a first set of the requested data, and providing a control signal to the host before providing a second set of the requested data. The control signal can indicate that a transmission of the requested data will complete. | 05-05-2016 |
20160124877 | Apparatus and Method for RDMA with Commit ACKs - Embodiments of apparatuses and methods for remote direct memory access (RDMA) with commit acknowledgements (ACKs) are described. In embodiments, a device may include a process queue to store a remote direct memory access (RDMA) request from an initiator to update a target memory. The device may further include a control module, coupled to the process queue, to issue a commit operation to the target memory based on the RDMA request and generate an acknowledgement, ACK, to be sent to the initiator on completion of the commit operation. Other embodiments may be described and/or claimed. | 05-05-2016 |
20160124878 | DATA TRANSFER - A controller coupled to a peripheral identifies an access type used by the controller for data transfer. The controller performs operations including: sending information to a peripheral coupled to a controller, the information indicating an access type for which the controller is configured for data transfer; monitoring a communication link with the peripheral for a signal indicating that the peripheral is ready to perform a data transfer according to the access type; and performing, in response to a receipt of the signal through the communication link, the data transfer using data transfer handshake signals that are adapted according to the access type. | 05-05-2016 |
20160124879 | SYSTEM INTERNAL LATENCY MEASUREMENTS IN REALTIME APPLICATIONS - Systems, methods, circuits and computer-readable mediums for system internal latency measurements in realtime applications are disclosed. In some implementations, a trigger signal is selected from a plurality of trigger signals for interrupting a processor of an integrated circuit system. The trigger signal includes a pulse having width. The system detects a rising edge of the pulse and starts a counter. The system detects a falling edge of the pulse and stops the counter. The system then compares a count of the counter with first and second values stored in first and second registers, respectively. The first value represents a minimum pulse width and the second value represents a maximum pulse width. The count is stored in the first or second register based on a result of the comparing. | 05-05-2016 |
20160132440 | MULTI-CHANNEL I2S TRANSMIT CONTROL SYSTEM AND METHOD - A serial peripheral interface is configurable to operate in a I | 05-12-2016 |
20160132442 | DATA WRITING SYSTEM AND METHOD FOR DMA - A data writing system is provided. A processing unit includes at least one core processor. The dynamic random access memory (DRAM) includes a user buffer storing data to be written to a storage device, a buffer cache and a direct memory access (DMA) buffer. The processing unit executes a plurality of write transactions for moving a portion of the data from the user buffer of the DRAM to the storage device via a first write path, and the remainder of the data from the user buffer of the DRAM to the storage device via a second write path. The first write path passes through the buffer cache of the DRAM, and the second write path does not pass through the buffer cache of the DRAM. | 05-12-2016 |
20160132443 | TRACKING VIRTUAL MACHINE MEMORY MODIFIED BY A SINGLE ROOT I/O VIRTUALIZATION (SR-IOV) DEVICE - Techniques for tracking, by a host system, virtual machine (VM) memory modified by a physical input/output (I/O) device that supports I/O virtualization are provided. In one embodiment, a hypervisor of the host system can receive a hardware interrupt from the physical I/O device, where the hardware interrupt indicates that a virtual function (VF) of the physical I/O device has completed a direct memory access (DMA) write to a guest memory space of a VM running on the host system. In response to the hardware interrupt, the hypervisor can invoke a function implemented by a physical function (PF) driver of the physical I/O device, where the function is configured to inspect the VF's state in order to identify memory portions modified by the DMA write. The hypervisor can then mark, in a hypervisor-level page table, one or more memory pages corresponding to the identified memory portions as dirty pages. | 05-12-2016 |
20160132444 | UNIVERSAL ETHERNET SOLUTION - A monolithic integrated circuit that supports multiple industrial Ethernet protocols, fieldbus protocols, and industrial application processing, providing a single hardware platform usable to build different automation devices/equipment implemented in an industrial network, such as controllers, field devices, network communication nodes, etc. The monolithic integrated circuit includes: one application processor core operable to execute an industrial application and Ethernet connectivity/management code, including standard Ethernet connectivity/management code and industrial Ethernet connectivity/management code; a real time processor configured to support a plurality of industrial Ethernet data link layers; an interface configured to be coupled to an external non volatile memory from which the at least one application processor is configured for execute in place processing; and an on-chip RAM having a capacity sufficient to eliminate the need for external RAM in execution by the at least one application processor core of an operating system, the industrial application, and the Ethernet connectivity/management code. | 05-12-2016 |
20160132445 | PERIPHERAL REGISTER PARAMETER REFRESHING - Systems, methods, circuits and computer-readable mediums for peripheral sequencing using an access sequence are disclosed. In some implementations, a control register and status register in a peripheral are initialized with control data for selecting peripheral registers of the peripheral to be refreshed during an access sequence. For each peripheral register to be refreshed during the access sequence: a data register of the peripheral register is accessed; the peripheral register is refreshed; and the status register is updated with a current status of the access sequence. The access sequence is determined to be completed based on contents of the status register. | 05-12-2016 |
20160162422 | DUAL ACCESS MEMORY MAPPED DATA STRUCTURE MEMORY - Systems and methods are provided for expanding the available memory of a storage controller. The systems and methods utilize a PCIe memory controller connected to the backend interface of the storage controller. Memory of the PCIe memory controller is memory mapped to controller memory of the storage controller. The PCIe connection allows the storage controller to access the memory of the PCIe memory controller with latencies similar to that of the controller memory. | 06-09-2016 |
20160162436 | PERIPHERAL COMPONENT INTERCONNECT EXPRESS DEVICES WITH EFFICIENT MEMORY MAPPING - Embodiments herein provide for efficient memory mapping in a PCIe device when a host changes memory allocations in the device. One PCIe device comprises a plurality of Base Address Registers (BARs) defined by the host. The device also includes a processor with an address space. The processor maps addresses of the address space to the BARs for routing PCIe packets from the host. The processor can determine that the host is reconfiguring the BARs, and, based on the determination, mark packets existing in the computer memory as old, change the BARs in the computer memory as directed by the host, mark packets received after the BAR change as new, process the old packets from the computer memory based on their addresses of the address space until a new packet is reached, and to remap the BARs to the addresses of the address space after the new packet is reached. | 06-09-2016 |
20160170905 | MIGRATING BUFFER FOR DIRECT MEMORY ACCESS IN A COMPUTER SYSTEM | 06-16-2016 |
20160172020 | OPTICAL INTERCONNECT IN HIGH-SPEED MEMORY SYSTEMS | 06-16-2016 |
20160179715 | SYNCHRONOUS BUS ARCHITECTURE FOR DIGITAL PRE-DISTORTION SYSTEM | 06-23-2016 |
20160179717 | SYSTEM ON A CHIP COMPRISING RECONFIGURABLE RESOURCES FOR MULTIPLE COMPUTE SUB-SYSTEMS | 06-23-2016 |
20160179718 | EARLY IDENTIFICATION IN TRANSACTIONAL BUFFERED MEMORY | 06-23-2016 |
20160179719 | COMPUTER SYSTEM, A SYSTEM MANAGEMENT MODULE AND METHOD OF BIDIRECTIONALLY INTERCHANGING DATA | 06-23-2016 |
20160179720 | DEVICE TABLE IN SYSTEM MEMORY | 06-23-2016 |
20160179733 | TWO-PART ELECTRICAL CONNECTOR | 06-23-2016 |
20160188469 | LOW OVERHEAD HIERARCHICAL CONNECTIVITY OF CACHE COHERENT AGENTS TO A COHERENT FABRIC - In an example, a system-on-a-chip comprises a plurality of multi-core processors, such as four dual-core processors for eight total cores. Each of the processors connects to shared resources such as memory and peripherals via a shared uncore fabric. Because each input bus for each core can include hundreds of data lines, the number of lines into the shared uncore fabric can become prohibitive. Thus, inputs from each core are multiplexed, such as in a two-to-one configuration. The multiplexing may be a non-blocking, queued (such as FIFO) multiplexing to ensure that all packets from all cores are delivered to the uncore fabric. In certain embodiment, some smaller input lines may be provided to the uncore fabric non-multiplexed, and returns (outputs) from the uncore fabric to the cores may also be non-multiplexed. | 06-30-2016 |
20160188516 | PASS-THROUGH CONVERGED NETWORK ADAPTOR (CNA) USING EXISTING ETHERNET SWITCHING DEVICE - According to one embodiment, a method includes performing functionality of a management plane and a control plane for a switch system using a processor of an external host coupled to the switch system via one or more peripheral component interconnect express (PCIe) ports. The method also includes providing a direct memory access (DMA) facility between the external host and switching logic of the switch system. The switch system includes a PCIe interface block coupled to PCIe ports configured to couple to external PCIe devices. Also, the PCIe interface block includes logic configured to provide DMA for each PCIe lane thereof. The switch system also includes multiple switched Ethernet ports configured to couple to one or more external Ethernet devices and switching logic configured to switch between the multiple switched Ethernet ports and the PCIe ports using DMA and a local processor coupled to the PCIe interface block. | 06-30-2016 |
20160196223 | FLASH-DRAM HYBRID MEMORY MODULE | 07-07-2016 |
20160196224 | HYBRID MEMORY BLADE | 07-07-2016 |
20160253093 | A new USB protocol based computer acceleration device using multi I/O channel SLC NAND and DRAM cache | 09-01-2016 |
20160253115 | TARGET PORT PROCESSING OF A DATA TRANSFER | 09-01-2016 |
20160378695 | Systems And Methods For Asymmetric Memory Access To Memory Banks Within Integrated Circuit Systems - Methods and systems are disclosed for asymmetric memory access to memory banks within integrated circuit (IC) systems. Disclosed embodiments include a memory and a memory controller within an integrated circuit. The memory includes a number of different memory banks, and the memory controller includes a number of different access ports coupled to the memory banks. The memory controller is also configured to provide asymmetric memory access for access requests to memory banks based upon access ports used for memory access requests. Additional disclosed embodiments further use asymmetric access times or asymmetric access bandwidths to provide this asymmetric access to memory banks within system memories for integrated circuit (IC) systems. By providing asymmetric access times or bandwidths for multiple access ports within a memory controller to multiple different memory banks within a system memory, overall access latency or system cost is reduced for the IC systems. | 12-29-2016 |
20160378700 | NON-INTERFERING TRANSACTIONS - Embodiments relate to non-interfering transactions. An aspect includes receiving, by a first transaction, a conflicting remote access request from a requester, the remote access request being directed to a memory area that is owned as part of at least one of a transactional read set and transactional write set by the first transaction. Another aspect includes determining whether the requester is a second transaction that is indicated as a non-interfering transaction with respect to the first transaction. Another aspect includes, based on determining that the requester is indicated as a non-interfering transaction with the first transaction, handling the remote access request. Yet another aspect includes continuing execution of the first transaction and the second transaction after handling the remote access request. | 12-29-2016 |
20160378701 | COHERENT FABRIC INTERCONNECT FOR USE IN MULTIPLE TOPOLOGIES - An apparatus having a fabric interconnect that supports multiple topologies and method for using the same are disclosed. In one embodiment, the apparatus comprises mode memory to store information indicative of one of the plurality of modes; and a first fabric operable in a plurality of modes, where the fabric comprises logic coupled to the mode memory to control processing of read and write requests to memory received by the first fabric according to the mode identified by the information indicative. | 12-29-2016 |
20160378709 | Enforcing transaction order in peer-to-peer interactions - A method for computing includes submitting a first command from a central processing unit (CPU) to a first peripheral device in a computer to write data in a first bus transaction over a peripheral component bus in the computer to a second peripheral device in the computer. A second command is submitted from the CPU to one of the first and second peripheral devices to execute a second bus transaction, subsequent to the first bus transaction, that will flush the data from the peripheral component bus to the second peripheral device. The first and second bus transactions are executed in response to the first and second commands. Following completion of the second bus transaction, the second peripheral device processes the written data in. | 12-29-2016 |
20160378712 | LOCK-FREE PROCESSING OF STATELESS PROTOCOLS OVER RDMA - Methods, systems, and computer storage mediums including a computer program product for managing data in a computing network are provided. One method includes registering a plurality of buffers with a work queue in a server and assigning ownership to each of the plurality of buffers to a different working thread in a plurality of working threads. The method further includes continuously polling, by a polling thread, the work queue to determine when work requests are received by the work queue, upon receipt of each work request, determining which buffer among the plurality of buffers each work request is associated, and performing each work request on each respective associated buffer by a working thread among the plurality of working threads that owns each respective associated buffer. One system includes a processor for performing the above method and one computer storage medium includes computer code for performing the above method. | 12-29-2016 |
20170235510 | SR-IOV-SUPPORTED STORAGE RESOURCE ACCESS METHOD AND STORAGE CONTROLLER AND STORAGE DEVICE | 08-17-2017 |
20170235520 | REPLICATION OF MEMORY IMAGE FOR EFFICIENT SIMULTANEOUS USES | 08-17-2017 |
20170235690 | PRODUCER/CONSUMER REMOTE SYNCHRONIZATION | 08-17-2017 |
20170235691 | INPUT/OUTPUT (I/O) BINDING WITH AUTOMATIC INTERNATIONAL ELECTROMECHANICAL COMMISSION (IEC) ADDRESS GENERATION IN REMOTE TERMINAL UNIT (RTU) CONFIGURATION | 08-17-2017 |
20170235692 | DATA COMMUNICATION INTERFACE FOR PROCESSING DATA IN LOW POWER SYSTEMS | 08-17-2017 |
20180024952 | COMPUTER, DEVICE CONTROL SYSTEM, AND DEVICE CONTROL METHOD | 01-25-2018 |
20190146853 | ENABLING LIVE MIGRATION OF VIRTUAL MACHINES WITH PASSTHROUGH PCI DEVICES | 05-16-2019 |
20190146937 | METHODS AND SYSTEMS FOR DEVICES WITH SELF-SELECTING BUS DECODER | 05-16-2019 |
20190146942 | Peer-To-Peer Communication For Graphics Processing Units | 05-16-2019 |
20220138120 | DATA BUS DUTY CYCLE DISTORTION COMPENSATION - An electrical circuit device includes a signal bus comprising a plurality of parallel signal paths and a calibration circuit, operatively coupled with the signal bus. The calibration circuit can perform operations including determining a representative duty cycle for a plurality of signals transferred via the plurality of parallel signal paths, the plurality of signals comprising a plurality of duty cycles and comparing the representative duty cycle for the plurality of signals transferred via the plurality of parallel signal paths to a reference value to determine a comparison result. The calibration circuit can perform further operations including adjusting, based on the comparison result, a trim value associated with the plurality of duty cycles of the plurality of signals to compensate for distortion in the plurality of duty cycles and calibrating the plurality of duty cycles of the plurality of signals using the adjusted trim value. | 05-05-2022 |