Entries |
Document | Title | Date |
20080201515 | Method and Systems for Interfacing With PCI-Express in an Advanced Mezannine Card (AMC) Form Factor - A cage that is received with a Personal Computer (PC) enclosure in the same manner a peripheral can be received within the PC. The cage is provided with fans, circuitry, connectors and structural features to create a ATCA or MicroTCA type environment required for the operation of an AMC card. The cage features a lateral connector for connecting to the motherboard and transferring PCI-Express protocolized signals between the cage and the CPU. The cage also features means to receive and support an AMC card within the ATCA and MicroTCA environment created for it by the cage. In this configuration, the CPU can communicate with the AMC card using the PCI-Express interconnect protocol as if the AMC card is another peripheral I/O device. In this manner, an advanced form factor AMC card may be tested and used within a PC environment suitable only for conventional form factor expansion cards and peripheral I/O devices. | 08-21-2008 |
20080228986 | ARCHITECTURE FOR CONTROLLING PERIPHERAL DEVICES - A peripheral component interface device capable of being removably coupled to an input-output interface in a computer, and at least one peripheral device is described. The peripheral component interface device includes a first communication bus configured to be removably coupled to the input-output interface associated with the computer, a second communication bus configured to be removably coupled to the input-output interface associated with the computer, and a signal regulation circuit electrically coupled to the first communication bus and the second communication bus. In one embodiment, the signal regulation circuit is responsive to commands from the second communication bus to control a signal from the first communication bus passing to the at least one peripheral device, when the at least one peripheral device is coupled to the peripheral component interface device. | 09-18-2008 |
20080235429 | Operating PCI Express Resources in a Logically Partitioned Computing System - Methods, systems, and products are disclosed for operating Peripheral Component Interconnect (‘PCI’) Express resources in a logically partitioned computing system that include: allocating, by a hypervisor installed on the computing system, a PCI Express adapter installed in the computing system to a logical partition of the computing system, including establishing a data communication path between a processor of the computing system and the PCI Express adapter, the data communication path including a link between a PCI Express root complex and the PCI Express adapter; and administering, by the hypervisor for the logical partition, the PCI Express root complex and the link between the PCI Express root complex and the PCI Express adapter. | 09-25-2008 |
20080244147 | Device Recognition Circuit and the Method of Recognition - A device recognition circuit for initiating a computer system includes an adapter module and a control module. The adapter module is capable of connecting a peripheral interface card the adapter module having I/O ports, the I/O ports carry present signals generated by the adapter module. The control module having general purpose input/output (GPIO) pins for receiving the present signals, wherein the control module determines an expansion type of the adapter module according to the present signals. The embodiment of present invention also provides a method of recognizing a device for initiating a computer system. | 10-02-2008 |
20080244148 | VoIP Enabled Femtocell with a USB Transceiver Station - Telephone calls between a mobile station (MS) and the mobile network or PSTN are routed through the Internet via VoIP using a femtocell, as opposed to the traditional macrocellular network. The femtocell can comprise a USB Transceiver Station that is connected to a personal computer through a universal serial bus port, which provides both power and a multi-megabit per second connection between the personal computer and the USB transceiver station. The USB transceiver station can comprise a microcontroller to manage signaling between the RF front end/baseband processor and the personal computer, as well as a precise timing mechanism to assist the synchronization of femtocell timing with the surrounding macrocellular network, if it is present. The USB transceiver station can have a compact form factor that that facilitates a high degree of portability by the subscriber, such as being readily attachable to their keychain. | 10-02-2008 |
20080244149 | Multiple module computer system and method - A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system. | 10-02-2008 |
20080250186 | BUS CONNECTING DEVICE FOR CONNECTING HOST WITH EXTERNAL DEVICE - A detecting unit detects a connection of an external device to a connection port and stores the connection in a bridge state storage unit. This setting is autonomously completed by a device before an initial configuration is started by a host. A data transfer unit receives initial configuration data of a link-connection bridge from the host. Data is transferred to the linked-uplink-connection bridge with reference to the bridge state storage unit, data to a bridge which is not linked up is wasted, or an Unsupported Request is returned to the host to represent the absence of the link-connection bridge. | 10-09-2008 |
20080250187 | Data processing system and data processor - One data processor is provided with an interface for realizing connection with the other data processor. This interface is provided with a function for connecting the other data processor as a bus master to an internal bus of the one data processor, and the relevant other data processor is capable of directly operating peripheral functions that are memory mapped to the internal bus from an external side via the interface. Accordingly, the data processor can utilize the peripheral functions of the other data processor without interruption of the program being executed. In short, one data processor can use in common the peripheral resources of the other data processor. | 10-09-2008 |
20080276031 | Method and apparatus for a federation control plane in an orthogonal system - A method of and architecture for controlling board elements in an orthogonal system architecture is provided. The method and architecture preferably utilize an internal bus architecture between control boards, such that a first control board can access board elements in its stack via I/O on a second control board and the second control board can access board elements in its stack via I/O on the first control board. Most preferably the internal bus architecture is a HyperTransport bus architecture. | 11-06-2008 |
20080282014 | Card reading apparatus for multi-directional data transmission - A card reading apparatus for multi-directional data transmission is provided, including a USB interface, a memory card interface, an ATA/ATAPI interface, and a USB OTG controller. The USB OTG controller is connected to the USB interface, the memory card interface, and the ATA/ATAPI interface so that the USB media device connected to the USB interface, the flash memory cards connected to the memory card interface, and the data storage devices, such as hard disk and CD-R/W, connected to the ATA/ATAPI interface can all perform multi-directional data transfer among themselves. | 11-13-2008 |
20080282015 | DESIGN STRUCTURE FOR HARDWARE ASSISTED BUS STATE TRANSITION CIRCUIT USING CONTENT ADDRESSABLE MEMORIES - A design structure including universal peripheral processor architecture on an integrated circuit (IC) includes a first data bus and a second data bus communicating with first and second ternary content addressable memory (TCAM) devices configured as state machines. First and second processors are coupled to the first bus interface logic and the second bus interface logic. First and second data storage devices communicate with the first and second processors and are coupled to the first and second data buses and communicate with each other. The TCAM devices are configured as state machines and are coupled to and adapted to interface with the processors, the data storage devices, and the bus interface logic using predefined protocols. | 11-13-2008 |
20080288708 | MULTIPLE VIRTUAL USB DEVICES WITH VIRTUAL HUB IMPLEMENTED USING ONE USB DEVICE CONTROLLER - A USB device using one USB device controller to simulate multiple virtual USB devices with a virtual USB hub is described. The USB device controller is assigned a USB address and communicates with the USB host under the control of an MCU and its firmware. The USB device also includes a CPLD (or FPGA or ASIC) and an analog switch for filtering the USB packets from the host and replacing the address in the packet by a fixed address before sending the packet to the USB device controller. The address in the original packet is stored in the CPLD and accessible by the MCU. The MCU controls the USB device controller to simulate one or more USB hubs and multiple USB devices. | 11-20-2008 |
20080288709 | Wide area network connection platform - Embodiments of the invention relate to a wide area network platform for use in conjunction with multiple distinct bus applications. The wide area network platform may include a hardware module for connection with system hardware, the hardware module including a universal serial bus interface and a wide area network interface. The hardware module is operable with multiple distinct bus applications. The platform may further include a universal device driver for interfacing with an operating system and with the system hardware and operating transparently through the multiple distinct bus applications. | 11-20-2008 |
20080301350 | Method for Reassigning Root Complex Resources in a Multi-Root PCI-Express System - A system for reassigning root complex resources in a multi-root PCI express system identifies resources from a lower performing root complex port and reassigns those resources to the higher performing root complex. The system does not change the number of PCI Express lanes, the resources each root complex uses may be reassigned to allow those resources to be translated to available credits for an endpoint. For example, in one embodiment, two root complexes are configured as x8 root complexes with the root complex resources distributed across the two root complexes based upon the usage of the root complex resources. | 12-04-2008 |
20080301351 | COMMUNICATION METHOD OF HOST APPARATUS CAPABLE OF CONNECTING WITH DEVICE BY USING WIRELESS UNIVERSAL SERIAL BUS AND WIRELESS CONNECTION SYSTEM INCLUDING HOST APPARATUS AND DEVICE - A communication method of a host apparatus capable of connecting with a device by using a Wireless Universal Serial Bus (WUSB) includes operations of receiving a connection request signal from the device to be connected to the host apparatus, according to a determination of whether a request to perform an operation in the device occurs in the host apparatus, selectively responding to the connection request signal to connect the device thereto, and performing data communication with the device to perform the operation. According to the communication method, the host apparatus is connected to the device when the host apparatus uses the device, to improve effective and convenient use of the device. | 12-04-2008 |
20080307148 | System and Method for Improved Bus Communication - A system for bus communication includes a first port coupled to a bus, comprising a first engine configured to respond to bus signals on the bus, according to a predetermined protocol. A second port couples to the bus, comprising a second engine configured to respond to bus signals according to the predetermined protocol. A control module couples to the second port and is configured to receive a port state signal, and to disable the second port based on the received port state signal. | 12-11-2008 |
20080313381 | Reconfigurable I/O card pins - In accordance with the present technique, a system and method for configuring pins of an input/output (I/O) card in a host system are provided. The method includes reading configuration information from a card field replaceable unit memory and reading system configuration information from a system field replaceable unit memory. Additionally, the method includes configuring pins of a system logic of the host system to be compatible with the I/O device of the I/O card, and configuring pins of an I/O device on the I/O card to in turn configure the pins of the I/O card with a configuration setting compatible with the host system. | 12-18-2008 |
20080320202 | Physical Device (PHY) Support Of The USB2.0 Link Power Management Addendum Using A ULPI PHY Interface Standard - A protocol may enable support of the USB 2.0 LPM (Link Power Management) Addendum by a ULPI PHY (Universal Serial Bus Transceiver Macrocell Low-Pin Interface Physical Layer Device), facilitating transmitting the reserved PID (Physical Interface Device) token, used in the LPM Extended Transaction, through a ULPI bus. Bits [ | 12-25-2008 |
20090006707 | METHOD OF USING THE DUAL BUS INTERFACE IN AN EXPRESSCARD SLOT - A peripheral device is disclosed having two associated memory modules, and which is configured to fit within the ExpressCard slot. One memory module communicates with a host over the PCIe bus interface of the ExpressCard slot, while the other memory module communicates with the host over the USB interface of the ExpressCard slot. | 01-01-2009 |
20090024782 | DISTRIBUTED INTERCONNECT BUS APPARATUS - A distributed interconnect bus apparatus for connecting peripheral devices. The apparatus can be utilized to wirelessly connect peripheral devices or to allow the connectivity of such devices over a network. The apparatus includes a first bridge coupled to a root component of an interconnect bus; and a second bridge coupled to an endpoint component of an interconnect bus. The apparatus may further include an acknowledgment (ACK) termination for generating at least an ACK signal; and a flow control mechanism including at least one receiver buffer for temporarily saving data packets of multiple different transactions. | 01-22-2009 |
20090063746 | Integral SATA Interface - An interface couples a host device and a peripheral device. The interface includes at least one tab integrally formed and extending from a main body of a printed circuit board. The at least one tab has a plurality of contact pads. The interface also includes at least one keying feature integrally formed with an enclosure of the peripheral device. The at least one keying feature configured to guide a receptacle connector of the host device into connection with the plurality of contact pads on the at least one tab. | 03-05-2009 |
20090063747 | APPLICATION NETWORK APPLIANCES WITH INTER-MODULE COMMUNICATIONS USING A UNIVERSAL SERIAL BUS - An application network appliance having inter-module communication using a universal serial bus (USB) is described herein. According to one embodiment, a network element includes a lossless data transport fabric (LDTF), multiple service modules coupled to each other over the LDTF, and a service control module (SCM) coupled to each of the service modules over the LDTF for routing network data between the SCM and the service modules. The SCM is also coupled to each of the service modules via a universal serial bus (USB) for managing the service modules, where the network element operates as a security gateway to a datacenter having multiple servers. Other methods and apparatuses are also described. | 03-05-2009 |
20090083470 | SYSTEM ON CHIP DEVICE AND METHOD FOR MULTIPLE DEVICE ACCESS THROUGH A SHARED INTERFACE - A system on chip device for communicating with a plurality of external devices is provided. The system on chip device comprises a plurality of host controllers, a shared interface and an arbiter. The plurality of host controllers with a plurality of protocols configures and drives the plurality of external devices. The shared interface coupled between the plurality of host controllers and the plurality of external devices comprise a plurality of data lines and plural sets of control lines, wherein the plurality of data lines are shared by the plurality of host controllers and the plural set of control lines are separately coupled to the plurality of host controllers. The arbiter is coupled to the plurality of host controllers for receiving a plurality of requests and granting one of the plurality of host controllers access to the corresponding external device through the shared interface in accordance with a priority scheme. | 03-26-2009 |
20090094400 | Method and apparatus for configuring electronic devices to perform selectable predefined functions using device drivers - A multifunctional mobile telephone handset is connected to a PC using a Universal Serial Bus. During bus enumeration, a device class descriptor is returned by the handset to the PC. The PC's operating system receives information relating to one of the functions of the handset and assigns an appropriate device driver. | 04-09-2009 |
20090100209 | UNIVERSAL SERIAL BUS HUB WITH SHARED HIGH SPEED HANDLER - A device may include an upstream port and several downstream ports configured to transfer data at a different data transfer rate than the upstream port. The device may also include several downstream data handlers, each coupled to a respective one of the downstream ports, and an upstream data handler coupled to the upstream port. The data handlers are configured to implement a USB protocol. The upstream data handler is configured to store specific transactions (comprising data) received through the upstream port. Each respective downstream data handler is configured to access respective transactions of the stored specific transactions intended for the downstream port associated with the respective downstream data handler, and transmit to its associated respective downstream port the data comprised in its respective transactions. Accordingly, the upstream data handler is shared between the various downstream data handlers. | 04-16-2009 |
20090125665 | USB DEVICE AND USB SYSTEM INCLUDING THE SAME - A Universal Serial Bus (USB) device includes an internal circuit and an interface circuit. The interface circuit is configured to interface the internal circuit and an external device for wireless USB (WUSB) communication and USB communication. The interface circuit includes a WUSB module enabling the WUSB communication, an on-the-go (OTG) module enabling the USB communication, and an interface module configured to selectively control the WUSB module and the OTG module to interface the internal circuit and the external device for the WUSB communication and the USB communication. | 05-14-2009 |
20090157939 | Multiple module computer system and method - A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system. | 06-18-2009 |
20090164693 | Accelerating input/output (IO) throughput on solid-state memory-based mass storage device - In one embodiment, a portable mass storage device may include a bus hub having a first port to couple to a bus and other ports to connect to multiple multi-channel memory controllers, where each memory controller is coupled to multiple non-volatile storage arrays, and the memory controllers can independently service the arrays to enable overlapping data transfer operations. Other embodiments are described and claimed. | 06-25-2009 |
20090172240 | METHODS AND APPARATUS FOR MEDIA REDIRECTION - A method includes generating a storage device request directed to a register of a computing device that is used to access a storage device of the compute device. The method further includes determining with a media redirection device to redirect the storage device request to a storage device connected to a network. The method further includes transmitting over a host bus of the computing device a packetized message representing the storage device request from the media redirection device to a network controller. An associated apparatus is also disclosed. | 07-02-2009 |
20090172241 | METHOD AND APPARATUS FOR ENHANCING THE GRAPHICS CAPABILITY OF A MOBILE COMPUTING DEVICE - One embodiment of the present invention sets forth a method, which includes the steps of detecting the presence of an external graphics subsystem after the external graphics subsystem is attached to the mobile computing device, transmitting a power enable signal to the external graphics subsystem, and activating PCIe signaling channels after having received a ready signal from the external graphics subsystem to enable data communications between the mobile computing device and the external graphics subsystem. | 07-02-2009 |
20090187693 | Device and method of inputting data, and image output system using the same - A first device is provided with a communicator having a first interface function and a second interface function defined in an asymmetric interface standard. A second device is connected to the first device. The first device detects whether the second device has at least one of the first interface function and the second interface function. Data is transmitted from the first device to the second device, through use of the first interface function, in a case where it is detected that the second device has the second interface function. A signal for processing the data is transmitted from the first device to the second device, through use of the second interface function, in a case where it is detected that the second device has the first interface function. | 07-23-2009 |
20090198859 | CONNECTIONS AND DYNAMIC CONFIGURATION OF INTERFACES FOR MOBILE PHONES AND MULTIFUNCTIONAL DEVICES - An apparatus and method in a mobile device having a digital application-specific integrated circuit (DASIC) and a multifunctional integrated circuit (chip) providing additional functions to the mobile device. An internal Universal Serial Bus (USB) link connects the DASIC and the multifunctional chip. In one embodiment, the multifunctional chip is an ultra wideband (UWB) Radio Module. The internal USB link may utilize a USB interface, a USB 2.0 Universal Transceiver Macrocell Interface (UMTI+) and Low Pin Interface (ULPI), or a High Speed InterChip (HSIC) interface. The UWB Radio Module communicates over the air with an external remote wireless device such as a wireless USB Host utilizing a UWB radio link. The internal USB link provides connection and maps logical data streams in the DASIC with logical data streams in the UWB Radio Module or multifunctional integrated circuit. | 08-06-2009 |
20090198860 | INTEGRATED DATA ACCESSING SYSTEM HAVING CONTROL APPARATUS FOR MULTI-DIRECTIONAL DATA TRANSMISSION - An integrated data accessing system having control apparatus for multi-directional data transmission is described. The integrated data accessing system includes a control apparatus, a plurality of communication interface engines. The control apparatus includes a plurality of bi-directional transmission modules, a control unit, a multi-directional transferring engine, and a memory unit. The control unit detects a source storage and a target storage. The multi-directional transferring engine selectively transfers the data content among storage units. The multi-directional transferring engine includes a first switch module, a second switch module, and a data buffer. The first switch module switches to the first bi-directional transmission module to select the source storage. The second switch module switches to the second bi-directional transmission module to select the target storage. The data buffer stores the data content transmitted from the source storage and the target storage. The multi-directional transferring engine transfers the data content in the source storage via the first bi-directional transmission module to the target storage via the second bi-directional transmission module when the control unit triggers the first switch module and the switch second module. | 08-06-2009 |
20090210606 | PCI-EXPRESS SYSTEM - A method and system to facilitate Peripheral Component Interconnect Express (PCIe). The PCIe may be facilitated in such as way as to limit pins consumed by a Root Complex, switch, or other chipset included on the same die a central processing unit (CPU). A slot interface card (SIC) or other devices having less expensive pins may be used to connect to and communicate with the slot. | 08-20-2009 |
20090240864 | INTERFACE ADAPTER FOR A PORTABLE MEDIA PLAYER DEVICE - A “smart cable” that connects one or more peripheral devices to a digital media player having multiple, different types of input and/or output connections. | 09-24-2009 |
20090248943 | SERVER - A server includes a mother board, a back board and a bridge board. A plurality of first connection lines and a first slot are disposed on the mother board. The first connection lines are employed for delivering a plurality of power signals and a plurality of control signals. A second slot is disposed on the back board. The bridge board has a first golden finger and a second golden finger, and a plurality of second connection lines are disposed on the bridge board and is electrically connected to the first golden finger and the second golden finger. The first golden finger and the second golden finger are respectively inserted into the first slot and the second slot. In this way, the control signals and the power signals from the mother board are delivered to the back board through the second connection lines on the bridge board. | 10-01-2009 |
20090271556 | CONNECTING MULTIPLE PERIPHERAL INTERFACES INTO ONE ATTACHMENT POINT - An interconnect apparatus is provided for connecting at least one peripheral device to a multi-channel interface. The apparatus includes an incoming connector having a first incoming channel connector and at least one second incoming channel connector, wherein the incoming connector is operable to detachably connect to an interface cable, a first outgoing connector having a first outgoing channel connector, at least one second outgoing connector having at least one second outgoing channel connector, and routing logic operable to propagate a first signal between the first incoming channel connector and the first outgoing channel connector, and to propagate at least one second signal between the at least one second incoming channel connector and the at least one second outgoing channel connector; wherein a position of the first outgoing channel connector in the first outgoing connector corresponds to a position of the at least one second outgoing channel connector in the at least one second outgoing connector. | 10-29-2009 |
20090300258 | SSD WITH A CHANNEL MULTIPLIER - An integrated circuit includes a first serial advanced technology attachment (SATA) channel, a plurality of second SATA channels, and a channel multiplier. The first SATA channel is configured to be coupled to a corresponding serial data bus of a host device. Each of the plurality of SATA channels is configured to be coupled to a respective separate memory device channel. The channel multiplier is configured to couple the first SATA channel to each of the plurality of second SATA channels. | 12-03-2009 |
20090300259 | SSD WITH SATA AND USB INTERFACES - In one embodiment, a data storage system, includes a controller and a plurality of solid state memory devices each including at least one memory unit. The controller includes a data interface of a first type, a data interface of a second type, and a first serial data bus. Each of the data interfaces of the first and second types is configured to be coupled to a corresponding data interface of a host device. The first serial data bus is coupled to each of the data interfaces of the first and second types and to the plurality of solid state memory devices. The controller is configured to manage data flow between the plurality of solid state memory devices and the host device through the data interfaces of the first and second types. | 12-03-2009 |
20090313412 | Hub Capable of Enhancing Power Supplying Capability - A hub capable of enhancing power supplying capability includes a plurality of ports, a first interface coupled to a first port of a computer system, a second interface coupled to a second port of the computer system, the second port with a format different from a format of the first port, a diversity unit coupled to the plurality of ports, a data processing unit coupled between the first interface and the diversity unit for processing data exchange between the plurality of ports and the first port via the first interface and the diversity, and a power supply unit coupled between the first interface, the second interface and the diversity interface for receiving power output by the first port and the second port via the first interface and the second interface, so as to provide power in conformation to a predefined requirement to the plurality of ports via the diversity unit. | 12-17-2009 |
20100005215 | Control Unit Including a Computing Device and a Peripheral Module which are Interconnected via a Serial Multiwire Bus - A control unit includes at least one computing device and at least one separate peripheral module which is connected to the computing device via a serial multiwire bus, the peripheral module including at least one output stage for transferring serial data to means outside of the control unit. In order to keep the number of pins required on a peripheral module to a minimum, thereby reducing costs for the entire control unit, the peripheral module has an asynchronous single-wire interface between one interface for the serial multiwire bus and the output stage. The asynchronous single-wire interface is preferably a UART (universal asynchronous receiver/transmitter) interface. The serial multiwire bus is preferably a microsecond bus. | 01-07-2010 |
20100036993 | Combination Power Memory Device - A portable power and/or memory device is disclosed, which device includes integrated management circuitry enabling on-board management of energy storage, power management, and memory management. In a preferred embodiment, the device of the present invention can store and make available both memory and power, and provides an on-board means for displaying the various memory and/or power parameters associated with the device, using a USB interface to receive power for storage and to communicate between onboard memory and a device to which the portable power and/or memory device is connected. | 02-11-2010 |
20100057973 | SYSTEM AND METHOD FOR INTERFACING AN ELECTRONIC DEVICE WITH A HOST SYSTEM - The disclosure describes a system and method for controlling interfacing parameters for a device when connected to a host. In the system and method, the communications interface is configurable to be in operable connection to a host using a microprocessor in the device having a first bus controller and a second bus controller, the second bus controller external to the microprocessor. The method comprises: establishing an initial connection by the device; conducting negotiations by the device to set a first data transmission rate for the device for the initial connection utilizing a communication bus controller contained in the microprocessor; and after detecting completion of enumeration of the device, re-establishing the connection by the device using the second bus controller in the device that processes the communications at a second transmission rate that is higher than the first data transmission rate. | 03-04-2010 |
20100070673 | HIGH PCI EXPRESS SIGNAL TRANSMISSION APPARATUS AND CONTROL METHOD THEREOF - Provided are a high PCI express signal transmission apparatus and a control method thereof. A high PCIe signal transmission apparatus for transceiving data of a computer storage device with an external device, the high PCIe signal transmission apparatus includes a host adapter receiving the data of the storage device through the PCIe signal, and converting the received PCIe signal into an optical signal to transmit the converted optical signal, and a signal conversion processor receiving the optical signal from the host adapter, converting the received optical signal into an electrical signal, and transmitting the converted electrical signal to an corresponding external device connection unit. | 03-18-2010 |
20100082873 | Ship Rudder Control (Autopilot) with a CAN Bus - Ship rudder control, so-called autopilot, includes a multiplicity of components connected with a bus interface to a CAN bus and via this also to each other. A further bus interface on each component of the control system is coupled to a separate, second bus, with the components being provided with unambiguous addresses and further information being assigned that mark the components as monitorable or non-monitorable. A device for emitting telegrams of component addresses and monitorability. A first comparator on all monitorable components start or switch off their own property as a monitoring component using the addresses of other components in received telegrams by comparison, and a second comparator on all monitorable components that use the number of received telegrams by comparison with the number of telegrams received on the other channel causing a change of the channel to that with the higher number of received telegrams under certain circumstances. | 04-01-2010 |
20100088453 | Multi-Processor Architecture and Method - Embodiments of a multi-processor architecture and method are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols. | 04-08-2010 |
20100088454 | Bridging device with power-saving function - A bridging device with power-saving function includes first and second interfaces, first and second physical layer processing devices, and a controller. The first interface is utilized for coupling a first external device complying with the first interface. The first external device receives a device request signal, and accordingly sends back a device response signal through the first physical layer processing device. The second interface is utilized for coupling a second external device complying with the second interface. The controller is coupled between the first and the second physical layer processing device for transmitting the device request signal with the predetermined frequency to the first physical layer processing device in order to receive the device response signal. When the controller does not receive the device response signal, the controller turns the second physical layer processing device off. | 04-08-2010 |
20100106881 | HOT PLUG AD HOC COMPUTER RESOURCE ALLOCATION - An adapter card adapting the ad hoc resource add/removal inherent to a host PCI or PCI Express-based system to a wireless link and wireless endpoint. The adaptation allows mobile PCI Express resources to ingress and be allocated system resources within a host's PCI system and then egress and have the allocated resources freed up for re-use/reassignment, emulating the hot plug insertion and removal of an adapter card. | 04-29-2010 |
20100138584 | Method and System for Addressing a Plurality of Ethernet Controllers Integrated into a Single Chip Which Utilizes a Single Bus Interface - A system for arbitrating access to a shared resource is disclosed and may include a bus interface, a first network controller for handling a first host function associated with a first host process, a second network controller for handling a second host function associated with a second host process, and an arbitrator for granting access to the shared resource for one of the first host process and the second host process. The arbitrator may facilitate a transfer of information to and from the bus interface and the shared resource. The first network controller and the second network controller may be integrated within a single chip. The shared resource may be a nonvolatile memory, flash memory interface, an EEPROM interface, and/or a Serial Programming Interface (SPI). | 06-03-2010 |
20100146185 | COMBINED FIBRE CHANNEL AND SAS HOST BUS ADAPTER - Apparatus, systems, and methods for coupling Fibre Channel (FC) storage devices and serial attached SCSI (SAS) storage device to a computer system through a single host bus adapter (HBA). The HBA includes a SAS storage controller four coupling to one or more SAS storage devices and an FC interface for coupling to one or more FC storage devices. The HBA also includes translation logic to translate information exchanged between the SAS storage controller and the FC storage device(s). Translation may include translation of addressing information between FC protocols and formats used by the SAS storage controller, may include use of a buffer to enable exchanges at different data rates, and may include use of a buffer to aggregate an inbound FC multiframe sequence into a single data buffer for use by the SAS storage controller. | 06-10-2010 |
20100153612 | TRANSPORT AGNOSTIC SCSI I/O REFERRALS - The present invention is a method for providing multi-pathing via Small Computer System Interface Input/Output (SCSI I/O) referral between an initiator and a storage cluster which are communicatively coupled via a network, the storage cluster including at least a first target device and a second target device. The method includes receiving an input/output (I/O) at the first target device from the initiator via the network. The I/O includes a data request. The method further includes transmitting a SCSI I/O referral list to the initiator when data included in the data request is not stored on the first target device, but is stored on the second target device. The referral list includes first and second port identifiers for identifying first and second ports of the second target device respectively. The first and second port identifiers are SCSI relative port identifiers. The first and second ports of the target device are identified as access ports for accessing the data requested in the data request. | 06-17-2010 |
20100153613 | SCALING OF SMALL COMPUTER SYSTEM INTERFACE INPUT OUTPUT (SCSI I/O) REFERRALS - A command is issued to a first data storage system for addressing a set of data and at least one of a first referral response including a referral to at least a second data storage system or at least a first subset of the set of data and the first referral response including the referral to the at least the second data storage system. The at least one of a first referral response including a referral to at least a second data storage system or at least a first subset of the set of data and the first referral response including the referral to the at least the second data storage system is accessed. A command is issued to the second data storage system for addressing the set of data and a second referral response including a referral to at least one of the first data storage system and a third data storage system, the second data storage system including at least a second subset of the set of data. The second subset of the set of data and the second referral response including the referral to the at least one of the first data storage system or the third data storage system is accessed. | 06-17-2010 |
20100161869 | INFORMATION PROCESSOR - According to one embodiment, an information processor has: an input/output module configured to input/output a data signal through a data signal line; a first voltage supply module configured to supply a first differential signal pair; a second voltage supply module configured to supply a second differential signal pair; a first switching module configured to select and output, in response to a first control signal, one of the first differential signal pair supplied from the first voltage supply module and the second differential signal pair supplied from the second voltage supply module; and a second switching module configured to receive one of the first differential signal pair and the second differential signal pair output from the first switching module, and output one of the first differential signal pair and the second differential signal pair to the electronic device through the data signal line, in response to a second control signal. | 06-24-2010 |
20100174844 | MULTIPLE MODULE COMPUTER SYSTEM AND METHOD INCLUDING DIFFERENTIAL SIGNAL CHANNEL COMPRISING UNDIRECTIONAL SERIAL BIT CHANNELS - A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system. | 07-08-2010 |
20100191891 | Combination Personal Data Assistant and Personal Computing System Dynamic Memory Reclamation - In order to continually receive messages in a dual personal computer system (PC) and personal digital assistant system (PDA) computer architecture, the PC system is deactivated to conserve battery power while the PDA continues to receive messages. As PDA memory is filled with messages, messages that are synchronized and archived with the PC system are deleted and space is freed for incoming messages. When new and non-synchronized messages completely fill the PDA memory array, the PC system is reactivated or the user is informed. | 07-29-2010 |
20100199016 | DEVICE FOR WIRLESS TRANSMISSION OF DIGITAL INFORMATION - Disclosed is to a USB device for receiving data from other data transmitting devices. The inventive USB device comprises a printed circuit board having a microprocessor and memory, a USB controller connected to the microprocessor, a USB connector connected to the printed circuit board, and wireless receiving means connected to the printer circuit board for receiving external data to be stored in the memory. The data stored in the memory include, but are not limited to, unique identifiers from external devices. The inventive USB device may further comprise means for transmitting data from the device to external devices. The inventive USB has a power source to provide power for it to work for an extended period of time. The above inventive USB device may further provide means for a user to initiate the device to transmit the ID to other receiving devices within the proximity. | 08-05-2010 |
20100217913 | Method and Apparatus for Handling Data and Aircraft Employing Same - These teachings present triple data transport redundancy in the form of three data bus interfaces that are each designed and manufactured independently from one another and compatible with a common data handling protocol. This protocol can be one that includes no error correction. These interfaces can each couple to a corresponding first, second, and third data bus that may comprise optical data busses. Information gauges can be realized through use a memory that stores a plurality of images comprising views of an information gauge (or gauges) of interest showing a variety of different readings. Upon receiving information regarding a monitored parameter of interest (via, for example, the aforementioned data busses and data bus interfaces), this information can be used to address the stored information gauge view that corresponds to the present parameter value. That particular view can be recalled and displayed to thereby provide the corresponding information to a viewer. | 08-26-2010 |
20100241781 | Bus Enumeration in a System with Multiple Buses - Enumerating an expanded bus system in a system. The expanded bus system may include a first bus, a bridge coupled to the first bus, and a second bus coupled to the bridge, where the second bus includes one or more downstream bus ports. One or more of the downstream bus ports may initially be masked. An initial bus enumeration may be performed during system boot, which may not include enumerating the masked bus ports. After the initial bus enumeration, the masked bus ports may be unmasked. An operating system may re-enumerate the bus system, which may include enumerating the no-longer-masked bus ports. | 09-23-2010 |
20100250821 | INTER-PROCESSOR COMMUNICATION LINK WITH MANAGEABILITY PORT - Manageability ports for inter-processor communication links, along with associated systems and methods, are generally provided. | 09-30-2010 |
20100262748 | USB REPEATER FOR ON BOARD AIRCRAFT INSTALLATIONS - A USB repeater assembly is provided for connecting a vehicle passenger entertainment system to a seat electronics box that may be at some distance from the entertainment system. The assembly comprises a host connector that connects with the seat electronics box and a device connector that connects with the passenger entertainment system. The passenger entertainment system comprises a USB personal control unit. The repeater assembly is housed within a shell, preferably a hardened one, enclosing a portion of the connectors as well as USB repeater circuitry and through-connects for connections associated with other components of the passenger entertainment system. | 10-14-2010 |
20100268861 | USB DRIVE - A universal serial bus (USB) drive includes a control button, a control signal generating circuit, a flash memory, a connection port, a processor, and an indication lamp. The USB drive generates a removal instruction from a connection device, according to a user operation thereon. The USB drive determines whether the flash memory is in a working state and controls the connection port to disconnect from the connection device, if the flash memory is not in the working state. The indication lamp on the USB drive provides a notification that the connection port is disconnected from the connection device. | 10-21-2010 |
20100287324 | CONFIGURABLE LOGIC INTEGRATED CIRCUIT HAVING A MULTIDIMENSIONAL STRUCTURE OF CONFIGURABLE ELEMENTS - Programming of modules which can be reprogrammed during operation is described. Partitioning of code sequences is also described. | 11-11-2010 |
20100306442 | DETECTING LOST AND OUT OF ORDER POSTED WRITE PACKETS IN A PERIPHERAL COMPONENT INTERCONNECT (PCI) EXPRESS NETWORK - An article of manufacture, an apparatus, and a method for processing packets in a peripheral component interconnect express (PCIe) network. An article of manufacture includes a computer program product that includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes receiving a PCIe posted write packet at a receiving device, the PCIe posted write packet including a received tag identifier and a requesting device identifier identifying a requesting device. An expected tag identifier is determined for the requesting device. The received tag identifier is compared to the expected tag identifier. An error flag is set if the received tag identifier does not match the expected tag identifier. | 12-02-2010 |
20100306443 | SIGNAL TRANSMISSION INTERFACE AND DIGITAL BROADCAST RECEIVING DEVICE - A signal transmission interface includes: a USB audio format encoding unit adapted to be coupled to a digital broadcast receiving end, for converting a digital audio signal that originates from the digital broadcast receiving end into a USB audio signal; a USB hub coupled to the USB audio format encoding unit and adapted to be coupled to a host end, for transmitting the USB audio signal to the host end and receiving a USB control signal that originates from the host end; and a USB/serial transmission bus bridge unit coupled to the USB hub and adapted to be coupled to the digital broadcast receiving end, for converting the USB control signal that is transmitted from the USB hub into a serial transmission bus control signal, and transmitting the serial transmission bus control signal to the digital broadcast receiving end. | 12-02-2010 |
20100318715 | METHOD FOR SENSING AND AUTO SWITCHING BETWEEN TWO USB INPUT PORTS TO A SINGLE PORT ON THE PDA - Routing circuitry for automatically routing either a first set of USB signals derived from an Ethernet local area network (LAN) at an Ethernet connector or a second set of USB signals derived from a USB host at a USB connector to an output connector which can interface with a data processing device includes USB supply voltage selection circuitry that passes a USB supply voltage from the first set of USB signals, or the second set of USB signals, or isolates the USB supply voltages from the first and second set of USB signals from the output connector in response to two or more first input signals, USB data selection circuitry that passes USB data signals from the first set of USB signals or the second set of USB signals to the output connector in response to one or more second input signals, and USB supply voltage detection circuitry that detects if the USB supply voltage from the second set of USB signals is present, and generates the two or more first input signals and the one or more second input signals in response to the detection, wherein the USB supply voltage detection circuitry generates a first set of first input signals which isolates the USB supply voltages from the first and second set of USB signals from the output connector when there is a change in the USB supply voltage from the second set of USB signals, and later generates a second set of first input signals to pass the USB data signals from the first set of USB signals or the second set of USB signals to the output connector. | 12-16-2010 |
20110004718 | SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR ORDERING A PLURALITY OF WRITE COMMANDS ASSOCIATED WITH A STORAGE DEVICE - A system, method, and computer program product are provided for ordering a plurality of write commands associated with a storage device. In operation, a plurality of write commands associated with a storage device to be sent to a device are identified. Additionally, an order of the plurality of write commands is determined, the determined order being known by the device. Further, the plurality of write commands are ordered in the determined order. | 01-06-2011 |
20110010481 | MASSIVE MULTI-CORE PROCESSOR BUILT WITH SERIAL SWITCHING - A multi-processor architecture for a network device that includes a plurality of barrel cards, each including: a plurality of processors, a PCIe switch coupled to each of the plurality of processors, and packet processing logic coupled to the PCIe switch. The PCIe switch on each barrel card provides high speed flexible data paths for the transmission of incoming/outgoing packets to/from the processors on the barrel card. An external PCIe switch is commonly coupled to the PCIe switches on the barrel cards, as well as to a management processor, thereby providing high speed connections between processors on separate barrel cards, and between the management processor and the processors on the barrel cards. | 01-13-2011 |
20110016252 | Multiple Minicard Interface System and Method Thereof - A system includes a minicard socket, a controller, a south bridge, and a differential multiplexer. The minicard socket is configured to receive a plurality of types of minicards. The controller is in communication with the minicard socket, and is configured to determine which one of the plurality of types of minicards is received within the minicard socket. The south bridge is configured to communicate with the minicard received within the minicard socket. The differential multiplexer is in communication with the controller and with the minicard socket. The differential multiplexer configured to switch the south bridge and the minicard socket between communicating over a plurality of buses based on the type of minicard received within the minicard socket. | 01-20-2011 |
20110016253 | Auto-function USB port - An auto-function port located within a host computing machine or an external peripheral device, wherein the auto-function port is identified by the host computing machine through a unique product and vendor identification associated with an internal USB hub controller, thereby allowing for execution of an automated function by the host computing machine upon connection of a USB device with the auto-function port depending on the software configuration of the host computing machine and the type of USB device. | 01-20-2011 |
20110016254 | SHARING OF HOST BUS ADAPTER CONTEXT - A system comprises a first host bus adapter (HBA) that uses a first context to facilitate the transmission of packets through a logical connection through the first HBA. The system also comprises a second HBA and memory in which the first context is stored. The memory is accessible by both of the first and second HBAs. Upon receiving a packet associated with the logical connection, the second HBA accesses the memory to use the first context to process the packet in accordance with the first context. | 01-20-2011 |
20110022769 | Translation USB Intermediate Device and Data Rate Apportionment USB Intermediate Device - One aspect of the technology is an apparatus with a USB intermediate device such as a USB hub or a USB composite device. The USB intermediate device includes control circuitry that performs translation between USB 2 communications of the multiple downstream USB 2 ports and USB 3 SuperSpeed communications of the upstream USB 3 port. Another USB intermediate device includes control circuitry that modifies apportionment of the USB 3 maximum data rate among the multiple downstream USB 2 ports, such that the multiple downstream USB 2 ports communicate at a collective data rate exceeding a USB 2 maximum data rate of USB High Speed. Another USB intermediate device includes control circuitry that performs translation and modifies apportionment. Other aspects are a system with a host computer, methods, and computer readable media. | 01-27-2011 |
20110022770 | SYSTEMS AND METHODS FOR PROVIDING A DYNAMICALLY MODULAR PROCESSING UNIT - Systems and methods for providing a modular processing unit. A modular processing unit is provided as a platform that is lightweight, compact, and is configured to be selectively used alone or oriented with one or more additional processing units in an enterprise. In some implementations, a modular processing unit includes a non-peripheral based encasement, a cooling process (e.g., a thermodynamic convection cooling process, a forced air cooling process, and/or a liquid cooling process), an optimized circuit board configuration, optimized processing and memory ratios, and a dynamic back plane that provides increased flexibility and support to peripherals and applications. The modular processing unit is customizable and may be employed in association with all types of computer enterprises. The platform allows for a plethora of modifications that may be made with minimal impact to the modular unit, thereby enhancing the usefulness of the platform across all type of application. | 01-27-2011 |
20110055450 | Multifunctional Storage Device with Built-in Software Controlled I/O Bus - A multifunctional storage device with a built-in software controlled I/O bus includes a transmission interface plug, a transmission interface hub, at least one I/O device, at least one bridge and a built-in storage device. The built-in storage device includes a memory controller and a memory module, and the memory module stores a software program and an auto-run setup program for automatically controlling and turning on or off connected to at least one I/O device (such as an extended device including a built-in device and an external device) of the bridge, such that a user can save the trouble of installing complicated driver programs and performing a manual setup to achieve a real plug-and-play function. | 03-03-2011 |
20110078356 | Providing A Peripheral Component Interconnect (PCI)-Compatible Transaction Level Protocol For A System On A Chip (SoC) - In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed. | 03-31-2011 |
20110093641 | USB SHARING SWITCH WITH AUTOMATIC SWITCHING CAPABILITIES - A USB printer sharing switch device with automatic switching capabilities is provided for multiple computers to share a USB printer. The sharing switch device transfers USB data between the computers and the printer without changing the data format. The automatic switching function is performed by hardware and firmware of the sharing switch device in cooperation with driver software on the computers. In one implementation, the sharing switch device includes multiple USB device controllers corresponding to the multiple computers, and employs multiple switches and a USB hub so that each computer is connected to its corresponding controller and the computer that is currently connected to the printer can communicate with its controller while printing. The current computer transmits a spooling finished command to its controller when spooling is finished. After receiving the spooling finished command, the sharing switch device automatically switches the printer to another computer. | 04-21-2011 |
20110107003 | REMOTE USB SYSTEM FOR SUPPORTING MULTIPLE VIRTUAL MACHINES OF MULTIPLE HOST AND METHOD THEREOF - There is a master server according to an embodiment of the present invention that includes: a remote USB information manager receiving information on a USB device connected to a remote USB bridge from the remote USB bridge and managing the received information; a virtual machine information manager receiving information of a user's virtual machine from a virtual machine host server and managing the received information; a user request processor, in accordance with a request of a user who wants to access a predetermined USB device on the remote USB bridge, extracting information on the corresponding USB device from the remote USB information manager and extracting the information on the user's virtual machine from the virtual machine information manager; and a remote USB connection controller connecting the user's virtual machine to the predetermined USB device by using the information extracted by the user request processor. | 05-05-2011 |
20110113178 | COMPUTER DEVICE AND CONTROL METHOD FOR THE SAME - Relay buffers | 05-12-2011 |
20110131361 | COMPUTER APPARATUS, COMPUTER SYSTEM AND ADAPTER CARRY-OVER METHOD - To obtain a computer that can change over from the active system to the standby system without reconnecting the I/O adapters. The computer according to the present invention carries over the identifiers logically identifying connection paths between computer modules and I/O adapters from active computers to standby computers. | 06-02-2011 |
20110131362 | Flexibly Integrating Endpoint Logic Into Varied Platforms - In one embodiment, the present invention is directed to an integrated endpoint having a virtual port coupled between an upstream fabric and an integrated device fabric that includes a multi-function logic to handle various functions for one or more intellectual property (IP) blocks coupled to the integrated device fabric. The integrated device fabric has a primary channel to communicate data and command information between the IP block and the upstream fabric and a sideband channel to communicate sideband information between the IP block and the multi-function logic. Other embodiments are described and claimed. | 06-02-2011 |
20110145468 | AGGREGATING UNOCCUPIED PCI-E LINKS TO PROVIDE GREATER BANDWIDTH - Embodiments of the claimed subject matter are directed to systems and a method that allows the aggregation of multiple interfaces of a single data communication bus to provide greater bandwidth for communication between a peripheral device and system memory within a computing system. In one embodiment, a system is provided wherein the unoccupied interfaces of the data communication bus is aggregated with an occupied interface coupled to a peripheral device to increase the bandwidth of data transfer requests between the peripheral device and the system memory. | 06-16-2011 |
20110153899 | Computer Peripheral Expansion Apparatus - Computer peripheral expansion apparatus, methods of operation, and computer program products including blade peripheral expansion units (‘BPEUs’), each BPEU including a peripheral interconnect multiplexer coupled for peripheral interconnect data communications through an upstream peripheral interconnect bus (‘PIB’) segment to a host blade, the upstream PIB segment fanned out by the multiplexer into two or more peripheral downstream interconnect channels, the multiplexer connecting the upstream PIB segment to only one of the downstream channels at a time; and the two or more downstream peripheral interconnect channels, at least one of the downstream channels connected to at least one peripheral interconnect device (‘PID’) in the BPEU, the peripheral interconnect device being a device that communicates with the host blade according to a peripheral interconnect data communications protocol, one of the downstream channels configured to connect to an upstream PIB segment in another BPEU. | 06-23-2011 |
20110153900 | VARIABLE READ LATENCY ON A SERIAL MEMORY BUS - Systems and/or methods are provided that facilitate employing a variable read latency on a serial memory bus. In an aspect, a memory can utilize an undefined amount of time to obtain data from a memory array and prepare the data for transfer on the serial memory bus. The serial memory bus can be driven to a defined state. When data is ready for transfer, the memory can assert a start bit on the serial memory bus to notify a host prior to initiating the data transfer. | 06-23-2011 |
20110153901 | VIRTUAL USB KEY FOR BLADE SERVER - A system for sharing data contained on a peripheral device amongst a plurality of blade servers is disclosed. The system includes a memory device for storing the data contained on the peripheral device. The memory device is partitioned into memory areas. Each memory area stores one copy of the data. The system also includes a processor coupled to the memory device for assigning one of the memory areas to each blade server. The system also includes a switch controller coupled to the processor and to the plurality of blade servers for establishing communication between the plurality of blade servers and the plurality of assigned memory areas. | 06-23-2011 |
20110153902 | Test Interface Card and Testing Method - A test interface card includes: a first specification bus adapted for coupling between a first specification interface controller of a device under test (DUT) and a signal converting interface card, and for transmitting a first test signal that is outputted by the first specification interface controller to the signal converting interface card for processing; a second specification bus adapted for coupling between the signal converting interface card and a storage module of the DUT, and for transmitting a processed signal that is outputted by the signal converting interface card as a result of processing the first test signal to the storage module; and a third specification bus adapted for forming a closed circuit with a second specification interface controller of the DUT, and for transmitting a second test signal that is outputted by the second specification interface controller back to the second specification interface controller. | 06-23-2011 |
20110153903 | METHOD AND APPARATUS FOR SUPPORTING STORAGE MODULES IN STANDARD MEMORY AND/OR HYBRID MEMORY BUS ARCHITECTURES - A memory/storage module is provided that implements a solid state drive compatible with Serial Advanced Technology Attachment (SATA) or Serial Attached SCSI (SAS) signaling on a double-data-rate compatible socket. A detachable daughter card may be coupled to the memory module for converting a memory bus voltage to a second voltage for memory devices on the memory module. Additionally, a hybrid memory bus on a host system is provided that supports either DDR-compatible memory modules and/or SATA/SAS-compatible memory modules. In one example, the memory/storage module couples to a first bus (DDR3 compatible socket) to obtain voltage and/or other signals, but uses a second bus for data transfers. In another example, the memory module may repurpose/reuse electrical paths that typically carry non-data signals for data traffic to/from the memory/storage module. Such data traffic for the memory/storage module permits concurrent data traffic for other memory modules on the same memory bus. | 06-23-2011 |
20110153904 | Wireless universal serial bus system and driving method thereof - Disclosed is a wireless universal serial bus system that includes a device; a first host communicating with the device according to a wireless universal serial bus protocol; and a second host communicating with the device according to a wireless universal serial bus protocol, wherein when the first host receives a beacon from the second host, the first host provides new host information read out from the beacon to the device. | 06-23-2011 |
20110167190 | Apparatus and method for distant bus extended system - The invention discloses a distant PCIe extended system. The distant PCIe extended system includes a local PCIe virtualization device (PVD), at least a transmission medium and at least a remote PVD. The PVD includes a PCIe PHY layer, a signal converting circuit, at least a PVD PHY layer and a transmission medium. The PCIe PHY layer is used to receive a PCIe physical signal. The signal converting circuit is coupled to the PCIe PHY layer and used to convert the PCIe data link layer packet into at least a PVD MAC packet. The PVD PHY layer is coupled to the signal converting circuit and used to process and transfer the PVD MAC packet. The transmission medium receives and transfers the PVD physical signal. | 07-07-2011 |
20110173367 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 07-14-2011 |
20110185103 | Serial communication device configurable to operate in root mode or endpoint mode - Systems and methods according to the present invention provide serial communication devices which are pin-configurable at power on to operate as either a root ( | 07-28-2011 |
20110202702 | METHOD AND SYSTEM FOR PCI HYBRID FUNCTION - A single root I/O virtualization (SR-IOV) capable peripheral component interconnect (PCI) device may be operable to configure resources to transparently operate in a non-SR-IOV environment utilizing a physical function (PF) and one or more hybrid functions (HFs). In instances when the SR-IOV capable PCI device is operating in a SR-IOV environment, the SR-IOV capable PCI device may expose a VF configuration space in the hybrid function to an associated PCI driver for configuring the hybrid function as a virtual function. In instances when the SR-IOV capable PCI device is operating in a non-SR-IOV environment, the SR-IOV capable PCI device may hide a SR-IOV extended header in the physical function from the associated PCI driver and expose a PF configuration space in the hybrid function to the associated PCI driver for configuring the hybrid function as a physical function. | 08-18-2011 |
20110202703 | RELIABILITY OF A COMPUTER SYSTEM EMPLOYING PCI EXPRESS DEVICES - An improved PCI Express multiplier device is disclosed. The PCI Express multiplier device comprises two or more device attachers to attach at least two identical PCI Express devices; a root complex attacher to attach a PCI Express root complex; a copier to copy and forward PCI Express data packets from the root complex to all of the attached identical devices; a collector to collect PCI Express data packets sent from the attached identical devices to the root complex; a selector responsive to the collector to select and forward PCI Express data packets from the collected PCI Express data packets to the root complex. | 08-18-2011 |
20110208891 | METHOD AND APPARATUS FOR TRACKING TRANSACTIONS IN A MULTI-SPEED BUS ENVIRONMENT - Systems and methods are provided to track the state of a data forwarding component, such as a USB transaction translator, included in a downstream hub within a multi-speed bus environment. The data forwarding component accommodates communication speed shifts at the hub. The method may comprise receiving a split packet request defining a transaction, performing a lookup in an associative array using hub-specific information provided in the split packet request to determine whether an identifier is allocated to the data forwarding component, and if it is determined, based on the lookup, that an identifier is allocated to the data forwarding component, storing state information associated with the split packet request. The associative array may include multiple identifiers, each of which has an associated state field configured to track information, such as the number of packets-in-progress and bytes-in-progress to a particular data forwarding component. | 08-25-2011 |
20110208892 | METHOD AND APPARATUS FOR SCHEDULING TRANSACTIONS IN A MULTI-SPEED BUS ENVIRONMENT - Systems and methods schedule periodic and non-periodic transactions in a multi-speed bus environment that includes in a downstream hub a data forwarding component, such as a USB transaction translator, which accommodates communication speed shifts at the hub. The method may comprise receiving a split packet request defining a transaction with a device, tagging the request with an identifier allocated to the data forwarding component, storing the request in a transaction list associated with the identifier, initiating transfer of payload data, and updating a counter associated with the identifier to reflect an amount of payload data for which transfer was initiated. The identifier may have associated therewith a counter for tracking a number of bytes-in-progress to the data forwarding component and one or more transaction lists configured to store a plurality of split packet requests awaiting execution and state information regarding an execution status of the requests. | 08-25-2011 |
20110208893 | MULTIPLE MODULE COMPUTER SYSTEM AND METHOD INCLUDING DIFFERENTIAL SIGNAL CHANNEL COMPRISING UNIDIRECTIONAL SERIAL BIT CHANNELS - A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system. | 08-25-2011 |
20110225338 | INTERFACE DEVICE FOR COORDINATING CONTROL OF AN OUTPUT DEVICE BY MULTIPLE CONTROL CONSOLES - A system and method for interfacing multiple inputs and outputs in a control system is provided. A digital input/output system provides a localized interface between multiple operator consoles and at least one output device to coordinate and monitor the operation of the at least one output device. The digital input/output system includes an interface device which re-routes discrete lines to and from the operator consoles and output devices and eliminates conflicting signals sent from the operator consoles to the output devices. | 09-15-2011 |
20110225339 | DATA TRANSMISSION SYSTEM AND A PROGRAMMABLE SPI CONTROLLER - A data transmission system is provided. The data transmission system includes a serial peripheral interface (SPI) and a programmable controller. The SPI is coupled between a first device and at least one second device. The programmable controller controls the SPI to switch between a single port data transmission mode and a multi-port data transmission mode. When there are more than one second device coupled to the SPI, the SPI is switched to the multi-port data transmission mode so as to perform multi-port data transmission between the first device and the second devices. At this time, the first device concurrently transmits data to each of the second devices via a first transmission bus terminal, and concurrently receives data from each of the second devices via a second transmission bus terminal. | 09-15-2011 |
20110225340 | EMULATOR INTERFACE DEVICE AND METHOD THEREOF - An interface device for an emulator is disclosed. The interface device includes a connection unit, a transmission unit, and an interface unit. The connection unit receives data, to be used to emulate a logic, from a host computer, and transmits result data, output from the logic, to the host computer. The transmission unit receives the data from the connection unit and stores (writes) the data in the first area of a register array. If the result data is stored in the second area of the register array, the transmission unit reads the result data and transmits the result data to the connection unit. The interface unit includes at least one register array, outputs a clock, set using the data stored in the first area, to the logic, and stores the result data, output from the logic, in the second area. | 09-15-2011 |
20110238883 | INFORMATION PROCESSING DEVICE - An information processing device is provided, in which a bit operation is performed without degradation in performance of a bus. An information processing device includes a CPU which fetches and executes an instruction, and a peripheral module which includes internally a register rewritable by the CPU, and is coupled to the CPU via a bus. The CPU has a function of issuing a bus command for commanding a bitwise write operation to the register comprised in the peripheral module, in order to execute a bit operation command fetched. When the bus command is issued, the peripheral module executes a bitwise write operation for the register. Since the CPU does not need to lock the bus after the bus command is issued, a bit operation can be performed without degradation in performance of the bus. | 09-29-2011 |
20110252176 | STORAGE SYSTEM MOUNTED WITH PLURALITY OF PROCESSORS - A storage system | 10-13-2011 |
20110252177 | SEMICONDUCTOR STORAGE DEVICE MEMORY DISK UNIT WITH PROGRAMMABLE HOST INTERFACE - In general, embodiments of the present invention provide a Semiconductor Storage Device (SSD) memory disk unit having a programmable host interface (unit). Specifically, in a typical embodiment, the SSD-based memory disk unit comprises a programmable host interface unit for coupling the SSD-based memory disk unit to at least one host; an adaptive host interface controller unit coupled to the programmable host interface unit; a DMA controller coupled to the adaptive host interface controller unit; an ECC controller coupled to the DMA controller; a memory controller coupled to the ECC controller; and a memory array coupled to the memory controller, the memory array comprising at least one SSD memory block. | 10-13-2011 |
20110264839 | Bridge apparatus for coupling a medical network with a non-medical network - A bridge apparatus for coupling a medical network with a non-medical network includes a storage unit to store data from the medical network, a first interface device for coupling the storage unit with the medical network, and a second interface device for coupling the storage unit with the non-medical network. The bridge apparatus is configured to execute write-only access requests on the storage unit via the first interface device or to execute read-only access requests on the storage unit via the second interface device. | 10-27-2011 |
20110271029 | HOST SYSTEM AND DATA TRANSMISSION CIRCUIT THEREOF - A data transmission circuit is provided by the present invention with a PCIe slot unit and a PCIe I/O interface card. Wherein the PCIe I/O interface card is inserted into the PCIe slot unit and coupled to a peripheral apparatus through a PCIe connection device. Therefore, a transmission data can be transmitted between the PCIe I/O interface card and the PCIe slot unit through the PCIe connection device. | 11-03-2011 |
20110283037 | INFORMATION PROCESSING APPARATUS AND DATA TRANSFER METHOD - An object is to provide an information processing apparatus capable of improving the availability as a system while improving the reliability of a data transfer path and a data transfer method. An information processing apparatus has a data transfer path branching in a tree structure, from a root node to a plurality of nodes while communicably coupling therebetween and transmitting serial data between the root node and the plurality of nodes, including two internode data transfer paths provided between at least a pair of nodes of the plurality of nodes, through which serial data transfer is performed; and a routing processing unit provided to each terminal nodes that are the nodes on both ends of the internode data transfer path, transfers the return data from the transmission destination node to the transmission source node by using the same internode data transfer path as the internode data transfer path used for data transfer to the transmission destination node, when each of the terminal nodes transfers data received from any of another nodes being a transmission source to any of the nodes being a transmission destination via the other terminal node. | 11-17-2011 |
20110307642 | DATA PROCESSING DEVICE - When a data processing device is disconnected from a computer system after mutual authen-tication has been completed between the computer system and the data processing device, the data processing device cancels an authenticated state, and is not able to transfer data to a device other than a specific computer system. Therefore, even when the data processing device is connected to a device other than the specific computer system after the connection of a cable supporting hot swapping has been changed, the data processing device maintains the confidentiality of data. | 12-15-2011 |
20110320673 | Providing A Peripheral Component Interconnect (PCI)-Compatible Transaction Level Protocol For A System On A Chip (SoC) - In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed. | 12-29-2011 |
20120005391 | PROCESSOR BUS BRIDGE SECURITY FEATURE FOR NETWORK PROCESSORS OR THE LIKE - Described embodiments provide a system having a bridge for communicating information between two processor buses. The bridge receives a command from a first bus, the command having an identification field and an address field. As the command is entered into a buffer in the bridge, the address field is checked against one or more addresses. If there is a match, then control bits are checked to see if the command will be allowed or not depending on the identification field value. If the command is not transferred to the second bus, a flag is set in the buffer, and an error message is returned to the first bus, and an interrupt may be generated. The control bits allow commands access to specific addresses on the second bus or deny the access depending on the command identification field. Bit-wise masking provides a range of values for identification and address field matching. | 01-05-2012 |
20120005392 | INFORMATION PROCESSING SYSTEM - It is desirable to flexibly provide a single information processing device with a system capable of connecting a large number of input-output devices, and an inexpensive system capable of sharing an input-output device by a plurality of servers. To achieve this, there is provided an information system including a server chassis and an IO chassis. The server chassis includes a plurality of server blades each having a processor, a memory, and a root complex, and a first multi-root PCIe switch connected to the individual server blades. The IO chassis includes a plurality of PCIe slots to which input-output devices are attached, and a second multi-root PCIe switch connected to the individual PCIe slots. The first multi-root PCIe switch and the second multi-root PCIe switch are connected together by a PCIe cable. | 01-05-2012 |
20120005393 | ELECTRICAL AND ELECTRONIC SYSTEM HAVING AN ELECTRICAL CENTER FOR A VEHICLE - An electrical and electronic system having a control unit connected to a remotely located electrical center by way of a data bus. The electrical center includes a bus interface unit and a main printed circuit board having a plurality of control devices such as relays, which selectively activate vehicle electrical circuits based on instructions from the control unit. The bus interface unit is that of a daughter board configured to be plugged into the main board of the electrical center, such as a Local Interconnect Network (LIN) interface board, and the data bus may be a LIN bus. | 01-05-2012 |
20120005394 | System and Method for Providing PCIE over Displayport - An apparatus and method is disclosed for providing an extensible information handling system (IHS) bus implemented on predetermined channels of a digital video interface. IHS video signal information is multiplexed with IHS bus information by a host multiplexer for transmission across a digital video connector. The multiplexed IHS video signal and IHS bus information is received by a display multiplexer, where it is demultiplexed. Demultiplexed IHS video signal information is received by a video interface receiver, where it is used to generate an image on a digital display. Demultiplexed IHS bus information is received by a host bus interface transmitter/receiver, where it is used to support peripheral devices attached to the digital display. | 01-05-2012 |
20120017024 | COMPONENT OF ANOTHER COMPUTING MACHINE - A method including initializing at least one component of another computing machine in response to the other computing machine coupling to a computing machine, loading a component driver onto the computing machine for at least one of the initialized components, and configuring the computing machine to use the component driver to control at least one of the initialized components of the other computing machine | 01-19-2012 |
20120017025 | System and Method for Accessing Resources of a PCI Express Compliant Device - A system and method using messages to access registers and memory in a PCI Express communications link environment. Vendor defined PCI Express messages can be used to read and write to the memory-mapped or register space of a device. Four types of accesses are defined using this messaging approach, namely memory read, memory write, configuration read and configuration write. The type of register access desired is defined by the appropriate value in a vendor-specific type field in the header of the vendor defined message. If a PCI Express compliant device at the other end of the PCI Express link does not support these types of messages, the messages are silently discarded by the receiver and no error is reported. | 01-19-2012 |
20120030399 | MOBILE PHONE DEVICE PLATFORM - Some embodiments relate to an apparatus, method and computer-medium for interacting with a peripheral device (e.g. a mobile phone device) via a USB port. Some embodiments relate to a routine and host device whereby using a technique of function interception, it I possible to intercept the plug-and-play (PnP) handler of the USB hub driver executing on the host device so as to prevent the loading into memory of the host device of a device driver which matches a hardware ID received by the host from a peripheral device. In some embodiments, it is possible to change the received hardware ID to a different hardware ID, and to load, into memory of the host device, a device driver which matches the different hardware ID. | 02-02-2012 |
20120030400 | USB CONNECTOR FOR WIRELESS COMMUNICATION DEVICE - A Universal Serial Bus (USB) apparatus for USB communication is provided. The USB apparatus includes a Printed Circuit Board (PCB) including a circuit for communicating data with an external device according to a USB communication standard, a connector for connecting to a USB terminal of the external device, and a noise reduction circuit connected between an output terminal of the PCB and the connector for reducing noise of a data signal. The noise reduction circuit includes a common-mode filter for removing harmonic components generated between a ‘+’ data signal and a ‘−’ data signal and passing the ‘+’ data signal and the ‘−’ data signal, which operate in a differential mode. | 02-02-2012 |
20120030401 | MAPPING NON-PREFETCHABLE STORAGE LOCATIONS INTO MEMORY MAPPED INPUT/OUTPUT SPACE - A system including a host and a device. The device has at least one non-prefetchable storage location. The host and the device are configured to map the at least one non-prefetchable storage location into memory mapped input/output space that is addressed via greater than 32 address bits. | 02-02-2012 |
20120030402 | PCI EXPRESS TLP PROCESSING CIRCUIT AND RELAY DEVICE PROVIDED WITH THIS - A PCI Express TLP processing circuit ( | 02-02-2012 |
20120036305 | DETERMINATION VIA AN INDEXED STRUCTURE OF ONE OR MORE PARTITIONABLE ENDPOINTS AFFECTED BY AN I/O MESSAGE - A data processing system includes a processor core, a system memory including a first data structure including entries mapping requester identifiers (IDs) to partitionable endpoint (PE) numbers and a second data structure, and an input/output (I/O) subsystem including an I/O bridge and a plurality of PEs each including one or more requesters each having a respective requester ID. The I/O host bridge, responsive to receiving an I/O message including a requester ID, determines a PE number by reference to a first entry from the first data structure, and responsive to determining the PE number, accesses a second entry of the second data structure utilizing the PE number as an index, where the second entry indicating one or more of the plurality of PEs affected by the message. The I/O host bridge services the I/O message with reference to each of the plurality of PEs indicated by the second entry. | 02-09-2012 |
20120042112 | INTERFACE ADAPTER SYSTEMS AND METHODS - Interface adapter systems and methods are provided. An adapter means can be provided for coupling a first interface to a second interface, the second interface configured to accommodate the coupling of a peripheral device. A detector means can be provided for detecting the peripheral device. A means can be provided for communicating a first signal to a first bus when the peripheral device is not detected. A converting means can be provided to convert a first signal to a second signal having a protocol different than the first and a communications means for communicating the second signal to a second bus can be provided when the detecting means has detected the peripheral device. | 02-16-2012 |
20120042113 | MOBILE COMPUTING APPLIANCE FOR HOSTING A PORTABLE, BOOTABLE MEDIUM - A portable computing hub appliance is configured to host a portable, bootable data storage medium, such as a USB flash, spinning device or compact disk having an operation system image saved thereupon. The appliance may not have a hard drive, operating system, or any other overhead that is typically found on a PC, Mac or tablet PC. The appliance may include the minimum components needed to host the portable, bootable medium, such as a USB flash, spinning drive, or compact disk with a Windows® or other operating system. The appliance may provide a user with the ability to boot any portable, bootable medium, such as a USB flash, spinning drive, or compact disk, eliminating security concerns caused by giving users access to the BIOS configurations or system hard drive. The appliance may include a power supply, an optional external Wi-Fi antenna port, audio input and output ports, an internal processor, an optional internal battery, an optional touchscreen, and the like. | 02-16-2012 |
20120059966 | STORAGE DEVICE AND METHOD FOR MANAGING SIZE OF STORAGE DEVICE - The invention relates to a storage device in which MR-IOV is applied to the internal network of a storage controller, whereby the size of the storage device can be easily expanded. The storage device is expanded on the basis of a network having processor-connected RPs, FE I/F, BE I/F, and CM I/F that are connected with a switch. In the switch, a plurality of ports other than those connected to the RPs, FE I/F, BE I/F, and CM I/F are connected with a cross-link. Each processor is allowed to control the FE I/F, BE I/F, or CM I/F either via a path that passes through the cross-link or via a path that does not pass through the cross-link within the unit device. When unit devices are connected to expand the size of a storage device, the cross-link is removed first and then the unit devices are connected with a new cross-link (see FIG. | 03-08-2012 |
20120059967 | MEMORY BUS ARCHITECTURE FOR CONCURRENTLY SUPPORTING VOLATILE AND NON-VOLATILE MEMORY MODULES - A memory/storage module is provided that implements a solid state drive compatible with Serial Advanced Technology Attachment (SATA) or Serial Attached SCSI (SAS) signaling on a double-data-rate compatible socket. A detachable daughter card may be coupled to the memory module for converting a memory bus voltage to a second voltage for memory devices on the memory module. Additionally, a hybrid memory bus on a host system is provided that supports either DDR-compatible memory modules and/or SATA/SAS-compatible memory modules. In one example, the memory/storage module couples to a first bus (DDR3 compatible socket) to obtain voltage and/or other signals, but uses a second bus for data transfers. In another example, the memory module may repurpose/reuse electrical paths that typically carry non-data signals for data traffic to/from the memory/storage module. Such data traffic for the memory/storage module permits concurrent data traffic for other memory modules on the same memory bus. | 03-08-2012 |
20120059968 | PROCESSING SYSTEM WITH RF DATA BUS FOR INTRA-DEVICE COMMUNICATION - A processing system includes a plurality of first circuit modules. A plurality of second circuit modules are coupled to an RF data bus via intra-device RF communications. The RF data bus receives first data from at least one of the plurality of first circuit modules, and transmits the first data via intra-device RF communications to at least one of the plurality of second circuit modules. | 03-08-2012 |
20120084485 | USB TRANSACTION TRANSLATOR AND AN ISOCHRONOUS-IN TRANSACTION METHOD - The present invention is directed to a universal serial bus (USB) transaction translator and an associated IN isochronous transaction method. A device interface is coupled to a device via a device bus, and a host interface is coupled to a host via a host bus, wherein the host USB version is higher than the device USB version. At least two buffers configured to store data are disposed between the device interface and the host interface. A controller stores the data in the buffers alternately. A register is used to record device bus information. Before the host sends an IN packet, the controller pre-fetches data from the device according to the device bus information and then stores the data in the buffers; the controller responds with the pre-fetched data to the host after the host sends the IN packet. | 04-05-2012 |
20120102254 | Virtualized Peripheral Hardware Platform System - The present invention discloses a virtualized peripheral hardware platform system. The virtualized peripheral hardware platform system includes a first hardware platform and a software platform, which is executed in a second hardware platform. The first hardware platform is in signal communication with the second hardware platform. The software platform not only simulates the operation of the peripheral device of the first hardware platform but also simulates input signals of virtual peripheral devices and then transmits the input signals to the first hardware platform to conduct further calculations. Furthermore, the input/output (I/O) interface of the second hardware platform can be simulated as the I/O interface of the first hardware platform, so as to decrease the number of the I/O interface which the first hardware platform needed and downsize the first hardware platform. | 04-26-2012 |
20120102255 | USB HUB SUPPORTING UNEQUAL NUMBERS OF HIGH-SPEED AND SUPER-SPEED PORTS - A super-speed USB3.0 hub is described to which, after configuration, there are more high-speed devices than super-speed devices connected. The difference in the numbers is recognized and logic is provided that responds to an upstream host that there is an equal or balanced number of super-speed and high-speed ports active. This is accomplished by providing a number of “dummy” ports that make up any actual difference. The “dummy” ports are never active and are never connected to any device. | 04-26-2012 |
20120102256 | DISABLING OUTBOUND DRIVERS FOR A LAST MEMORY BUFFER ON A MEMORY CHANNEL - Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface. | 04-26-2012 |
20120110233 | I/O SYSTEM, DOWNSTREAM PCI EXPRESS BRIDGE, INTERFACE SHARING METHOD, AND PROGRAM - Fault tolerance is improved, a functional limitation at the time of start-up of an I/O system is avoided, and a start-up time is shortened. A downstream PCI Express bridge sets a PCI Express device connected to the downstream PCI Express bridge itself, among a plurality of single root-compatible PCI Express devices shared by a plurality of root complexes connected to a plurality of upstream PCI Express bridges that exchange data with the downstream PC Express bridge itself through a network, controls and monitors a state of a physical link with the PCI Express device connected to the downstream PCI Express bridge itself, and performs monitoring and notification of an error of the PCI Express device connected to the downstream PCI Express bridge itself. | 05-03-2012 |
20120117292 | Method and system for initiating distinct USB connections over a network - Connecting USB devices with USB hosts over distinct network paths, including the following steps: Connecting USB hosts with respective USB host adaptors (USBHs), essentially according to USB specification timings. Connecting USB devices with respective USB device adaptors (USBDs). Enabling the USBDs and the USBHs to communicate over a network that can connect each USBD with each USBH. Initiating USB connections over the network between the USB devices and the USB hosts. And operating at least two of the USB connections over the network essentially simultaneously and without any common network node. | 05-10-2012 |
20120117293 | USB host adaptor for initiating a USB connection over a non-USB network - Initiating, by USB host adaptors, USB connections over a non-USB network, including the steps of: Connecting non-collocated USB hosts with respective non-collocated USB host adaptors (USBHs), according to USB specification timings. Connecting non-collocated USB devices with respective non-collocated USB device adaptors (USBDs). Enabling the USBHs and the USBDs to communicate over the non-USB network that enables each USBD to discover the presence and capabilities of each USBH. Receiving, by the USBHs, information about the USB devices. And then initiating, by the USBHs, USB-over-network connections between the USB hosts and the USB devices. | 05-10-2012 |
20120137041 | NETBOOK SYNCHRONIZATION CHIP DEVICE - The present invention discloses a netbook synchronization chip device for data communication and power line connection between a netbook and an external device, including: a first USB interface, coupled to a USB host of the netbook; a second USB interface, coupled to the external device; a memory unit, used for buffering transmission data and storing an application software and a firmware, wherein the application software can be downloaded and executed by the netbook and the external device to transform a peripheral device into a USB device with an accessible root directory; and a synchronization chip controller, used for identifying the external device and performing data communication and power line connection between the netbook and the external device according to the firmware. | 05-31-2012 |
20120137042 | METHOD AND SYSTEM FOR TAKING OVER DEVICES - A method and system for taking over devices are provided. In a solution, a first control board first performs topology discovery on a Peripheral Component Interconnect Express (PCIE) bus, and reserves resources for a Switch (SW) where a NON-Transparent (NT) bridge is located and devices connected to down ports of the SW according to a set resource reservation policy when the topology discovery proceeds to the NT bridge, where the SW and the devices are currently controlled by a second control board. After the SW and the devices are taken over from the second control board, the resource reserved in advance may be allocated to the SW and the devices, so that the devices that are taken over operate normally under control of the first control board. Dual control is implemented through direct taking over devices, and a response speed for processing a device request is improved. | 05-31-2012 |
20120144086 | USB TRANSACTION TRANSLATOR AND A METHOD THEREOF - The present invention is directed to a universal serial bus (USB) transaction translator and a micro-frame synchronization method. A device interface is coupled to a device via a device bus, and a host interface is coupled to a host via a host bus, wherein the host USB version is higher than the device USB version. At least two buffers configured to store data are disposed between the device interface and the host interface. A controller stores the data in the buffers alternately. A start-of-frame (SOF) counter is used to count the SOF packets, wherein the counting value of the SOF counter is compared to a predefined value. Specifically, the controller resets a SOF timer for sending the SOF packet when the counting value achieves the predefined value or is greater than the predefined value, such that the SOF packet and an isochronous timestamp packet (ITP) from the host are sent at the same time. Further, the controller delays the sending of the SOF packet for a period of time according to the ITP from the host. In another embodiment, the sending period of SOF packets may be dynamically adjusted in isochronous transfer. | 06-07-2012 |
20120159034 | COMMUNICATION PORT AND CONNECTOR - A communication port and connector are described. A mobile computing device may include a hardware element, with the hardware element being communicatively coupled to a connection. The connection is communicatively coupled to a communication port, and the communication port includes a first pin and a second pin. Additionally, at least one of the first pin and the second pin is comprised of a ferromagnetic material. Other embodiments are described and claimed. | 06-21-2012 |
20120173787 | ANALOG INTERFACE FOR A MICROPROCESSOR-BASED DEVICE - An apparatus includes an integrated circuit, which includes a processor and a driver. The integrated circuit is fabricated by a process that establishes a nominal maximum voltage for components of the integrated circuit. The driver is adapted to selectively electrically couple a voltage that is higher than the nominal maximum voltage to an external terminal of the integrated circuit. | 07-05-2012 |
20120173788 | Computing Element Virtualization - System and method for virtualization of computing elements. A hypervisor provides virtualization of one or more peripherals for one or more computing elements. The hypervisor may further allow separate instances of an operating system to be suspended on one computing element to allow another application to be processed by replacing the state information of the computing element. The suspended instance may be resumed on the same or a different computing element. | 07-05-2012 |
20120191894 | DISPLAY WITH MULTIPLE VIDEO INPUTS AND PERIPHERAL ATTACHMENTS - A display device that has multiple inputs for receiving video data and peripheral data from multiple computing devices, and an output for attaching a peripheral. The display is operable in one of two states, to provide both a video and peripheral signal paths between a selected one of the interconnected computing devices and the display's panel and attached peripherals. At any given time only one of the computing devices may utilize both the display and any attached peripherals. Exemplary embodiments may handle video and peripheral data streams received from a computing device over a single physical link. | 07-26-2012 |
20120191895 | APPARATUS AND METHODS FOR COMMUNICATING POWER AND DATA WITH ELECTRONIC DEVICES - Embodiments of a system, topology, and methods for providing power and transceiving data to, and backing up data from electronic devices having a data interface are described generally herein. Other embodiments may be described and claimed. | 07-26-2012 |
20120215957 | SEMICONDUCTOR STORAGE DEVICE-BASED CACHE STORAGE SYSTEM - Embodiments of the present invention provide a SSD-based storage system. Specifically, in a typical embodiment, a network cache server is coupled to an internal storage network and an external storage network. Coupled to the network cache server is a network cache component (NCC) that comprises: a set of semiconductor storage device (SSD) memory disk units for storing data; a network cache controller coupled to the set of SSD memory units; a network traffic analysis component coupled to the network cache controller; and a set of network interfaces coupled to the network traffic analysis component. The internal storage network can be coupled to a set of internal storage systems while the external storage network can be coupled to a set of external storage servers. | 08-23-2012 |
20120221763 | GATEWAY APPARATUS FOR SUBSTATION AUTOMATION SYSTEM - A communication gateway apparatus for a substation automation system, the gateway includes a VERSA Module Eurocard (VME) bus to provide a data communication path, a Peripheral Component Interconnect (PCI)-VME module connected to the VME bus for communication and having a PCI-VME bus bridge circuit to transfer data of the VME bus to a PCI bus or data of the PCI bus to the VME bus, and a plurality of input/output modules connected to the VME bus for communication. | 08-30-2012 |
20120226848 | INCREASING INPUT OUTPUT HUBS IN CONSTRAINED LINK BASED MULTI-PROCESSOR SYSTEMS - Methods and apparatus relating to increase Input Output Hubs in constrained link based multi-processor systems are described. In one embodiment, a first input output hub (IOH) and a second IOH are coupled a link interconnect and a plurality of processors, coupled to the first and second IOHs include pre-allocated resources for a single IOH. Other embodiments are also disclosed and claimed. | 09-06-2012 |
20120233373 | ELECTRONIC EQUIPMENT SYSTEM, ELECTRONIC EQUIPMENT AND CONNECTION EQUIPMENT - A branching device (connection equipment) | 09-13-2012 |
20120233374 | DUAL MODE SERIAL/PARALLEL INTERFACE AND USE THEREOF IN IMPROVED WIRELESS DEVICES AND SWITCHING COMPONENTS - Systems, methods, and devices for communicating with a serial/parallel interface are described herein. In an aspect, a wireless device includes a transceiver configured to output a plurality of transmission paths, and an antenna configured to output a signal corresponding to at least one of the transmission paths. The wireless device further includes a wireless switching component including a radio-frequency switch configured to selectively connect the antenna to one of the transmission paths, a plurality of signal pins, a serial interface including a plurality of serial inputs electrically coupled to at least one pin of the plurality of signal pins, a parallel interface including a plurality of parallel inputs electrically coupled to at least one pin of the plurality of signal pins, a decoder, and a level shifter configured to control the radio-frequency switch, the at least one pin electrically coupled to both a serial input and a parallel input. | 09-13-2012 |
20120239849 | SYSTEM AND METHOD FOR PERFORMING RAID I/O OPERATIONS IN PCIE-BASED STORAGE RESOURCES - Systems and methods for performing RAID I/O operations in PCIe-based storage resources are disclosed. In accordance with embodiments of the present disclosure, a method for performing a read operation may be provided. The method may include overlaying memory address space of storage resources of a source logical unit for the read operation onto a destination address. The method may also include determining whether the source logical unit is a RAIDO array. The method may additionally include generating a source address in a receive buffer for each storage resource of the source logical unit if the source logical unit is a RAIDO array. The method may further include storing data received from each storage address of the logical unit at the generated source address of the receive buffer associated with such storage resource. | 09-20-2012 |
20120246377 | HID over Simple Peripheral Buses - In embodiments of HID over simple peripheral buses, a peripheral sensor receives inputs from a peripheral device, and the peripheral sensor implements an HID SPB interface to interface the peripheral device with a computing system via a simple peripheral bus (SPB) in an HID data format. The peripheral sensor can also receive extensibility data for a proprietary function of the peripheral device, and communicate the inputs from the peripheral device and the extensibility data via the simple peripheral bus in the computing system. Alternatively or in addition, a peripheral sensor can generate sensor data and the HID SPB interface interfaces the peripheral sensor with the computing system via the simple peripheral bus. The peripheral sensor can then communicate the sensor data as well as extensibility data for a proprietary function of the peripheral sensor via the simple peripheral bus in the HID data format to the computing system. | 09-27-2012 |
20120284448 | EXECUTING VIRTUAL FUNCTIONS USING MEMORY-BASED DATA IN A PCI EXPRESS SR-IOV AND MR-IOV ENVIRONMENT - A method, including receiving, by an extended virtual function shell positioned on a Peripheral Component Interconnect Express (PCIe) configuration space, a virtual function call comprising a request to perform a specific computation, and identifying a physical function associated with the called virtual function, the physical function one of multiple physical functions positioned on the PCIe configuration space. One or more first data values are then retrieved from a virtual function instance stored in the memory, one or more first data values, the virtual function instance associated with the called virtual function, and one or more second data values are retrieved from the identified physical function. The specific computation is then performed using the first data values and the second data values, thereby calculating a result. | 11-08-2012 |
20120290764 | SHARED SYSTEM OF I/O EQUIPMENT, SHARED SYSTEM OF INFORMATION PROCESSING APPARATUS, AND METHOD USED THERETO - An I/O equipment sharing system includes CPUs, a plurality of route complexes coupled to the CPUs, upstream PCI Express-bridges coupled to the route complexes, downstream PCI Express-bridges coupled to the upstream PCI Express-bridges through a network, and I/O equipment coupled to the downstream PCI Express-bridges. In the above configuration, the I/O equipment are shared between the CPUs using the identifiers of the network (for example, Ethernet VLAN IDs), the identifiers are set so that they do not overlap between the respective CPUs and necessary I/O equipment is set to a set identifier. Further, an identifier is set to a plurality of the same I/O equipment required by the respective CPUs. | 11-15-2012 |
20120297107 | STORAGE CONTROLLER SYSTEM WITH DATA SYNCHRONIZATION AND METHOD OF OPERATION THEREOF - A method of operation of a storage controller system includes: accessing a first controller having a synchronization bus; accessing a second controller, by the first controller, through the synchronization bus; and receiving a first transaction layer packet by the first controller including performing a multi-cast transmission between the first controller and the second controller through the synchronization bus. | 11-22-2012 |
20120311219 | Patient Monitoring Platform Interface - Physical monitoring systems are disclosed which may include a platform interface between a platform device and a monitoring module. The platform interface may allow physiological information from a patient such as sensor signal data, physiological trend data, other suitable data, or combinations thereof to be communicated from the monitoring module to the platform device. The platform interface may include a connector with pins configured to receive UART communications, transmit UART communications, communicate diagnostic information, be coupled to a ground, be coupled to a serial clock, receive serial data, transmit serial data, be coupled to a regulated power supply, be coupled to an unregulated power supply, communicate using USB standard, communicate using any other suitable standards, perform any other suitable functions, or any combinations thereof. The monitoring module may connect directly to the platform device, or a wired cable with suitable connectors may be used to electrically couple the monitoring module to the platform device. | 12-06-2012 |
20120311220 | COMPUTER BUS WITH ENHANCED FUNCTIONALITY - A method for computing includes connecting a host device to a peripheral device via a bus that is physically configured in accordance with a predefined standard and includes multiple connection pins that are specified by the standard, including a plurality of ground pins. At least one pin, selected from among the pins on the bus that are specified as the ground pins, is used in order to indicate to the peripheral device that the host device has an extended operational capability. | 12-06-2012 |
20120311221 | USING A PCI STANDARD HOT PLUG CONTROLLER TO MODIFY THE HIERARCHY OF A DISTRIBUTED SWITCH - The standard hot-plug controller (SHPC) specification may be used to generate PCI messages in a distributed switch to disconnect and/or connect virtual hierarchies of an endpoint from hosts that are connected based on multi-root input/output virtualization (MR-IOV). A management controller may instruct a SHPC to generate a PCI packet that specifies a particular virtual hierarchy to disconnect from a particular host. An upstream port connected to the host and the SHPC receives the PCI packet and uses a header that identifies the virtual endpoint in the packet to index into a routing table to identify a downstream port in the distributed switch that is connected to the endpoint. Once the PCI packet traverses the switch and arrives at the downstream port, the downstream port changes routing logic which logically disconnects the host from the specified virtual hierarchy. | 12-06-2012 |
20120331202 | SYSTEMS AND METHODS FOR DRIVERLESS OPERATION OF USB DEVICE - Systems and methods of re-enumerating peripheral devices operatively connected to a computer system are provided. In one example, a system is configured to disable an existing connection between an operating system and a peripheral device established through a device driver by re-describing the peripheral device to the OS. In another example, the system can be further configured to execute operation(s) on the peripheral device without new driver installation using communication channels native to the OS. Once the operation(s) are complete, the system can be configured to restore the existing connection. | 12-27-2012 |
20130007332 | CONTROLLABLE TRANSACTION SYNCHRONIZATION FOR PERIPHERAL DEVICES - Embodiments of the invention describe a host system capable of associating a PCIe device and another separate device to the same device identifier (e.g., device number). A cycle routing module or logic will identify an I/O transaction involving the device identifier, and route the transaction to one or both of the devices (or, in some instances, identify the I/O transaction as a configuration transaction, and simply update the cycle routing module/logic only). In one embodiment of the invention, a root port of the host system is configured to operate as the above described cycle router. | 01-03-2013 |
20130007333 | Controller Interface Providing Improved Signal Integrity - In one implementation, a memory device includes non-volatile memory and a memory controller communicatively coupled to the non-volatile memory over a first bus. The memory device can also include a host device interface through which the memory controller communicates with a host device over a second bus, wherein the host device interface includes an impedance calibration circuit that is adapted to calibrate a signal transmitted over the second bus by host device interface so that a source impedance associated with the signal matches, within a threshold value, a load impedance associated with the host device over the second bus. | 01-03-2013 |
20130013841 | Apparatus And Method of Universal Serial Bus, USB, Communication - The USB device (e.g. an audio class device) comprises a USB bus interface that connects to an upstream USB port and a USB logical device that provides first USB endpoints for upstream communication on a first channel. The USB host comprises a USB host controller that connects to a downstream USB port, and a USB driver that provides second USB endpoints for downstream communication on a second channel; wherein the USB host operates concurrently with the USB device. The processor is configured to communicate data between the first channel and the second channel via the first USB endpoints and the second USB endpoints, respectively. | 01-10-2013 |
20130019045 | Consolidating Computer Memory Drive Management In A Computing SystemAANM Andresen; Mark E.AACI CaryAAST NCAACO USAAGP Andresen; Mark E. Cary NC USAANM Newsom; Thomas H.AACI CaryAAST NCAACO USAAGP Newsom; Thomas H. Cary NC USAANM Nichols; Scott A.AACI CaryAAST NCAACO USAAGP Nichols; Scott A. Cary NC US - Consolidating computer memory drive management in a computing system, the computing system including a plurality of computer memory drives, a system memory drive manager, and one or more light pipes, including: detecting, by a system memory drive manager, an multi-drive tray memory drive manager; configuring the system memory drive manager to communicate with the memory drive over the light pipe; and communicating, by the system memory drive manager, with the memory drive over the light pipe. | 01-17-2013 |
20130024596 | Computer System Including CPU or Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits - A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system. | 01-24-2013 |
20130042046 | COMPUTING MODULE WITH SERIAL DATA CONNECTIVITY - A computing module includes an interface to asynchronously, serially exchange parallel system bus data with one or more other modules of a computer system that includes the computing module. The computing module can asynchronously, serially transfer first parallel bus data to another module of the computer system, and can asynchronously, serially receive second parallel bus data from another module of the computer system. | 02-14-2013 |
20130054865 | MOUSE - A mouse includes a universal serial bus (USB) 3.0 port, a mouse control circuit, and a memory card port for connecting a memory card. The USB 3.0 port transmits data of the mouse from the mouse control circuit through a first to a fourth pins of the USB 3.0 port, and transmits data of the memory card through the first and a fifth to ninth pins of the USB 3.0 port. | 02-28-2013 |
20130054866 | USB HUB AND CONTROL METHOD OF USB HUB - A USB hub capable of reducing power consumption in a USB system. The USB hub includes an upstream USE port, a downstream USB port, a clock pin that supplies an operation clock to a USE peripheral device, and a hub controller that stops clock supply to the USB peripheral device via the clock pin when a connecting between the upstream USB port and a USB host is disconnected or when the hub controller receives a suspend request to the downstream USB port from the USB host. | 02-28-2013 |
20130086295 | COMMUNICATION CONTROL SYSTEM, SWITCHING NODE, COMMUNICATION CONTROL METHOD AND COMMUNICATION CONTROL PROGRAM - In a switching node, high-speed and advanced service protocol processing function is achieved by utilizing an external control server without affecting performance of conventional service protocol processing. Specifically, a forwarding engine has PCI express and an LAN interface. Depending on a type of an input packet, destination of the packet is switched to the PCI express side for conventional network service and to the LAN interface side for extended network service that cooperates with the external control server. A CPU having the PCI express and the LAN interface is provided ahead of the LAN interface. The CPU performs communication of service inquiry with the external control server at high speed via the LAN interface. After response from the control server is obtained, setting of the forwarding engine is performed through the PCI express. | 04-04-2013 |
20130091317 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 04-11-2013 |
20130097352 | Computer System Including CPU or Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits - A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system. | 04-18-2013 |
20130097353 | PCI EXPRESS ENHANCEMENTS AND EXTENSIONS - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 04-18-2013 |
20130103876 | System and Method for Providing PCIE over Displayport - An apparatus and method is disclosed for providing an extensible information handling system (IHS) bus implemented on predetermined channels of a digital video interface. IHS video signal information is multiplexed with IHS bus information by a host multiplexer for transmission across a digital video connector. The multiplexed | 04-25-2013 |
20130117489 | USB HOST WAKE FROM SLEEP STATE FOR MOBILE DEVICES - A USB host for wakeup from a sleep state includes a hold memory, a USB host controller, and a USB driver. When going to sleep, the USB driver sends a suspend command to the USB host controller in response to receiving a sleep command. The USB driver also reads a controller context from the USB host controller and saves the controller context in the hold memory. Thereafter, the USB driver turns off one or more supply potentials and one or more clocks in the host controller, and returns a sleep acknowledgement. While in sleep, the interface pins are placed in a hold state and notification to the operating system are disabled. | 05-09-2013 |
20130117490 | COMMUNICATING A MESSAGE REQUEST TRANSACTION TO A LOGICAL DEVICE - A general input/output communication port implements a communication stack that includes a physical layer, a data link layer and a transaction layer. The transaction layer includes assembling a packet header for a message request transaction to one or more logical devices. The packet header includes a format field to indicate the length of the packet header and to further specify whether the packet header includes a data payload, a subset of a type field to indicate the packet header relates to the message request transaction and a message field. The message field includes a message to implement the message request transaction. The message includes at least one message that is selected from a group of messages. The group of messages to include a message to unlock a logical device, a message to reset a logical device, a message to indicate a correctable error condition, a message to indicate an uncorrectable error condition, a message to indicate a fatal error condition, a message to report a bad request packet, a message to indicate power management and a message to emulate an interrupt signal. | 05-09-2013 |
20130124770 | Configuring Expansion Component Interconnect ('ECI') Physical Functions On An ECI Device In A Computing System - Configuring expansion component interconnect (‘ECI’) physical functions on an ECI device in a computing system, including: configuring by an ECI device configuration manager, during run-time of the computing system, vital product data to include an ECI physical function configuration, wherein the ECI physical function configuration comprises data describing a type of ECI physical function; retrieving by an ECI device configuration manager, upon a subsequent startup of the computing system, the ECI physical function configuration from the vital product data; and configuring, by an ECI device configuration manager, a physical function of the ECI device to carry out the type of ECI physical function described in the ECI physical function configuration. | 05-16-2013 |
20130124771 | AUXILIARY DEVICE FOR CAMERA MODULE TEST - An auxiliary device includes a first interface of a bandwidth higher than about 1 Gbps for connecting a camera module, a second interface of a bandwidth higher than about 1 Gbps for connecting an image analysis device, a buffer, and a processor connected to the first interface, the second interface, and the buffer. The processor reads commands, which contain a set of predetermined parameters of the camera module, via the second interface and transmits the set of predetermined parameters to the camera module via the first interface. The processor also reads frames of image from the camera module to the buffer via the first interface at a rate above about 1 Gbps, and reads the frames of image from the buffer to the image analysis device frame by frame via the second interface at a rate above about 1 Gbps. | 05-16-2013 |
20130124772 | GRAPHICS PROCESSING - In one embodiment, a computer system comprises two or more graphics cards, each graphics card comprising: a graphics processing unit and an interface. An interface of the first graphics card is coupled to an interface of the second graphics card for enabling communication between the first and second graphics cards. A cable couples the interface of the first graphics card with the interface of the second graphics card. The transmitting speed of data exchanging between graphics cards of the computer system is increased, and the arrangement of the PCB (printed circuit board) of the graphics card is simple and the cost thereof is low. | 05-16-2013 |
20130138860 | USB CLASS PROTOCOL MODULES - A computer system includes USB class protocol-aware modules for USB devices as part of a xHCI host controller. The protocol-aware modules serve as accelerators by implementing critical portions of the device class protocols, which includes fetching higher level protocol data directly from client buffers for transmission and delivering decoded data to client buffers on receipt; and emulating a register-based interface for the benefit of system software on the host computer. | 05-30-2013 |
20130145071 | ELECTRONIC DEVICE AND METHOD FOR SWITCHING MODES OF THUNDERBOLT CONNECTOR THEREOF - An electronic device and a method for switching mode of a thunderbolt connector thereof are provided. The electronic device includes a core unit, a PCIE device, a thunderbolt control unit, a first switch circuit and a second switch circuit. The thunderbolt control unit has a host mode and an end-point device mode. A common terminal of the first switch circuit is coupled to a PCIE port of the PCIE device. A first selection terminal of the first switch circuit is coupled to a first PCIE port of the core unit. A common terminal of the second switch circuit is coupled to a PCIE port of the thunderbolt control unit. A first selection terminal of the second switch circuit is coupled to a second PCIE port of the core unit. A second selection terminal of the first switch circuit is coupled to a second selection terminal of the second switch circuit. | 06-06-2013 |
20130151748 | STRUCTURE FOR TRANSMITTING SIGNALS OF PCI EXPRESS AND METHOD THEREOF - A structure for transmitting signals of PCI express and a method thereof provides a converting device and a high-definition multimedia interface (HDMI) cable. The converting device has a plug connector to into a PCI express slot, along with a HDMI connector. The signal converting circuit connects the signal pins of the PCI express slot to the signal pins of HDMI connector. One end of the HDMI cable is connected with the HDMI connector of the converting device. The present invention can extends the signal distance of the PCI express to exactly perform the signal test. | 06-13-2013 |
20130151749 | APPARATUS FOR COUPLING TO A USB DEVICE AND A HOST AND METHOD THEREOF - An apparatus is provided for coupling a Universal Serial Bus (USB) device and a USB host. The apparatus includes a memory and a controller. The memory includes one or more descriptor entries. The controller is configured to obtain a descriptor of the USB device upon detection of the USB device on a USB bus, and compare the descriptor to a specific descriptor entry to generate a comparing result. Then the controller enables or disables a link path between the USB host and the USB device according the comparing result. | 06-13-2013 |
20130151750 | MULTI-ROOT INPUT OUTPUT VIRTUALIZATION AWARE SWITCH - A system having a multi protocol multi-root aware (MP-MRA) switch ( | 06-13-2013 |
20130166811 | METHODS AND STRUCTURE FOR COMMUNICATING BETWEEN A SATA HOST AND A SATA TARGET DEVICE THROUGH A SAS DOMAIN - Methods and structure for directly coupling SATA hosts (SATA initiators) with SATA target devices through a SAS fabric and an enhanced SAS expander supporting such direct couplings. The enhanced SAS expander comprises SATA/STP connection logic to open a SAS (STP) connection between a directly attached SATA host and a SATA target device in response to receipt of an FIS from the host or target while no connection is presently open. The opened connection is closed after expiration of a predetermined timeout period of inactivity between the connected host and target. Thus, simpler, less costly SATA hosts and SATA target devices may be utilized while gaining the advantage of SAS architecture flexibility in configuration and scalability. SATA hosts may be coupled through the SAS fabric with a larger number of SATA target devices and multiple SATA hosts may be coupled with the SAS fabric. | 06-27-2013 |
20130179621 | EXTENSIBLE DAISY-CHAIN TOPOLOGY FOR COMPUTE DEVICES - Devices, systems and methods for providing a daisy-chain topology for networking compute devices having PCIe bridges are disclosed. The daisy-chain topology is an extensible PCIe or similar standard solution that allows for a variable number of nodes. The topology has no chassis and no fixed slots, and there is no single device or bridge designated as the PCIe root. This topology allows additional devices to be added to the daisy-chain without construction of a new chassis. Some or all of can be mechanically coupled to provide a common communication channel. Once connected on the expansion link, any device has the ability to communicate to any other device on the daisy-chain. The devices on the daisy-chain are able to let their CPU or processors directly talk to those of another device. This results in a master/master relationship rather than one device serving as the master and the remaining devices the slaves. | 07-11-2013 |
20130219101 | COMMUNICATION WITH TWO OR MORE STORAGE DEVICES VIA ONE SAS COMMUNICATION PORT - One or more techniques and/or systems are disclosed for enabling communication between a SAS communication port of a SAS communication component and multiple storage devices. In a first example, a first SAS to SATA bridge chip and a second SAS to SATA bridge chip may be configured to route data from a SAS communication component to multiple storage devices. In a second example, a SAS to SATA bridge chip and a port multiplier may be configured to route data from a SAS communication component to multiple storage devices. In a third example, a four port SAS to SATA bridge comprising two SAS ports and two SATA ports may be configured to route data from a SAS communication component to multiple storage devices. Supporting two or more storage devices with a single SAS communication port allows storage enclosures to increase storage capacity, while decreasing cost per slot. | 08-22-2013 |
20130268713 | PCIE SWITCH APPARATUS AND METHOD OF CONTROLLING CONNECTION THEREOF - The present invention relates to a PCIe switch apparatus and a method of controlling the connection thereof. The PCIe switch apparatus includes a PCIe photoconversion unit for converting an electrical signal input from a local host into packet data and converting the converted packet data into an optical signal. A PCIe slot board unit reconverts the optical signal into the packet data, reconverts the packet data into the electrical signal, and outputs the electrical signal to a PCIe-based device. An optical cable connects the PCIe photoconversion unit and the PCIe slot board unit to each other. The PCIe switch apparatus controls a long-distance communication interface between the local host and the PCIe-based device. | 10-10-2013 |
20130282949 | ACCESS TO INTERNAL MEMORY OF A COMPUTING DEVICE - A connection is established between a host device and an internal memory of a computing device. A voltage is received by the computing device from the host device. Upon receiving the regulated voltage, the internal memory of the computing device can exchange data with the host device. | 10-24-2013 |
20130290594 | CORE-DRIVEN TRANSLATION AND LOOPBACK TEST - A translation and loopback test for input/output ports is described. In one example, a method includes receiving a test packet on an output of a high speed processor link, looping the test packet back to an input of the high speed processor link, and detecting the receipt of the looped back test packet to test operation of the high speed link. | 10-31-2013 |
20130297846 | Providing A Peripheral Component Interconnect (PCI)-Compatible Transaction Level Protocol For A System On A Chip (SoC) - In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed. | 11-07-2013 |
20130304961 | HUB CONTROL CHIP - A HUB control chip implemented in a specific package is provided. The HUB control chip includes a plurality of transmission modules and a plurality of pins. The plurality of the pins include: a plurality of data pin groups coupled to one of the plurality of transmission modules respectively. Each of the plurality of data pin groups includes: a first sub-group, receiving and transmitting a first pair of differential signals conforming to the USB 2.0 standard; a second sub-group, receiving a second pair of differential signals conforming to the USB 3.0 standard; and a third sub-group, transmitting a third pair of differential signals conforming to the USB 3.0 standard. The number of the plurality of the pins is less than or equal to 52. | 11-14-2013 |
20130311695 | Flexray Gateway and Method for Operating a Flexray Gateway - A Flexray gateway comprising a first and a second bus interface for connecting a first and a second Flexray bus, wherein the Flexray gateway comprises coupling means for coupling a first and a second Flexray bus and for transmitting bus messages between the first and the second Flexray bus, wherein the Flexray gateway comprises a Flexray controller with a first and a second channel interface for transmitting and receiving bus messages of a first and a second channel type of a Flexray bus. | 11-21-2013 |
20130318278 | COMPUTING DEVICE AND METHOD FOR ADJUSTING BUS BANDWIDTH OF COMPUTING DEVICE - In a method for adjusting bus bandwidth applied on a computing device, the computing device includes a bus controller and several graphics processing units (GPUs). The bus controller establishes a data flow of each signal channel of the peripheral component interconnect express (PCI-E) bus connected to each GPU, and obtains a total data flow of the PCI-E bus connected to each GPU according to the data flow of each of the signal channels. If there is a fully-utilized GPU according to the total data flow of the PCI-E bus; the method locates an available idle signal channel of the PCI-E bus according to the data flow of each of signal channels, and reroutes the data flow of the fully-utilized GPU to the idle signal channel using a switch of the bus controller. | 11-28-2013 |
20130318279 | Providing A Load/Store Communication Protocol With A Low Power Physical Unit - In one embodiment, a converged protocol stack can be used to unify communications from a first communication protocol to a second communication protocol to provide for data transfer across a physical interconnect. This stack can be incorporated in an apparatus that includes a protocol stack for a first communication protocol including transaction and link layers, and a physical (PHY) unit coupled to the protocol stack to provide communication between the apparatus and a device coupled to the apparatus via a physical link. This PHY unit may include a physical unit circuit according to the second communication protocol. Other embodiments are described and claimed. | 11-28-2013 |
20130332643 | HID OVER SIMPLE PERIPHERAL BUSES - In embodiments of HID over simple peripheral buses, a peripheral sensor receives inputs from a peripheral device, and the peripheral sensor implements an HID SPB interface to interface the peripheral device with a computing system via a simple peripheral bus (SPB) in an HID data format. The peripheral sensor can also receive extensibility data for a proprietary function of the peripheral device, and communicate the inputs from the peripheral device and the extensibility data via the simple peripheral bus in the computing system. Alternatively or in addition, a peripheral sensor can generate sensor data and the HID SPB interface interfaces the peripheral sensor with the computing system via the simple peripheral bus. The peripheral sensor can then communicate the sensor data as well as extensibility data for a proprietary function of the peripheral sensor via the simple peripheral bus in the HID data format to the computing system. | 12-12-2013 |
20130346665 | VERSATILE LANE CONFIGURATION USING A PCIE PIE-8 INTERFACE - Each PCIe device may include a media access control (MAC) interface and a physical (PHY) interface that support a plurality of different lane configurations. These interfaces may include hardware modules that support 1×32, 2×16, 4×8, 8×4, 16×2, and 32×1 communication. Instead of physically connecting each of the hardware modules in the MAC interface to respective hardware modules in the PHY interface using dedicated traces, the device may include two bus controllers that arbitrate which hardware modules are connected to a internal bus coupling the two interfaces. When a different lane configuration is desired, the bus controller couples the corresponding hardware module to the internal bus. In this manner, the different lane configurations share the same lanes (and wires) of the bus as the other lane configurations. Accordingly, the shared bus only needs to include enough lanes (and wires) necessary to accommodate the widest lane configuration. | 12-26-2013 |
20130346666 | TUNNELING PLATFORM MANAGEMENT MESSAGES THROUGH INTER-PROCESSOR INTERCONNECTS - Methods and apparatus for tunneling platform management messages through inter-processor interconnects. Platform management messages are received from a management entity such as a management engine (ME) at a management component of a first processor targeted for a managed device operatively coupled to a second processor. Management message content is encapsulated in a tunnel message that is tunneled from the first processor to a second management component in the second processor via a socket-to-socket interconnect link between the processors. Once received at the second management component the encapsulated management message content is extracted and the original management message is recreated. The recreated management message is then used to manage the targeted device in a manner similar to if the ME was directly connected to the second processor. The disclosed techniques enable management of platform devices operatively coupled to processors in a multi-processor platform via a single management entity. | 12-26-2013 |
20140006674 | UNIVERSAL SERIAL BUS REPEATER | 01-02-2014 |
20140013023 | SYSTEM AND METHOD FOR SENDING ARBITRARY PACKET TYPES ACROSS A DATA CONNECTOR - A processing unit exchanges data with another processing unit across a data connector that supports a particular communication protocol. When the communication protocol is updated to support a new packet type, a specification of that new packet type may be stored within software registers included within the processing unit. Under circumstances that require the use of the new packet type, packet generation logic may read the packet specification of the new packet type, then generate and transmit a packet of the new type. | 01-09-2014 |
20140013024 | INTERPOSER AND INTELLIGENT MULTIPLEXER TO PROVIDE A PLURALITY OF PERIPHERIAL BUSES - A communication connector is described that provides an increase in the number and type of communication circuits available on an electronic device without increasing the number and type of physical connectors. The communication connector electrically includes a set of inputs to couple to both a USB 2.0 connector and a HDMI connector. A set of outputs from the communication connector provides a third connector with a pin out specification compatible with a USB 3.0 connector or a PCIe connector. | 01-09-2014 |
20140019666 | USB APPARATUS AND EMBEDDED SYSTEM INCORPORATING SAME - USB apparatus suitable for interconnection with a USB host having a D− bus coupled to ground via a pull-down resistance, the USB apparatus including a microcontroller having a first port and a second port, the first port being coupled via a resistance to a voltage source and a switch, operated by the microcontroller via the second port, selectably interconnecting the first port and the bus of the USB host. | 01-16-2014 |
20140032809 | COMPOSITE DATA TRANSMISSION INTERFACE AND A JUDGMENT METHOD THEREOF - The present invention relates to a composite data transmission interface and a judgment method thereof which is based on metal contacts shared by a smart card and a universal series bus and comprise steps as follows: link a composite pin to a socket; electrical conductivity is completed with a socket linking a composite pin; a controller connected to the composite pin is activated by electricity; a smart card's or a universal series bus's electrical conductivity mode is enabled by the controller by means of the smart card's or the universal series bus's electrical connection mode. | 01-30-2014 |
20140040525 | METHOD AND APPARATUS FOR ENHANCING UNIVERSAL SERIAL BUS APPLICATIONS - A system for enhancing universal serial bus (USB) applications comprises an upstream processor, a downstream processor and a main controller. The upstream processor accepts standard USB signals from a USB host and independently provides responses required by USB specification within the required time frame. The upstream processor also contains storage for descriptors for a device associated with this upstream processor. The main controller obtains the descriptors by commanding the downstream processor, and passes them to the upstream processor. The downstream processor connectable to USB-compliant devices accepts the USB signals from the USB-compliant devices and provides responses required by USB specification within the required time frame. The main controller interconnects the upstream and downstream processors, and provides timing independence between upstream and downstream timing. The main controller also commands the downstream processor to obtain device descriptors independent of the USB host. | 02-06-2014 |
20140052888 | Method and apparatus for providing two way control and data communications to and from transportation refrigeration units (TRUs) - An RS-485 bus is directly connected to transportation refrigeration unit sensors for transmitting information from the sensors to a remote location and for controlling sensor parameters from the remote location. The GENSET associated with the transportation refrigeration unit also utilizes the RS-485 bus, in which the bus is directly connected to the GENSET sensors for bi-directional communication therewith. | 02-20-2014 |
20140059265 | Fabric Independent PCIe Cluster Manager - A cluster manager of a computer cluster determines an allocation of resources from the endpoints for running applications on the nodes of the computer cluster and configures the computer cluster to provide resources for the applications in accordance with the allocation. The cluster may include a Peripheral Component Interconnect express (PCIe) fabric. The cluster manager may configure PCIe multi-root input/output (I/O) virtualization topologies of the computer cluster. The allocations may satisfy Quality of Service requirements, including priority class and maximum latency requirements. The allocations may involve splitting I/O traffic. | 02-27-2014 |
20140059266 | METHODS AND APPARATUS FOR SHARING A NETWORK INTERFACE CONTROLLER - Methods, apparatus, and systems for enhancing communication between compute resources and networks in a micro-server environment. Micro-server modules configured to be installed in a server chassis include a plurality of processor subsystems coupled in communication to a shared Network Interface Controller (NIC) via PCIe links. The shared NIC includes at least one Ethernet port and a PCIe block including a shared PCIe interface having a first number of lanes. The PCIe lines between the processor sub-systems and the shared PCIe interface employ a number of lanes that is less than the first number of lanes, and during operation of the micro-server module, the shared NIC is configured to enable each processor sub-system to access the at least one Ethernet port using the PCIe link between that processor sub-system and the shared PCIe block on the shared NIC. | 02-27-2014 |
20140059267 | USB TRANSACTION TRANSLATOR AND USB TRANSACTION TRANSLATION METHOD - A universal serial bus (USB) transaction translator is provided along with a micro-frame synchronization method. A device interface is coupled to a device via a device bus, and a host interface is coupled to a host via a host bus. At least two buffers are configured to store data. A controller stores the data in the buffers alternately. A start-of-frame (SOF) counter is used to count the SOF packets, with the counting value of the SOF counter being compared to a predefined value. Specifically, the controller resets a SOF timer for sending the SOF packet when the counting value achieves or exceeds the predefined value, such that the SOF packet and an isochronous timestamp packet (ITP) from the host are sent at the same time. Further, the controller delays the sending of the SOF packet for a period of time according to the ITP from the host. | 02-27-2014 |
20140068135 | Providing A Consolidated Sideband Communication Channel Between Devices - In an embodiment, the present invention includes a protocol stack having a transaction layer and a link layer. In addition a first physical (PHY) unit is coupled to the protocol stack to provide communication between a processor and a device coupled to the processor via a physical link, where the first PHY unit is of a low power communication protocol and includes a first physical unit circuit. In turn, a second PHY unit is coupled to the protocol stack to provide communication between the processor and the device via a sideband channel coupled between the multicore processor and the device separate from the physical link, where the second PHY unit includes a second physical unit circuit. Other embodiments are described and claimed. | 03-06-2014 |
20140089552 | USB HUBS WITH GALVANIC ISOLATION - A universal serial bus (USB) hub includes a USB AFE circuit module, a hub core and an isolator circuit module interposed between the USB AFE circuit module and the hub core. Data communications between the hub core and the first USB AFE circuit module pass through the isolator circuit module. A method for communicating through a universal serial bus hub includes providing a USB AFE circuit module, providing a hub core, providing an isolator circuit module interposed between the USB AFE circuit module and the hub core, and directing communication from the USB AFE circuit module to the hub core through the isolator circuit module. | 03-27-2014 |
20140101356 | TRANSMISSION DEVICE, TRANSMISSION SYSTEM, AND CONTROL METHOD FOR TRANSMISSION DEVICE - A transmission device includes a plurality of transmitting units that transmit data to an opposing device via different paths, a determining unit that compares a first speed of an operation clock for the opposing device with a second speed of an operation clock for the transmission device, and an inserting unit that inserts, when the first speed is same as the second speed, first difference absorbing data that has a predetermined data length into the data to be transmitted by the transmitting units, that inserts, when the first speed is higher, second difference absorbing data that has a data length smaller than the predetermined data length into the data, and that inserts, when the second speed is higher, third difference absorbing data that has a data length greater than the predetermined data length into the data. | 04-10-2014 |
20140108697 | Controlling A Physical Link Of A First Protocol Using An Extended Capability Structure Of A Second Protocol - In one embodiment, a method includes accessing a first field of a first link capabilities register of a first device having a protocol stack including a transaction layer and a link layer according to a first communication protocol and a physical layer of the protocol stack having a physical unit of a second communication protocol, using the first field as a pointer value to a location in a second link capabilities register of the first device, and using information from the location in the second link capabilities register to perform a configuration operation for a physical link coupled to the device. Other embodiments are described and claimed. | 04-17-2014 |
20140108698 | Architected Protocol For Changing Link Operating Mode - In one embodiment, a device having a link training state machine including a reconfiguration logic to perform a dynamic link reconfiguration of a physical link coupled between the device and a second device during a run-time in which the physical link does not enter a link down state, including transmission of a plurality of bandwidth change requests to the second device, each of the plurality of bandwidth change requests to request a bandwidth change from a first bandwidth to a second bandwidth. Other embodiments are described and claimed. | 04-17-2014 |
20140115222 | HIGH SPEED SERIAL PERIPHERAL INTERFACE SYSTEM - A serial peripheral interface (SPI) system including a bus adapter is disclosed. The bus adapter may include a data converter that may be adapted to receive respective first and second data from a first master output peripheral input (MOPI) line and a chip select line from a SPI master device. The data converter may also be adapted to interleave the first and second data, and the data converter may be adapted to transmit the interleaved first and second data synchronously with a second clock signal on a second MOPI line. The bus adapter may also include a clock rate adjuster adapted to generate the second clock signal to transmit to a SPI peripheral device. The second clock signal may be adapted to enable the SPI peripheral device to read the transmitted data. | 04-24-2014 |
20140122766 | HIGH SPEED DIFFERENTIAL WIRING STRATEGY FOR SERIALLY ATTACHED SCSI SYSTEMS - A serial attached SCSI (SAS) system may include a host bus adaptor, a bus expander, and a multi-layer data transmission medium coupled between the host bus adaptor and the bus expander. The multi-layer data transmission medium may include a first microstrip structure located at a top surface portion of the multi-layer data transmission medium and a first stripline structure located within a first internal portion of the multi-layer data transmission medium. The microstrip structure provides, among other things, a repeaterless high-speed serial communications link between the host bus adaptor and the bus expander. | 05-01-2014 |
20140122767 | OPERATING M-PHY BASED COMMUNICATIONS OVER PERIPHERAL COMPONENT INTERCONNECT (PCI)-BASED INTERFACES, AND RELATED CABLES, CONNECTORS, SYSTEMS AND METHODS - Embodiments disclosed herein include operating the M-PHY communications over peripheral component interconnect (PCI)-based interfaces. Related cables, connectors, systems, and methods are also disclosed. In particular, embodiments disclosed herein take the M-PHY standard compliant signals and direct them through a PCI compliant connector (and optionally cable) so as to allow two M-PHY standard compliant devices having PCI connectors to communicate. | 05-01-2014 |
20140136749 | CABLE DOCK ASSEMBLY AND METHOD OF MANUFACTURING THE SAME - A cable dock assembly can include a first sub-assembly including a power adapter configured to attach to a power source, a second sub-assembly including a first video display plug configured to attach to a first video display, a third sub-assembly including a universal serial bus plug configured to attach to a computing device placed on a surface, a first electrical cable attached at the first sub-assembly and the second sub-assembly, a second electrical cable attached at the second sub-assembly and the third sub-assembly, and one or more controller chips. The one or more controller chips can be fully contained within at least one of the first, second, or third sub-assemblies. Other related assemblies and methods are also provided. | 05-15-2014 |
20140149627 | SYSTEMS AND METHODS FOR SIGNAL DETECTION - A system for detecting one or more signals at a PCI Express interface includes a receiver configured to receive a signal at the PCI Express interface, and a peak detector configured to detect one or more signals based on level sensing, and identify one or more data sampling points to set an amplitude threshold. A comparator is configured to compare an amplitude of the received signal with the amplitude threshold, and a processor is configured to confirm that the received signal is a valid signal when the amplitude of the signal is at least one of greater than or equal to the amplitude threshold over a predefined period of time. The processor is also configured to disable a signal detector that can detect one or more low frequency signals. The system also includes a tester configured to test whether the detected signal is correct. | 05-29-2014 |
20140149628 | SUPER SPEED USB HUB AND TRAFFIC MANAGEMENT METHOD THEREOF - A super speed USB hub includes an upstream port, a plurality of device ports, a transaction dispatching unit, a downstream buffer, a hub local packet parser, a traffic control unit, and a forwarding unit. The transaction dispatching unit is used for receiving a plurality of packets from a USB hot, wherein the plurality of packets comprise a plurality of downstream packets and a hub command packet. If the hub command packet contains a traffic management command, the hub local packet parser generates a selected target and a control mode according to the traffic management command. The traffic control unit is used for managing a downstream packet corresponding to the selected target among the plurality of downstream packets in the downstream buffer according to the selected target and the control mode. | 05-29-2014 |
20140149629 | SYSTEMS AND METHODS FOR SIGNAL DETECTION - Methods for detecting one or more signals at a PCI Express interface includes receiving, a signal by a receiver at the PCI Express interface. The methods further include identifying one or more data sampling points to set an amplitude threshold. Further, the method includes comparing an amplitude of the received signal with the amplitude threshold. The method also includes confirming that the received signal is a valid signal when the amplitude of the signal is at least one of greater than or equal to the amplitude threshold over a predefined period of time. The method also includes disabling a signal detector of the PCI Express interface to save power. The signal detector is configured to detect one or more low frequency signals; and testing whether the detected signal is correct. | 05-29-2014 |
20140164668 | Power Stack Control Systems - The disclosed inventions relate to the field of power control electronics. More specifically the disclosed inventions pertain to Power Stack Control Systems which are used to control the generation of AC power from a DC or AC input voltage. The disclosed Power Stack Control Systems include a serial interface connection, the serial interface connection being in serial electrical communication with a plurality of power stacks, the plurality of power stacks comprising at least one interface board and at least one IGBT driver board, the at least one interface board being in parallel communication with at least one IGBT driver board. | 06-12-2014 |
20140173164 | Providing A Load/Store Communication Protocol With A Low Power Physical Unit - In one embodiment, a converged protocol stack can be used to unify communications from a first communication protocol to a second communication protocol to provide for data transfer across a physical interconnect. This stack can be incorporated in an apparatus that includes a protocol stack for a first communication protocol including transaction and link layers, and a physical (PHY) unit coupled to the protocol stack to provide communication between the apparatus and a device coupled to the apparatus via a physical link. This PHY unit may include a physical unit circuit according to the second communication protocol. Other embodiments are described and claimed. | 06-19-2014 |
20140181350 | Method and Apparatus Pertaining to Universal Serial Bus-Based Charging - A control circuit (comprising, for example, a part of a charging hub for a portable electronic communications device) that is not configured to support USB On-The-Go-compatible Host Negotiation Protocol is operably coupled to a USB-ID connector and is configured to transmit an identifier via that USB-ID connector to prompt a USB device in function mode to serve as a USB host. A locally-available power supply can then serve to provide power to that USB device notwithstanding the latter's role as the host. | 06-26-2014 |
20140181351 | INTELLIGENT INTERRUPT DISTRIBUTOR - An intelligent interrupt distributor balances interrupts (workload) in a highly parallelized system. The intelligent interrupt distributor distributes the interrupts between the processor cores. This allows lowering of voltage and frequency of individual processors and ensures that the overall system power consumption is reduced. | 06-26-2014 |
20140181352 | INTERCONNECT TO COMMUNICATE INFORMATION UNI-DIRECTIONALLY - A processor includes at least one core, a power control unit, and a first interconnect to couple with a peripheral controller. The first interconnect is to provide a first uni-directional communication path for communication of first power management data from the processor to the peripheral controller. Other embodiments are described and claimed. | 06-26-2014 |
20140181353 | INTERFACE EXTENSION DEVICE - An interface extension device is disclosed. The interface extension device includes a USB port, a USB hub and a first interface conversion circuit. The USB hub has a first port connected to the USB port. The first interface conversion circuit includes first and second USB hosts. The first USB host is connected to the USB hub and is connected to the USB port through the USB hub. The second host has a bus and is directly connected to the USB port without routing though any USB hub. | 06-26-2014 |
20140181354 | SYSTEM AND METHOD FOR TRANSMITTING DATA BASED ON PCIe - Embodiments of the present invention provide a system and a method for transmitting data based on Peripheral Component Interconnect Express 9PCIe). The system includes: a PCIe switching network, multiple switch terminal devices, a managing unit, multiple host processing units, multiple terminal processing units, multiple hosts, and multiple terminal devices. After a PCIe data packet sent by a host is processed by a host processing unit, a new PCIe data packet that can be transmitted in a PCIe switch is constructed, and is transferred, by using a switch terminal device and a terminal processing unit, to a terminal device. The embodiments can break through a limitation about a single root node of PCIe and implement sharing of a PCIe switching network by multiple hosts. | 06-26-2014 |
20140195711 | PCI EXPRESS CHANNEL IMPLEMENTATION IN INTELLIGENT PLATFORM MANAGEMENT INTERFACE STACK - Certain embodiments of the present disclosure are directed to a baseboard management controller (BMC) that includes a PCI express (PCIe) interface controller configured to provide access to a PCIe channel over a PCIe link, and firmware. The firmware includes a PCIe module being configured to access the PCIe channel through the PCIe interface controller and registered as a PCIe function. A software stack of the BMC communicates, through the PCIe module, with a PCIe device over the PCIe channel. | 07-10-2014 |
20140195712 | PROCESSOR MODULE, MICRO-SERVER, AND METHOD OF USING PROCESSOR MODULE - A processor module includes at least one storage device, at least one central processing unit (CPU) that uses a preset interface, and a module controller to relay a connection between a common interface bus formed on the based board and an interface used by the CPU. | 07-10-2014 |
20140195713 | Computer System Including CPU or Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits - A computer system for multi-processing purposes. The computer system has a console comprising a first coupling site and a second coupling site. Each coupling site comprises a connector. The console is an enclosure that is capable of housing each coupling site. The system also has a plurality of computer modules, where each of the computer modules is coupled to a connector. Each of the computer modules has a processing unit, a main memory coupled to the processing unit, a graphics controller coupled to the processing unit, and a mass storage device coupled to the processing unit. Each of the computer modules is substantially similar in design to each other to provide independent processing of each of the computer modules in the computer system. | 07-10-2014 |
20140201418 | Net-centric adapter for interfacing enterprises systems to legacy systems - A configurable system for translating, exchanging and integrating data and services among disparate software applications is provided. The system includes a first connection that interfaces with an enterprise system, a second connection that interfaces with a legacy system, and an adapter module coupled to the first and second connections. The adapter module is configured to receive data from the first connection and pass data to the second connection. The system may also include a transform module configured to manipulate data received at the second connection. The adapter module may be single-channel or multi-channel. A multi-channel adapter module is able to interface with multiple legacy systems and/or multiple enterprise systems. | 07-17-2014 |
20140201419 | EXECUTING VIRTUAL FUNCTIONS USING MEMORY-BASED DATA IN A PCI EXPRESS SR-IOV AND MR-IOV ENVIRONMENT - A method, including receiving, by an extended virtual function shell positioned on a Peripheral Component Interconnect Express (PCIe) configuration space, a virtual function call comprising a request to perform a specific computation, and identifying a physical function associated with the called virtual function, the physical function one of multiple physical functions positioned on the PCIe configuration space. One or more first data values are then retrieved from a virtual function instance stored in the memory, one or more first data values, the virtual function instance associated with the called virtual function, and one or more second data values are retrieved from the identified physical function. The specific computation is then performed using the first data values and the second data values, thereby calculating a result. | 07-17-2014 |
20140237153 | DEVICE-READY-STATUS TO FUNCTION-READY-STATUS CONVERSION - A method for sending readiness notification messages to a root complex in a peripheral component interconnect express (PCIe) subsystem. The method includes receiving a device-ready-status (DRS) message in a downstream port that is coupled to an upstream port in a PCIe component. The method further includes setting a bit in the downstream port indicating that the DRS message has been received. | 08-21-2014 |
20140237154 | Integrating Non-Peripheral Component Interconnect (PCI) Resources Into A Computer System - In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed. | 08-21-2014 |
20140237155 | Providing A Peripheral Component Interconnect (PCI)-Compatible Transaction Level Protocol For A System On A Chip (SoC) - In one embodiment, the present invention includes an apparatus having an adapter to communicate according to a personal computer (PC) protocol and a second protocol. A first interface coupled to the adapter is to perform address translation and ordering of transactions received from upstream of the adapter. The first interface is coupled in turn via one or more physical units to heterogeneous resources, each of which includes an intellectual property (IP) core and a shim, where the shim is to implement a header of the PC protocol for the IP core to enable its incorporation into the apparatus without modification. Other embodiments are described and claimed. | 08-21-2014 |
20140244888 | USING PCI-E EXTENDED CONFIGURATION SPACE TO SEND IOCTLS TO A PCI-E ADAPTER - An adapter includes a network interface module configured to interface the adapter to a network and a Peripheral Component Interconnect Express (PCIe) interface module configured to interface the adapter to a PCIe bus. The PCIe interface module comprises registers in PCIe extended configuration space. The registers are configured to receive ioctls from the PCIe bus. The adapter also includes an ioctl processing module configured to receive the ioctls from the registers, to perform the ioctls, and to provide results of the ioctls to the registers for provision by the registers to the PCIe bus. The ioctls comprise commands that relate to transceiving of frames by the adapter on the network. The network interface may be Ethernet, Fibre Channel, Infiniband, etc. Examples of the ioctls include retrieving operation or error statistics, setting virtual channel tag and priorities, and setting a protocol address associated with a port of the adapter. | 08-28-2014 |
20140250253 | BRIDGING AND INTEGRATING DEVICES ACROSS PROCESSING SYSTEMS - Particular embodiments described herein can offer an electronic fabric for a processing system that includes a fabric adapter to couple to a first fabric associated with a first system and to couple to a second fabric associated with a second system. The fabric adapter is configured to pass bidirectional communications between the first system and the second system. The electronic fabric can further include an address translation agent configured to map a first physical address in a first address space of the first system to a second physical address in a second address space of the second system. | 09-04-2014 |
20140250254 | APPARATUS AND METHOD FOR CONNECTING MOBILE TERMINAL TO EXTERNAL DEVICE - An apparatus performs a method for connecting a mobile terminal to an external device. The method includes determining a connection method of the external device among a plurality of connection methods based on values of at least two ports among a plurality of ports included in a connector, and switching at least one switch included in the connection unit so as to connect to the external device according to the determined connection method of the external device. | 09-04-2014 |
20140258584 | BUS RELAY APPARATUS, INTEGRATED CIRCUIT APPARATUS, CABLE, CONNECTOR, ELECTRONIC APPLIANCE, AND BUS RELAY METHOD - A bus relay apparatus includes: an upstream port unit to which a USB host is connected; a downstream port unit to which a USB device is connected; an upstream port control unit; a downstream port control unit; and a relay unit configured to relay a packet transferred between the upstream port unit and the downstream port unit. In the bus relay apparatus, the downstream port unit reproduces a bus status detected by the upstream port unit and transmits the bus status, and the upstream port unit reproduces a bus status detected by the downstream port unit and transmits the bus status. | 09-11-2014 |
20140281106 | DIRECT ROUTING BETWEEN ADDRESS SPACES THROUGH A NONTRANSPARENT PERIPHERAL COMPONENT INTERCONNECT EXPRESS BRIDGE - A system includes a PCIe controller coupled to a device through a nontransparent PCIe bridge. The controller is operable to direct I/O operations to the device on behalf of a host system. The system also includes a PCIe driver operable within the host system to generate I/O request descriptors that specify movement of data from the PCIe controller to the host system as well as from the host system to the PCIe controller. The PCIe controller processes the I/O request descriptors and determines which device is involved in the specified movement of data. The PCIe controller generates I/O commands that contain routing information for the device (e.g., memory addresses and steering information) to route the data between the memory address of the host system and the memory address of the device, bypassing a memory of the PCIe controller. | 09-18-2014 |
20140281107 | EFFICIENT INPUT/OUTPUT (I/O) OPERATIONS - A system includes a bus, a processor operably coupled to the bus, a memory operably coupled to the bus, a plurality of input/output (I/O) devices operably coupled to the bus, where each of the I/O devices has a set of control registers, and a first shared I/O unit operably coupled to the bus. The first shared I/O unit has a plurality of shared functions and is configured to perform the shared functions, where the shared I/O functions are not included as functions on the I/O devices and the I/O devices and the processor interact with the first shared I/O unit to use one or more of the shared functions performed by the first shared I/O unit. | 09-18-2014 |
20140281108 | DEVICE, SYSTEM AND METHOD FOR COMMUNICATION WITH HETEROGENOUS PHYSICAL LAYERS - A device to process data packets for communication across PHY layers which are of different respective communication protocols. In an embodiment, the device includes a first protocol stack and a second protocol stack which are each for a PCIe™ communication protocol. The first protocol stack and a second protocol stack may interface, respectively, with a first physical (PHY) layer and a second PHY layer of the device. The first protocol stack and the second protocol stack may exchange packets to facilitate communications via both the first PHY layer and the second PHY layer. In another embodiment, the first PHY layer is for communication according to the PCIe™ communication protocol and the second PHY layer is for communication according to another, comparatively low power communication protocol. | 09-18-2014 |
20140281109 | BUS INDEPENDENT PLATFORM FOR SENSOR HUB PERIPHERALS - A microcontroller for a peripheral hub includes a plurality of host bus interface microdrivers and a corresponding plurality of host transports. A first manager client, associated with a supported peripheral device, processes messages from a first host. A host manager module routes asynchronous communications, including but not limited to HID input reports, from a client to a host via one of a plurality of supported transports via a targeted transport indicated in the communication. The host manager modules routes synchronous communications from a host to a client via a targeted transport selected from a plurality of transports. | 09-18-2014 |
20140281110 | PCIE TRAFFIC TRACKING HARDWARE IN A UNIFIED VIRTUAL MEMORY SYSTEM - Techniques are disclosed for tracking memory page accesses in a unified virtual memory system. An access tracking unit detects a memory page access generated by a first processor for accessing a memory page in a memory system of a second processor. The access tracking unit determines whether a cache memory includes an entry for the memory page. If so, then the access tracking unit increments an associated access counter. Otherwise, the access tracking unit attempts to find an unused entry in the cache memory that is available for allocation. If so, then the access tracking unit associates the second entry with the memory page, and sets an access counter associated with the second entry to an initial value. Otherwise, the access tracking unit selects a valid entry in the cache memory; clears an associated valid bit; associates the entry with the memory page; and initializes an associated access counter. | 09-18-2014 |
20140297915 | PERIPHERAL COMPONENT INTERCONNECT DEVICE AND ELECTRONIC DEVICE WITH PERIPHERAL COMPONENT INTERCONNECT PORT - An electronic device includes a peripheral component interface (PCI) port, a first storage unit storing a basic input/output system (BIOS), a second storage unit storing a relationship table defining a number of register values and PCI setting information, and a processing unit. The PCI port is used to connect to at least one PCI device. The first storage unit stores a basic input/output system (BIOS). The processing unit runs the BIOS when the electronic device is starting up. When the BIOS is running, the BIOS reads a register value from the PCI device connected to the PCI port and determines a setting information of the PCI port corresponding to the register value according to the relationship table. The BIOS then sets the pins the PCI port according to the determined setting information. | 10-02-2014 |
20140337558 | MEDIATING COMMUNICATION OF A UNIVERSAL SERIAL BUS DEVICE - In an example, an apparatus includes a memory storing a hypervisor, where the hypervisor is configured to determine whether one or more universal serial bus (USB) devices in communication with the hypervisor are authorized to communicate with a guest operating system of the hypervisor and, after determining that the one or more USB devices are authorized to communicate with the guest, virtualize the one or more USB devices at the guest operating system and transfer messages between the one or more USB devices and the virtualized USB device. | 11-13-2014 |
20140344499 | IN-VEHICLE SENSOR AND IN-VEHICLE SENSOR SYSTEM - An in-vehicle sensor ( | 11-20-2014 |
20140351483 | MOTHERBOARD WITH PERIPHERAL COMPONENT INTERCONNECT EXPRESS SLOTS - A motherboard ( | 11-27-2014 |
20140372657 | Hidden Base Address Register Programming in Peripheral Component Interconnect Express Buses - A mapping and correspondence may be established between a virtual topology and a physical topology of a PCIe subsystem, and a host may be presented with the virtual topology but not the actual physical topology. A semi transparent bridge may couple an upstream host to the PCIe subsystem that includes intermediary bridges and respective PCIe endpoints coupled downstream from the intermediary bridges. The intermediary bridges may be hidden from the host, while the respective PCIe endpoints may be visible to the host. A configuration block may provide to the upstream host, during a setup mode, first memory allocation information corresponding to the intermediary switches, responsive to the upstream host expecting second memory allocation information corresponding to the respective PCIe endpoints. The configuration block may then provide to the upstream host, during a runtime mode, the second memory allocation information, responsive to the upstream host expecting the second memory allocation information. | 12-18-2014 |
20150019788 | Providing A Sideband Message Interface For System On A Chip (SoC) - According to one embodiment, a system on a chip includes multiple agents each corresponding to an intellectual property (IP) logic and a fabric to couple the agents. The fabric can include a primary message interface and a sideband message interface. The fabric further includes one or more routers to provide out-of-band communications between the agents via this sideband message interface. To effect such communication, the router can perform a subset of ordering rules of a personal computer (PC)-based specification for sideband messages. Other embodiments are described and claimed. | 01-15-2015 |
20150026384 | Network Switch - A network switch, based on the PCI Express protocol, is disclosed. The switch is in communication with a processor, local memory and includes a plurality of non-transparent bridges and, optionally transparent bridges, leading to PCI Express endpoints. By configuring the non-transparent bridges appropriately, the network switch can facilitate simultaneous communication between any two sets of servers without needing to store any data in the local memory or FIFO resources of the switch. For example, the network switch may configure the non-transparent bridges so as to have access to the physical memory of every server attached to it. It can then move data from the memory of any server to the memory of any other server. | 01-22-2015 |
20150046626 | LOW POWER SECONDARY INTERFACE ADJUNCT TO A PCI EXPRESS INTERFACE BETWEEN INTEGRATED CIRCUITS - A method, apparatus, and system for a secondary/adjunct interface between two Integrated Circuits (ICs) already having a Peripheral Component Interconnection Express (PCIe) interface, where the PCIe interface performs high-throughput data transfers and the adjunct/secondary interface performs low-throughput data transfers, thereby reducing power consumption for the low-throughput data transfers, are described. | 02-12-2015 |
20150058515 | Allocating Lanes In A Peripheral Connect Interface Express ('PCIe') Bus - Allocating lanes in a Peripheral Connect Interface Express (‘PCIe’) bus, including: determining, by a lane allocation module, performance capabilities of a device coupled to the PCIe bus; and allocating, by the lane allocation module, a number of lanes in the PCIe bus for use by the device in dependence upon the performance capabilities of the device. | 02-26-2015 |
20150058516 | MOTHERBOARD WITH COMPATIBLE CONNECTOR - A motherboard includes a connector, an identification module, a Serial Advanced Technology Attachment (SATA) signal module, a Universal Serial Bus (USB) signal module, and a selection module. The connector is used to determine compatibility and connect a SATA-type external device with a SATA connector and a USB-type external device with a USB connector. The identification module is coupled to the connector. The identification module outputs a first signal when the connector is coupled to the SATA-type external device and outputs a second signal when the connector is coupled to the USB-type external device. The selection module connects either the SATA signal module or the USB signal module to the connector as appropriate. | 02-26-2015 |
20150074320 | UNIVERSAL PCI EXPRESS PORT - Methods and systems are disclosed herein for providing a universal PCIe port. The same port can be configured to accept a PCIe component as a host or an endpoint (device) symmetrically. The PCIe port can be connected to the host interface or the root complex interface if the PCIe connection is to be configured as a host or an endpoint, respectively. A virtual topology can be provided for a host that associates the host with corresponding endpoints. A mapping between virtual addresses of the corresponding endpoints in the virtual topology and local addresses of the corresponding endpoints is provided. | 03-12-2015 |
20150074321 | UNIVERSAL PCI EXPRESS PORT - Methods and systems are disclosed herein for providing a universal PCIe port. In one example, the same port is configured to accept a PCIe connection as a host or an endpoint symmetrically. Downstream transactions towards an endpoint can be intercepted and a virtual address in the downstream transaction can be translated to a local address using a mapping. The downstream transactions can be forwarded to the endpoint using the local address instead of the virtual address. For endpoints that share the same local address with multiple hosts, a reverse lookup may be provided to determine which one of the hosts a local address corresponds when forwarding upstream transactions. PCIe over Ethernet is provided as one embodiment for allowing remote PCIe endpoints to be associated with a local host transparently. | 03-12-2015 |
20150074322 | UNIVERSAL PCI EXPRESS PORT - Methods and systems are disclosed herein for providing a universal PCIe port. In one example, the same port is configured to accept a PCIe connection as a host or an endpoint symmetrically. Downstream transactions towards an endpoint can be intercepted and a virtual address in the downstream transaction can be translated to a local address using a mapping. The downstream transactions can be forwarded to the endpoint using the local address instead of the virtual address. For endpoints that share the same local address with multiple hosts, a reverse lookup may be provided to determine which one of the hosts a local address corresponds when forwarding upstream transactions. PCIe over Ethernet is provided as one embodiment for allowing remote PCIe endpoints to be associated with a local host transparently. | 03-12-2015 |
20150081945 | METHODS AND APPARATUS TO MANAGE CACHE MEMORY IN MULTI-CACHE ENVIRONMENTS - Methods, apparatus, systems and articles of manufacture are disclosed to manage cache memory in multi-cache environments. A disclosed apparatus includes a remote cache manager to identify a remote cache memory communicatively connected to a bus, a delegation manager to constrain the remote cache memory to share data with a host cache memory via the bus, and a lock manager to synchronize the host cache memory and the remote cache memory with a common lock state. | 03-19-2015 |
20150089113 | EXPANSION CARD HAVING TWO SWITCHABLE CONNECTORS - An expansion card includes a PCIe connector, a non-PCIe connector, a signal switching module, and a signal processing module. The signal switching module includes a signal receiving unit and a signal transmitting unit. The PCIe connector is connected to the signal receiving unit and the signal transmitting unit. The non-PCIe connector is connected to the signal receiving unit and the signal transmitting unit. The signal processing module is connected to the signal receiving unit and the signal transmitting unit. When both of the signal receiving unit and the signal transmitting unit receive a high-level signal, the PCIe connector is connected to the signal processing module. When both of the signal receiving unit and the signal transmitting unit receive a low-level signal, the non-PCIe connector is connected to the signal processing module. | 03-26-2015 |
20150089114 | COMMUNICATION DEVICE - A first circuit and a second circuit perform communication using a first end point. The second circuit and an external device perform communication using a second end point. Upon receiving receive data from the external device with communication using the second end point, the second circuit gives first information indicating the second end point to the receive data. The second circuit sends the receive data given the first information to the first circuit with communication using the first end point. The first circuit interprets the second end point based on the first information given to the received receive data. | 03-26-2015 |
20150095543 | DATA BUS SYSTEM AND RECORDING APPARATUS - A data bus system includes a plurality of recording apparatuses, a transmission path, and a management apparatus. The plurality of recording apparatuses are configured to record and hold data. The transmission path is connected to the plurality of recording apparatuses by wireless communication and configured to transmit the data. The management apparatus is configured to manage the plurality of recording apparatuses and the transmission path. | 04-02-2015 |
20150106544 | CONNECTOR INTERFACE PIN MAPPING - Methods and apparatus, including computer program products, are provided for connector interface mapping. In one aspect there is provided a method. The method may include detecting, at a first device, an orientation of a data connector connectable to a data interface, the data interface having a first portion and a second portion, the first portion coupled to a single port of a first type at the first device; sending, by the first device, the detected orientation information to a second device; and receiving, at the first device including the single port, data sent by the second device to the single port. Related apparatus, systems, methods, and articles are also described. | 04-16-2015 |
20150113197 | DATA STORAGE DEVICE COMPRISING MULTIPLE STORAGE UNITS - A data storage device including a first storage unit comprising a first media of a first type and an enclosure defining an aperture, a printed circuit board assembly (“PCBA”) located below the first storage unit, wherein the PCBA comprises a bridge unit and a host interface for connecting the data storage device to a host, and a second storage unit located above the first storage unit and comprising a second media of a second type different than the first type and a communications interface configured to be connected to the bridge unit through the aperture. | 04-23-2015 |
20150127874 | PLATFORM COMMUNICATION PROTOCOL - A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state. | 05-07-2015 |
20150143016 | METHOD AND APPARATUS FOR DELIVERING MSI-X INTERRUPTS THROUGH NON-TRANSPARENT BRIDGES TO COMPUTING RESOURCES IN PCI-EXPRESS CLUSTERS - An apparatus for initialization. The apparatus includes a management I/O device controller for managing initialization of a plurality of I/O devices coupled to a PCI-Express (PCIe) fabric. The management I/O device controller is configured for receiving a request to register a target interrupt register address of a first worker computing resource, wherein the target interrupt register address is associated with a first interrupt generated by a first I/O device coupled to the PCIe fabric. A mapping module of the management I/O device controller is configured for mapping the target interrupt register address to a mapped interrupt register address of a domain in which the first I/O device resides. A translating interrupt register table includes a plurality of mapped interrupt register addresses in the domain that is associated with a plurality of target interrupt register addresses of a plurality of worker computing resources. | 05-21-2015 |
20150149683 | PCI EXPRESS TRANSACTION DESCRIPTOR - A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses. | 05-28-2015 |
20150149684 | HANDLING TWO SES SIDEBANDS USING ONE SMBUS CONTROLLER ON A BACKPLANE CONTROLLER - Present disclosure relates to a computer-implemented method for handling two SES sidebands using one SMBUS controller. The method includes one or more of following operations: (a) establishing communication between a backplane controller and a host computer through HBA, (b) receiving control commands and control data from host computer for monitoring and controlling at least one drive of first and second group of drives, (c) determining address and device number of drive to which received control commands and control data are directed, (d) forwarding control commands and control data to first or second SMBUS sideband handler based on address received, (e) controlling the blinking of the LEDs of the drive by first or second SMBUS sideband handler, (f) generating responses by the first or second SMBUS sideband handler, (g) receiving responses by the SMBUS controller, and (h) sending the responses back to the host computer within a predetermined time period. | 05-28-2015 |
20150149685 | PCI-E STANDARD SELECTION SETTING SYSTEM AND MICROSERVER - A peripheral component interface-express (PCI-E) standard selection setting system and microserver are disclosed, in which a selection controller selects an arrangement setting in storage elements to arrange the PCI-E control chip, whereby each of the second PCI-E standard ports is or is not arranged as an upstream PCI-E standard port, so that a single PCI-E standard control chip may arrange one of the multitude of PCI-E standard ports as an upstream PCI-E standard port, so that the upstream PCI-E standard port may have a data transmission with one of the multitude of system on chips (SOCs) connected with the PCI-E standard control chip. | 05-28-2015 |
20150293872 | DUAL SERIAL/PARALLEL INTERFACE DEVICES AND SWITCHING COMPONENTS - Systems, methods, and devices for communicating with a serial/parallel interface are described herein. In an aspect, a wireless device includes a transceiver configured to output a plurality of transmission paths, and an antenna configured to output a signal corresponding to at least one of the transmission paths. The wireless device further includes a wireless switching component including a radio-frequency switch configured to selectively connect the antenna to one of the transmission paths, a plurality of signal pins, a serial interface including a plurality of serial inputs electrically coupled to at least one pin of the plurality of signal pins, a parallel interface including a plurality of parallel inputs electrically coupled to at least one pin of the plurality of signal pins, a decoder, and a level shifter configured to control the radio-frequency switch, the at least one pin electrically coupled to both a serial input and a parallel input. | 10-15-2015 |
20150293875 | USB HUBS WITH GALVANIC ISOLATION - A universal serial bus (USB) hub includes a USB AFE circuit module, a hub core and an isolator circuit module interposed between the USB AFE circuit module and the hub core. Data communications between the hub core and the first USB AFE circuit module pass through the isolator circuit module. A method for communicating through a universal serial bus hub includes providing a USB AFE circuit module, providing a hub core, providing an isolator circuit module interposed between the USB AFE circuit module and the hub core, and directing communication from the USB AFE circuit module to the hub core through the isolator circuit module. | 10-15-2015 |
20150301966 | SHARING MESSAGE-SIGNALED INTERRUPTS BETWEEN PERIPHERAL COMPONENT INTERCONNECT (PCI) I/O DEVICES - A PCI function, such as a device driver, may request that additional MSI resources be allocated to an I/O device coupled to a PCI Host Bridge (PHB). However, there may not be any unallocated MSI resource remaining in the PHB. Instead, a hypervisor may request to borrow MSI resources assigned to other PCI functions in the system. For example, the PCI function requesting the additional MSI resources may ask for a certain number of MSI resources for a certain period of time e.g., a lease. The hypervisor then determines which of the other PCI functions (referred to as a loaning PCI functions) are willing to lend or loan their MSI resources. Once the MSI resources available for lease are known, the hypervisor informs the requesting PCI function of these resources which, in turn, binds the additional MSI resources to the I/O device. | 10-22-2015 |
20150301967 | SHARING MESSAGE-SIGNALED INTERRUPTS BETWEEN PERIPHERAL COMPONENT INTERCONNECT (PCI) I/O DEVICES - A PCI function, such as a device driver, may request that additional MSI resources be allocated to an I/O device coupled to a PCI Host Bridge (PHB). However, there may not be any unallocated MSI resource remaining in the PHB. Instead, a hypervisor may request to borrow MSI resources assigned to other PCI functions in the system. For example, the PCI function requesting the additional MSI resources may ask for a certain number of MSI resources for a certain period of time—e.g., a lease. The hypervisor then determines which of the other PCI functions (referred to as a loaning PCI functions) are willing to lend or loan their MSI resources. Once the MSI resources available for lease are known, the hypervisor informs the requesting PCI function of these resources which, in turn, binds the additional MSI resources to the I/O device. | 10-22-2015 |
20150301969 | VERIFYING RUNTIME SWITCH-OVER BETWEEN MULTIPLE I/O PROTOCOLS ON SHARED I/O CONNECTION - A verification environment enables verification of runtime switch-over—i.e., a switch-over without restarting the device under test—between multiple I/O protocols that share a same physical interface. The device under test can be a switch unit having multiple logical protocol processing units and a logical protocol multiplexor. The verification environment includes a switch-over detector which monitors the state of the device under test, and a switch-over controller that controls the switch-over sequence by pausing and re-starting traffic on all or specific protocol drivers of the verification environment. | 10-22-2015 |
20150301976 | Bus interface unit and operating method therefor - A bus interface unit for exchanging data via a bus system includes at least one bus control unit for connection to the bus system, having a control unit that is configured to output data received via the bus control unit from the bus system, and/or data derived therefrom, to an external unit, and/or to output data obtained from an external unit, and/or data derived therefrom, via the bus control unit to the bus system. | 10-22-2015 |
20150301978 | ELECTRICAL NODE FOR DAISY-CHAIN BUSES WITH SERIAL DATA TRANSMISSION AND CONCURRENT TRANSMISSION OF ELECTRIC ENERGY - Electrical node ( | 10-22-2015 |
20150309951 | POWER HANDLING IN A SCALABLE STORAGE SYSTEM - Systems, methods, apparatuses, and software for data storage systems are provided herein. In one example, a data storage assembly is provided. The data storage assembly includes a plurality of storage drives each comprising a PCIe host interface and solid state storage media, with each of the storage drives configured to store and retrieve data responsive to storage operations received over an associated PCIe host interface. The data storage assembly includes a PCIe switch circuit coupled to the PCIe host interfaces of the storage drives and configured to receive the storage operations issued by one or more host systems over a shared PCIe interface and transfer the storage operations for delivery to the storage drives over selected ones of the PCIe host interfaces. The data storage assembly includes holdup circuitry configured to provide power to at least the storage drives after input power is lost to the data storage assembly. | 10-29-2015 |
20150309952 | STATISTICAL POWER HANDLING IN A SCALABLE STORAGE SYSTEM - Systems, methods, apparatuses, and software for data storage systems are provided herein. In one example, a data storage assembly is provided that includes a plurality of storage drives each comprising a PCIe host interface and solid state storage media. The data storage assembly includes a PCIe switch circuit coupled to the PCIe host interfaces of the storage drives and configured to receive storage operations issued by one or more host systems over a shared PCIe interface and transfer the storage operations for delivery to the storage drives over selected ones of the PCIe host interfaces. The data storage assembly includes a control processor configured to monitor usage statistics of the storage drives, and power control circuitry configured to selectively remove the power from ones of the storage drives based at least on the usage statistics of the storage drives. | 10-29-2015 |
20150324318 | BUS PROTOCOL COMPATIBLE DEVICE AND METHOD THEREFOR - A bus protocol compatible device includes an encoder having an input for receiving a local clock signal, and an output, a multiplexer having a first input for receiving a reference clock signal, a second input coupled to said output of said encoder, a control input for receiving a select signal, and an output, and a driver having an input coupled to said output of said multiplexer, and an output for coupling to a bus protocol link. | 11-12-2015 |
20150331826 | SWITCHLESS USB C-CONNECTOR HUB - A USB hub integrated circuit device, comprising USB hub logic comprising a plurality USB ports, wherein at least one port comprises a pair of bi-directional transmission channels, wherein for the at least one port two physical layers are provided in parallel, each physical layer being associated with one bidirectional transmission channel, wherein the USB hub logic is further configured to select one of said physical layers for each port depending on a logic condition. | 11-19-2015 |
20150347348 | SMART CONNECTOR FOR ELECTRONIC COMPONENTS - A cable connector has an integrated computer-based controller. The integrated computer-based controller is configured to receive signals from the electronic component, and to scale the signals into a format compatible with a system controller, as well as to receive signals from the system controller, and to scale the signals into a format compatible with the electronic component. | 12-03-2015 |
20150356050 | Interface Emulator using FIFOs - An interface emulator for an IC is disclosed. An interface emulator includes a first first-in, first-out memory (FIFO) and a second FIFO. The first FIFO is coupled to receive data from an access port and a second FIFO coupled to receive data from at least one functional unit in the IC. The access port may be coupled to a device that is external to the IC. The external device may write information into the first FIFO, and this information may subsequently be read by a functional unit in the IC. Similarly, the functional unit may write information into the second FIFO, with the external device subsequently reading the information. Information may be written into the FIFOs in accordance with a predefined protocol. Thus, a particular type of interface may be emulated even though the physical connection and supporting circuitry for that interface is not otherwise implemented in the IC. | 12-10-2015 |
20150356051 | MODULARIZED COMMUNICATION DEVICE - A modularized intermediate communication device for a sensor network includes multiple electronic modules assembled in a stack and configured to communicate with one another. Each of the stackable electronic modules includes a housing including first and second stacking portions mechanically complementary to each other. Each module further includes a first inter-module communication connector arranged on the first stacking portion, a second inter-module communication connector arranged on the second stacking portion, and a communication device electrically connected to the first and second inter-module communication connectors and communicating with a matching electronic module using at least one communication protocol. | 12-10-2015 |
20150363349 | LINK LAYER TO PHYSICAL LAYER (PHY) SERIAL INTERFACE - A link layer to physical layer (PHY) serial interface is disclosed. In one aspect, a system on a chip (SoC) integrated circuit (IC) includes a link layer circuit, and a remote IC includes a Universal Serial Bus (USB) PHY circuit. A bus having four or fewer wires connects the two ICs. A link bridge communicates with the link layer circuit and serializes USB Transceiver Macrocell Interface (UTMI) signaling received from the link layer circuit as high speed (HS) USB messages for transmission to the remote IC. The link bridge also receives HS messages from the USB PHY circuit on the remote IC. The link bridge deserializes the HS messages to extract UTMI signaling and passes the extracted UTMI signaling to the link layer circuit. | 12-17-2015 |
20150370742 | FRONT END TRAFFIC HANDLING IN MODULAR SWITCHED FABRIC BASED DATA STORAGE SYSTEMS - Systems, methods, apparatuses, and software for data storage systems are provided herein. In one example, a data storage system is provided that includes storage drives each comprising a PCIe interface, and configured to store data and retrieve the data stored on associated storage media responsive to data transactions received over a switched PCIe fabric. The data storage system includes processors configured to each manage only an associated subset of the storage drives over the switched PCIe fabric. A first processor is configured to identify first data packets received over a network interface associated with the first processor within a network buffer of the first processor as comprising a storage operation associated with at least one of the plurality of storage drives managed by a second processor, and responsively transfer the first data packets into a network buffer of the second processor. | 12-24-2015 |
20150370747 | USB CONTROLLERS COUPLED TO USB PORTS - Examples related to the universal serial bus (USB) protocol are provided. In one example, a computer or other device includes USB controllers according to at least two different protocols. A first of the USB controllers is coupled to communicate directly with one or more USB ports. A second of the USB controllers is coupled to communicate with one or more USB ports by way of a USB hub. | 12-24-2015 |
20150378957 | EMPLOYING MULTIPLE I2C DEVICES BEHIND A MICROCONTROLLER IN A DETACHABLE PLATFORM - Methods and apparatus relating to employing multiple I2C (Interface to Communicate) devices behind a microcontroller in a detachable platform are described. In an embodiment, first logic receives a first message via a serial single ended (such as an Interface to Communicate (I2C)) bus. The first logic generates a second message to be transmitted to second logic in response to a determination that the first message is not directed to an address space assigned to the first logic. The second message includes information from the first message. Other embodiments are also disclosed. | 12-31-2015 |
20160004652 | Computer System and A Computer Device - A computer system is provided. The computer system includes a hub board, a common bus, and a plurality of Sibling boards. The hub board has an I/O controller hub, which includes a main communication chipset. The plurality of Sibling boards is coupled to the hub board by the common bus. Each of the Sibling boards includes a memory and at least one CPU. The memory is operative to host a Sibling operating system. The CPU is coupled to the memory. The Southbridge type chipset which resides in the hub board is shared amongst the plurality of Sibling boards. At least one of the plurality of Sibling boards functions as a master processing unit of the system. Sibling boards offer processing flexibility through the means of how they are configured in the system. | 01-07-2016 |
20160004658 | USB DEVICE AND METHOD FOR PROCESSING DATA BY USB DEVICE - A universal serial bus device receives a data packet from a host. The universal serial bus device includes a first virtual device, a second virtual device and a data-assigning device. The data-assigning device performs a determination operation, including: transmitting data corresponding to the a first logical address to the first virtual device, when the first logical address is the same as an address of the first virtual device wherein the data corresponding to the first logical address and the first logical address are recorded in the data packet; transmitting data corresponding to the a second logical address to the first virtual device, when the first logical address is the same as an address of the first virtual device wherein the data corresponding to the second logical address and the second logical address are recorded in the data packet. | 01-07-2016 |
20160011999 | APPARATUS FOR INTER-CONNECTION AND MULTI-SCREEN INTERACTIVE COMMUNICATION, SYSTEM AND METHOD EMPLOYING THE SAME | 01-14-2016 |
20160021099 | DATA SECURITY - In one embodiment, a method is provided that may include one or more operations. One of these operations may include, in response, at least in part, to a request to store input data in storage, encrypting, based least in part upon one or more keys, the input data to generate output data to store in the storage. The one or more keys may be authorized by a remote authority. Alternatively or additionally, another of these operations may include, in response, at least in part, to a request to retrieve the input data from the storage, decrypting, based at least in part upon the at least one key, the output data. Many modifications, variations, and alternatives are possible without departing from this embodiment. | 01-21-2016 |
20160026589 | Adaptive Circuit Board Assembly and Flexible PCI Express Bus - A system and method for adaptive bus configuration operable to respond to hardware changes and other configuration changes is disclosed. In an embodiment, the computing system includes a circuit assembly having at least one processing resource coupled to a respective set of bus traces, at least one peripheral device socket coupled to a respective set of bus traces, and a bus switch coupled to the bus traces of the processing resource and the bus traces of the peripheral device. The bus switch implements a set of connections between the bus traces of the processing resource and the bus traces of the peripheral device sockets according to an instruction. The instruction may specify an allocation of peripheral device sockets to processing resources based on the number of installed processing resources so that no peripheral device is connected to a bus without an attached processor. | 01-28-2016 |
20160026595 | SYSTEM AND METHOD FOR CONTROLLING BUS-NETWORKED DEVICES VIA AN OPEN FIELD BUS - A method for controlling bus-networked devices is useable in a system comprising a gateway, an open field bus electrically connected to the gateway, and a pluggable connection cable electrically connecting the gateway to a plurality of bus subscribers. The gateway starts a configuration mode to control a bus subscriber and to generate a new target configuration including the bus subscriber. According to an initial target configuration, the bus subscriber is not expected by the gateway. | 01-28-2016 |
20160026596 | SYSTEMS, DEVICES, AND METHODS FOR SELECTIVE COMMUNICATION THROUGH AN ELECTRICAL CONNECTOR - Electrical systems and related methods are disclosed. An electrical system comprises an electronic device configured to communicate through an electrical connector using one of a plurality of different communication protocols responsive to receiving an indication of the one of the plurality of different communication protocols through the electrical connector from a another electronic device. The other electronic device is configured to provide a protocol indicator that indicates a particular communication protocol with which the other electronic device is configured to communicate through an electrical connector of the electronic device. A method includes receiving a protocol indicator from another electronic device through an electrical connector. The protocol indicator indicates a communication protocol. The method also includes communicating with the other electronic device through the electrical connector using the indicated communication protocol. | 01-28-2016 |
20160034025 | Physical Layer for Peripheral Interconnect with Reduced Power and Area - An integrated circuit (IC) implements an industry standard-defined peripheral interconnect to connect to another integrated circuit or component in a system. The industry standard specification includes a software interface that is well-defined and implemented by various software in the system, and thus is desirable to retain. However, the physical interconnect in the systems employing the integrated circuit may be short, and thus the elaborate physical layer definition may consume more integrated circuit area and power than is otherwise desirable in the IC. The IC may implement a simpler and more power-efficient physical layer, reducing both power consumption and semiconductor substrate area consumption, in some embodiments. | 02-04-2016 |
20160034415 | METHOD AND SYSTEM MAINTAINING QUALITY OF SERVICE (QOS) OF HOST COMMANDS IN MULTI-PORT, MULTI-FUNCTION PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) DEVICES - A method maintaining a fixed QoS for a PCIe device accessed by multiple hosts includes; receiving commands from the hosts in PCIe function queues of the PCIe device, fetching the commands from the PCIe function command queues, queuing the commands according to a command arbitration policy established for the PCIe device, storing the queued commands in an internal memory of the PCIe device, retrieving the queued commands from the internal memory in a sequence determined by applying a calculated QoS to at least one of the queued commands, and allocating PCIe device resources based on payload information corresponding to each one of the retrieved commands. | 02-04-2016 |
20160041604 | SEMICONDUCTOR DEVICE FOR REDUCING POWER CONSUMPTION IN LOW POWER MODE AND SYSTEM INCLUDING SAME - A semiconductor device can reduce power consumption in a low power mode and includes a first input/output circuit configured to detect a first entry signal transiting at a first time and output a detection signal indicating an entry into a power saving mode according to a result of the detection. A second input/output circuit is configured to receive a second entry signal transiting at a second time earlier than the first time, and a control circuit is configured to block power supplied to the second input/output circuit in response to the detection signal indicating the entry. | 02-11-2016 |
20160041936 | INTERFACE CIRCUIT AND PACKET TRANSMISSION METHOD THEREOF - A packet transmission method includes packaging a plurality of data in the form of a payload; storing information on whether the plurality of data are packaged in a header, the payload or a CRC area including a transmission error check code of the plurality of data; combining the header, the payload, and the CRC area with each other to generate a transaction layer packet; and outputting a packet including the transaction layer packet. | 02-11-2016 |
20160041937 | NETWORK INTERFACE CARD COUPLED TO DRIVE CARRIER - An example drive carrier in accordance with an aspect of the present disclosure may he mounted within a drive bay of a computing device. A network interface card may be coupled to the drive carrier, and the network interface card may be communicatively coupled to the computing device. | 02-11-2016 |
20160041938 | INFORMATION PROCESSING APPARATUS, STORAGE SYSTEM, AND COMPUTER-READABLE NON-TRANSITORY STORAGE MEDIUM STORING COMMUNICATION CONTROL PROGRAM - An information processing apparatus includes: an interface unit that communicates with another device through a plurality of physical links; a setting unit that determines a value of a setting parameter for setting a signal transmission characteristic for each of the plurality of physical links by performing a negotiation with the other device and that outputs a plurality of determined values of the setting parameter, each of the plurality of determined values corresponding to one of the plurality of physical links; and a judgment unit that judges whether each of the plurality of determined values is correct or not by judging whether or not a difference between a maximum value and a minimum value among the plurality of determined values falls within a predetermined range. | 02-11-2016 |
20160048475 | Method, Apparatus, and System for Configuring High-Speed Serial Bus Parameter - A method for configuring a high-speed serial bus parameter, including sending an application signal from a transmit end of a high-speed serial bus to a receive end of the high-speed serial bus, searching a parameter configuration table for a high-speed serial bus parameter that matches all of a frequency of the application signal, a loss of the application signal on the high-speed serial bus, and a material type of a wiring board of the high-speed serial bus, and configuring the high-speed serial bus according to the high-speed serial bus parameter. According to the method, a problem involving configuration of a high-speed serial bus parameter when a transmitted signal is compensated may be solved. | 02-18-2016 |
20160054786 | LOW POWER CONNECTION DETECT METHOD AND SYSTEM FOR USB CHARGING - A USB hub has a USB hub controller, and an embedded controller, a USB port connector and associated port power control device and a controllable bypass switch providing a supply voltage to the USB port connector when the embedded controller enables it, a controllable voltage supply regulator unit providing a first output voltage which can be turned off and supplied to the port power control device, and a programmable current monitor circuit with a current sensor providing a second supply voltage to the monitor circuit, wherein during a low power mode, the USB hub controller and any port power control device are turned off and the monitor circuit is configured to provide the second supply voltage through the sensor and bypass switch to the USB connector and detects a current when a USB device is plugged into the USB port connector and wakes up the embedded controller. | 02-25-2016 |
20160055117 | Dual Mode USB and Serial Console Port - An information handling system includes a service connector operable to receive an RS-232 signal and a USB signal. The service connector is a USB type connector. The information handling system also includes a voltage converter operable to convert the RS-232 signal from a first voltage level to a first serial signal at a second voltage level when a signal received by the service connector is the RS-232 signal, a protocol converter operable to convert the USB signal to a second serial signal at the second voltage level when the signal received by the service connector is the USB signal, and a UART operable to receive the first serial signal and the second serial signal. | 02-25-2016 |
20160055119 | Disaggregated Server Architecture for Data Centers - A system comprising a unified interconnect network, a plurality of process memory modules, and a plurality of processor modules configured to share access to the memory modules via the unified interconnect network. Also disclosed is a method comprising communicating data between a plurality of processor modules and a plurality of shared resource pools via a unified interconnect network, wherein the communications comprise a protocol that is common to all resource pools, and wherein each resource pool comprises a plurality of resource modules each configured to perform a common function. Also disclosed is an apparatus comprising a network interface controller (NIC) module configured to receive data from a plurality of processor modules via a unified interconnect network, and provide core network connectivity to the processor modules. | 02-25-2016 |
20160062424 | METHODS AND APPARATUS TO EFFECT HOT RESET FOR AN ON DIE NON-ROOT PORT INTEGRATED DEVICE - In an embodiment, a processor includes at least one core to initiate a hot reset, and a peripheral device that is coupled to a root complex fabric via through the root port via an peripheral component interconnect express to on-chip system fabric (PCIE to OSF) bridge. The processor also includes a power control unit that includes reset logic to decouple the peripheral device from the root complex fabric responsive to initiation of the hot reset. After the peripheral device is decoupled from the root complex fabric, the reset logic is to assert a reset of the peripheral device while a first core of the at least one core is in operation. Other embodiments are described and claimed. | 03-03-2016 |
20160062932 | Universal Serial Bus Emulation Layer - A universal serial bus stack may use an emulation layer to grant a non-universal serial bus device access to universal serial bus drivers and applications. The universal serial bus stack may exchange a device communication at an emulation layer. The universal serial bus stack may translate between a universal serial bus communication and the device communication at the emulation layer, and then may exchange the universal serial bus communication at a universal serial bus client interface. | 03-03-2016 |
20160062940 | Safely Sharing USB Devices During PCI Passthrough Operation - Examples of the disclosure safely share universal service bus (USB) devices with peripheral component interconnect (PCI) passthrough, and share devices in the USB hierarchy. An in-use counter is maintained for the USB bus and/or for USB hubs. The in-use counter is checked and adjusted when a VM or entity claims and/or unclaims a device. For example, when a PCI passthrough of a USB host controller device is requested, the global in-use counter is checked to determine whether to grant the request. When a VM or entity requests to claim a USB hub, the in-use counter is checked to determine whether to grant the request. The in-use counter indicates whether any USB device attached has been claimed and/or whether the USB host controller device has been claimed by a PCI passthrough operation. | 03-03-2016 |
20160070671 | COMMUNICATING A MESSAGE REQUEST TRANSACTION TO A LOGICAL DEVICE - A general input/output communication port implements a communication stack that includes a physical layer, a data link layer and a transaction layer. The transaction layer includes assembling a packet header for a message request transaction to one or more logical devices. The packet header includes a format field to indicate the length of the packet header and to further specify whether the packet header includes a data payload, a subset of a type field to indicate the packet header relates to the message request transaction and a message field. The message field includes a message to implement the message request transaction. The message includes at least one message that is selected from a group of messages. The group of messages to include a message to unlock a logical device, a message to reset a logical device, a message to indicate a correctable error condition, a message to indicate an uncorrectable error condition, a message to indicate a fatal error condition, a message to report a bad request packet, a message to indicate power management and a message to emulate an interrupt signal. | 03-10-2016 |
20160077738 | Fibre Channel Storage Array Methods for Port Management - Methods and systems for processing failover operations in a storage array configured for Fibre Channel communication are provided. One example method includes executing a primary process in user space of a controller of the storage array. The primary process is configured to process request commands from one or more initiators and has access to a volume manager for serving data input/output (I/O) requests. The primary process has a connection to a port of storage array when in operation. The method further executes a secondary process in the user space of the controller to process request commands from one or more of the initiators. The secondary process is not provided access to the volume manger and is provided access to data for responding to non-I/O requests. The secondary process is not provided a connection to the port when the primary process is in operation. The second process is configured to detect that the primary process has entered a state of non-operation, and in response performing a port grab of the port by the secondary process. The method further includes causing a replay of in-progress commands that were being executed by the primary process before entering the state of non-operation and deleting the in-progress commands. The method continues to execute the secondary process while the primary process is in the non-operation state. | 03-17-2016 |
20160077982 | METHOD FOR SETTING UNIVERSAL SERIAL BUS (USB) INTERFACE OF ELECTRONIC DEVICE, AND ELECTRONIC DEVICE - Certain aspects of the disclosure relates to a method for operating an electronic device. A control device detects a Universal Serial Bus (USB) interface being connected to the electronic device, where the USB interface has a plurality of virtual ports. Then the control device receives one or more descriptors through the USB interface, each descriptor corresponding to a function of the electronic device. Then the control device matches each descriptor corresponding to each function with one driver file corresponding to each function, and after the matching is successful, determines a virtual function device corresponding to execution of each function. In response to receiving an operating command for executing one function, the control device sends the operating command to the corresponding virtual function device to the function to be executed through a corresponding driver interface, such that the corresponding virtual function device is operated on the electronic device. | 03-17-2016 |
20160077992 | USB extension for lossy channel - Methods and systems for operating a USB extension over a lossy channel. The USB extension includes at least a state machine and packet loss inference mechanism. The state machine includes a first state in which the USB extension receives a USB data packet from a standard USB host, a second state, unsupported by the USB Specification, in which the packet loss inference mechanism may indicate the state machine to switch back to its first state, and a third state in which the USB extension switches the state machine back to its first state. | 03-17-2016 |
20160077994 | INTERFACE CIRCUIT - According to one embodiment, a first module is responsible for protocol control in compliance with a first interface standard. A second module is provided separately from the first module and is responsible for protocol control in compliance with a second interface standard. A third module is responsible for a physical layer shared between the first interface standard and the second interface standard. | 03-17-2016 |
20160078054 | File System Extension System and Method - A file system extension (FSE) system and method that permits an on-disk-structure (ODS) incorporating spatially diverse data (SDD) to be stored on a daisy-chain of multiple SATA disk drive storage elements (DSE) that are coupled together with one or more pass-thru disk drive controllers (PTDDC) is disclosed. The PTDDC chain appears as a single logical disk drive to a host computer system (HCS) via a host bus adapter (HBA) or pass-thru input (PTI) port. The PTDDC chain may appear to the HCS as virtual disk storage (VDS) that is larger than the actual physical disk storage (PDS) contained within the DSEs. The PTDDC chain is configured to map the SDD to portions of the DSE that are actually present within the VDS and thus allow critical portions of the ODS to reside on the PTDDC chain with transparent access by an operating system running on the HCS. | 03-17-2016 |
20160085448 | ENHANCED INTERFACE TO FIRMWARE OPERATING IN A SOLID STATE DRIVE - An embodiment of the invention includes a storage subsystem having a storage central processing unit (SCPU) operable to receive and send a command to a host, the command requiring data computation, a compute engine coupled to the SCPU, and a bank of memory devices coupled to the SCPU and the compute engine and configured to store data required by the commands, wherein the SCPU or the compute engine are operable to perform computation of the data and to further invoke an appropriate Flash Translation Layer (FTL) application based on workload. | 03-24-2016 |
20160085458 | SYSTEM AND METHOD FOR CONTROLLING VARIOUS ASPECTS OF PCIe DIRECT ATTACHED NONVOLATILE MEMORY STORAGE SUBSYSTEMS - Techniques for controlling PCIe direct attached non-volatile memory storage system are disclosed. In one particular embodiment, the techniques may be realized as a method including monitoring a temperature of a memory attached via the PCIe interface, determining whether an operation implemented on the attached memory has caused the temperature of the memory to exceed a preset threshold, and controlling an I/O rate of the attached memory based on the determination such that the I/O rate is greater than zero. | 03-24-2016 |
20160085703 | DISCOVERY MECHANISMS FOR UNIVERSAL SERIAL BUS (USB) PROTOCOL ADAPTATION LAYER - A WiFi serial bus (WSB) attribute for use in Wi-Fi Alliance defined point-to-point (P2P) discovery mechanism includes a plurality of fields disposed in the frame. The WiFi serial bus attribute is arranged to provide information in the plurality of fields to support connectivity decisions for a USB device in a point-to-point network using a WSB protocol. The WSB attribute includes WSB architectural element information and information associated with a USB device behind a USB protocol adaptation layer (PAL). | 03-24-2016 |
20160085705 | SHARED PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) END POINT SYSTEM WITH A PCIe SWITCH AND METHOD FOR INITIALIZING THE SAME - A method of accessing a server address space of a shared PCIe end point system includes programming a primary address translation table with a server address of a server address space, setting up a direct memory access (DMA) to access a primary port memory map, the primary port memory map correlating with addresses in the primary address translation table, and re-directing the direct memory accesses to the primary port memory map to the server address space according to the primary address translation table. | 03-24-2016 |
20160085710 | Reconfigurable Modular Computing Device - A configurable computing device comprising a housing, a printed circuit board disposed within the housing, a first microcontroller and a second microcontroller each coupled to the PCB, wherein the first microcontroller and the second microcontroller are in electrical signal communication with each other, a computer-on-module (COM) coupled to the PCB, wherein the COM is in electrical signal communication with the first microcontroller and the second microcontroller, and one or more peripheral modules coupled to the PCB, wherein, the peripheral modules are each in electrical signal communication with the first microcontroller and wherein, the peripheral modules are each in electrical signal communication with the COM via the second microcontroller. | 03-24-2016 |
20160085722 | DATA PACKET PROCESSING - Proposed is an action machine for processing packet data in a network processor. The action machine comprises: first and second data storage units adapted to store data for processing; and a processing unit adapted to process data from the first and second data storage units. The first storage unit is adapted to be accessed by the processing unit and a unit external to the action machine, and the second storage unit is adapted to only be accessed by the processing unit. | 03-24-2016 |
20160092126 | Shared Virtualized Local Storage - An embedded processing unit (eCPU) processes an input/output (I/O) request from a host using a virtual storage controller. The eCPU associates a virtual network interface with a host. The virtual storage controller uses a first transport protocol. The eCPU receives an I/O request directed at a storage device from the virtual storage controller. The eCPU determines a second transport protocol used by the storage device, and converts the I/O request from a format according to the first transport protocol to a format according to the second transport protocol. The eCPU transmits the I/O request to the storage device using the second transport protocol. | 03-31-2016 |
20160098358 | PCI DEVICE, INTERFACE SYSTEM INCLUDING THE SAME, AND COMPUTING SYSTEM INCLUDING THE SAME - A peripheral component interconnect (PCI) device includes a first memory which includes a plurality of page buffers, a base address register which includes a plurality of base addresses, and a first address translation unit which translates each of the plurality of base addresses to a corresponding one of a plurality of virtual addresses. A map table includes a plurality of map table entries each accessed in correspondence to each of the plurality of virtual addresses, and maps each of the plurality of virtual addresses onto a physical address of physical addresses of the plurality of page buffers. The first address translation unit translates each of the plurality of virtual addresses to a corresponding one of the physical addresses using the map table. | 04-07-2016 |
20160098372 | METHOD TO USE PCIe DEVICE RESOURCES BY USING UNMODIFIED PCIe DEVICE DRIVERS ON CPUs IN A PCIe FABRIC WITH COMMODITY PCI SWITCHES - A method for accessing a device in a primary peripheral component interconnect express (PCIe) domain from a secondary PCIe domain includes determining which one or more virtual functions of the device in the primary PCIe domain are to be made available to the secondary PCIe domain. A virtual function driver is installed in the primary PCIe domain associated with the one or more virtual functions. Information corresponding to the one or more virtual functions is provided to the secondary PCIe domain. A virtual function driver associated with the one or more virtual functions is installed in the secondary PCIe domain from the information. The virtual function driver in the secondary PCIe domain has same properties as the virtual function driver in the primary PCIe domain. The device in the primary PCIe domain is accessed from the virtual function driver in the secondary PCIe domain. | 04-07-2016 |
20160098374 | METHOD FOR A DETERMINISTIC SELECTION OF A SENSOR FROM A PLURALITY OF SENSORS - A method for a deterministic selection of a sensor from a plurality of sensors, having a control unit and multiple sensors connected to the control unit by means of a three-wire bus, wherein the sensors are connected to the three-wire bus through at least two lines in parallel to one another, and a protocol frame in conformity with the SENT specification is used between the control unit and the sensors for a data exchange, and a particular sensor is selected within the protocol frame by the control unit through the predefined duration of a selection signal, wherein the duration of the selection signal is determined by the interval between a first falling signal edge and a second falling signal edge. | 04-07-2016 |
20160103480 | METHODS AND APPARATUS FOR MANAGING POWER WITH AN INTER-PROCESSOR COMMUNICATION LINK BETWEEN INDEPENDENTLY OPERABLE PROCESSORS - Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling. | 04-14-2016 |
20160103689 | METHODS AND APPARATUS FOR RUNNING AND BOOTING AN INTER-PROCESSOR COMMUNICATION LINK BETWEEN INDEPENDENTLY OPERABLE PROCESSORS - Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a “shared” memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling. | 04-14-2016 |
20160110104 | APPARATUS AND METHOD FOR ROUTING INFORMATION IN A NON-VOLATILE MEMORY-BASED STORAGE DEVICE - Various systems, methods, apparatuses, and computer-readable media for accessing a storage device are described. In certain example embodiments, an active/active fault-tolerant storage device comprising two or more controllers may be implemented. In one aspect, each controller may have two or more processing entities for distributing the processing of the I/O requests. In one embodiment, the configuration of the components, modules and the controller board may be arranged in a manner to enhance heat dissipation, reduce power consumption, spread the power and work load, and reduce latency. In one embodiment, each controller may be coupled to the non-volatile memory (NVM) blades comprising the non-volatile memory (NVM) storage medium. In one example implementation, a standardized protocol, such as the Peripheral Component Interconnect Express protocol may be used for communicating amongst the various components of the controller and also the NVM storage medium. | 04-21-2016 |
20160110290 | DATA CACHE AND METHOD FOR DATA CACHING - Embodiments of the present invention disclose a data cache and a system, a computer program product and a method for data caching, wherein a data cache includes: at least one memory bank adapted for enabling high-speed data access; and at least one converter configured to receive a first instruction for a data access operation, and convert the first instruction to a second instruction compatible with the at least one memory bank so as to perform the data access operation, the first instruction being transmitted from a high-speed bus interface of a host device to the data cache. | 04-21-2016 |
20160117281 | INFORMATION SYSTEM CAPABLE OF EXPANDING DRIVE AND BUS NUMBER ALLOCATION METHOD OF THE INFORMATION SYSTEM - In a storage device applying PCIe to a back-end network connection, in order to be capable of allocating bus numbers and making a PCIe switch expanded afterwards usable, it is necessary to once reset all PCIe switches. To dissolve this necessity, PCIe switches of the back-end network of the storage device are connected in series, a range of continuous bus numbers that are managed and stored in bus number management table is allocated for the back-end network connection, and when expanding the PCIe switch, the bus numbers are allocated in ascending order from a minimum value of the allocatable bus numbers to each of a link between the PCIe switches and to a virtual PCI bus within the PCIe switch, and the bus numbers are allocated in descending order from a maximum value of the allocatable bus numbers to the link between the PCIe switch and a drive. | 04-28-2016 |
20160124754 | Virtual Function Boot In Single-Root and Multi-Root I/O Virtualization Environments - A method for virtual function boot in a system including a single-root I/O virtualization (SR-IOV) enabled server includes loading a PF driver of the PF of a storage adapter onto the server utilizing the virtual machine manager of the server; creating a plurality of virtual functions utilizing the PF driver, detecting each of the virtual functions on an interconnection bus, maintaining a boot list associated with the plurality of virtual functions, querying the storage adapter for the boot list utilizing a VMBIOS associated with the plurality of VMs, presenting the detected boot list to a VM boot manager of the VMM, and booting each of the plurality of virtual machines utilizing each of the virtual functions, wherein each VF of the plurality of VFs is assigned to a VM of the plurality of VMs via an interconnect passthrough between the VMM and the plurality of VMs. | 05-05-2016 |
20160124893 | INFORMATION PROCESSING APPARATUS AND METHOD OF CONTROLLING THE SAME - Provided is an information processing apparatus including a processor and a PCI node connected to the processor via a first PCI bus, the processor obtaining a class code and a subclass code from the PCI node connected to the first PCI bus, determining whether or not the PCI node is a bridge based on the obtained class code and subclass code, searching for a PCI node connected to the PCI node via a second PCI bus based on having determined that the PCI node is a bridge, and searching for another PCI node connected to the first PCI bus based on having determined that the PCI node is not a bridge. | 05-05-2016 |
20160140069 | PCI EXPRESS TUNNELING OVER A MULTI-PROTOCOL I/O INTERCONNECT - Described are embodiments of methods, apparatuses, and systems for PCIe tunneling across a multi-protocol I/O interconnect of a computer apparatus. A method for PCIe tunneling across the multi-protocol I/O interconnect may include establishing a first communication path between ports of a switching fabric of a multi-protocol I/O interconnect of a computer apparatus in response to a peripheral component interconnect express (PCIe) device being connected to the computer apparatus, and establishing a second communication path between the switching fabric and a PCIe controller. The method may further include routing, by the multi-protocol I/O interconnect, PCIe protocol packets of the PCIe device from the PCIe device to the PCIe controller over the first and second communication paths. Other embodiments may be described and claimed. | 05-19-2016 |
20160140074 | MEMORY MAPPING METHOD AND MEMORY MAPPING SYSTEM - A memory mapping method for coupling a plurality of servers with a PCI express bus is disclosed. The method comprises: configuring an extended memory address on a management host having a memory address; mapping the extended memory address of the management host corresponding to each of the servers to memory addresses of each of the servers respectively by a plurality of non-transparent bridges of the PCI express bus; configuring an extended memory address on each of the servers; and mapping the extended memory address of each of the servers to the memory address and the extended memory address of the management host by the non-transparent bridges, the extended memory address of each of the servers corresponding to the servers and the management host. | 05-19-2016 |
20160147693 | MULTICASTING COMPUTER BUS SWITCH - There is disclosed apparatus and methods of multicasting in a shared address space. A shared memory address space may include two or more multicast portions. Each multicast portion may be associated with a respective end point and with at least one other multicast portion. Data units may be transmitted to at least some of the end points via memory-mapped I/O into the shared memory address space. When a destination address of a data unit is in a first multicast portion associated with a first end point, the data unit may be transmitted to the first end point, revised to specify a destination address in a second multicast portion associated with the first multicast portion, and transmitted to a second end point associated with the second multicast portion. | 05-26-2016 |
20160147696 | CONFIGURING A COMMUNICATION INTERCONNECT FOR ELECTRONIC DEVICES - Logic determines a connection arrangement for communication between electronic devices over a communication interconnect. A first group of signals of the communication interconnect is enabled in response to determining that a first connection arrangement is to be used. A second, different group of signals of the communication interconnect is enabled in response to determining that a second, different connection arrangement is to be used. | 05-26-2016 |
20160147701 | BRIDGE FOR BUS-POWERED PERIPHERAL DEVICE POWER MANAGEMENT - Technologies are described herein for power management in a peripheral device. A bridge is coupled to a communication link that provides power. The bridge determines an available power from the communication link. The bridge informs a peripheral device coupled to the bridge of the available power. | 05-26-2016 |
20160154591 | SYSTEMS AND METHODS FOR OPTIMIZING DATA STORAGE AMONG A PLURALITY OF STORAGE DRIVES | 06-02-2016 |
20160154757 | INTERFACE SWITCH APPARATUS | 06-02-2016 |
20160154766 | PROVIDING I2C BUS OVER ETHERNET | 06-02-2016 |
20160162427 | INTEGRATED SYSTEMS WITH UNIVERSAL SERIAL BUS 2.0 AND EMBEDDED UNIVERSAL SERIAL BUS 2 CONNECTIVITY - An integrated circuit is provided. The integrated circuit includes a mapping circuit configured to determine a state associated with a first universal series bus (USB) communication mode based on one or both of a signal level on a first data line and a signal level on a second data line. The integrated circuit also includes a line state converter circuit configured to generate a line state associated with a second USB communication mode based on the determined state and based on one or both of the signal level on the first data line and the signal level on the second data line. | 06-09-2016 |
20160162428 | Operation of a Switch in Linear Mode - Examples disclose a computing device comprising a switch to operate in a linear mode according to a threshold. The switch operates in the linear mode based on a detection of increase of current drawn by a device. Upon reaching the threshold, the switch is to exit the linear mode. | 06-09-2016 |
20160162430 | INTEGRATED CIRCUITS WITH UNIVERSAL SERIAL BUS 2.0 AND EMBEDDED UNIVERSAL SERIAL BUS 2 CONNECTIVITY - An integrated circuit is provided. The integrated circuit includes a communication-mode determination circuitry configured to detect a signal level at one or both of a first data line and a second data line and to determine whether a communication mode of the first data line and the second data line is a first universal series bus (USB) communication mode or a second USB communication mode. The integrated circuit also includes a first transceiver circuitry configured to operate in one of multiple modes, based on the communication mode determined. The integrated circuit also includes a second transceiver circuitry configured to operate in one of multiple modes, based on the communication mode determined. A maximum signal level of the first USB communication mode is greater than a maximum signal level of the second USB communication mode. | 06-09-2016 |
20160162431 | ELECTRONIC DEVICE WITH MULTIPLE INTERFACES - An electronic device with multiple interfaces includes at least two interfaces, a memory, and a controller. The memory stores a first operation setting parameter group corresponding to a first device and a second operation setting parameter group corresponding to a second device. The controller is electrically connected to the first interface, the second interface, and the memory. When a first interface of the at least two interface is electrically connected to the first device, the controller loads the first operation setting parameter group and utilizes a first transmission protocol and the first operation setting parameter group to communicate the first device; and when a second interface of the at least two interface is electrically connected to the second device, the controller loads the second operation setting parameter group and utilizes a second transmission protocol and the second operation setting parameter group to communicate the second device. | 06-09-2016 |
20160162433 | IO-LINK ADAPTER - An IO-Link adapter ( | 06-09-2016 |
20160170473 | CONTROL CIRCUIT FOR CONTROLLING POWER OF USB | 06-16-2016 |
20160170923 | AGGREGATE BASEBOARD MANAGEMENT CONTROLLER (BMC) CONTROLLER | 06-16-2016 |
20160170928 | PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIe) CARD HAVING MULTIPLE PCIe CONNECTORS | 06-16-2016 |
20160170929 | DATA TRANSMISSION USING PCIe PROTOCOL VIA USB PORT | 06-16-2016 |
20160170931 | CONSOLE SERVER WITH USB CONSOLE PORT | 06-16-2016 |
20160170932 | Cost-Effective Device Interface For Data Input And Output | 06-16-2016 |
20160179565 | Device Remote Access Method, Thin Client, and Virtual Machine | 06-23-2016 |
20160179727 | PERIPHERAL COMPONENT INTERFACE (PCI) SYSTEM AND METHOD FOR EXPANDING PCI NODES IN AN INFORMATION HANDLING SYSTEM | 06-23-2016 |
20160179732 | CONNECTION DEVICE | 06-23-2016 |
20160179741 | DYNAMIC LANE MANAGEMENT FOR INTERFERENCE MITIGATION | 06-23-2016 |
20160179743 | SYSTEMS, METHODS, AND DEVICES FOR MEDIA AGNOSTIC USB PACKET SCHEDULING | 06-23-2016 |
20160179745 | COMPUTER SYSTEM FOR VIRTUALIZING I/O DEVICE AND METHOD OF OPERATING THE SAME AND HUB DEVICE | 06-23-2016 |
20160180115 | TECHNIQUES FOR DETECTING FALSE POSITIVE RETURN-ORIENTED PROGRAMMING ATTACKS | 06-23-2016 |
20160181866 | REMOTE PROTECTION AND SWITCHING DEVICE FOR ELECTRICAL SYSTEMS | 06-23-2016 |
20160182398 | SYSTEM ON A CHIP COMPRISING MULTIPLE COMPUTE SUB-SYSTEMS | 06-23-2016 |
20160187958 | TECHNIQUES FOR MANAGING POWER AND PERFORMANCE FOR A NETWORKING DEVICE - Various embodiments are generally directed to an apparatus, method and other techniques to create an idle period for a processing unit and a switching circuit by buffering one or more packets in a buffer for one or more input/output (I/O) ports. Embodiments may include causing the processing unit and/or the switching circuit to operate in a lower power state during the idle period and causing the processing unit and/or the switching circuit to exit the lower power state by communicating one or more out-of-band messages to the processing unit and/or the switching circuit. | 06-30-2016 |
20160187963 | POWER DELIVERY INFORMATION OVER DATA INTERFACE - It is inter alia disclosed to transmit a signal between a communication pin ( | 06-30-2016 |
20160188216 | Hard Disk and Management Method - A hard disk includes a manager, a managed component, a management interface a network interface, and a system on chip (SOC). The management interface receives an external management command. The manager performs an operation according to the received external management command on a managed component corresponding to the received external management command, and returns an operation result through the management interface to the cloud server. The network interface receive an external read/write operation command sent by the cloud server. The SOC performs a read/write operation according to the received external read/write operation command and returns a read/write operation result through the network interface. | 06-30-2016 |
20160188514 | CIRCUIT AND METHOD FOR INTERFACING UNIVERSAL SERIAL BUS - USB controllers, systems and methods are presented to conserve power in a USB controller, in which a transmitter transmits data to a line of a connected USB cable according to a transmit data signal, and a pull down circuit selectively sinks current from a supply node of the transmitter when the transmit data signal is in a first state, refrains from sinking the first current from the supply node when the transmit data signal is in a different second state. | 06-30-2016 |
20160195910 | FAREWELL RESET AND RESTART METHOD FOR COEXISTENCE OF LEGACY AND NEXT GENERATION DEVICES OVER A SHARED MULTI-MODE BUS | 07-07-2016 |
20160202743 | Hub Having Complex Power Converters | 07-14-2016 |
20160202921 | STORAGE DEVICE, DATA STORAGE DEVICE INCLUDING THE SAME, AND OPERATION METHOD THEREOF | 07-14-2016 |
20160203094 | APPARATUS AND METHOD FOR BUFFERED INTERCONNECT | 07-14-2016 |
20160253277 | SHARED PCI INTERRUPT LINE MANAGEMENT | 09-01-2016 |
20160253280 | USB HUB AND CONTROL METHOD OF USB HUB | 09-01-2016 |
20160378153 | SENSOR DEVICE AND METHOD - In embodiments, apparatuses, methods and storage media (transitory and non-transitory) are described that include a plurality of sensor connectors to removably receive a corresponding plurality of sensors and a power management module to selectively provide power to sensor connector power terminals in response to power management signals from a sensor control module. Other embodiments may be described and/or claimed. | 12-29-2016 |
20160378155 | CHARGE PROCESS IN USB SETUP - A power delivery capability is described. In an embodiment, a device is described, comprising: a processor; and a storage comprising a set of instructions; wherein the set of instructions causes the processor to: Detect a power supplying device by universal serial bus based communication; Use a power delivery communication of the universal serial bus to read a capability of the power supplying device; Based on the capability, set a level of a power supply voltage different to universal serial bus voltages in case different voltages are supported by the power supplying device; Based on the capability, set a level of a power supply current in a linear current limiting mode in case the different voltages are not supported by the power supplying device. In other embodiments, a device and a method are discussed. | 12-29-2016 |
20160378706 | METHOD AND SYSTEM FOR AGGREGATION-FRIENDLY ADDRESS ASSIGNMENT TO PCIE DEVICES - A peripheral component interconnect express PCI-e network system having a processor for (a) assigning addresses to the PCI-e topology tree, comprising: traversing, at a given level and in a breadth direction, down-link couplings to an interconnection; ascertaining, at the level, which of the down-link couplings are connected to nodes; assigning, at the level, addresses to nodes of ascertained down-link coupling having nodes; and (b) propagating, a level, comprising: traversing, at the level and in a depth direction, down-link couplings to the interconnection of the PCI-e network, ascertaining, at the level, which of the downlink couplings are coupled to other interconnections in the depth direction, consecutively proceeding in the depth direction, to a next level of the down-link coupling of a next interconnection; and alternatively repeating (a) and (b) until the nodes are assigned addresses within the PCI-e tree topology network. | 12-29-2016 |
20160378708 | PCI Express to PCI Express based Low Latency Interconnect Scheme for Clustering Systems - PCI Express is a Bus or I/O interconnect standard for use inside the computer or embedded system enabling faster data transfers to and from peripheral devices. The standard is still evolving but has achieved a degree of stability such that other applications can be implemented using PCIE as basis. A PCIE based interconnect scheme to enable switching and inter-connection between multiple PCIE enabled systems each having its own PCIE root complex, such that the scalability of PCIE architecture can be applied to enable data transport between connected systems to form a cluster of systems, is proposed. These connected systems can be any computing, control, storage or embedded system. The scalability of the interconnect will allow the cluster to grow the bandwidth between the systems as they become necessary without changing to a different connection architecture. | 12-29-2016 |
20170235494 | METHODS FOR MANAGING ARRAY LUNS IN A STORAGE NETWORK WITH A MULTI-PATH CONFIGURATION AND DEVICES THEREOF | 08-17-2017 |
20170235519 | Device Management Method, Device, and Device Management Controller | 08-17-2017 |
20170235638 | SYSTEM-ON-CHIP FOR SPECULATIVE EXECUTION EVENT COUNTER CHECKPOINTING AND RESTORING | 08-17-2017 |
20170235695 | RING PROTOCOL FOR LOW LATENCY INTERCONNECT SWITCH | 08-17-2017 |
20170235700 | PERIPHERAL COMPONENT | 08-17-2017 |
20170235701 | SERIAL SIDEBAND SIGNALING LINK | 08-17-2017 |
20180024960 | TECHNIQUES TO SUPPORT MULTIPLE INTERCONNECT PROTOCOLS FOR A COMMON SET OF INTERCONNECT CONNECTORS | 01-25-2018 |
20220138134 | SCHEDULING TECHNIQUES FOR ISOCHRONOUS IN TRAFFIC IN A USB EXTENSION ENVIRONMENT - In some embodiments, a system for communicating USB information via a non-USB extension medium is provided. The system comprises an upstream facing port device (UFP device) and a downstream facing port device (DFP device). The DFP device is configured to receive, from the UFP device via the extension medium, a first ACK IN packet addressed to a first endpoint and a second ACK IN packet addressed to a second endpoint after receiving the first ACK IN packet. In response to detecting that the USB-compliant connection is available, the DFP device compares a bInterval value for the first endpoint to a bInterval value for the second endpoint; and in response to determining that the bInterval value for the second endpoint is smaller than the bInterval value for the first endpoint, the DFP device transmits a synthetic ACK IN packet to the second endpoint based on the second ACK IN packet. | 05-05-2022 |