| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 710312000 | Multiple bridges | 18 |
| 20080270669 | TRANSLATION OF DATA TO/FROM STORAGE DEVICES BASED ON A REDUNDANCY CONFIGURATION AND HOST INTERFACE TYPE - A system comprises a bridge translator adapted to be coupled to a plurality of storage devices and to a host. The bridge translator translates data from the host to a format compatible with the redundantly configured storage devices. A controller coupled to the bridge translator configures the bridge translator to translate the data based on a redundancy configuration of the storage devices and based on a type of interface to the host. | 10-30-2008 |
| 20090006706 | Structure for Hub for Supporting High Capacity Memory Subsystem - A design structure is provided for a hub for use in a high-capacity memory subsystem in which memory modules arranged in one or more clusters, each attached to a respective hub which in turn is attached to a memory controller. Within a cluster, data is interleaved so that each data access command accesses all modules of the cluster. The hub communicates with the memory modules at a lower bus frequency, but the distributing of data among multiple modules enables the cluster to maintain the composite data rate of the memory-controller-to-hub bus. Preferably, the memory system employs buffered memory chips having dual-mode operation, one of which supports a cluster configuration in which data is interleaved and the communications buses operate at reduced bus width and/or reduced bus frequency to match the level of interleaving | 01-01-2009 |
| 20090265501 | COMPUTER SYSTEM AND METHOD FOR MONITORING AN ACCESS PATH - Provided is a computer system including I/O devices coupled to PCI switches coupled via interfaces of a plurality of servers, and a management block for managing configurations of the PCI switches. The management block is configured to: set, to the PCI switch, a first access path including a virtual bridge coupling the interface of a first server and a virtual switch, and a virtual bridge coupling the I/O device and the virtual switch; set, to the PCI switch, a second access path including a virtual bridge coupling the interface of a second server of the plurality of servers and a virtual switch, and a virtual bridge coupling the I/O device used by the first server and the virtual switch; disable mapping of the second access path between the I/O device and the virtual bridge; and instruct the second server to make access to the I/O device. | 10-22-2009 |
| 20090292854 | USE OF BOND OPTION TO ALTERNATE BETWEEN PCI CONFIGURATION SPACE - An adaptor for adapting one of a first device complying with a first bus, and a second device complying with a second bus to a Peripheral Component Interconnect Express (PCIe) interface. The adaptor comprises a first bridge for interconnecting the first bus with the PCIe bus, a second bridge for interconnecting the second bus with the PCIe bus, and a PCIe core coupled to the two bridges. A bond option signal is coupled to the two bridges and the PCIe core for enabling one of the two bridges, and one of the two bridges is configured by the PCIe core. | 11-26-2009 |
| 20100138583 | REMOTE ACCESS GATEWAY FOR SEMICONDUCTOR PROCESSING EQUIPMENT - An apparatus for providing an interface for semiconductor processing equipment is disclosed. In some embodiments, an apparatus for providing an interface for semiconductor processing equipment having an interface card includes a display logic subsystem to provide an interface to one or more devices such as video and information displays, light pens, keyboards, computer mice, and warning light networks and alarms via a data and control bus; a bridge to provide access to the data and control bus; and a local computer subsystem coupled to the bridge and the display logic subsystem, wherein the local computer subsystem provides access to one or more remote devices. | 06-03-2010 |
| 20110107002 | SAS Expander-Based SAS/SATA Bridging - Described herein is an improved mechanism for bridging between SAS and SATA drives based upon existing SAS expanders in a SAS domain. In particular, a bridge capable of translating between SAS and SATA protocols is embedded in or coupled to an expander. When a SAS initiator request is received at the expander, the expander can route the request, based on a routing table, either directly to a destination SAS device or to the bridge for necessary translation before it is transmitted to a destination SATA drive. The routing table includes corresponding relationships between all SAS addresses and Phys through which those SAS and SATA devices are attached to the expander. SATA devices can be virtualized in the expander through a few assigned addresses in the routing table in a SAS discovery process. | 05-05-2011 |
| 20110161546 | COMPUTER SYSTEM WITH BRIDGE - A computer system includes a central processing unit (CPU), a north bridge, a south bridge, a bridge and a slot. The north bridge is electrically connected to the CPU. The bridge is electrically connected to the north bridge and the south bridge, and the connector is connected to the bridge. The bridge generates a first data and a second data according to the data packages transmitted from the north bridge and adjusts the output bandwidth of the first data and the second data according to a channel control signal. The south bridge receives or transfers the first data via the bridge so as to communicate with the north bridge. The slot is electrically connected to the bridge and receives or transfers the second data via the bridge so as to communicate with the north bridge. | 06-30-2011 |
| 20110296074 | MEMORY MAPPED INPUT/OUTPUT BUS ADDRESS RANGE TRANSLATION FOR VIRTUAL BRIDGES - In an embodiment, a south chip comprises a first virtual bridge connected to a shared egress port and a second virtual bridge also connected to the shared egress port. The first virtual bridge receives a first secondary bus identifier, a first subordinate bus identifier, and a first MMIO bus address range from a first north chip. The second virtual bridge receives a second secondary bus identifier, a second subordinate bus identifier, and a second MMIO bus address range from a second north chip. The first virtual bridge stores the first secondary bus identifier, the first subordinate bus identifier, and the first MMIO bus address range. The second virtual bridge stores the second secondary bus identifier, the second subordinate bus identifier, and the second MMIO bus address range. The first north chip and the second north chip are connected to the south chip via respective first and second point-to-point connections. | 12-01-2011 |
| 20120017023 | COMPUTING MODULE WITH SERIAL DATA CONNECTIVITY - A computing module includes an interface to asynchronously, serially exchange parallel system bus data with one or more other modules of a computer system that includes the computing module. The computing module can asynchronously, serially transfer first parallel bus data to another module of the computer system, and can asynchronously, serially receive second parallel bus data from another module of the computer system. | 01-19-2012 |
| 20120023281 | Single-chip microcomputer - A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced. | 01-26-2012 |
| 20120131254 | SWITCH APPARATUS FOR SWITCHING DISPLAY, KEYBOARD, AND MOUSE - A switch apparatus includes first to third video graphics array (VGA) interfaces, first to sixth universal serial bus (USB) interfaces, a single-pole double-throw (SPDT) switch, and first to eighteenth electronic switches. The first VGA interface is connected to the second and third VGA interfaces through the electronic switches. The first USB interface is connected the second and third USB interfaces through the electronic switches. The fourth USB interface is connected to the fifth and sixth USB interfaces through the electronic switches. The SPDT switch is used to control the first VGA interface to be selectively connected to the second or third VGA interface, and control the first USB interface to be selectively connected to the second or third USB interface, and control the fourth USB interface to be selectively connected to the fifth or sixth USB interface. | 05-24-2012 |
| 20120198119 | High Current Multi-Port USB Hub - A high-current Multi-Port USB hub has a microcontroller that selectively switches the hub between low current synchronizing state and high current charging state. During charging state in excess of two Amps of current can be provided to each device connected to the hub. Each USB port circuit includes a power FET to selectively provide current to the USB port according to the state of the hub. Current sensors on each of the USB ports detects an amount of current being drawn by a device connected to the USB port. Each USB port is provided with indicators to indicate the charged state of the device connected to that port. The charge state of the device is also provided to the microcontroller which provides a summary status indication of the set of devices connected to the USB hub. | 08-02-2012 |
| 20120324139 | WIRELESS COMMUNICATION FOR POINT-TO-POINT SERIAL LINK PROTOCOL - A wireless communication link, such as a PCIe endpoint-to-endpoint communication link, can be configured as a link in the communication protocol hierarchy, such that the wireless communication link is assigned its own bus identifier, and communications are routed to the wireless communication segment by a switch module based on the bus number. The wireless communication link can also be associated with the same link as a downstream wireless communication module. By employing the wireless communication segment as a link features of the communication protocol can be conventionally implemented by the host and downstream devices. | 12-20-2012 |
| 20130042045 | METHOD AND APPARATUS TO FACILITATE SYSTEM TO SYSTEM PROTOCOL EXCHANGE IN BACK TO BACK NON-TRANSPARENT BRIDGES - A dual host system and method with back to back non-transparent bridges and a proxy packet generating mechanism. The proxy packet generating mechanism enables the hosts to send interrupt generating packets to each other. | 02-14-2013 |
| 20140089551 | COMMUNICATION OF DEVICE PRESENCE BETWEEN BOOT ROUTINE AND OPERATING SYSTEM - Various embodiments are directed to creating multiple device blocks associated with hardware devices, arranging the device blocks in an order indicative of positions of the hardware devices in a hierarchy of buses and bridges, and enabling access to the multiple device blocks from an operating system. An apparatus comprises a processor circuit and storage storing instructions operative on the processor circuit to create a device table comprising multiple device blocks, each device block corresponding to one of multiple hardware devices accessible to the processor circuit, the device blocks arranged in an order indicative of relative positions of the hardware devices in a hierarchy of buses and at least one bridge device; enable access to the device table by an operating system; and execute a second sequence of instructions of the operating system operative on the processor circuit to access the device table. Other embodiments are described and claimed herein. | 03-27-2014 |
| 20140207994 | CIRCUIT ARRANGEMENT FOR UNIVERSAL CONNECTION OF A BUS PARTICIPANT TO AT LEAST ONE BUS - A circuit arrangement for connecting a bus participant to at least one bus, having an interface for connecting the bus participant to the circuit arrangement, a first bus input, and a first bus output between which the bus participant is switchable via the interface. The circuit arrangement includes a second bus input and output for connecting the bus to the circuit arrangement in a ring topology in such a way that the first bus output is connected at least indirectly to the second bus input and the second bus output is connected at least indirectly to the first bus input via the bus. The bus in the circuit arrangement can be separated to obtain a line topology and can be configured as bus-terminating at one of the bus inputs or bus outputs. A system for the functional testing of bus participants on a bus in a simulation environment is provided. | 07-24-2014 |
| 20140258583 | Providing Multiple Decode Options For A System-On-Chip (SoC) Fabric - In one embodiment, a system-on-chip (SoC) can be configured to receive a request from a master agent in a fabric coupled to the master agent, send a show command grant to the master agent responsive to selection of the request by the fabric, receive a command portion of a transaction corresponding to the request in the fabric and determine a target agent to receive the transaction based on the command portion, and thereafter send a transaction grant to the master agent for the transaction. Other embodiments are described and claimed. | 09-11-2014 |
| 20140281105 | HIGH SPEED DISK ARRAY SPIDER CABLE - Embodiments of the invention includes a plurality of connectors configured to connect a plurality of data storage host bus adaptors to a plurality of data storage device subassemblies such that at least one lane of low voltage differential signal pairs from each of the plurality of host bus adaptors is connected to each of the data storage device subassemblies. The invention improves the electrical interconnections in a data storage array such as a JBOD enclosure or data storage server. The invention minimizes the number of connectors by reducing the number of printed circuit boards, and eliminates the need to add signal repeaters to maintain signal quality. The invention also increases the cooling efficiency of the enclosure by increasing air flow by reducing the number of printed circuit boards in the data storage array. | 09-18-2014 |
