| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 708501000 |
Multiplication followed by addition
| 38 |
| 708496000 |
Compensation for finite word length
| 24 |
| 708505000 |
Addition or subtraction
| 23 |
| 708503000 |
Multiplication
| 10 |
| 708502000 |
Reciprocal
| 7 |
| 708500000 |
Evaluation of root
| 6 |
| 708504000 |
Division | 4 |
| 20090216823 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR VERIFYING FLOATING POINT DIVIDE OPERATION RESULTS - A method, system and computer program product for verifying a result of a floating point division operation are provided. The method includes: receiving a result of a floating point division operation for a dividend and a divisor; performing a comparison of a magnitude of a least significant bit (LSB) of the dividend and a magnitude of a most significant bit (MSB) of a remainder; and determining whether the result is correct based on the comparison. | 08-27-2009 |
| 20090216824 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR DETERMINING REQUIRED PRECISION IN FIXED-POINT DIVIDE OPERATIONS - A method, computer program product and a system for controlling a fixed point division operation are provided. The method includes: receiving an instruction to perform a division operation for a dividend and a divisor, the operation comprising a maximum number of iterations to produce a quotient having a maximum precision; calculating a magnitude of at least one of the dividend and the divisor; determining a quotient precision based on the magnitude; and computing a required number of iterations needed to produce the quotient precision and performing the number of iterations. | 08-27-2009 |
| 20100250639 | APPARATUS AND METHOD FOR IMPLEMENTING HARDWARE SUPPORT FOR DENORMALIZED OPERANDS FOR FLOATING-POINT DIVIDE OPERATIONS - A floating-point circuit may include a floating-point operand normalization circuit configured to receive input floating-point operands of a given floating-point divide operation, the operands comprising a dividend and a divisor, as well as a divide engine coupled to the normalization circuit. In response to determining that one or more of the input floating-point operands is a denormal number, the operand normalization circuit may be further configured to normalize the one or more of the input floating-point operands and output a normalized dividend and normalized divisor to the divide engine, and dependent upon respective numbers of leading zeros of the dividend and divisor prior to normalization, generate a value indicative of a maximum possible number of digits of a quotient (NDQ). The divide engine may be configured to iteratively generate NDQ digits of a floating-point quotient from the normalized dividend and the normalized divisor provided by the floating-point operand normalization circuit. | 09-30-2010 |
| 20130173681 | Range Check Based Lookup Tables - Mechanisms for utilizing a reduced lookup table circuit to perform an operation in a data processing device are provided. A first input value is input for selecting a subset of values from the reduced lookup table circuit. The reduced lookup table circuit stores only boundary cell values from a fully filled lookup table corresponding to the reduced lookup table circuit. The subset of values comprises only a subset of boundary cell values corresponding to the first input value. A second value is input and a comparison, by the reduced lookup table circuit, of the second value to each of the boundary cell values in the subset of boundary cell values is performed. The reduced lookup table circuit outputs an output value based on results of the comparison of the second value to each of the boundary cell values in the subset of boundary cell values. | 07-04-2013 |
| 708511000 |
Complex number format | 4 |
| 20090187616 | Method for Representing Complex Numbers in a Communication System - A method for storage for complex numbers that employs a shared exponent field is disclosed. Rather than each floating point component of an complex number having its own distinct signed mantissa and exponent fields, each component includes a distinct signed mantissa field and shares an exponent field, thereby increasing the possible size of each distinct signed mantissa field by as much as one half the number of bits formerly employed to store a single distinct exponent field. | 07-23-2009 |
| 20100138468 | Digital Signal Processor Having Instruction Set With One Or More Non-Linear Complex Functions - Methods and apparatus are provided for a digital signal processor having an instruction set with one or more non-linear complex functions. A method is provided for a processor. One or more non-linear complex software instructions are obtained from a program. The non-linear complex software instructions have at least one complex number as an input. One or more non-linear complex functions are applied from a predefined instruction set to the at least one complex number. An output is generated comprised of one complex number or two real numbers. A functional unit can implement the one or more non-linear complex functions. In one embodiment, a vector-based digital signal processor is disclosed that processes a complex vector comprised of a plurality of complex numbers. The processor can process the plurality of complex numbers in parallel. | 06-03-2010 |
| 20110004648 | COMPLEX AND HYPERCOMPLEX INCLUSIVE INTERVAL EXPRESSION EVALUATIONS WITH STABLE NUMERIC EVALUATIONS AND PRECISION EFFICACY TESTING - Improvements to optimal interval operators are developed for interval expression evaluation using arithmetic and real power operators applied to complex and hypercomplex number systems. A method for determining efficacy of numeric precision, incorporating minor changes to interval operators, provides detection of insufficient numeric evaluation precision. | 01-06-2011 |
| 20110082895 | EXPLOITATION OF TOPOLOGICAL CATEGORIZATION OF CHAOTIC AND FRACTAL FUNCTIONS INCLUDING FIELD LINE CALCULATIONS - A topological categorization method, based on inclusive intervals, provides a general method of analyzing escape topologies for discrete dynamic systems, in complex and higher dimensions, including the calculation of both potential for complex and hypercomplex and field lines for complex iterations | 04-07-2011 |
| 708510000 |
Microprocessor | 3 |
| 20080270508 | DETECTION OF POTENTIAL NEED TO USE A LARGER DATA FORMAT IN PERFORMING FLOATING POINT OPERATIONS - Detection of whether a result of a floating point operation is safe. Characteristics of the result are examined to determine whether the result is safe or potentially unsafe, as defined by the user. An instruction is provided to facilitate detection of safe or potentially unsafe results. | 10-30-2008 |
| 20080270509 | EXTRACT BIASED EXPONENT OF DECIMAL FLOATING POINT DATA - A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format. For composition and decomposition, one or more instructions may be employed, including an insert biased exponent or extract biased exponent instruction. | 10-30-2008 |
| 20110060785 | FAST FLOATING POINT RESULT FORWARDING USING NON-ARCHITECTED DATA FORMAT - A microprocessor having an instruction set architecture (ISA) that specifies at least one architected data format (ADF) for floating-point operands. The microprocessor includes a plurality of floating-point units, each comprising an arithmetic unit configured to receive non-ADF source operands and to perform a floating-point operation on the non-ADF source operands to generate a non-ADF result. The microprocessor also includes forwarding buses, configured to forward the non-ADF result generated by each arithmetic unit of the plurality of floating-point units to each of the plurality of floating-point units for selective use as one of the non-ADF source operands. | 03-10-2011 |
| 708512000 |
Logarithmic format | 3 |
| 20100030833 | APPARATUS, METHOD, AND PROGRAM FOR ARITHMETIC PROCESSING - A mantissa/exponent splitter splits an input value X=(1+X | 02-04-2010 |
| 20120166510 | METHOD FOR ENCODING FLOATING-POINT DATA, METHOD FOR DECODING FLOATING-POINT DATA, AND CORRESPONDING ENCODER AND DECODER - An algorithm for efficiently compressing floating-point data in 3D meshes is disclosed. 3D meshes are represented by topology data, geometry data and property data. Geometry data specify vertex locations and are usually represented by floating-point coordinates. While geometry data are usually compressed by quantization, prediction and entropy coding, the present invention uses no prediction. A floating-point number consists of mantissa and exponent, and normally the exponent, sign and mantissa are compressed separately. A method for encoding floating-point formatted data comprises determining if a current floating-point value was previously stored in a memory, storing the current value in the memory if it was not previously stored in the memory, and encoding it. Otherwise, if the current floating-point value was previously stored in a memory, the storage position of the value within the memory is determined and a reference pointing to the storage position is encoded. | 06-28-2012 |
| 20130339417 | RESIDUE-BASED EXPONENT FLOW CHECKING - A technique for checking an exponent calculation for an execution unit that supports floating point operations includes generating, using a residue prediction circuit, a predicted exponent residue for a result exponent of a floating point operation. The technique also includes generating, using an exponent calculation circuit, the result exponent for the floating point operation and generating, using the residue prediction circuit, a result exponent residue for the result exponent. Finally, the technique includes comparing the predicted exponent residue to the result exponent residue to determine whether the result exponent generated by the exponent calculation circuit is correct and, if not, signaling an error. | 12-19-2013 |
| 708514000 |
Matrix array | 2 |
| 20090094309 | SYSTEM AND METHOD TO IMPLEMENT A MATRIX MULTIPLY UNIT OF A BROADBAND PROCESSOR - The present invention provides a system and method for improving the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128b by 128b multiplier regardless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources. | 04-09-2009 |
| 20130073599 | HARDWARE FOR PERFORMING ARITHMETIC OPERATIONS - Hardware for performing sequences of arithmetic operations. The hardware comprises a scheduler operable to generate a schedule of instructions from a bitmap denoting whether an entry in a matrix is zero or not. An arithmetic circuit is provided which is configured to perform arithmetic operations on the matrix in accordance with the schedule. | 03-21-2013 |
| 708513000 |
Variable length or precision | 2 |
| 20080235316 | PROCESSOR WITH ADAPTIVE MULTI-SHADER - The disclosure describes an adaptive multi-shader within a processor that uses one or more high-precision arithmetic logic units (ALUs) and low-precision ALUs to process data based on the type of the data. Upon receiving a stream of data, the adaptive multi-shader first determines the type of the data. For example, the adaptive multi-shader may determine whether the data is suitable for high-precision processing or low-precision processing. The adaptive multi-shader then processes the data using the high-precision ALUs when the data is suitable for high-precision processing, and processes the data using the high-precision ALUs and the low-precision ALUs when the data is suitable for low-precision processing. The adaptive multi-shader may substantially reduce power consumption and silicon size of the processor by implementing the low-precision ALUs while maintaining the ability to process data using high-precision processing by implementing the high-precision ALUs. | 09-25-2008 |
| 20090240757 | SINGLE-PRECISION FLOATING-POINT DATA STORING METHOD AND PROCESSOR - A single-precision floating-point data storing method for use in a processor including a register, which has a size that can store double-precision floating-point data, for storing double-precision floating-point data and single-precision floating-point data comprises writing input single-precision floating-point data to the high-order half of the register, and writing all zeros to the low-order half of the register if a single-precision floating-point data process is specified. | 09-24-2009 |
| 708507000 |
Parallel | 1 |
| 20130173682 | FLOATING-POINT ERROR PROPAGATION IN DATAFLOW - A process for propagating an error in a floating-point calculation is disclosed. A floating-point error occurring from the floating-point arithmetic calculation is trapped, and a special value is generated. Information regarding the error is stored as a payload of the special value. Program operations are resumed with the special value applied to further calculations dependent on the floating-point arithmetic calculation. | 07-04-2013 |
| Entries |
| Document | Title | Date |
|---|
| 20080263120 | METHOD AND SYSTEM FOR OPTIMIZING FLOATING POINT CONVERSION BETWEEN DIFFERENT BASES - A method of streamlining floating-point conversions includes determining a source coefficient and a source exponent of an input value represented by a floating-point number in a source base; estimating an approximated target exponent (ATE) using the source coefficient and the source exponent, in the event the source coefficient has a non-zero value; determining whether the ATE exceeds a maximum exponent so as to result an overflow, and outputting a predefined overflow value in the event of an overflow; determining whether the ATE exceeds a minimum exponent so as to result an underflow, and outputting a predefined underflow value in the event of an underflow; and in the event the ATE does not result in either an overflow or underflow, converting the input value to an output value represented by a converted coefficient, a converted base and the exponent of the output value. | 10-23-2008 |
| 20080270506 | CONVERT SIGNIFICAND OF DECIMAL FLOATING POINT DATA FROM PACKED DECIMAL FORMAT - A decimal floating point finite number in a decimal floating point format is composed from the number in a different format. A decimal floating point format includes fields to hold information relating to the sign, exponent and significand of the decimal floating point finite number. Other decimal floating point data, including infinities and NaNs (not a number), are also composed. Decimal floating point data are also decomposed from the decimal floating point format to a different format. For composition and decomposition, one or more instructions may be employed, including one or more convert instructions. | 10-30-2008 |
| 20080307028 | GENERATION OF TEST CASES WITH RANGE CONSTRAINTS FOR FLOATING POINT ADD AND SUBTRACT INSTRUCTIONS - Methods, apparatus and systems are disclosed for the generation of range-constrained test cases for verification of designs of arithmetic floating point units. Given three ranges of floating point numbers Rx, Ry, Rz, a floating point operation (op), and a rounding-mode (round), three floating point numbers | 12-11-2008 |
| 20090083358 | EMULATION OF A FIXED POINT OPERATION USING A CORRESPONDING FLOATING POINT OPERATION - A computer emulates a fixed-point operation that is normally performed on fixed-point operands, by use of a floating-point operation that is normally performed on floating-point operands. Several embodiments emulate a fixed-point operation by: expanding at least one fixed-point operand into a floating-point representation (also called “floating-point equivalent”), performing, on the floating-point equivalent, a floating-point operation that corresponds to the fixed-point operation, and reducing a floating-point result into a fixed-point result. The just-described fixed-point result may have the same representation as the fixed-point operand(s) and/or any user-specified fixed-point representation, depending on the embodiment. Also the operands and the result may be either real or complex, and may be either scalar or vector. The above-described emulation may be performed either with an interpreter or with a compiler, depending on the embodiment. A conventional interpreter for an object-oriented language (such as MATLAB version 6) may be extended to perform the emulation. | 03-26-2009 |
| 20090100121 | APPARATUS AND METHOD FOR LOW COMPLEXITY COMBINATORIAL CODING OF SIGNALS - During operation of an encoder, a signal vector (x) is received. A first multi-precision operand (Ψ′ | 04-16-2009 |
| 20100023573 | EFFICIENT FORCING OF CORNER CASES IN A FLOATING POINT ROUNDER - The forcing of the result or output of a rounder portion of a floating point processor occurs only in a fraction non-increment data path within the rounder and not in the fraction increment data path within the rounder. The fraction forcing is active on a corner case such as a disabled overflow exception. A disabled overflow exception may be detected by inspecting the normalized exponent. If a disabled overflow exception is detected, the round mode is selected to execute only in the non-increment data path thereby preventing the fraction increment data path from being selected. | 01-28-2010 |
| 20100063987 | SUPPORTING MULTIPLE FORMATS IN A FLOATING POINT PROCESSOR - In a binary floating point processor, the exponents of each of the various types of operands are recoded into an internal format, by biasing the exponents with the minimum exponent value of the result precision (“Emin”), i.e., the recoded value of the exponent is the represented value of the exponent minus Emin. Emin depends only on the result precision of the instruction that is currently being executed in the binary floating point processor. The exponent computations are then performed in this new format. The underflow check for all result precisions is a check against zero and overflow checks are performed against a positive number that depends on the result precision. The exponent values are in a 2's complement representation, so the underflow check simply becomes a check of the sign bit. | 03-11-2010 |
| 20100198901 | Managing Floating Point Variables in Constraint Satisfaction Problems - Systems and methods for managing floating point variables are described in the present disclosure. According to one example, an embodiment of a method includes analyzing a constraint on a floating point variable in a system that supports both floating point variables and integer variables. The constraint is designed to have the ability to numerically limit the domain of the floating point variable. The method also includes determining whether or not the floating point variable can be handled as an integer variable and converting the floating point variable to a pseudo integer variable when it is determined that the floating point variable can be handled as an integer variable. This conversion of the floating point variable to a pseudo integer variable allows the domain of the floating point variable to be processed as an integer domain. | 08-05-2010 |
| 20110078225 | Extended-Precision Integer Arithmetic and Logical Instructions - The invention set forth herein describes a mechanism for efficiently performing extended precision operations on multi-word source operands. Corresponding data words of the source operands are processed together via each instruction of a cascading sequence of instructions. State information generated when each instruction is processed is stored in condition code flags. The state information is optionally used in the processing of subsequent instructions in the sequence and/or accumulated with previously set state information. | 03-31-2011 |
| 20120191766 | Multiplication of Complex Numbers Represented in Floating Point - A multiplier circuit that operates on a novel complex data format where the real and imaginary parts of the source and result operands are represented by single precision floating point numbers. The invention provides direct support for complex numbers in floating point representation, thus reducing the number of instructions and processor cycles with improved performance. | 07-26-2012 |
| 20120203813 | GENERATION OF TEST CASES WITH RANGE CONSTRAINTS FOR FLOATING POINT ADD AND SUBTRACT INSTRUCTIONS - Methods, apparatus and systems are disclosed for the generation of range-constrained test cases for verification of designs of arithmetic floating point units. Given three ranges of floating point numbers Rx, Ry, Rz, a floating point operation (op), and a rounding-mode (round), three floating point numbers | 08-09-2012 |
| 20130191432 | DYNAMIC RANGE ADJUSTING FLOATING POINT EXECUTION UNIT - A floating point execution unit is capable of selectively repurposing a subset of the significand bits in a floating point value for use as additional exponent bits to dynamically provide an extended range for floating point calculations. A significand field of a floating point operand may be considered to include first and second portions, with the first portion capable of being concatenated with the second portion to represent the significand for a floating point value, or, to provide an extended range, being concatenated with the exponent field of the floating point operand to represent the exponent for a floating point value. | 07-25-2013 |
| 20130246496 | FLOATING-POINT VECTOR NORMALISATION - When performing vector normalisation upon floating point values, an approximate reciprocal value generating instruction is used to generate an approximate reciprocal value with a mantissa of one and an exponent given by a bitwise inversion of the exponent field of the input floating point number. A modified number of multiplication instruction is used which performs a multiplication giving the standard IEEE 754 results other than when a signed zero is multiplied by a signed infinity which results a signed predetermined substitute value, such as 2. The normalisation operation may be performed by calculating a scaling value in dependence upon the vector floating point value using the approximate reciprocal value generating instruction. Each of the input components may then be scaled using the modify multiplication instruction to generate a scaled vector floating point value formed of a plurality of scaled components. The magnitude of the scaled vector floating point value can then be calculated and each of the individual scaled components divided by this magnitude to generate a normalised vector floating point value. The scaling value may be set to 2, where C is an integer value selected such that the sum of the squares of the plurality of scale components is less than a predetermined limit value. | 09-19-2013 |
| 20130262546 | ARITHMETIC CIRCUIT AND ARITHMETIC METHOD - An arithmetic circuit includes a storage circuit configured to store a decimal floating point number in an encoded state, a detection circuit configured to detect a pattern of an arrangement of zeros from a bit pattern of the decimal floating point number by decoding the decimal floating point number stored in the storage circuit, and a leading-zero-count circuit configured to generate data indicative of a number of consecutive zeros starting from a most significant bit or from a least significant bit in a significand of the decimal floating point number in response to a detection result obtained by the detection circuit. | 10-03-2013 |
| 20140019506 | METHOD AND APPARATUS FOR DECIMAL FLOATING-POINT DATA LOGICAL EXTRACTION - Embodiments of systems, apparatuses, and methods for performing BIDSplit instructions in a computer processor are described. In some embodiments, the execution of a BIDSplit instruction tests the encoding of a binary-integer decimal source value and extracts a sign, exponent, and/or significand into a destination. | 01-16-2014 |
| 20140032624 | INSTRUCTION AND LOGIC FOR PERFORMING A DOT-PRODUCT OPERATION - Method, apparatus, and program means for performing a dot-product operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location a result value equal to a dot-product of at least two operands. | 01-30-2014 |
| 20140059104 | ARITHMETIC CIRCUIT FOR CALCULATING CORRECTION VALUE - An arithmetic circuit for calculating a correction value for a result of an arithmetic operation that is an addition or subtraction performed with respect to a first floating-point number and a second floating-point number smaller than the first floating-point number. The arithmetic circuit includes a generation unit configured to generate a significand of a normalized correction value for the result of the arithmetic operation and an exponent of the normalized correction value based on the sign, the significand, and the exponent of the second floating-point number when a difference between a result of subtracting the leading zero count of the significand of the first floating-point number from the corresponding exponent and a result of subtracting a leading zero count of the significand of the second floating-point number from the corresponding exponent is larger than or equal to a second predetermined value. | 02-27-2014 |
| 20140074902 | NUMBER REPRESENTATION AND MEMORY SYSTEM FOR ARITHMETIC - A method, device and system for representing numbers in a computer including storing a floating-point number M in a computer memory; representing the floating-point number M as an interval with lower and upper bounds A and B when it is accessed by using at least two floating-point numbers in the memory; and then representing M as an interval with lower and upper bounds A and B when it is used in a calculation by using at least three floating-point numbers in the memory. Calculations are performed using the interval and when the data is written back to the memory it may be stored as an interval if the size of the interval is significant, i.e. larger than a first threshold value. A warning regarding the suspect accuracy of any data stored as an interval may be issued if the interval is too large, i.e. larger than a second threshold value. | 03-13-2014 |
| 20140280424 | METHOD AND DEVICE FOR HANDLING DATA VALUES - A floating point value can represent a number or something that is not a number (NaN). A floating point value that is a NaN having data field that stores information, such as a propagation count that indicates the number of times a NaN value has been propagated through instructions. A NaN evaluation instruction can determine whether one or more operands is a NaN operand of a particular type, and if so can generate a result that is a NaN of a different type. An exception can be generated based upon the NaN of the different type being provided as a resultant | 09-18-2014 |
| 20140280425 | METHOD AND DEVICE FOR GENERATING AN EXCEPTION - A floating point value can represent a number or something that is not a number (NaN). A floating point value that is a NaN having data field that stores information, such as a propagation count that indicates the number of times a NaN value has been propagated through instructions. A NaN evaluation instruction can determine whether one or more operands is a NaN operand of a particular type, and if so can generate a result that is a NaN of a different type. An exception can be generated based upon the NaN of the different type being provided as a resultant | 09-18-2014 |
| 20140379772 | PROCESSOR AND CONTROL METHOD OF PROCESSOR - A processor includes: an exponent generating unit that generates an exponent part of a coefficient represented by a floating point number format based on a first part of received input data, the coefficient being obtained when an exponential function is decomposed into a series operation and the coefficient for the series operation; a storage unit that stores a mantissa part of the coefficient; a constant generating unit that reads constant data corresponding to a second part of the input data from the storage unit; and a selecting unit that selects and outputs the constant data from the constant generating unit when an instruction to be executed is a coefficient calculation instruction for calculation of the coefficient of the exponential function. | 12-25-2014 |
| 20150074162 | Performing Arithmetic Operations Using Both Large and Small Floating Point Values - Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands. | 03-12-2015 |
| 20150095393 | METHOD AND DEVICE FOR GENERATING FLOATING-POINT VALUES - A floating-point value can represent a number or something that is not a number (NaN). A floating-point value that is a NaN includes a portion that stores information about the source operands of the instruction. | 04-02-2015 |
| 20150149521 | FAST NORMALIZATION IN A MIXED PRECISION FLOATING-POINT UNIT - A hardware circuit for returning single precision denormal results to double precision. A hardware circuit component configured to count leading zeros of an unrounded single precision denormal result. A hardware circuit component configured to pre-compute a first exponent and a second exponent for the unrounded single precision denormal result. A hardware circuit component configured to perform a second normalization of the rounded single precision denormal result back to architected format. | 05-28-2015 |
| 20150149522 | FAST NORMALIZATION IN A MIXED PRECISION FLOATING-POINT UNIT - A hardware circuit for returning single precision denormal results to double precision. A hardware circuit component configured to count leading zeros of an unrounded single precision denormal result. A hardware circuit component configured to pre-compute a first exponent and a second exponent for the unrounded single precision denormal result. A hardware circuit component configured to perform a second normalization of the rounded single precision denormal result back to architected format. | 05-28-2015 |
| 20150293747 | PROCESSING FIXED AND VARIABLE LENGTH NUMBERS - Embodiments of a processor are disclosed for performing arithmetic operations on variable-length and fixed-length machine independent numbers. The processor may include a floating point unit, and a logic circuit. The number unit may be configured to receive an operation, and first and second operands. Each of the first and second operands may include a sign byte, and multiple mantissa bytes, and may be processed in response to a determination that the operands are fixed-length numbers. The logic circuit may be further configured to perform the received operation on the processed first and second operands. | 10-15-2015 |
| 20150378676 | IDEMPOTENT REPRESENTATION OF NUMBERS IN EXTENSIBLE LANGUAGES - Technologies and implementations for representing floating-point numbers in an extensible language are generally disclosed. | 12-31-2015 |
| 20160124710 | DATA PROCESSING APPARATUS AND METHOD USING PROGRAMMABLE SIGNIFICANCE DATA - An apparatus may have processing circuitry to perform one or more arithmetic operations for generating a result value based on at least one operand. For at least one arithmetic operation, the processing circuitry is responsive to programmable significance data indicative of a target significance for the result value, to generate the result value having the target significance. For example, this allows programmers to set a significance boundary for the arithmetic operation so that it is not necessary for the processing circuitry to calculate bit values having a significance outside the specified boundary, enabling a performance improvement. | 05-05-2016 |
| 20160124712 | EXPONENT MONITORING - A processing apparatus | 05-05-2016 |
| 20160139881 | ACCURACY-CONSERVING FLOATING-POINT VALUE AGGREGATION - A method for enhancing an accuracy of a sum of a plurality of floating-point numbers. The method receives a floating-point number and generates a plurality of provisional numbers with a value of zero. The method further generates a surjective map from the values of an exponent and a sign of a mantissa to the provisional numbers in the plurality of provisional numbers. The method further maps a value of the exponent and the sign of the mantissa to a first provisional number with the surjective map. The method further generates a test number from the first provisional number and if the test number exceeds a limit, modifies a second provisional number by using at least part of the test number. The method further equates the first provisional number to the test number if the test number does not exceed the limit. The method further sums the plurality of provisional numbers. | 05-19-2016 |
| 20160188293 | Digital Signal Processor - A processor configured to: receive, at a floating-point-input-terminal, an input-block of data comprising a plurality of floating-point numbers each floating-point number comprising a mantissa and an exponent; determine an input-scale-factor based on a previous-input-block-exponent-value associated with a previous-input-block of data; and convert the input-block of data into a fixed-point-block of data in accordance with the input-scale-factor, wherein the fixed-point-block of data comprises a plurality of fixed-point-values that can represent the plurality of floating-point numbers within a particular range. | 06-30-2016 |
| 20220137925 | DEVICE AND METHOD FOR HARDWARE-EFFICIENT ADAPTIVE CALCULATION OF FLOATING-POINT TRIGONOMETRIC FUNCTIONS USING COORDINATE ROTATE DIGITAL COMPUTER (CORDIC) - A system and an accelerator circuit including a register file comprising instruction registers to store a trigonometric calculation instruction for evaluating a trigonometric function, and data registers comprising a first data register to store a floating-point input value associated with the trigonometric calculation instruction. The accelerator circuit further includes a determination circuit to identify the trigonometric calculation function and the floating-point input value associated with the trigonometric calculation instruction and determine whether the floating-point input value is in a small value range, and an approximation circuit to responsive to determining that the floating-point input value is in the small value, receive the floating-point input value and calculate an approximation of the trigonometric function with respect to the input value. | 05-05-2022 |
