| Entries |
| Document | Title | Date |
|---|
| 20080270494 | Method for the Exponentiation or Scalar Multiplication of Elements - In order to further develop a method for the multi-exponentiation (Ii | 10-30-2008 |
| 20080313247 | Page Ranking Based on a Behavioral WEB Graph - A computer implemented method for scoring a first network node comprising data accessible to a user when connected to the network has steps of (a) determining at least an approximate probability for the first network node that a user not connected to the node will connect to the first node before connecting to any other node; and (b) assigning a score to the node based at least in part on the determined probability. | 12-18-2008 |
| 20090006509 | High-radix multiplier-divider - The high-radix multiplier-divider provides a system and method utilizing an SRT digit recurrence algorithm that provides for simultaneous multiplication and division using a single recurrence relation. When A, B, D and Q are fractions (e.g., Q=0.q | 01-01-2009 |
| 20090019099 | MATH CALCULATION IN WORD PROCESSORS - Architecture for a word processing application that facilitates operating on mathematical symbols, expressions, and/or equations input to a word processing document, and returning results back to the document. User input to the document in the form of math symbols, expressions or equations is transformed into a format for processing by a math engine. The engine returns one or more operations to the user that can be performed on the input, including calculating mathematical solutions, graphing equations and viewing steps to solving math problems. A user interface allows the user choose from the possible operations and to interactively manipulate input and graphs in the word application. The results can be inserted directly into the document and also be graded automatically. | 01-15-2009 |
| 20090106335 | Speed-Level Calculator And Calculating Method For Dynamic Voltage Scaling - Disclosed is directed to a speed-level calculator and calculating method for dynamic voltage scaling. The speed-level calculator comprises a deadline counter, a shifter, and a fixed-point multiplier. The deadline counter calculates the residual time D from current time through to each task deadline for completing an episode. The shifter generates a D′ value by shifting the D value to the right for e−m bits, and takes the decimal fraction part of the D′ value for m bits. The speed-level calculator further comprises a saturation control circuit to detect if an overflow occurs on the D′ value. According to a pre-calculated parameter a | 04-23-2009 |
| 20090112954 | A ROBUST SPECTRAL ANALYZER FOR ONE-DIMENSIONAL AND MULTI-DIMENSIONAL DATA ANALYSIS - A method of analyzing a spectrum of one-dimensional or multi-dimensional signal X(t) requires a number of steps including deriving coefficients [A | 04-30-2009 |
| 20090119355 | ARITHMETIC LOGICAL UNIT, COMPUTATION METHOD AND COMPUTER SYSTEM - This arithmetic logical unit outputs data to be used in checking the final result of an AES unit that encrypts a plain text block into an encrypted text block based on AES operation, and includes an arithmetic unit for computing parity data created based on XOR operation from an encryption key to be used as a key during AES encryption, parity data created based on XOR operation from a plain text block, and an AES operation halfway result output from the AES unit, and outputting a value that is equivalent to parity data created based on XOR operation from the final result of the AES unit. | 05-07-2009 |
| 20090157778 | COMPUTER SYSTEMS USING QUANTUM ALLEGORIES AS ORACLES - A computer system includes a deterministic computer that provides a non-recursive functional to a quantum system encoder. The quantum system encoder encodes the non-recursive functional into a first quantum system. The first quantum state is transformed to a second quantum state by an operator that includes a Topological Order Processing Element (TOPE). A quantum allegory generator provides an oracle to the operator. | 06-18-2009 |
| 20090248767 | SYSTEM AND METHOD FOR STATISTICALLY SEPARATING AND CHARACTERIZING NOISE WHICH IS ADDED TO A SIGNAL OF A MACHINE OR A SYSTEM - Method for finding the probability density function type and the variance properties of the noise component N of a raw signal S of a machine or a system, said raw signal S being combined of a pure signal component P and said noise component N, the method comprising: (a) defining a window within said raw signal; (b) recording the raw signal S; (c) numerically differentiating the raw signal S within the range of said window at least a number of times m to obtain an m order differentiated signal; (d) finding a histogram that best fits the m order differentiated signal; (e) finding a probability density function type that fits the distribution of the histogram; (f) determining the variance of the histogram, said histogram variance being essentially the m order variance σ | 10-01-2009 |
| 20090259703 | Handling Mask and Range Constraints - Handling mask and range constraints. For example, a method of handling range and mask constraints, may include determining whether or not to utilize a mask constraint and a range constraint by determining whether or not the range and mask constraints are satisfiable. Other embodiments are described and claimed. | 10-15-2009 |
| 20090287753 | PARALLEL EFFICIENCY CALCULATION METHOD AND APPARATUS - This invention is to provide a parallel efficiency calculation method, which can be applied, even in a case where a load balance is not kept, to many parallel processings including a heterogeneous computer system environment, and quantitatively correlates a parallel efficiency with a load balance contribution ratio and a virtual parallelization ratio, as parallel performance evaluation indexes, and parallel performance impediment factor contribution ratios. A parallel efficiency E | 11-19-2009 |
| 20110055300 | Method for Securely Determining Manhattan Distances - Embodiments disclose a method and a system for determining securely the Manhattan distance between a first and a second signal. The system is mapping the first signal to a first binary signal; mapping the second signal to a second binary signal, such that the squared distance between the first signal and the second binary signals equals the Manhattan distance; reducing respectively dimensions of the first binary signal and the second binary signal to produce a first low dimensional signal and a second low dimensional signal, such that the squared distance between the first low dimensional signal and the second low dimensional signals approximates the squared distance between the first binary signal and the second binary signals; and determining securely the squared distance between the first low dimensional signal and the second low dimensional signals to securely determine the Manhattan distance between the first signal and the second signal. | 03-03-2011 |
| 20110087715 | METHOD AND APPARATUS FOR PREPARING MAP DATA - A method is disclosed for using a suitably programmed computer to fit a circular arc to a plurality of points, which form map data representing a feature. In at least one embodiment, the method includes determining whether a region, in which a centre of a circle intersecting a first point and a region around at least one mid-point lies, intersects a perpendicular bisector of a line intersecting the first point and a second point. At least one embodiment of the method is suitable for preparing navigation maps and is applicable to any processing device configured to execute navigation software. | 04-14-2011 |
| 20110106865 | DYNAMIC EDITING OF DATA REPRESENTATIONS USING CASCADING WEIGHTS - A method and system for representing data includes providing a data representation according to defined variables and a functional relationship between the defined variables and receiving an assigned weight assigned to a defined variable. The method includes receiving a modification of a selected defined variable, and providing a further data representation according to a recalculation of an unselected defined variable, based upon the functional relationship, the assigned weight and the modified variable. Assigned weights and a plurality of modifications of the weighted variable are received. A further data representation is provided according to a further recalculation of the weighted variable based upon a weight selected from the assigned weights according to a previous modification of the weighted variable. The recalculating is performed according to a number of modifications performed since the previous modification of the weighted variable and according to a period of time since the previous modification of the weighted variable. | 05-05-2011 |
| 20110106866 | Hash Function for Hardware Implementations - A logic block is presented that generates avalanche criterion hash values using minimal logic. The logic block includes a first exclusive-OR function, a second exclusive-OR function, and an OR function. The first exclusive-OR function receives two input bits from a data packet and generates a linear output value based upon exclusive disjunction between the two input bits. The OR function receives two different input bits from the data packet and generates a first nonlinear output value based upon logical disjunction between the two different input bits. The second exclusive-OR function receives the linear output value and the first nonlinear output value, and generates a second nonlinear output value based upon exclusive disjunction between the linear output value and the first nonlinear output value. In turn, the second nonlinear output value is utilized to generate a hash value for the data packet. | 05-05-2011 |
| 20120072475 | MEASURING "CLOSENESS" IN A NETWORK - Closeness between nodes in a weighted network may be measured using an asymmetric generalization of classical Erdös numbers. | 03-22-2012 |
| 20120303689 | ARITHMETIC CIRCUIT AND A/D CONVERTER - An arithmetic circuit includes: an input terminal for receiving an input signal; plural capacitors; and an amplifier circuit including an amplifying input terminal and an output terminal and configured to amplify a signal input from the amplifying input terminal and output it as an output signal from the output terminal. A first switch circuit becomes conductive based on a first control signal and connects the plural capacitors in parallel between the input terminal and a first voltage terminal for supplying a first voltage. A second switch circuit becomes conductive based on a second control signal and connects a first capacitor of the plural capacitors between the amplifying input terminal and a second voltage terminal for supplying a second voltage to form a first current path and a second capacitor of the plural capacitors between the amplifying input terminal and the output terminal to form a second current path. | 11-29-2012 |
| 20120331024 | INFORMATION PROCESSING DEVICE, METHOD OF PROCESSING INFORMATION AND STORAGE MEDIUM - An information processing device can obtain an accurate result of regression analysis even if a mean and a variance of a response variable depends on an explanatory variable taking continuous variable. | 12-27-2012 |
| 20120331025 | SYSTEMS AND METHODS FOR LARGE-SCALE RANDOMIZED OPTIMIZATION FOR PROBLEMS WITH DECOMPOSABLE LOSS FUNCTIONS - Systems and methods directed toward processing optimization problems using loss functions, wherein a loss function is decomposed into at least one stratum loss function, a loss is decreased for each stratum loss function to a predefined stratum loss threshold individually using gradient descent, and the overall loss is decreased to a predefined threshold for the loss function by appropriately ordering the processing of the strata and spending appropriate processing time in each stratum. Other embodiments and aspects are also described herein. | 12-27-2012 |
| 20130054659 | INFORMATION PROCESSING TECHNIQUE FOR OPTIMIZATION - The disclosed method includes: generating a problem for a quantifier elimination (QE) method from a cost function representing a relationship between a parameter set and a cost; executing, by a module that executes a processing for the QE method by term substitution, a processing for the problem, to obtain a first processing result; when the first processing result includes a first partial problem for which the term substitution is impossible, executing, by a module that execute a numerical analysis processing, a processing to minimize the cost for the first partial problem, to obtain a second processing result; when the first processing result includes a logical expression as a solution of a second partial problem for which the term substitution has been completed, generating data to identify a minimum cost value from the logical expression; and generating a minimum cost for the problem from at least the second processing result. | 02-28-2013 |
| 20130054660 | APPROXIMATE ORDER STATISTICS OF REAL NUMBERS IN GENERIC DATA - A method, system, and processor-readable storage medium are directed towards calculating approximate order statistics on a collection of real numbers. In one embodiment, the collection of real numbers is processed to create a digest comprising hierarchy of buckets. Each bucket is assigned a real number N having P digits of precision and ordinality O. The hierarchy is defined by grouping buckets into levels, where each level contains all buckets of a given ordinality. Each individual bucket in the hierarchy defines a range of numbers—all numbers that, after being truncated to that bucket's P digits of precision, are equal to that bucket's N. Each bucket additionally maintains a count of how many numbers have fallen within that bucket's range. Approximate order statistics may then be calculated by traversing the hierarchy and performing an operation on some or all of the ranges and counts associated with each bucket. | 02-28-2013 |
| 20130103730 | Microprocessor Shifter Circuits Utilizing Butterfly and Inverse Butterfly Routing Circuits, and Control Circuits Therefor - Microprocessor shifter circuits utilizing butterfly and inverse butterfly circuits, and control circuits therefor, are provided. The same shifter circuits can also perform complex bit manipulations at high speeds, including butterfly and inverse butterfly operations, parallel extract and deposit operations, group operations, mix operations, permutation operations, as well as instructions executed by existing microprocessors, including shift right, shift left, rotate, extract, deposit and multimedia mix operations. The shifter circuits can be provided in various combinations to provide microprocessor functional units which perform a plurality of bit manipulation operations. | 04-25-2013 |
| 20130124586 | METHOD AND APPARATUS FOR EVALUATION OF MATHEMATICAL FUNCTIONS - An aspect includes an apparatus for evaluating a mathematical function at an input value. The apparatus includes a selector for selecting a mathematical function, an input for a value at which to evaluate the function, an identifier for identifying an interval containing the input value. The interval is described by at least one polynomial function. At least one control point representing the polynomial function is retrieved from at least one look up table, and the polynomial function can be derived from the control points. The function is evaluated at the input value and an output of the evaluation is used as a value of the function at that input value. | 05-16-2013 |
| 20130124587 | Circuit for a Radio System, Use and Method for Operation - A circuit and method of operation for a circuit of a radio system in which a system time is divided into symbols, in which a system clock generator is activated in an operating mode, so that the system time is determined from an output clock signal of the system clock generator by counting, in which the system clock generator is deactivated in a sleep mode, in which an output clock signal of a sleep clock generator is blanked as a function of an output signal of a modulo divider in the sleep mode, and the system time is determined by counting, wherein an output frequency of the output clock signal of the sleep clock generator is a non-integer multiple of a symbol frequency, in which the modulo divider divides the output clock signal of the sleep clock generator by a division factor, and in which the division factor of the modulo divider is produced by changing between at least two integer divisor values. | 05-16-2013 |
| 20130132450 | NODE DETERMINING PROGRAM, NODE DETERMINING APPARATUS, AND NODE DETERMINING METHOD - A computer-readable recording medium storing a program causing a processor to execute an operation, the operation includes associating a mathematical function of which a domain includes a key to uniquely specify data to be stored, with each node; associating an index value indicating an amount of the data, with each node; substituting the key in the mathematical function to calculate a value of the mathematical function; substituting the value of the mathematical function and the index value in a weighting function, of which a domain includes the value of the mathematical function and the index value, and in which a size relationship of values of the weighting function is defined in a range of the weighting function, to calculate a value of the weighting function for every node; determining a node in which the data is to be stored, based on the size relationship; and outputting the node. | 05-23-2013 |
| 20130132451 | POWER SUPPLY CONTROL APPARATUS - A power supply control apparatus includes a first adder configured to generate a difference signal based on a target value and a feedback signal; a compensator having a first transfer function Wc(z) and configured to generate a control signal based on the difference signal; a control target having a second transfer function Wp(z) and configured to output an output signal generated in response to the control signal; a disturbance canceller having a third transfer function {1+Wc(z)·Wp(z)}/{Wc(z)·Wp(z)} and configured to generate a disturbance cancelling signal based on the output signal corresponding to a control amount y; a second adder configured to generate a differential disturbance signal based on an output of the first adder and the disturbance cancelling signal; and a filter circuit which generates the feedback signal based on the differential disturbance signal. | 05-23-2013 |
| 20130166615 | CONTINUUM MOTION ANALYSIS METHOD, AND CONTINUUM MOTION ANALYSIS APPARATUS - A computer-readable recording medium has stored therein a communication-path control program causing a computer to execute a process which includes receiving input of data including information of an influence range representing each of continuum particles when the continuum is represented as a particle, and data representing each micro-surface component, which includes information of a normal direction when a fixed boundary is represented as a set of minute regions; calculating a repulsive force of a normal direction of the micro-surface component, which acts on the continuum particle from each of the micro-surface components intersected with the influence range of the continuum particle; calculating a force from the fixed boundary acting on each of the continuum particles by adding the repulsive forces acting on each of the continuum particles from each of the micro-surface components; and analyzing the motion of the continuum, based on the force from the fixed boundary. | 06-27-2013 |
| 20130185343 | SPACE EFFICIENT COUNTERS IN NETWORK DEVICES - A network device includes a memory and a counter update logic module. The memory is configured to store a plurality of bits. The counter update logic module is configured to estimate a count of quanta within a plurality of data units in a data flow based on statistical sampling of the plurality of data units, and to store the estimated count of quanta in the memory as m mantissa bits and e exponent bits. Them mantissa bits represent a mantissa value M and the e exponent bits represent an exponent value E. | 07-18-2013 |
| 20130204914 | PATIENT IDENTIFICATION BASED ON IMMUTABLE CHARACTERISTICS - Techniques are described herein that are capable of identifying patients based on immutable characteristics. For instance, each patient identifier is based on immutable characteristics of the patient who is to be identified by that patient identifier. Examples of an immutable characteristic of a patient include but are not limited to the patient's first name, the patient's last name, the patient's birth date, the patient's birth city, the patient's birth state, the patient's birth country, the patient's mother's maiden name, the patient's gender, etc. For instance, portions of a patient identifier that identifies a patient may be based on respective subsets of immutable characteristics of the patient. Logical operations may be performed with respect to the respective portions of the patient identifier to determine a checksum identifier to facilitate detection of an error with respect to reproduction (e.g., scanning, manually typing, etc.) of the patient identifier. | 08-08-2013 |
| 20130212138 | CURVE REPRESENTATIONS - Among other things, one or more techniques and/or systems are provided for creating a hierarchical multi-resolution representation of a curve. That is, a first-level curve (e.g., a relatively lower resolution of the curve) may be represented as a set of points within a first-level curve representation. A non-first-level curve (e.g., a second-level curve associated with a relatively higher resolution of the curve) may be represented as a set of offsets from the first-level curve (e.g., distances along offsets vectors starting from the first-level curve to the second-level curve), which is more efficient than storing complete data sets for different resolutions of the curve. In this way, various resolutions of the curve may be efficiently represented within the hierarchical multi-resolution representation. The various resolutions (e.g., levels) of the curve may also be acted upon or manipulated independently of one another. | 08-15-2013 |
| 20130246489 | COMPUTING DEVICE - According to an embodiment, a computing device includes a receiving unit, a calculating unit, a solving unit, a selecting unit, and a determining unit. The receiving unit is configured to receive pieces of input data indicative of elements of a subgroup of a multiplicative group in a finite field and pieces of first additional data for identifying conjugates of the respective pieces of input data. The elements are represented by traces. The calculating unit is configured to calculate a coefficient of an equation based on the pieces of input data. The solving unit is configured to obtain solutions of the equation. The selecting unit is configured to select one of the solutions as a result of computation, based on the first additional data. The determining unit is configured to determine second additional data for identifying a conjugate of the selected result of computation based on the first additional data. | 09-19-2013 |
| 20130254249 | APPARATUS AND METHOD FOR LOW COMPLEXITY COMBINATORIAL CODING OF SIGNALS - The invention utilizes low complexity estimates of complex functions to perform combinatorial coding of signal vectors. The invention disregards the accuracy of such functions as long as certain sufficient properties are maintained. The invention in turn may reduce computational complexity of certain coding and decoding operations by two orders of magnitude or more for a given signal vector input. | 09-26-2013 |
| 20130275481 | Method for the Low Cost Operation of a Processing Machine - A method for low cost operation of a processing machine comprising determining a suitable processing speed, operating the processing machine at the suitable processing speed, and determining costs as a function of the processing speed. The suitable processing speed is the processing speed which leads to predetermined costs in a predetermined processing time during the operation of the processing machine. | 10-17-2013 |
| 20130275482 | PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO GENERATE SEQUENCES OF CONSECUTIVE INTEGERS IN NUMERICAL ORDER - A method of an aspect includes receiving an instruction indicating a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes a sequence of at least four consecutive non-negative integers in numerical order. In an aspect, the instruction does not indicate a source packed data operand having a plurality of packed data elements in an architecturally-visible storage location. Other methods, apparatus, systems, and instructions are disclosed. | 10-17-2013 |
| 20130325917 | MAINTAINING DEPENDENCIES AMONG SUPERNODES DURING REPEATED MATRIX FACTORIZATIONS - Advantageously, embodiments of the invention provide techniques for determining dependency relationships between matrix supernodes by storing a list of dependencies for each supernode in a data structure and augmenting this list as needed when a column is moved from one supernode to another while factorizing a series A | 12-05-2013 |
| 20130332495 | DOWNSAMPLING WITH PARTIAL-SUM RE-USE - The sampling rate of a digital signal is reduced by storing a series of partial sums of the digital signal instead of the signal itself, thus reducing the memory size required to perform the sampling-rate reduction. | 12-12-2013 |
| 20130339410 | METHOD OF FRACTAL-BASED DATA DISTRIBUTION - A reader is utilized to detect motion of a user's fingers when a user mimics a typing motion. The system can be used to define various key press states for particular finger positions and then monitor the motion of fingers to detect when a key state is entered. The system can then provide the detected key state as input to a system expecting the data input. | 12-19-2013 |
| 20140032621 | Simple and Fast Method to Find Inside Points - A commonly recurring computational geometry problem in many diverse science and engineering disciplines is to determine if a point is inside an enclosed body. Usually this needs to be solved for a very large set of points. Many algorithms for different applications have been proposed. But fundamentally, they are all based on the same underlying strategy of focusing solely on the 2D body surface as the defining boundary. For a general solution, these traditional algorithms remain very complex and computationally costly. A new concept for a simple and efficient approach not specifically tied to any application is described here. | 01-30-2014 |
| 20140122550 | SYSTEM FOR NONPARAMETRIC ENTROPY ESTIMATION - The claimed invention discloses method, systems, and computer program products for providing nonparametric entropy estimation. The method comprises receiving a sample having a sample size of two or more symbols; calculating a number of distinct symbols in the sample, where the sample has one or more distinct symbols; calculating a relative frequency for each of the one or more distinct symbols; calculating, for a plurality of pairs having a first and second value, a set of numerical terms for each pair; calculating, based on the plurality of pairs and sets of numerical terms, one or more values for a first and second matrix; calculating, based on the first and second matrices, a plurality of vector components for a first, second, and third vector; and calculating an entropy estimation based at least partially on the one or more components in the third vector. | 05-01-2014 |
| 20140129600 | Interleaver Employing Quotient-Remainder Reordering - A method of generating an interleaved symbol sequence location from a symbol location of a symbol sequence comprises determining the interleaved symbol location based on an interleaver sequence function which relates a linear symbol location to the interleaved symbol location. This is done by acquiring values of the interleaver sequence function in quotient and remainder form and then calculating the interleaved symbol location by performing operations of the interleaver sequence function in quotient and remainder form. | 05-08-2014 |
| 20140156718 | Definition of Two Self-weights for Continuous Random Variable and Their Applications in Basic Statistics - This invention is for how to define two self-weights for continuous random variable based on sampling, how to SAC-normalize a skewed sampling distribution of a continuous random variable without changing the structure of the original measurement scale of the continuous random variable, how to infer representativeness of mathematical mean, and how to take the advantage of the two self-weights to do t-tests in a two-population comparison. | 06-05-2014 |
| 20140164456 | ITERATIVELY CALCULATING STANDARD DEVIATION FOR STREAMED DATA - The present invention extends to methods, systems, and computer program products for iteratively calculating standard deviation for streamed data. Embodiments of the invention include iteratively calculating standard deviation in a current computation window based on the standard deviation calculation for a previous computation window. Iteratively calculating standard deviation avoids visiting all previous input and performing redundant computations thereby increasing calculation efficiency. In general, streaming data is added to a buffer of size n until the buffer is filled up. Once the buffer is filled, a sum and standard deviation are calculated for the first n data points. As new data elements are received, a new sum is calculated by reusing the prior sum and a new standard deviation is calculated by reusing the prior standard deviation. | 06-12-2014 |
| 20140188959 | METHOD OF RECONSTRUCTING ASPHERIC SURFACE EQUATIONS FROM MEASUREMENTS - Surface measurement data just provides the coordinates of an object surface without giving various parameters like the radius of curvature, conic constant, and deformation coefficients. In this paper, we propose a novel method for extracting the important parameters for the determination of unknown aspheric surface equations from the measurement of aspheric surfaces. The largest error between the original surface and the reconstructed surface in the theoretical case is shown to be about 8.6 nm. This fact implies that the new method is well suited for the reconstruction of unknown surface equations. | 07-03-2014 |
| 20140188960 | CONFORMED DIMENSIONAL DATA GRAVITY WELLS - A processor-implemented method, system, and/or computer program product defines multiple dimensional data gravity wells on a conformed dimensional data gravity wells membrane. Non-dimensional data objects are associated with dimension objects to define conformed dimensional objects. The conformed dimensional objects are parsed into an n-tuple that includes a pointer to one of the non-dimensional data objects, a probability that a non-dimensional data object has been associated with a correct dimension object, and a weighting factor of importance of the conformed dimensional object. A virtual mass of each parsed conformed dimensional object is calculated, in order to define a shape of multiple dimensional data gravity wells that are created when conformed dimensional objects are pulled into each of the dimensional data gravity well frameworks on a conformed dimensional data gravity wells membrane. | 07-03-2014 |
| 20140250159 | INTEGER RATIOMETRIC ANALYSIS OF ROTATING ASSETS - A computer-executable ratiometric analysis method determines integer components of a rational number ratio or a close approximation of an irrational number ratio. In one embodiment the method uses a ratio of rotational speeds of two rotating assets in a machine or process, generates a new rational number based on the ratio of speeds, and calculates the integer components of the new rational number. The result is the integer ratio relationship between the initial two rational numbers. The method may be used in machinery analysis applications to determine whether a low-order integer ratio relationship exists between two machinery rotating components. Low-order integer ratio relationships in machinery are generally harmful in related machinery rotating components, and detection of such relationships is an important tool in preventing damage to machinery components. In a more general embodiment the algorithm can be used to determine the closest integer roots of any fractional number where this information would be of interest to an analyst in understanding the fractional number. | 09-04-2014 |
| 20140280404 | METHOD AND SYSTEM THAT PRODUCES NON-STABILIZER QUANTUM STATES THAT ARE USED IN VARIOUS QUANTUM CIRCUITS AND SYSTEMS - The current application is directed to methods and quantum circuits that prepare qubits in specified non-stabilizer quantum states that can, in turn, be used for a variety of different purposes, including in a quantum-circuit implementation of an arbitrary single-qubit unitary quantum gate that imparts a specified, arbitrary rotation to the state-vector representation of the state of an input qubit. In certain implementations, the methods and systems consume multiple magic-state qubits in order to carry out probabilistic rotation operators to prepare qubits with state vectors having specified rotation angles with respect to a rotation axis. These qubits are used as resources input to various quantum circuits, including the quantum-circuit implementation of an arbitrary single-qubit unitary quantum gate. | 09-18-2014 |
| 20140324933 | SYSTEMS AND METHODS THAT FORMULATE PROBLEMS FOR SOLVING BY A QUANTUM PROCESSOR USING HARDWARE GRAPH DECOMPOSITION - Systems and methods formulate problems for solving by a quantum processor using hardware graph decomposition. A decomposition of a primal graph may be built in a first stage based on a hardware specific graph, and refined in a second stage by, for example, removing vertices from the decomposition. The hardware specific graph may be a graph that is specific to a piece of hardware, for instance a quantum processor comprising a plurality of qubits and couplers operable to communicatively couple pairs of qubits. | 10-30-2014 |
| 20140344319 | ALGORITHM FOR PRIMALITY TESTING BASED ON INFINITE, SYMMETRIC, CONVERGENT, CONTINUOUS, CONVOLUTION RING GROUP - This primality testing is based on Infinite, Symmetric, Convergent, Continuous, Convolution Ring Group. The computational complexity of any primality testing depends in the factor less than √{square root over (N)} and becomes increasingly complex for large numbers as the lesser factor approaches └√N┘. But in the present algorithm the Infinite, Symmetry, Convergent, Continuous, Convolution Ring Group causes the numerator (i.e. the left side of the modulus) to converge smoothly towards └√N┘ as the testing factor approaches └√N┘. The normal operation for primality testing has computational complexity of O(n | 11-20-2014 |
| 20150095386 | FIELD DEVICE - A field device includes a first program area storing a first program, a second program area storing a second program designed such that if a program execution portion executes each of the first and second programs using the same data, a result of a calculation performed according to the second program is the same as a result of a calculation performed according to the first program, a first calculation result storage buffer storing a result of the calculation performed by the program execution portion according to the first program, and a second calculation result storage buffer storing a result of the calculation performed by the program execution portion according to the second program, and a calculation result comparator comparing the calculation result stored in the first calculation result storage buffer with the calculation result stored in the second calculation result storage buffer. | 04-02-2015 |
| 20150134712 | SIGNAL PROCESSING DEVICE, SIGNAL PROCESSING METHOD, AND PROGRAM - To improve the stability of numerical calculation for finding a continuous phase of a pair of signal sequences, provided is a signal processing device ( | 05-14-2015 |
| 20170235703 | MODAL INTERVAL CALCULATIONS BASED ON DECORATION CONFIGURATION | 08-17-2017 |
| 20190146755 | TEST CASE AND DATA SELECTION USING A SAMPLING METHODOLOGY | 05-16-2019 |
| 20220137922 | BIT-WIDTH OPTIMIZATION METHOD FOR PERFORMING FLOATING POINT TO FIXED POINT CONVERSION - Provided is a bit-width optimization method for performing floating point to fixed point conversion (FFC) by at least one processor. The bit-width optimization method includes receiving a first floating-point value which represents a minimum value among floating-point values to be converted, receiving a second floating-point value which represents a maximum value among the floating-point values to be converted, receiving a maximum permissible error rate for performing FFC, calculating a minimum bit width of fixed-point notation which satisfies the maximum permissible error rate on the basis of the first floating-point value, the second floating-point value, and the maximum permissible error rate, and calculating a scale factor for FFC on the basis of the second floating-point value and the calculated minimum bit width. | 05-05-2022 |
