| Class / Patent application number | Description | Number of patent applications / Date published |
|---|
| 708211000 | Determining number of like-valued leading or trailing bits | 7 |
| 20090172054 | EFFICIENT LEADING ZERO ANTICIPATOR - Embodiments of the present invention provide a system that estimates the location of the leading zero or the leading one in the result of an addition of floating-point numbers A and B. The system includes a half-adder circuit associated with each separate bit position i in A and B. The half-adder circuits compute a sum (S) for the associated bit position of A and B and a carry (K) for a next bit position of A and B. The system also includes a set of estimation circuits coupled to the set of half-adder circuits. The set of estimation circuits computes an estimate for the location of the leading zero or the leading one in the result from the K and S computed by each half-adder circuit. | 07-02-2009 |
| 20100063985 | NORMALIZER SHIFT PREDICTION FOR LOG ESTIMATE INSTRUCTIONS - A floating point processor unit includes a shift amount calculation circuit within a normalizer portion of the floating point unit, wherein the shift amount calculation circuit is utilized to compute the normalizer shift amount for a log estimate instruction that runs as a pipelinable instruction. | 03-11-2010 |
| 20110231461 | Identifier selection - A data processing apparatus is provided which is configured to select 2 | 09-22-2011 |
| 20120203811 | METHOD AND APPARATUS FOR CALCULATING THE NUMBER OF LEADING ZERO BITS OF A BINARY OPERATION - Provided are an apparatus and method for calculating the number of leading zero bits of a binary operation. The apparatus and method may accurately predict the number of leading zero bits using a binary tree structure of an input operand for a binary operation and reduce operation delay time due to the increase in number of bits of the operand. The method may include generating 2 | 08-09-2012 |
| 20120221614 | Processor Pipeline which Implements Fused and Unfused Multiply-Add Instructions - Implementing an unfused multiply-add instruction within a fused multiply-add pipeline. The system may include an aligner having an input for receiving an addition term, a multiplier tree having two inputs for receiving a first value and a second value for multiplication, and a first carry save adder (CSA), wherein the first CSA may receive partial products from the multiplier tree and an aligned addition term from the aligner. The system may include a fused/unfused multiply add (FUMA) block which may receive the first partial product, the second partial product, and the aligned addition term, wherein the first partial product and the second partial product are not truncated. The FUMA block may perform an unfused multiply add operation or a fused multiply add operation using the first partial product, the second partial product, and the aligned addition term, e.g., depending on an opcode or mode bit. | 08-30-2012 |
| 20130080491 | FAST CONDITION CODE GENERATION FOR ARITHMETIC LOGIC UNIT - In one embodiment, a microprocessor includes fetch logic for retrieving an instruction, decode logic configured to identify a plurality of operands and a multiply operation specified in the instruction, and execution logic configured to receive the plurality of operands and the multiply operation. The execution logic includes a first logic path configured to perform the multiply operation on the plurality of operands and output a result, and a second logic path, arranged in parallel with the first logic path, configured to output metadata associated with the result of the multiply operation. | 03-28-2013 |
| 20130282779 | DECIMAL FLOATING-POINT ADDER WITH LEADING ZERO ANTICIPATION - A decimal floating-point (DFP) adder includes a decimal leading-zero anticipator (LZA). The DFP adder receives DFP operands. Each operand includes a significand, an exponent, a sign bit and a leading zero count for the significand. The DFP adder adds or subtracts the DFP operands to obtain a DFP result. The LZA determines the leading zero count associated with the significand of the DFP result. The LZA operates at least partially in parallel with circuitry (in the DFP adder) that computes the DFP result. The LZA does not wait for that circuitry to finish computation of the DFP result. Instead it “anticipates” the number of leading zeros that the result's significand will contain. | 10-24-2013 |
